drivers/spi/spi-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3 // Copyright (C) 2008 Juergen Beisert
   4
   5 #include <linux/clk.h>
   6 #include <linux/completion.h>
   7 #include <linux/delay.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/err.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pinctrl/consumer.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/slab.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/spi_bitbang.h>
  22 #include <linux/types.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/property.h>
  26
  27 #include <linux/platform_data/dma-imx.h>
  28
  29 #define DRIVER_NAME "spi_imx"
  30
  31 static bool use_dma = true;
  32 module_param(use_dma, bool, 0644);
  33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
  34
  35 #define MXC_RPM_TIMEOUT         2000 /* 2000ms */
  36
  37 #define MXC_CSPIRXDATA          0x00
  38 #define MXC_CSPITXDATA          0x04
  39 #define MXC_CSPICTRL            0x08
  40 #define MXC_CSPIINT             0x0c
  41 #define MXC_RESET               0x1c
  42
  43 /* generic defines to abstract from the different register layouts */
  44 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  45 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  46 #define MXC_INT_RDR     BIT(4) /* Receive date threshold interrupt */
  47
  48 /* The maximum bytes that a sdma BD can transfer. */
  49 #define MAX_SDMA_BD_BYTES (1 << 15)
  50 #define MX51_ECSPI_CTRL_MAX_BURST       512
  51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
  52 #define MX53_MAX_TRANSFER_BYTES         512
  53
  54 enum spi_imx_devtype {
  55         IMX1_CSPI,
  56         IMX21_CSPI,
  57         IMX27_CSPI,
  58         IMX31_CSPI,
  59         IMX35_CSPI,     /* CSPI on all i.mx except above */
  60         IMX51_ECSPI,    /* ECSPI on i.mx51 */
  61         IMX53_ECSPI,    /* ECSPI on i.mx53 and later */
  62 };
  63
  64 struct spi_imx_data;
  65
  66 struct spi_imx_devtype_data {
  67         void (*intctrl)(struct spi_imx_data *, int);
  68         int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
  69         int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
  70         void (*trigger)(struct spi_imx_data *);
  71         int (*rx_available)(struct spi_imx_data *);
  72         void (*reset)(struct spi_imx_data *);
  73         void (*setup_wml)(struct spi_imx_data *);
  74         void (*disable)(struct spi_imx_data *);
  75         void (*disable_dma)(struct spi_imx_data *);
  76         bool has_dmamode;
  77         bool has_slavemode;
  78         unsigned int fifo_size;
  79         bool dynamic_burst;
  80         enum spi_imx_devtype devtype;
  81 };
  82
  83 struct spi_imx_data {
  84         struct spi_bitbang bitbang;
  85         struct device *dev;
  86
  87         struct completion xfer_done;
  88         void __iomem *base;
  89         unsigned long base_phys;
  90
  91         struct clk *clk_per;
  92         struct clk *clk_ipg;
  93         unsigned long spi_clk;
  94         unsigned int spi_bus_clk;
  95
  96         unsigned int bits_per_word;
  97         unsigned int spi_drctl;
  98
  99         unsigned int count, remainder;
 100         void (*tx)(struct spi_imx_data *);
 101         void (*rx)(struct spi_imx_data *);
 102         void *rx_buf;
 103         const void *tx_buf;
 104         unsigned int txfifo; /* number of words pushed in tx FIFO */
 105         unsigned int dynamic_burst;
 106
 107         /* Slave mode */
 108         bool slave_mode;
 109         bool slave_aborted;
 110         unsigned int slave_burst;
 111
 112         /* DMA */
 113         bool usedma;
 114         u32 wml;
 115         struct completion dma_rx_completion;
 116         struct completion dma_tx_completion;
 117
 118         const struct spi_imx_devtype_data *devtype_data;
 119 };
 120
 121 static inline int is_imx27_cspi(struct spi_imx_data *d)
 122 {
 123         return d->devtype_data->devtype == IMX27_CSPI;
 124 }
 125
 126 static inline int is_imx35_cspi(struct spi_imx_data *d)
 127 {
 128         return d->devtype_data->devtype == IMX35_CSPI;
 129 }
 130
 131 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 132 {
 133         return d->devtype_data->devtype == IMX51_ECSPI;
 134 }
 135
 136 static inline int is_imx53_ecspi(struct spi_imx_data *d)
 137 {
 138         return d->devtype_data->devtype == IMX53_ECSPI;
 139 }
 140
 141 #define MXC_SPI_BUF_RX(type)                                            \
 142 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 143 {                                                                       \
 144         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 145                                                                         \
 146         if (spi_imx->rx_buf) {                                          \
 147                 *(type *)spi_imx->rx_buf = val;                         \
 148                 spi_imx->rx_buf += sizeof(type);                        \
 149         }                                                               \
 150                                                                         \
 151         spi_imx->remainder -= sizeof(type);                             \
 152 }
 153
 154 #define MXC_SPI_BUF_TX(type)                                            \
 155 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 156 {                                                                       \
 157         type val = 0;                                                   \
 158                                                                         \
 159         if (spi_imx->tx_buf) {                                          \
 160                 val = *(type *)spi_imx->tx_buf;                         \
 161                 spi_imx->tx_buf += sizeof(type);                        \
 162         }                                                               \
 163                                                                         \
 164         spi_imx->count -= sizeof(type);                                 \
 165                                                                         \
 166         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 167 }
 168
 169 MXC_SPI_BUF_RX(u8)
 170 MXC_SPI_BUF_TX(u8)
 171 MXC_SPI_BUF_RX(u16)
 172 MXC_SPI_BUF_TX(u16)
 173 MXC_SPI_BUF_RX(u32)
 174 MXC_SPI_BUF_TX(u32)
 175
 176 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 177  * (which is currently not the case in this driver)
 178  */
 179 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 180         256, 384, 512, 768, 1024};
 181
 182 /* MX21, MX27 */
 183 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 184                 unsigned int fspi, unsigned int max, unsigned int *fres)
 185 {
 186         int i;
 187
 188         for (i = 2; i < max; i++)
 189                 if (fspi * mxc_clkdivs[i] >= fin)
 190                         break;
 191
 192         *fres = fin / mxc_clkdivs[i];
 193         return i;
 194 }
 195
 196 /* MX1, MX31, MX35, MX51 CSPI */
 197 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 198                 unsigned int fspi, unsigned int *fres)
 199 {
 200         int i, div = 4;
 201
 202         for (i = 0; i < 7; i++) {
 203                 if (fspi * div >= fin)
 204                         goto out;
 205                 div <<= 1;
 206         }
 207
 208 out:
 209         *fres = fin / div;
 210         return i;
 211 }
 212
 213 static int spi_imx_bytes_per_word(const int bits_per_word)
 214 {
 215         if (bits_per_word <= 8)
 216                 return 1;
 217         else if (bits_per_word <= 16)
 218                 return 2;
 219         else
 220                 return 4;
 221 }
 222
 223 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
 224                          struct spi_transfer *transfer)
 225 {
 226         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 227
 228         if (!use_dma || master->fallback)
 229                 return false;
 230
 231         if (!master->dma_rx)
 232                 return false;
 233
 234         if (spi_imx->slave_mode)
 235                 return false;
 236
 237         if (transfer->len < spi_imx->devtype_data->fifo_size)
 238                 return false;
 239
 240         spi_imx->dynamic_burst = 0;
 241
 242         return true;
 243 }
 244
 245 #define MX51_ECSPI_CTRL         0x08
 246 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 247 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 248 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 249 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 250 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 251 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 252 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 253 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
 254 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 255 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 256
 257 #define MX51_ECSPI_CONFIG       0x0c
 258 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
 259 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
 260 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
 261 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
 262 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
 263
 264 #define MX51_ECSPI_INT          0x10
 265 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 266 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 267 #define MX51_ECSPI_INT_RDREN            (1 <<  4)
 268
 269 #define MX51_ECSPI_DMA          0x14
 270 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 271 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 272 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 273
 274 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 275 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 276 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 277
 278 #define MX51_ECSPI_STAT         0x18
 279 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 280
 281 #define MX51_ECSPI_TESTREG      0x20
 282 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 283
 284 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
 285 {
 286         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
 287 #ifdef __LITTLE_ENDIAN
 288         unsigned int bytes_per_word;
 289 #endif
 290
 291         if (spi_imx->rx_buf) {
 292 #ifdef __LITTLE_ENDIAN
 293                 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 294                 if (bytes_per_word == 1)
 295                         val = cpu_to_be32(val);
 296                 else if (bytes_per_word == 2)
 297                         val = (val << 16) | (val >> 16);
 298 #endif
 299                 *(u32 *)spi_imx->rx_buf = val;
 300                 spi_imx->rx_buf += sizeof(u32);
 301         }
 302
 303         spi_imx->remainder -= sizeof(u32);
 304 }
 305
 306 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 307 {
 308         int unaligned;
 309         u32 val;
 310
 311         unaligned = spi_imx->remainder % 4;
 312
 313         if (!unaligned) {
 314                 spi_imx_buf_rx_swap_u32(spi_imx);
 315                 return;
 316         }
 317
 318         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 319                 spi_imx_buf_rx_u16(spi_imx);
 320                 return;
 321         }
 322
 323         val = readl(spi_imx->base + MXC_CSPIRXDATA);
 324
 325         while (unaligned--) {
 326                 if (spi_imx->rx_buf) {
 327                         *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
 328                         spi_imx->rx_buf++;
 329                 }
 330                 spi_imx->remainder--;
 331         }
 332 }
 333
 334 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
 335 {
 336         u32 val = 0;
 337 #ifdef __LITTLE_ENDIAN
 338         unsigned int bytes_per_word;
 339 #endif
 340
 341         if (spi_imx->tx_buf) {
 342                 val = *(u32 *)spi_imx->tx_buf;
 343                 spi_imx->tx_buf += sizeof(u32);
 344         }
 345
 346         spi_imx->count -= sizeof(u32);
 347 #ifdef __LITTLE_ENDIAN
 348         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 349
 350         if (bytes_per_word == 1)
 351                 val = cpu_to_be32(val);
 352         else if (bytes_per_word == 2)
 353                 val = (val << 16) | (val >> 16);
 354 #endif
 355         writel(val, spi_imx->base + MXC_CSPITXDATA);
 356 }
 357
 358 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 359 {
 360         int unaligned;
 361         u32 val = 0;
 362
 363         unaligned = spi_imx->count % 4;
 364
 365         if (!unaligned) {
 366                 spi_imx_buf_tx_swap_u32(spi_imx);
 367                 return;
 368         }
 369
 370         if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
 371                 spi_imx_buf_tx_u16(spi_imx);
 372                 return;
 373         }
 374
 375         while (unaligned--) {
 376                 if (spi_imx->tx_buf) {
 377                         val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
 378                         spi_imx->tx_buf++;
 379                 }
 380                 spi_imx->count--;
 381         }
 382
 383         writel(val, spi_imx->base + MXC_CSPITXDATA);
 384 }
 385
 386 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
 387 {
 388         u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
 389
 390         if (spi_imx->rx_buf) {
 391                 int n_bytes = spi_imx->slave_burst % sizeof(val);
 392
 393                 if (!n_bytes)
 394                         n_bytes = sizeof(val);
 395
 396                 memcpy(spi_imx->rx_buf,
 397                        ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
 398
 399                 spi_imx->rx_buf += n_bytes;
 400                 spi_imx->slave_burst -= n_bytes;
 401         }
 402
 403         spi_imx->remainder -= sizeof(u32);
 404 }
 405
 406 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
 407 {
 408         u32 val = 0;
 409         int n_bytes = spi_imx->count % sizeof(val);
 410
 411         if (!n_bytes)
 412                 n_bytes = sizeof(val);
 413
 414         if (spi_imx->tx_buf) {
 415                 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
 416                        spi_imx->tx_buf, n_bytes);
 417                 val = cpu_to_be32(val);
 418                 spi_imx->tx_buf += n_bytes;
 419         }
 420
 421         spi_imx->count -= n_bytes;
 422
 423         writel(val, spi_imx->base + MXC_CSPITXDATA);
 424 }
 425
 426 /* MX51 eCSPI */
 427 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 428                                       unsigned int fspi, unsigned int *fres)
 429 {
 430         /*
 431          * there are two 4-bit dividers, the pre-divider divides by
 432          * $pre, the post-divider by 2^$post
 433          */
 434         unsigned int pre, post;
 435         unsigned int fin = spi_imx->spi_clk;
 436
 437         if (unlikely(fspi > fin))
 438                 return 0;
 439
 440         post = fls(fin) - fls(fspi);
 441         if (fin > fspi << post)
 442                 post++;
 443
 444         /* now we have: (fin <= fspi << post) with post being minimal */
 445
 446         post = max(4U, post) - 4;
 447         if (unlikely(post > 0xf)) {
 448                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 449                                 fspi, fin);
 450                 return 0xff;
 451         }
 452
 453         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 454
 455         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 456                         __func__, fin, fspi, post, pre);
 457
 458         /* Resulting frequency for the SCLK line. */
 459         *fres = (fin / (pre + 1)) >> post;
 460
 461         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 462                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 463 }
 464
 465 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 466 {
 467         unsigned val = 0;
 468
 469         if (enable & MXC_INT_TE)
 470                 val |= MX51_ECSPI_INT_TEEN;
 471
 472         if (enable & MXC_INT_RR)
 473                 val |= MX51_ECSPI_INT_RREN;
 474
 475         if (enable & MXC_INT_RDR)
 476                 val |= MX51_ECSPI_INT_RDREN;
 477
 478         writel(val, spi_imx->base + MX51_ECSPI_INT);
 479 }
 480
 481 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 482 {
 483         u32 reg;
 484
 485         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 486         reg |= MX51_ECSPI_CTRL_XCH;
 487         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 488 }
 489
 490 static void mx51_disable_dma(struct spi_imx_data *spi_imx)
 491 {
 492         writel(0, spi_imx->base + MX51_ECSPI_DMA);
 493 }
 494
 495 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
 496 {
 497         u32 ctrl;
 498
 499         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 500         ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
 501         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 502 }
 503
 504 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 505                                       struct spi_message *msg)
 506 {
 507         struct spi_device *spi = msg->spi;
 508         struct spi_transfer *xfer;
 509         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 510         u32 min_speed_hz = ~0U;
 511         u32 testreg, delay;
 512         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 513
 514         /* set Master or Slave mode */
 515         if (spi_imx->slave_mode)
 516                 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
 517         else
 518                 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 519
 520         /*
 521          * Enable SPI_RDY handling (falling edge/level triggered).
 522          */
 523         if (spi->mode & SPI_READY)
 524                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 525
 526         /* set chip select to use */
 527         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
 528
 529         /*
 530          * The ctrl register must be written first, with the EN bit set other
 531          * registers must not be written to.
 532          */
 533         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 534
 535         testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 536         if (spi->mode & SPI_LOOP)
 537                 testreg |= MX51_ECSPI_TESTREG_LBC;
 538         else
 539                 testreg &= ~MX51_ECSPI_TESTREG_LBC;
 540         writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
 541
 542         /*
 543          * eCSPI burst completion by Chip Select signal in Slave mode
 544          * is not functional for imx53 Soc, config SPI burst completed when
 545          * BURST_LENGTH + 1 bits are received
 546          */
 547         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 548                 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 549         else
 550                 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 551
 552         if (spi->mode & SPI_CPHA)
 553                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 554         else
 555                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 556
 557         if (spi->mode & SPI_CPOL) {
 558                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 559                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 560         } else {
 561                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 562                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 563         }
 564
 565         if (spi->mode & SPI_CS_HIGH)
 566                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 567         else
 568                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 569
 570         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 571
 572         /*
 573          * Wait until the changes in the configuration register CONFIGREG
 574          * propagate into the hardware. It takes exactly one tick of the
 575          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 576          * effect of the delay it takes for the hardware to apply changes
 577          * is noticable if the SCLK clock run very slow. In such a case, if
 578          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 579          * be asserted before the SCLK polarity changes, which would disrupt
 580          * the SPI communication as the device on the other end would consider
 581          * the change of SCLK polarity as a clock tick already.
 582          *
 583          * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
 584          * callback, iterate over all the transfers in spi_message, find the
 585          * one with lowest bus frequency, and use that bus frequency for the
 586          * delay calculation. In case all transfers have speed_hz == 0, then
 587          * min_speed_hz is ~0 and the resulting delay is zero.
 588          */
 589         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 590                 if (!xfer->speed_hz)
 591                         continue;
 592                 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
 593         }
 594
 595         delay = (2 * 1000000) / min_speed_hz;
 596         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
 597                 udelay(delay);
 598         else                    /* SCLK is _very_ slow */
 599                 usleep_range(delay, delay + 10);
 600
 601         return 0;
 602 }
 603
 604 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 605                                        struct spi_device *spi)
 606 {
 607         u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 608         u32 clk;
 609
 610         /* Clear BL field and set the right value */
 611         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 612         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 613                 ctrl |= (spi_imx->slave_burst * 8 - 1)
 614                         << MX51_ECSPI_CTRL_BL_OFFSET;
 615         else
 616                 ctrl |= (spi_imx->bits_per_word - 1)
 617                         << MX51_ECSPI_CTRL_BL_OFFSET;
 618
 619         /* set clock speed */
 620         ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
 621                   0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
 622         ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
 623         spi_imx->spi_bus_clk = clk;
 624
 625         if (spi_imx->usedma)
 626                 ctrl |= MX51_ECSPI_CTRL_SMC;
 627
 628         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 629
 630         return 0;
 631 }
 632
 633 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
 634 {
 635         /*
 636          * Configure the DMA register: setup the watermark
 637          * and enable DMA request.
 638          */
 639         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
 640                 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
 641                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 642                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 643                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 644 }
 645
 646 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 647 {
 648         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 649 }
 650
 651 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 652 {
 653         /* drain receive buffer */
 654         while (mx51_ecspi_rx_available(spi_imx))
 655                 readl(spi_imx->base + MXC_CSPIRXDATA);
 656 }
 657
 658 #define MX31_INTREG_TEEN        (1 << 0)
 659 #define MX31_INTREG_RREN        (1 << 3)
 660
 661 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 662 #define MX31_CSPICTRL_MASTER    (1 << 1)
 663 #define MX31_CSPICTRL_XCH       (1 << 2)
 664 #define MX31_CSPICTRL_SMC       (1 << 3)
 665 #define MX31_CSPICTRL_POL       (1 << 4)
 666 #define MX31_CSPICTRL_PHA       (1 << 5)
 667 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 668 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 669 #define MX31_CSPICTRL_BC_SHIFT  8
 670 #define MX35_CSPICTRL_BL_SHIFT  20
 671 #define MX31_CSPICTRL_CS_SHIFT  24
 672 #define MX35_CSPICTRL_CS_SHIFT  12
 673 #define MX31_CSPICTRL_DR_SHIFT  16
 674
 675 #define MX31_CSPI_DMAREG        0x10
 676 #define MX31_DMAREG_RH_DEN      (1<<4)
 677 #define MX31_DMAREG_TH_DEN      (1<<1)
 678
 679 #define MX31_CSPISTATUS         0x14
 680 #define MX31_STATUS_RR          (1 << 3)
 681
 682 #define MX31_CSPI_TESTREG       0x1C
 683 #define MX31_TEST_LBC           (1 << 14)
 684
 685 /* These functions also work for the i.MX35, but be aware that
 686  * the i.MX35 has a slightly different register layout for bits
 687  * we do not use here.
 688  */
 689 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 690 {
 691         unsigned int val = 0;
 692
 693         if (enable & MXC_INT_TE)
 694                 val |= MX31_INTREG_TEEN;
 695         if (enable & MXC_INT_RR)
 696                 val |= MX31_INTREG_RREN;
 697
 698         writel(val, spi_imx->base + MXC_CSPIINT);
 699 }
 700
 701 static void mx31_trigger(struct spi_imx_data *spi_imx)
 702 {
 703         unsigned int reg;
 704
 705         reg = readl(spi_imx->base + MXC_CSPICTRL);
 706         reg |= MX31_CSPICTRL_XCH;
 707         writel(reg, spi_imx->base + MXC_CSPICTRL);
 708 }
 709
 710 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
 711                                 struct spi_message *msg)
 712 {
 713         return 0;
 714 }
 715
 716 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
 717                                  struct spi_device *spi)
 718 {
 719         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 720         unsigned int clk;
 721
 722         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 723                 MX31_CSPICTRL_DR_SHIFT;
 724         spi_imx->spi_bus_clk = clk;
 725
 726         if (is_imx35_cspi(spi_imx)) {
 727                 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
 728                 reg |= MX31_CSPICTRL_SSCTL;
 729         } else {
 730                 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
 731         }
 732
 733         if (spi->mode & SPI_CPHA)
 734                 reg |= MX31_CSPICTRL_PHA;
 735         if (spi->mode & SPI_CPOL)
 736                 reg |= MX31_CSPICTRL_POL;
 737         if (spi->mode & SPI_CS_HIGH)
 738                 reg |= MX31_CSPICTRL_SSPOL;
 739         if (!spi->cs_gpiod)
 740                 reg |= (spi->chip_select) <<
 741                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 742                                                   MX31_CSPICTRL_CS_SHIFT);
 743
 744         if (spi_imx->usedma)
 745                 reg |= MX31_CSPICTRL_SMC;
 746
 747         writel(reg, spi_imx->base + MXC_CSPICTRL);
 748
 749         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 750         if (spi->mode & SPI_LOOP)
 751                 reg |= MX31_TEST_LBC;
 752         else
 753                 reg &= ~MX31_TEST_LBC;
 754         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 755
 756         if (spi_imx->usedma) {
 757                 /*
 758                  * configure DMA requests when RXFIFO is half full and
 759                  * when TXFIFO is half empty
 760                  */
 761                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 762                         spi_imx->base + MX31_CSPI_DMAREG);
 763         }
 764
 765         return 0;
 766 }
 767
 768 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 769 {
 770         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 771 }
 772
 773 static void mx31_reset(struct spi_imx_data *spi_imx)
 774 {
 775         /* drain receive buffer */
 776         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 777                 readl(spi_imx->base + MXC_CSPIRXDATA);
 778 }
 779
 780 #define MX21_INTREG_RR          (1 << 4)
 781 #define MX21_INTREG_TEEN        (1 << 9)
 782 #define MX21_INTREG_RREN        (1 << 13)
 783
 784 #define MX21_CSPICTRL_POL       (1 << 5)
 785 #define MX21_CSPICTRL_PHA       (1 << 6)
 786 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 787 #define MX21_CSPICTRL_XCH       (1 << 9)
 788 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 789 #define MX21_CSPICTRL_MASTER    (1 << 11)
 790 #define MX21_CSPICTRL_DR_SHIFT  14
 791 #define MX21_CSPICTRL_CS_SHIFT  19
 792
 793 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 794 {
 795         unsigned int val = 0;
 796
 797         if (enable & MXC_INT_TE)
 798                 val |= MX21_INTREG_TEEN;
 799         if (enable & MXC_INT_RR)
 800                 val |= MX21_INTREG_RREN;
 801
 802         writel(val, spi_imx->base + MXC_CSPIINT);
 803 }
 804
 805 static void mx21_trigger(struct spi_imx_data *spi_imx)
 806 {
 807         unsigned int reg;
 808
 809         reg = readl(spi_imx->base + MXC_CSPICTRL);
 810         reg |= MX21_CSPICTRL_XCH;
 811         writel(reg, spi_imx->base + MXC_CSPICTRL);
 812 }
 813
 814 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
 815                                 struct spi_message *msg)
 816 {
 817         return 0;
 818 }
 819
 820 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
 821                                  struct spi_device *spi)
 822 {
 823         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 824         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 825         unsigned int clk;
 826
 827         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
 828                 << MX21_CSPICTRL_DR_SHIFT;
 829         spi_imx->spi_bus_clk = clk;
 830
 831         reg |= spi_imx->bits_per_word - 1;
 832
 833         if (spi->mode & SPI_CPHA)
 834                 reg |= MX21_CSPICTRL_PHA;
 835         if (spi->mode & SPI_CPOL)
 836                 reg |= MX21_CSPICTRL_POL;
 837         if (spi->mode & SPI_CS_HIGH)
 838                 reg |= MX21_CSPICTRL_SSPOL;
 839         if (!spi->cs_gpiod)
 840                 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
 841
 842         writel(reg, spi_imx->base + MXC_CSPICTRL);
 843
 844         return 0;
 845 }
 846
 847 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 848 {
 849         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 850 }
 851
 852 static void mx21_reset(struct spi_imx_data *spi_imx)
 853 {
 854         writel(1, spi_imx->base + MXC_RESET);
 855 }
 856
 857 #define MX1_INTREG_RR           (1 << 3)
 858 #define MX1_INTREG_TEEN         (1 << 8)
 859 #define MX1_INTREG_RREN         (1 << 11)
 860
 861 #define MX1_CSPICTRL_POL        (1 << 4)
 862 #define MX1_CSPICTRL_PHA        (1 << 5)
 863 #define MX1_CSPICTRL_XCH        (1 << 8)
 864 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 865 #define MX1_CSPICTRL_MASTER     (1 << 10)
 866 #define MX1_CSPICTRL_DR_SHIFT   13
 867
 868 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 869 {
 870         unsigned int val = 0;
 871
 872         if (enable & MXC_INT_TE)
 873                 val |= MX1_INTREG_TEEN;
 874         if (enable & MXC_INT_RR)
 875                 val |= MX1_INTREG_RREN;
 876
 877         writel(val, spi_imx->base + MXC_CSPIINT);
 878 }
 879
 880 static void mx1_trigger(struct spi_imx_data *spi_imx)
 881 {
 882         unsigned int reg;
 883
 884         reg = readl(spi_imx->base + MXC_CSPICTRL);
 885         reg |= MX1_CSPICTRL_XCH;
 886         writel(reg, spi_imx->base + MXC_CSPICTRL);
 887 }
 888
 889 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
 890                                struct spi_message *msg)
 891 {
 892         return 0;
 893 }
 894
 895 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
 896                                 struct spi_device *spi)
 897 {
 898         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 899         unsigned int clk;
 900
 901         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
 902                 MX1_CSPICTRL_DR_SHIFT;
 903         spi_imx->spi_bus_clk = clk;
 904
 905         reg |= spi_imx->bits_per_word - 1;
 906
 907         if (spi->mode & SPI_CPHA)
 908                 reg |= MX1_CSPICTRL_PHA;
 909         if (spi->mode & SPI_CPOL)
 910                 reg |= MX1_CSPICTRL_POL;
 911
 912         writel(reg, spi_imx->base + MXC_CSPICTRL);
 913
 914         return 0;
 915 }
 916
 917 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 918 {
 919         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 920 }
 921
 922 static void mx1_reset(struct spi_imx_data *spi_imx)
 923 {
 924         writel(1, spi_imx->base + MXC_RESET);
 925 }
 926
 927 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 928         .intctrl = mx1_intctrl,
 929         .prepare_message = mx1_prepare_message,
 930         .prepare_transfer = mx1_prepare_transfer,
 931         .trigger = mx1_trigger,
 932         .rx_available = mx1_rx_available,
 933         .reset = mx1_reset,
 934         .fifo_size = 8,
 935         .has_dmamode = false,
 936         .dynamic_burst = false,
 937         .has_slavemode = false,
 938         .devtype = IMX1_CSPI,
 939 };
 940
 941 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
 942         .intctrl = mx21_intctrl,
 943         .prepare_message = mx21_prepare_message,
 944         .prepare_transfer = mx21_prepare_transfer,
 945         .trigger = mx21_trigger,
 946         .rx_available = mx21_rx_available,
 947         .reset = mx21_reset,
 948         .fifo_size = 8,
 949         .has_dmamode = false,
 950         .dynamic_burst = false,
 951         .has_slavemode = false,
 952         .devtype = IMX21_CSPI,
 953 };
 954
 955 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
 956         /* i.mx27 cspi shares the functions with i.mx21 one */
 957         .intctrl = mx21_intctrl,
 958         .prepare_message = mx21_prepare_message,
 959         .prepare_transfer = mx21_prepare_transfer,
 960         .trigger = mx21_trigger,
 961         .rx_available = mx21_rx_available,
 962         .reset = mx21_reset,
 963         .fifo_size = 8,
 964         .has_dmamode = false,
 965         .dynamic_burst = false,
 966         .has_slavemode = false,
 967         .devtype = IMX27_CSPI,
 968 };
 969
 970 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
 971         .intctrl = mx31_intctrl,
 972         .prepare_message = mx31_prepare_message,
 973         .prepare_transfer = mx31_prepare_transfer,
 974         .trigger = mx31_trigger,
 975         .rx_available = mx31_rx_available,
 976         .reset = mx31_reset,
 977         .fifo_size = 8,
 978         .has_dmamode = false,
 979         .dynamic_burst = false,
 980         .has_slavemode = false,
 981         .devtype = IMX31_CSPI,
 982 };
 983
 984 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
 985         /* i.mx35 and later cspi shares the functions with i.mx31 one */
 986         .intctrl = mx31_intctrl,
 987         .prepare_message = mx31_prepare_message,
 988         .prepare_transfer = mx31_prepare_transfer,
 989         .trigger = mx31_trigger,
 990         .rx_available = mx31_rx_available,
 991         .reset = mx31_reset,
 992         .fifo_size = 8,
 993         .has_dmamode = true,
 994         .dynamic_burst = false,
 995         .has_slavemode = false,
 996         .devtype = IMX35_CSPI,
 997 };
 998
 999 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1000         .intctrl = mx51_ecspi_intctrl,
1001         .prepare_message = mx51_ecspi_prepare_message,
1002         .prepare_transfer = mx51_ecspi_prepare_transfer,
1003         .trigger = mx51_ecspi_trigger,
1004         .rx_available = mx51_ecspi_rx_available,
1005         .reset = mx51_ecspi_reset,
1006         .setup_wml = mx51_setup_wml,
1007         .disable_dma = mx51_disable_dma,
1008         .fifo_size = 64,
1009         .has_dmamode = true,
1010         .dynamic_burst = true,
1011         .has_slavemode = true,
1012         .disable = mx51_ecspi_disable,
1013         .devtype = IMX51_ECSPI,
1014 };
1015
1016 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1017         .intctrl = mx51_ecspi_intctrl,
1018         .prepare_message = mx51_ecspi_prepare_message,
1019         .prepare_transfer = mx51_ecspi_prepare_transfer,
1020         .trigger = mx51_ecspi_trigger,
1021         .rx_available = mx51_ecspi_rx_available,
1022         .disable_dma = mx51_disable_dma,
1023         .reset = mx51_ecspi_reset,
1024         .fifo_size = 64,
1025         .has_dmamode = true,
1026         .has_slavemode = true,
1027         .disable = mx51_ecspi_disable,
1028         .devtype = IMX53_ECSPI,
1029 };
1030
1031 static const struct platform_device_id spi_imx_devtype[] = {
1032         {
1033                 .name = "imx1-cspi",
1034                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1035         }, {
1036                 .name = "imx21-cspi",
1037                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1038         }, {
1039                 .name = "imx27-cspi",
1040                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1041         }, {
1042                 .name = "imx31-cspi",
1043                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1044         }, {
1045                 .name = "imx35-cspi",
1046                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1047         }, {
1048                 .name = "imx51-ecspi",
1049                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1050         }, {
1051                 .name = "imx53-ecspi",
1052                 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1053         }, {
1054                 /* sentinel */
1055         }
1056 };
1057
1058 static const struct of_device_id spi_imx_dt_ids[] = {
1059         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1060         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1061         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1062         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1063         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1064         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1065         { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1066         { /* sentinel */ }
1067 };
1068 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1069
1070 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1071 {
1072         u32 ctrl;
1073
1074         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1075         ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1076         ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1077         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1078 }
1079
1080 static void spi_imx_push(struct spi_imx_data *spi_imx)
1081 {
1082         unsigned int burst_len, fifo_words;
1083
1084         if (spi_imx->dynamic_burst)
1085                 fifo_words = 4;
1086         else
1087                 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1088         /*
1089          * Reload the FIFO when the remaining bytes to be transferred in the
1090          * current burst is 0. This only applies when bits_per_word is a
1091          * multiple of 8.
1092          */
1093         if (!spi_imx->remainder) {
1094                 if (spi_imx->dynamic_burst) {
1095
1096                         /* We need to deal unaligned data first */
1097                         burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1098
1099                         if (!burst_len)
1100                                 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1101
1102                         spi_imx_set_burst_len(spi_imx, burst_len * 8);
1103
1104                         spi_imx->remainder = burst_len;
1105                 } else {
1106                         spi_imx->remainder = fifo_words;
1107                 }
1108         }
1109
1110         while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1111                 if (!spi_imx->count)
1112                         break;
1113                 if (spi_imx->dynamic_burst &&
1114                     spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1115                                                      fifo_words))
1116                         break;
1117                 spi_imx->tx(spi_imx);
1118                 spi_imx->txfifo++;
1119         }
1120
1121         if (!spi_imx->slave_mode)
1122                 spi_imx->devtype_data->trigger(spi_imx);
1123 }
1124
1125 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1126 {
1127         struct spi_imx_data *spi_imx = dev_id;
1128
1129         while (spi_imx->txfifo &&
1130                spi_imx->devtype_data->rx_available(spi_imx)) {
1131                 spi_imx->rx(spi_imx);
1132                 spi_imx->txfifo--;
1133         }
1134
1135         if (spi_imx->count) {
1136                 spi_imx_push(spi_imx);
1137                 return IRQ_HANDLED;
1138         }
1139
1140         if (spi_imx->txfifo) {
1141                 /* No data left to push, but still waiting for rx data,
1142                  * enable receive data available interrupt.
1143                  */
1144                 spi_imx->devtype_data->intctrl(
1145                                 spi_imx, MXC_INT_RR);
1146                 return IRQ_HANDLED;
1147         }
1148
1149         spi_imx->devtype_data->intctrl(spi_imx, 0);
1150         complete(&spi_imx->xfer_done);
1151
1152         return IRQ_HANDLED;
1153 }
1154
1155 static int spi_imx_dma_configure(struct spi_master *master)
1156 {
1157         int ret;
1158         enum dma_slave_buswidth buswidth;
1159         struct dma_slave_config rx = {}, tx = {};
1160         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1161
1162         switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1163         case 4:
1164                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1165                 break;
1166         case 2:
1167                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1168                 break;
1169         case 1:
1170                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1171                 break;
1172         default:
1173                 return -EINVAL;
1174         }
1175
1176         tx.direction = DMA_MEM_TO_DEV;
1177         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1178         tx.dst_addr_width = buswidth;
1179         tx.dst_maxburst = spi_imx->wml;
1180         ret = dmaengine_slave_config(master->dma_tx, &tx);
1181         if (ret) {
1182                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1183                 return ret;
1184         }
1185
1186         rx.direction = DMA_DEV_TO_MEM;
1187         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1188         rx.src_addr_width = buswidth;
1189         rx.src_maxburst = spi_imx->wml;
1190         ret = dmaengine_slave_config(master->dma_rx, &rx);
1191         if (ret) {
1192                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1193                 return ret;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int spi_imx_setupxfer(struct spi_device *spi,
1200                                  struct spi_transfer *t)
1201 {
1202         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1203
1204         if (!t)
1205                 return 0;
1206
1207         if (!t->speed_hz) {
1208                 if (!spi->max_speed_hz) {
1209                         dev_err(&spi->dev, "no speed_hz provided!\n");
1210                         return -EINVAL;
1211                 }
1212                 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1213                 spi_imx->spi_bus_clk = spi->max_speed_hz;
1214         } else
1215                 spi_imx->spi_bus_clk = t->speed_hz;
1216
1217         spi_imx->bits_per_word = t->bits_per_word;
1218
1219         /*
1220          * Initialize the functions for transfer. To transfer non byte-aligned
1221          * words, we have to use multiple word-size bursts, we can't use
1222          * dynamic_burst in that case.
1223          */
1224         if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1225             (spi_imx->bits_per_word == 8 ||
1226             spi_imx->bits_per_word == 16 ||
1227             spi_imx->bits_per_word == 32)) {
1228
1229                 spi_imx->rx = spi_imx_buf_rx_swap;
1230                 spi_imx->tx = spi_imx_buf_tx_swap;
1231                 spi_imx->dynamic_burst = 1;
1232
1233         } else {
1234                 if (spi_imx->bits_per_word <= 8) {
1235                         spi_imx->rx = spi_imx_buf_rx_u8;
1236                         spi_imx->tx = spi_imx_buf_tx_u8;
1237                 } else if (spi_imx->bits_per_word <= 16) {
1238                         spi_imx->rx = spi_imx_buf_rx_u16;
1239                         spi_imx->tx = spi_imx_buf_tx_u16;
1240                 } else {
1241                         spi_imx->rx = spi_imx_buf_rx_u32;
1242                         spi_imx->tx = spi_imx_buf_tx_u32;
1243                 }
1244                 spi_imx->dynamic_burst = 0;
1245         }
1246
1247         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1248                 spi_imx->usedma = true;
1249         else
1250                 spi_imx->usedma = false;
1251
1252         if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1253                 spi_imx->rx = mx53_ecspi_rx_slave;
1254                 spi_imx->tx = mx53_ecspi_tx_slave;
1255                 spi_imx->slave_burst = t->len;
1256         }
1257
1258         spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1259
1260         return 0;
1261 }
1262
1263 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1264 {
1265         struct spi_master *master = spi_imx->bitbang.master;
1266
1267         if (master->dma_rx) {
1268                 dma_release_channel(master->dma_rx);
1269                 master->dma_rx = NULL;
1270         }
1271
1272         if (master->dma_tx) {
1273                 dma_release_channel(master->dma_tx);
1274                 master->dma_tx = NULL;
1275         }
1276 }
1277
1278 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1279                              struct spi_master *master)
1280 {
1281         int ret;
1282
1283         /* use pio mode for i.mx6dl chip TKT238285 */
1284         if (of_machine_is_compatible("fsl,imx6dl"))
1285                 return 0;
1286
1287         spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1288
1289         /* Prepare for TX DMA: */
1290         master->dma_tx = dma_request_chan(dev, "tx");
1291         if (IS_ERR(master->dma_tx)) {
1292                 ret = PTR_ERR(master->dma_tx);
1293                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1294                 master->dma_tx = NULL;
1295                 goto err;
1296         }
1297
1298         /* Prepare for RX : */
1299         master->dma_rx = dma_request_chan(dev, "rx");
1300         if (IS_ERR(master->dma_rx)) {
1301                 ret = PTR_ERR(master->dma_rx);
1302                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1303                 master->dma_rx = NULL;
1304                 goto err;
1305         }
1306
1307         init_completion(&spi_imx->dma_rx_completion);
1308         init_completion(&spi_imx->dma_tx_completion);
1309         master->can_dma = spi_imx_can_dma;
1310         master->max_dma_len = MAX_SDMA_BD_BYTES;
1311         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1312                                          SPI_MASTER_MUST_TX;
1313
1314         return 0;
1315 err:
1316         spi_imx_sdma_exit(spi_imx);
1317         return ret;
1318 }
1319
1320 static void spi_imx_dma_rx_callback(void *cookie)
1321 {
1322         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1323
1324         complete(&spi_imx->dma_rx_completion);
1325 }
1326
1327 static void spi_imx_dma_tx_callback(void *cookie)
1328 {
1329         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1330
1331         complete(&spi_imx->dma_tx_completion);
1332 }
1333
1334 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1335 {
1336         unsigned long timeout = 0;
1337
1338         /* Time with actual data transfer and CS change delay related to HW */
1339         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1340
1341         /* Add extra second for scheduler related activities */
1342         timeout += 1;
1343
1344         /* Double calculated timeout */
1345         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1346 }
1347
1348 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1349                                 struct spi_transfer *transfer)
1350 {
1351         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1352         unsigned long transfer_timeout;
1353         unsigned long timeout;
1354         struct spi_master *master = spi_imx->bitbang.master;
1355         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1356         struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1357         unsigned int bytes_per_word, i;
1358         int ret;
1359
1360         /* Get the right burst length from the last sg to ensure no tail data */
1361         bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1362         for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1363                 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1364                         break;
1365         }
1366         /* Use 1 as wml in case no available burst length got */
1367         if (i == 0)
1368                 i = 1;
1369
1370         spi_imx->wml =  i;
1371
1372         ret = spi_imx_dma_configure(master);
1373         if (ret)
1374                 goto dma_failure_no_start;
1375
1376         if (!spi_imx->devtype_data->setup_wml) {
1377                 dev_err(spi_imx->dev, "No setup_wml()?\n");
1378                 ret = -EINVAL;
1379                 goto dma_failure_no_start;
1380         }
1381         spi_imx->devtype_data->setup_wml(spi_imx);
1382
1383         /*
1384          * The TX DMA setup starts the transfer, so make sure RX is configured
1385          * before TX.
1386          */
1387         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1388                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1389                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1390         if (!desc_rx) {
1391                 ret = -EINVAL;
1392                 goto dma_failure_no_start;
1393         }
1394
1395         desc_rx->callback = spi_imx_dma_rx_callback;
1396         desc_rx->callback_param = (void *)spi_imx;
1397         dmaengine_submit(desc_rx);
1398         reinit_completion(&spi_imx->dma_rx_completion);
1399         dma_async_issue_pending(master->dma_rx);
1400
1401         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1402                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1403                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1404         if (!desc_tx) {
1405                 dmaengine_terminate_all(master->dma_tx);
1406                 dmaengine_terminate_all(master->dma_rx);
1407                 return -EINVAL;
1408         }
1409
1410         desc_tx->callback = spi_imx_dma_tx_callback;
1411         desc_tx->callback_param = (void *)spi_imx;
1412         dmaengine_submit(desc_tx);
1413         reinit_completion(&spi_imx->dma_tx_completion);
1414         dma_async_issue_pending(master->dma_tx);
1415
1416         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1417
1418         /* Wait SDMA to finish the data transfer.*/
1419         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1420                                                 transfer_timeout);
1421         if (!timeout) {
1422                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1423                 dmaengine_terminate_all(master->dma_tx);
1424                 dmaengine_terminate_all(master->dma_rx);
1425                 return -ETIMEDOUT;
1426         }
1427
1428         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1429                                               transfer_timeout);
1430         if (!timeout) {
1431                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1432                 spi_imx->devtype_data->reset(spi_imx);
1433                 dmaengine_terminate_all(master->dma_rx);
1434                 return -ETIMEDOUT;
1435         }
1436
1437         return transfer->len;
1438 /* fallback to pio */
1439 dma_failure_no_start:
1440         transfer->error |= SPI_TRANS_FAIL_NO_START;
1441         return ret;
1442 }
1443
1444 static int spi_imx_pio_transfer(struct spi_device *spi,
1445                                 struct spi_transfer *transfer)
1446 {
1447         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1448         unsigned long transfer_timeout;
1449         unsigned long timeout;
1450
1451         spi_imx->tx_buf = transfer->tx_buf;
1452         spi_imx->rx_buf = transfer->rx_buf;
1453         spi_imx->count = transfer->len;
1454         spi_imx->txfifo = 0;
1455         spi_imx->remainder = 0;
1456
1457         reinit_completion(&spi_imx->xfer_done);
1458
1459         spi_imx_push(spi_imx);
1460
1461         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1462
1463         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1464
1465         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1466                                               transfer_timeout);
1467         if (!timeout) {
1468                 dev_err(&spi->dev, "I/O Error in PIO\n");
1469                 spi_imx->devtype_data->reset(spi_imx);
1470                 return -ETIMEDOUT;
1471         }
1472
1473         return transfer->len;
1474 }
1475
1476 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1477                                       struct spi_transfer *transfer)
1478 {
1479         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1480         int ret = transfer->len;
1481
1482         if (is_imx53_ecspi(spi_imx) &&
1483             transfer->len > MX53_MAX_TRANSFER_BYTES) {
1484                 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1485                         MX53_MAX_TRANSFER_BYTES);
1486                 return -EMSGSIZE;
1487         }
1488
1489         spi_imx->tx_buf = transfer->tx_buf;
1490         spi_imx->rx_buf = transfer->rx_buf;
1491         spi_imx->count = transfer->len;
1492         spi_imx->txfifo = 0;
1493         spi_imx->remainder = 0;
1494
1495         reinit_completion(&spi_imx->xfer_done);
1496         spi_imx->slave_aborted = false;
1497
1498         spi_imx_push(spi_imx);
1499
1500         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1501
1502         if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1503             spi_imx->slave_aborted) {
1504                 dev_dbg(&spi->dev, "interrupted\n");
1505                 ret = -EINTR;
1506         }
1507
1508         /* ecspi has a HW issue when works in Slave mode,
1509          * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1510          * ECSPI_TXDATA keeps shift out the last word data,
1511          * so we have to disable ECSPI when in slave mode after the
1512          * transfer completes
1513          */
1514         if (spi_imx->devtype_data->disable)
1515                 spi_imx->devtype_data->disable(spi_imx);
1516
1517         return ret;
1518 }
1519
1520 static int spi_imx_transfer(struct spi_device *spi,
1521                                 struct spi_transfer *transfer)
1522 {
1523         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1524
1525         transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1526
1527         /* flush rxfifo before transfer */
1528         while (spi_imx->devtype_data->rx_available(spi_imx))
1529                 readl(spi_imx->base + MXC_CSPIRXDATA);
1530
1531         if (spi_imx->slave_mode)
1532                 return spi_imx_pio_transfer_slave(spi, transfer);
1533
1534         if (spi_imx->usedma)
1535                 return spi_imx_dma_transfer(spi_imx, transfer);
1536
1537         return spi_imx_pio_transfer(spi, transfer);
1538 }
1539
1540 static int spi_imx_setup(struct spi_device *spi)
1541 {
1542         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1543                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1544
1545         return 0;
1546 }
1547
1548 static void spi_imx_cleanup(struct spi_device *spi)
1549 {
1550 }
1551
1552 static int
1553 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1554 {
1555         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1556         int ret;
1557
1558         ret = pm_runtime_get_sync(spi_imx->dev);
1559         if (ret < 0) {
1560                 pm_runtime_put_noidle(spi_imx->dev);
1561                 dev_err(spi_imx->dev, "failed to enable clock\n");
1562                 return ret;
1563         }
1564
1565         ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1566         if (ret) {
1567                 pm_runtime_mark_last_busy(spi_imx->dev);
1568                 pm_runtime_put_autosuspend(spi_imx->dev);
1569         }
1570
1571         return ret;
1572 }
1573
1574 static int
1575 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1576 {
1577         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1578
1579         pm_runtime_mark_last_busy(spi_imx->dev);
1580         pm_runtime_put_autosuspend(spi_imx->dev);
1581         return 0;
1582 }
1583
1584 static int spi_imx_slave_abort(struct spi_master *master)
1585 {
1586         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1587
1588         spi_imx->slave_aborted = true;
1589         complete(&spi_imx->xfer_done);
1590
1591         return 0;
1592 }
1593
1594 static int spi_imx_probe(struct platform_device *pdev)
1595 {
1596         struct device_node *np = pdev->dev.of_node;
1597         const struct of_device_id *of_id =
1598                         of_match_device(spi_imx_dt_ids, &pdev->dev);
1599         struct spi_master *master;
1600         struct spi_imx_data *spi_imx;
1601         struct resource *res;
1602         int ret, irq, spi_drctl;
1603         const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1604                 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1605         bool slave_mode;
1606         u32 val;
1607
1608         slave_mode = devtype_data->has_slavemode &&
1609                         of_property_read_bool(np, "spi-slave");
1610         if (slave_mode)
1611                 master = spi_alloc_slave(&pdev->dev,
1612                                          sizeof(struct spi_imx_data));
1613         else
1614                 master = spi_alloc_master(&pdev->dev,
1615                                           sizeof(struct spi_imx_data));
1616         if (!master)
1617                 return -ENOMEM;
1618
1619         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1620         if ((ret < 0) || (spi_drctl >= 0x3)) {
1621                 /* '11' is reserved */
1622                 spi_drctl = 0;
1623         }
1624
1625         platform_set_drvdata(pdev, master);
1626
1627         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1628         master->bus_num = np ? -1 : pdev->id;
1629         master->use_gpio_descriptors = true;
1630
1631         spi_imx = spi_master_get_devdata(master);
1632         spi_imx->bitbang.master = master;
1633         spi_imx->dev = &pdev->dev;
1634         spi_imx->slave_mode = slave_mode;
1635
1636         spi_imx->devtype_data = devtype_data;
1637
1638         /*
1639          * Get number of chip selects from device properties. This can be
1640          * coming from device tree or boardfiles, if it is not defined,
1641          * a default value of 3 chip selects will be used, as all the legacy
1642          * board files have <= 3 chip selects.
1643          */
1644         if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1645                 master->num_chipselect = val;
1646         else
1647                 master->num_chipselect = 3;
1648
1649         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1650         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1651         spi_imx->bitbang.master->setup = spi_imx_setup;
1652         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1653         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1654         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1655         spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1656         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1657                                              | SPI_NO_CS;
1658         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1659             is_imx53_ecspi(spi_imx))
1660                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1661
1662         spi_imx->spi_drctl = spi_drctl;
1663
1664         init_completion(&spi_imx->xfer_done);
1665
1666         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1667         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1668         if (IS_ERR(spi_imx->base)) {
1669                 ret = PTR_ERR(spi_imx->base);
1670                 goto out_master_put;
1671         }
1672         spi_imx->base_phys = res->start;
1673
1674         irq = platform_get_irq(pdev, 0);
1675         if (irq < 0) {
1676                 ret = irq;
1677                 goto out_master_put;
1678         }
1679
1680         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1681                                dev_name(&pdev->dev), spi_imx);
1682         if (ret) {
1683                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1684                 goto out_master_put;
1685         }
1686
1687         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1688         if (IS_ERR(spi_imx->clk_ipg)) {
1689                 ret = PTR_ERR(spi_imx->clk_ipg);
1690                 goto out_master_put;
1691         }
1692
1693         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1694         if (IS_ERR(spi_imx->clk_per)) {
1695                 ret = PTR_ERR(spi_imx->clk_per);
1696                 goto out_master_put;
1697         }
1698
1699         ret = clk_prepare_enable(spi_imx->clk_per);
1700         if (ret)
1701                 goto out_master_put;
1702
1703         ret = clk_prepare_enable(spi_imx->clk_ipg);
1704         if (ret)
1705                 goto out_put_per;
1706
1707         pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1708         pm_runtime_use_autosuspend(spi_imx->dev);
1709         pm_runtime_get_noresume(spi_imx->dev);
1710         pm_runtime_set_active(spi_imx->dev);
1711         pm_runtime_enable(spi_imx->dev);
1712
1713         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1714         /*
1715          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1716          * if validated on other chips.
1717          */
1718         if (spi_imx->devtype_data->has_dmamode) {
1719                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1720                 if (ret == -EPROBE_DEFER)
1721                         goto out_runtime_pm_put;
1722
1723                 if (ret < 0)
1724                         dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1725                                 ret);
1726         }
1727
1728         spi_imx->devtype_data->reset(spi_imx);
1729
1730         spi_imx->devtype_data->intctrl(spi_imx, 0);
1731
1732         master->dev.of_node = pdev->dev.of_node;
1733         ret = spi_bitbang_start(&spi_imx->bitbang);
1734         if (ret) {
1735                 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1736                 goto out_bitbang_start;
1737         }
1738
1739         pm_runtime_mark_last_busy(spi_imx->dev);
1740         pm_runtime_put_autosuspend(spi_imx->dev);
1741
1742         return ret;
1743
1744 out_bitbang_start:
1745         if (spi_imx->devtype_data->has_dmamode)
1746                 spi_imx_sdma_exit(spi_imx);
1747 out_runtime_pm_put:
1748         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1749         pm_runtime_set_suspended(&pdev->dev);
1750         pm_runtime_disable(spi_imx->dev);
1751
1752         clk_disable_unprepare(spi_imx->clk_ipg);
1753 out_put_per:
1754         clk_disable_unprepare(spi_imx->clk_per);
1755 out_master_put:
1756         spi_master_put(master);
1757
1758         return ret;
1759 }
1760
1761 static int spi_imx_remove(struct platform_device *pdev)
1762 {
1763         struct spi_master *master = platform_get_drvdata(pdev);
1764         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1765         int ret;
1766
1767         spi_bitbang_stop(&spi_imx->bitbang);
1768
1769         ret = pm_runtime_get_sync(spi_imx->dev);
1770         if (ret < 0) {
1771                 pm_runtime_put_noidle(spi_imx->dev);
1772                 dev_err(spi_imx->dev, "failed to enable clock\n");
1773                 return ret;
1774         }
1775
1776         writel(0, spi_imx->base + MXC_CSPICTRL);
1777
1778         pm_runtime_dont_use_autosuspend(spi_imx->dev);
1779         pm_runtime_put_sync(spi_imx->dev);
1780         pm_runtime_disable(spi_imx->dev);
1781
1782         spi_imx_sdma_exit(spi_imx);
1783         spi_master_put(master);
1784
1785         return 0;
1786 }
1787
1788 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1789 {
1790         struct spi_master *master = dev_get_drvdata(dev);
1791         struct spi_imx_data *spi_imx;
1792         int ret;
1793
1794         spi_imx = spi_master_get_devdata(master);
1795
1796         ret = clk_prepare_enable(spi_imx->clk_per);
1797         if (ret)
1798                 return ret;
1799
1800         ret = clk_prepare_enable(spi_imx->clk_ipg);
1801         if (ret) {
1802                 clk_disable_unprepare(spi_imx->clk_per);
1803                 return ret;
1804         }
1805
1806         return 0;
1807 }
1808
1809 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1810 {
1811         struct spi_master *master = dev_get_drvdata(dev);
1812         struct spi_imx_data *spi_imx;
1813
1814         spi_imx = spi_master_get_devdata(master);
1815
1816         clk_disable_unprepare(spi_imx->clk_per);
1817         clk_disable_unprepare(spi_imx->clk_ipg);
1818
1819         return 0;
1820 }
1821
1822 static int __maybe_unused spi_imx_suspend(struct device *dev)
1823 {
1824         pinctrl_pm_select_sleep_state(dev);
1825         return 0;
1826 }
1827
1828 static int __maybe_unused spi_imx_resume(struct device *dev)
1829 {
1830         pinctrl_pm_select_default_state(dev);
1831         return 0;
1832 }
1833
1834 static const struct dev_pm_ops imx_spi_pm = {
1835         SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1836                                 spi_imx_runtime_resume, NULL)
1837         SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1838 };
1839
1840 static struct platform_driver spi_imx_driver = {
1841         .driver = {
1842                    .name = DRIVER_NAME,
1843                    .of_match_table = spi_imx_dt_ids,
1844                    .pm = &imx_spi_pm,
1845         },
1846         .id_table = spi_imx_devtype,
1847         .probe = spi_imx_probe,
1848         .remove = spi_imx_remove,
1849 };
1850 module_platform_driver(spi_imx_driver);
1851
1852 MODULE_DESCRIPTION("SPI Controller driver");
1853 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1854 MODULE_LICENSE("GPL");
1855 MODULE_ALIAS("platform:" DRIVER_NAME);