GNU Linux-libre 5.10.219-gnu1
[releases.git] / drivers / spi / spi-fsl-spi.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Freescale SPI controller driver.
4  *
5  * Maintainer: Kumar Gala
6  *
7  * Copyright (C) 2006 Polycom, Inc.
8  * Copyright 2010 Freescale Semiconductor, Inc.
9  *
10  * CPM SPI and QE buffer descriptors mode support:
11  * Copyright (c) 2009  MontaVista Software, Inc.
12  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
13  *
14  * GRLIB support:
15  * Copyright (c) 2012 Aeroflex Gaisler AB.
16  * Author: Andreas Larsson <andreas@gaisler.com>
17  */
18 #include <linux/delay.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/fsl_devices.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
35 #include <linux/types.h>
36
37 #ifdef CONFIG_FSL_SOC
38 #include <sysdev/fsl_soc.h>
39 #endif
40
41 /* Specific to the MPC8306/MPC8309 */
42 #define IMMR_SPI_CS_OFFSET 0x14c
43 #define SPI_BOOT_SEL_BIT   0x80000000
44
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
48
49 #define TYPE_FSL        0
50 #define TYPE_GRLIB      1
51
52 struct fsl_spi_match_data {
53         int type;
54 };
55
56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
57         .type = TYPE_FSL,
58 };
59
60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
61         .type = TYPE_GRLIB,
62 };
63
64 static const struct of_device_id of_fsl_spi_match[] = {
65         {
66                 .compatible = "fsl,spi",
67                 .data = &of_fsl_spi_fsl_config,
68         },
69         {
70                 .compatible = "aeroflexgaisler,spictrl",
71                 .data = &of_fsl_spi_grlib_config,
72         },
73         {}
74 };
75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
76
77 static int fsl_spi_get_type(struct device *dev)
78 {
79         const struct of_device_id *match;
80
81         if (dev->of_node) {
82                 match = of_match_node(of_fsl_spi_match, dev->of_node);
83                 if (match && match->data)
84                         return ((struct fsl_spi_match_data *)match->data)->type;
85         }
86         return TYPE_FSL;
87 }
88
89 static void fsl_spi_change_mode(struct spi_device *spi)
90 {
91         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
92         struct spi_mpc8xxx_cs *cs = spi->controller_state;
93         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
94         __be32 __iomem *mode = &reg_base->mode;
95         unsigned long flags;
96
97         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
98                 return;
99
100         /* Turn off IRQs locally to minimize time that SPI is disabled. */
101         local_irq_save(flags);
102
103         /* Turn off SPI unit prior changing mode */
104         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
105
106         /* When in CPM mode, we need to reinit tx and rx. */
107         if (mspi->flags & SPI_CPM_MODE) {
108                 fsl_spi_cpm_reinit_txrx(mspi);
109         }
110         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
111         local_irq_restore(flags);
112 }
113
114 static void fsl_spi_chipselect(struct spi_device *spi, int value)
115 {
116         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
117         struct fsl_spi_platform_data *pdata;
118         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
119
120         pdata = spi->dev.parent->parent->platform_data;
121
122         if (value == BITBANG_CS_INACTIVE) {
123                 if (pdata->cs_control)
124                         pdata->cs_control(spi, false);
125         }
126
127         if (value == BITBANG_CS_ACTIVE) {
128                 mpc8xxx_spi->rx_shift = cs->rx_shift;
129                 mpc8xxx_spi->tx_shift = cs->tx_shift;
130                 mpc8xxx_spi->get_rx = cs->get_rx;
131                 mpc8xxx_spi->get_tx = cs->get_tx;
132
133                 fsl_spi_change_mode(spi);
134
135                 if (pdata->cs_control)
136                         pdata->cs_control(spi, true);
137         }
138 }
139
140 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
141                                       int bits_per_word, int msb_first)
142 {
143         *rx_shift = 0;
144         *tx_shift = 0;
145         if (msb_first) {
146                 if (bits_per_word <= 8) {
147                         *rx_shift = 16;
148                         *tx_shift = 24;
149                 } else if (bits_per_word <= 16) {
150                         *rx_shift = 16;
151                         *tx_shift = 16;
152                 }
153         } else {
154                 if (bits_per_word <= 8)
155                         *rx_shift = 8;
156         }
157 }
158
159 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
160                                      int bits_per_word, int msb_first)
161 {
162         *rx_shift = 0;
163         *tx_shift = 0;
164         if (bits_per_word <= 16) {
165                 if (msb_first) {
166                         *rx_shift = 16; /* LSB in bit 16 */
167                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
168                 } else {
169                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
170                 }
171         }
172 }
173
174 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
175                                 struct spi_device *spi,
176                                 struct mpc8xxx_spi *mpc8xxx_spi,
177                                 int bits_per_word)
178 {
179         cs->rx_shift = 0;
180         cs->tx_shift = 0;
181         if (bits_per_word <= 8) {
182                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
183                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
184         } else if (bits_per_word <= 16) {
185                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
186                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
187         } else if (bits_per_word <= 32) {
188                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
189                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
190         } else
191                 return -EINVAL;
192
193         if (mpc8xxx_spi->set_shifts)
194                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
195                                         bits_per_word,
196                                         !(spi->mode & SPI_LSB_FIRST));
197
198         mpc8xxx_spi->rx_shift = cs->rx_shift;
199         mpc8xxx_spi->tx_shift = cs->tx_shift;
200         mpc8xxx_spi->get_rx = cs->get_rx;
201         mpc8xxx_spi->get_tx = cs->get_tx;
202
203         return bits_per_word;
204 }
205
206 static int fsl_spi_setup_transfer(struct spi_device *spi,
207                                         struct spi_transfer *t)
208 {
209         struct mpc8xxx_spi *mpc8xxx_spi;
210         int bits_per_word = 0;
211         u8 pm;
212         u32 hz = 0;
213         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
214
215         mpc8xxx_spi = spi_master_get_devdata(spi->master);
216
217         if (t) {
218                 bits_per_word = t->bits_per_word;
219                 hz = t->speed_hz;
220         }
221
222         /* spi_transfer level calls that work per-word */
223         if (!bits_per_word)
224                 bits_per_word = spi->bits_per_word;
225
226         if (!hz)
227                 hz = spi->max_speed_hz;
228
229         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
230                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
231                                                            mpc8xxx_spi,
232                                                            bits_per_word);
233
234         if (bits_per_word < 0)
235                 return bits_per_word;
236
237         if (bits_per_word == 32)
238                 bits_per_word = 0;
239         else
240                 bits_per_word = bits_per_word - 1;
241
242         /* mask out bits we are going to set */
243         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
244                                   | SPMODE_PM(0xF));
245
246         cs->hw_mode |= SPMODE_LEN(bits_per_word);
247
248         if ((mpc8xxx_spi->spibrg / hz) > 64) {
249                 cs->hw_mode |= SPMODE_DIV16;
250                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
251                 WARN_ONCE(pm > 16,
252                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
253                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
254                 if (pm > 16)
255                         pm = 16;
256         } else {
257                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
258         }
259         if (pm)
260                 pm--;
261
262         cs->hw_mode |= SPMODE_PM(pm);
263
264         fsl_spi_change_mode(spi);
265         return 0;
266 }
267
268 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
269                                 struct spi_transfer *t, unsigned int len)
270 {
271         u32 word;
272         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
273
274         mspi->count = len;
275
276         /* enable rx ints */
277         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
278
279         /* transmit word */
280         word = mspi->get_tx(mspi);
281         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
282
283         return 0;
284 }
285
286 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
287                             bool is_dma_mapped)
288 {
289         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
290         struct fsl_spi_reg __iomem *reg_base;
291         unsigned int len = t->len;
292         u8 bits_per_word;
293         int ret;
294
295         reg_base = mpc8xxx_spi->reg_base;
296         bits_per_word = spi->bits_per_word;
297         if (t->bits_per_word)
298                 bits_per_word = t->bits_per_word;
299
300         if (bits_per_word > 8) {
301                 /* invalid length? */
302                 if (len & 1)
303                         return -EINVAL;
304                 len /= 2;
305         }
306         if (bits_per_word > 16) {
307                 /* invalid length? */
308                 if (len & 1)
309                         return -EINVAL;
310                 len /= 2;
311         }
312
313         mpc8xxx_spi->tx = t->tx_buf;
314         mpc8xxx_spi->rx = t->rx_buf;
315
316         reinit_completion(&mpc8xxx_spi->done);
317
318         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
319                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
320         else
321                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
322         if (ret)
323                 return ret;
324
325         wait_for_completion(&mpc8xxx_spi->done);
326
327         /* disable rx ints */
328         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
329
330         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
331                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
332
333         return mpc8xxx_spi->count;
334 }
335
336 static int fsl_spi_do_one_msg(struct spi_master *master,
337                               struct spi_message *m)
338 {
339         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
340         struct spi_device *spi = m->spi;
341         struct spi_transfer *t, *first;
342         unsigned int cs_change;
343         const int nsecs = 50;
344         int status, last_bpw;
345
346         /*
347          * In CPU mode, optimize large byte transfers to use larger
348          * bits_per_word values to reduce number of interrupts taken.
349          */
350         list_for_each_entry(t, &m->transfers, transfer_list) {
351                 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
352                         if (t->len < 256 || t->bits_per_word != 8)
353                                 continue;
354                         if ((t->len & 3) == 0)
355                                 t->bits_per_word = 32;
356                         else if ((t->len & 1) == 0)
357                                 t->bits_per_word = 16;
358                 } else {
359                         /*
360                          * CPM/QE uses Little Endian for words > 8
361                          * so transform 16 and 32 bits words into 8 bits
362                          * Unfortnatly that doesn't work for LSB so
363                          * reject these for now
364                          * Note: 32 bits word, LSB works iff
365                          * tfcr/rfcr is set to CPMFCR_GBL
366                          */
367                         if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)
368                                 return -EINVAL;
369                         if (t->bits_per_word == 16 || t->bits_per_word == 32)
370                                 t->bits_per_word = 8; /* pretend its 8 bits */
371                         if (t->bits_per_word == 8 && t->len >= 256 &&
372                             (mpc8xxx_spi->flags & SPI_CPM1))
373                                 t->bits_per_word = 16;
374                 }
375         }
376
377         /* Don't allow changes if CS is active */
378         cs_change = 1;
379         list_for_each_entry(t, &m->transfers, transfer_list) {
380                 if (cs_change)
381                         first = t;
382                 cs_change = t->cs_change;
383                 if (first->speed_hz != t->speed_hz) {
384                         dev_err(&spi->dev,
385                                 "speed_hz cannot change while CS is active\n");
386                         return -EINVAL;
387                 }
388         }
389
390         last_bpw = -1;
391         cs_change = 1;
392         status = -EINVAL;
393         list_for_each_entry(t, &m->transfers, transfer_list) {
394                 if (cs_change || last_bpw != t->bits_per_word)
395                         status = fsl_spi_setup_transfer(spi, t);
396                 if (status < 0)
397                         break;
398                 last_bpw = t->bits_per_word;
399
400                 if (cs_change) {
401                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
402                         ndelay(nsecs);
403                 }
404                 cs_change = t->cs_change;
405                 if (t->len)
406                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
407                 if (status) {
408                         status = -EMSGSIZE;
409                         break;
410                 }
411                 m->actual_length += t->len;
412
413                 spi_transfer_delay_exec(t);
414
415                 if (cs_change) {
416                         ndelay(nsecs);
417                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
418                         ndelay(nsecs);
419                 }
420         }
421
422         m->status = status;
423
424         if (status || !cs_change) {
425                 ndelay(nsecs);
426                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
427         }
428
429         fsl_spi_setup_transfer(spi, NULL);
430         spi_finalize_current_message(master);
431         return 0;
432 }
433
434 static int fsl_spi_setup(struct spi_device *spi)
435 {
436         struct mpc8xxx_spi *mpc8xxx_spi;
437         struct fsl_spi_reg __iomem *reg_base;
438         bool initial_setup = false;
439         int retval;
440         u32 hw_mode;
441         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
442
443         if (!spi->max_speed_hz)
444                 return -EINVAL;
445
446         if (!cs) {
447                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
448                 if (!cs)
449                         return -ENOMEM;
450                 spi_set_ctldata(spi, cs);
451                 initial_setup = true;
452         }
453         mpc8xxx_spi = spi_master_get_devdata(spi->master);
454
455         reg_base = mpc8xxx_spi->reg_base;
456
457         hw_mode = cs->hw_mode; /* Save original settings */
458         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
459         /* mask out bits we are going to set */
460         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
461                          | SPMODE_REV | SPMODE_LOOP);
462
463         if (spi->mode & SPI_CPHA)
464                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
465         if (spi->mode & SPI_CPOL)
466                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
467         if (!(spi->mode & SPI_LSB_FIRST))
468                 cs->hw_mode |= SPMODE_REV;
469         if (spi->mode & SPI_LOOP)
470                 cs->hw_mode |= SPMODE_LOOP;
471
472         retval = fsl_spi_setup_transfer(spi, NULL);
473         if (retval < 0) {
474                 cs->hw_mode = hw_mode; /* Restore settings */
475                 if (initial_setup)
476                         kfree(cs);
477                 return retval;
478         }
479
480         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
481         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
482
483         return 0;
484 }
485
486 static void fsl_spi_cleanup(struct spi_device *spi)
487 {
488         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
489
490         kfree(cs);
491         spi_set_ctldata(spi, NULL);
492 }
493
494 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
495 {
496         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
497
498         /* We need handle RX first */
499         if (events & SPIE_NE) {
500                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
501
502                 if (mspi->rx)
503                         mspi->get_rx(rx_data, mspi);
504         }
505
506         if ((events & SPIE_NF) == 0)
507                 /* spin until TX is done */
508                 while (((events =
509                         mpc8xxx_spi_read_reg(&reg_base->event)) &
510                                                 SPIE_NF) == 0)
511                         cpu_relax();
512
513         /* Clear the events */
514         mpc8xxx_spi_write_reg(&reg_base->event, events);
515
516         mspi->count -= 1;
517         if (mspi->count) {
518                 u32 word = mspi->get_tx(mspi);
519
520                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
521         } else {
522                 complete(&mspi->done);
523         }
524 }
525
526 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
527 {
528         struct mpc8xxx_spi *mspi = context_data;
529         irqreturn_t ret = IRQ_NONE;
530         u32 events;
531         struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
532
533         /* Get interrupt events(tx/rx) */
534         events = mpc8xxx_spi_read_reg(&reg_base->event);
535         if (events)
536                 ret = IRQ_HANDLED;
537
538         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
539
540         if (mspi->flags & SPI_CPM_MODE)
541                 fsl_spi_cpm_irq(mspi, events);
542         else
543                 fsl_spi_cpu_irq(mspi, events);
544
545         return ret;
546 }
547
548 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
549 {
550         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
551         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
552         u32 slvsel;
553         u16 cs = spi->chip_select;
554
555         if (spi->cs_gpiod) {
556                 gpiod_set_value(spi->cs_gpiod, on);
557         } else if (cs < mpc8xxx_spi->native_chipselects) {
558                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
559                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
560                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
561         }
562 }
563
564 static void fsl_spi_grlib_probe(struct device *dev)
565 {
566         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
567         struct spi_master *master = dev_get_drvdata(dev);
568         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
569         struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
570         int mbits;
571         u32 capabilities;
572
573         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
574
575         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
576         mbits = SPCAP_MAXWLEN(capabilities);
577         if (mbits)
578                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
579
580         mpc8xxx_spi->native_chipselects = 0;
581         if (SPCAP_SSEN(capabilities)) {
582                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
583                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
584         }
585         master->num_chipselect = mpc8xxx_spi->native_chipselects;
586         pdata->cs_control = fsl_spi_grlib_cs_control;
587 }
588
589 static struct spi_master *fsl_spi_probe(struct device *dev,
590                 struct resource *mem, unsigned int irq)
591 {
592         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
593         struct spi_master *master;
594         struct mpc8xxx_spi *mpc8xxx_spi;
595         struct fsl_spi_reg __iomem *reg_base;
596         u32 regval;
597         int ret = 0;
598
599         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
600         if (master == NULL) {
601                 ret = -ENOMEM;
602                 goto err;
603         }
604
605         dev_set_drvdata(dev, master);
606
607         mpc8xxx_spi_probe(dev, mem, irq);
608
609         master->setup = fsl_spi_setup;
610         master->cleanup = fsl_spi_cleanup;
611         master->transfer_one_message = fsl_spi_do_one_msg;
612         master->use_gpio_descriptors = true;
613
614         mpc8xxx_spi = spi_master_get_devdata(master);
615         mpc8xxx_spi->max_bits_per_word = 32;
616         mpc8xxx_spi->type = fsl_spi_get_type(dev);
617
618         ret = fsl_spi_cpm_init(mpc8xxx_spi);
619         if (ret)
620                 goto err_cpm_init;
621
622         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
623         if (IS_ERR(mpc8xxx_spi->reg_base)) {
624                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
625                 goto err_probe;
626         }
627
628         if (mpc8xxx_spi->type == TYPE_GRLIB)
629                 fsl_spi_grlib_probe(dev);
630
631         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
632                 master->bits_per_word_mask =
633                         (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));
634         else
635                 master->bits_per_word_mask =
636                         (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));
637
638         master->bits_per_word_mask &=
639                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
640
641         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
642                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
643
644         if (mpc8xxx_spi->set_shifts)
645                 /* 8 bits per word and MSB first */
646                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
647                                         &mpc8xxx_spi->tx_shift, 8, 1);
648
649         /* Register for SPI Interrupt */
650         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
651                                0, "fsl_spi", mpc8xxx_spi);
652
653         if (ret != 0)
654                 goto err_probe;
655
656         reg_base = mpc8xxx_spi->reg_base;
657
658         /* SPI controller initializations */
659         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
660         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
661         mpc8xxx_spi_write_reg(&reg_base->command, 0);
662         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
663
664         /* Enable SPI interface */
665         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
666         if (mpc8xxx_spi->max_bits_per_word < 8) {
667                 regval &= ~SPMODE_LEN(0xF);
668                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
669         }
670         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
671                 regval |= SPMODE_OP;
672
673         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
674
675         ret = devm_spi_register_master(dev, master);
676         if (ret < 0)
677                 goto err_probe;
678
679         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
680                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
681
682         return master;
683
684 err_probe:
685         fsl_spi_cpm_free(mpc8xxx_spi);
686 err_cpm_init:
687         spi_master_put(master);
688 err:
689         return ERR_PTR(ret);
690 }
691
692 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
693 {
694         if (spi->cs_gpiod) {
695                 gpiod_set_value(spi->cs_gpiod, on);
696         } else {
697                 struct device *dev = spi->dev.parent->parent;
698                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
699                 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
700
701                 if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
702                         return;
703                 iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
704         }
705 }
706
707 static int of_fsl_spi_probe(struct platform_device *ofdev)
708 {
709         struct device *dev = &ofdev->dev;
710         struct device_node *np = ofdev->dev.of_node;
711         struct spi_master *master;
712         struct resource mem;
713         int irq, type;
714         int ret;
715         bool spisel_boot = false;
716 #if IS_ENABLED(CONFIG_FSL_SOC)
717         struct mpc8xxx_spi_probe_info *pinfo = NULL;
718 #endif
719
720
721         ret = of_mpc8xxx_spi_probe(ofdev);
722         if (ret)
723                 return ret;
724
725         type = fsl_spi_get_type(&ofdev->dev);
726         if (type == TYPE_FSL) {
727                 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
728 #if IS_ENABLED(CONFIG_FSL_SOC)
729                 pinfo = to_of_pinfo(pdata);
730
731                 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
732                 if (spisel_boot) {
733                         pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
734                         if (!pinfo->immr_spi_cs)
735                                 return -ENOMEM;
736                 }
737 #endif
738                 /*
739                  * Handle the case where we have one hardwired (always selected)
740                  * device on the first "chipselect". Else we let the core code
741                  * handle any GPIOs or native chip selects and assign the
742                  * appropriate callback for dealing with the CS lines. This isn't
743                  * supported on the GRLIB variant.
744                  */
745                 ret = gpiod_count(dev, "cs");
746                 if (ret < 0)
747                         ret = 0;
748                 if (ret == 0 && !spisel_boot) {
749                         pdata->max_chipselect = 1;
750                 } else {
751                         pdata->max_chipselect = ret + spisel_boot;
752                         pdata->cs_control = fsl_spi_cs_control;
753                 }
754         }
755
756         ret = of_address_to_resource(np, 0, &mem);
757         if (ret)
758                 goto unmap_out;
759
760         irq = platform_get_irq(ofdev, 0);
761         if (irq < 0) {
762                 ret = irq;
763                 goto unmap_out;
764         }
765
766         master = fsl_spi_probe(dev, &mem, irq);
767
768         return PTR_ERR_OR_ZERO(master);
769
770 unmap_out:
771 #if IS_ENABLED(CONFIG_FSL_SOC)
772         if (spisel_boot)
773                 iounmap(pinfo->immr_spi_cs);
774 #endif
775         return ret;
776 }
777
778 static int of_fsl_spi_remove(struct platform_device *ofdev)
779 {
780         struct spi_master *master = platform_get_drvdata(ofdev);
781         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
782
783         fsl_spi_cpm_free(mpc8xxx_spi);
784         return 0;
785 }
786
787 static struct platform_driver of_fsl_spi_driver = {
788         .driver = {
789                 .name = "fsl_spi",
790                 .of_match_table = of_fsl_spi_match,
791         },
792         .probe          = of_fsl_spi_probe,
793         .remove         = of_fsl_spi_remove,
794 };
795
796 #ifdef CONFIG_MPC832x_RDB
797 /*
798  * XXX XXX XXX
799  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
800  * only. The driver should go away soon, since newer MPC8323E-RDB's device
801  * tree can work with OpenFirmware driver. But for now we support old trees
802  * as well.
803  */
804 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
805 {
806         struct resource *mem;
807         int irq;
808         struct spi_master *master;
809
810         if (!dev_get_platdata(&pdev->dev))
811                 return -EINVAL;
812
813         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
814         if (!mem)
815                 return -EINVAL;
816
817         irq = platform_get_irq(pdev, 0);
818         if (irq <= 0)
819                 return -EINVAL;
820
821         master = fsl_spi_probe(&pdev->dev, mem, irq);
822         return PTR_ERR_OR_ZERO(master);
823 }
824
825 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
826 {
827         struct spi_master *master = platform_get_drvdata(pdev);
828         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
829
830         fsl_spi_cpm_free(mpc8xxx_spi);
831
832         return 0;
833 }
834
835 MODULE_ALIAS("platform:mpc8xxx_spi");
836 static struct platform_driver mpc8xxx_spi_driver = {
837         .probe = plat_mpc8xxx_spi_probe,
838         .remove = plat_mpc8xxx_spi_remove,
839         .driver = {
840                 .name = "mpc8xxx_spi",
841         },
842 };
843
844 static bool legacy_driver_failed;
845
846 static void __init legacy_driver_register(void)
847 {
848         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
849 }
850
851 static void __exit legacy_driver_unregister(void)
852 {
853         if (legacy_driver_failed)
854                 return;
855         platform_driver_unregister(&mpc8xxx_spi_driver);
856 }
857 #else
858 static void __init legacy_driver_register(void) {}
859 static void __exit legacy_driver_unregister(void) {}
860 #endif /* CONFIG_MPC832x_RDB */
861
862 static int __init fsl_spi_init(void)
863 {
864         legacy_driver_register();
865         return platform_driver_register(&of_fsl_spi_driver);
866 }
867 module_init(fsl_spi_init);
868
869 static void __exit fsl_spi_exit(void)
870 {
871         platform_driver_unregister(&of_fsl_spi_driver);
872         legacy_driver_unregister();
873 }
874 module_exit(fsl_spi_exit);
875
876 MODULE_AUTHOR("Kumar Gala");
877 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
878 MODULE_LICENSE("GPL");