drivers/spi/spi-fsl-spi.c

   1 /*
   2  * Freescale SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * GRLIB support:
  14  * Copyright (c) 2012 Aeroflex Gaisler AB.
  15  * Author: Andreas Larsson <andreas@gaisler.com>
  16  *
  17  * This program is free software; you can redistribute  it and/or modify it
  18  * under  the terms of  the GNU General  Public License as published by the
  19  * Free Software Foundation;  either version 2 of the  License, or (at your
  20  * option) any later version.
  21  */
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/fsl_devices.h>
  25 #include <linux/gpio.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/kernel.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mutex.h>
  32 #include <linux/of.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/spi/spi.h>
  39 #include <linux/spi/spi_bitbang.h>
  40 #include <linux/types.h>
  41
  42 #include "spi-fsl-lib.h"
  43 #include "spi-fsl-cpm.h"
  44 #include "spi-fsl-spi.h"
  45
  46 #define TYPE_FSL        0
  47 #define TYPE_GRLIB      1
  48
  49 struct fsl_spi_match_data {
  50         int type;
  51 };
  52
  53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  54         .type = TYPE_FSL,
  55 };
  56
  57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  58         .type = TYPE_GRLIB,
  59 };
  60
  61 static const struct of_device_id of_fsl_spi_match[] = {
  62         {
  63                 .compatible = "fsl,spi",
  64                 .data = &of_fsl_spi_fsl_config,
  65         },
  66         {
  67                 .compatible = "aeroflexgaisler,spictrl",
  68                 .data = &of_fsl_spi_grlib_config,
  69         },
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  73
  74 static int fsl_spi_get_type(struct device *dev)
  75 {
  76         const struct of_device_id *match;
  77
  78         if (dev->of_node) {
  79                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  80                 if (match && match->data)
  81                         return ((struct fsl_spi_match_data *)match->data)->type;
  82         }
  83         return TYPE_FSL;
  84 }
  85
  86 static void fsl_spi_change_mode(struct spi_device *spi)
  87 {
  88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  90         struct fsl_spi_reg *reg_base = mspi->reg_base;
  91         __be32 __iomem *mode = &reg_base->mode;
  92         unsigned long flags;
  93
  94         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  95                 return;
  96
  97         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  98         local_irq_save(flags);
  99
 100         /* Turn off SPI unit prior changing mode */
 101         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 102
 103         /* When in CPM mode, we need to reinit tx and rx. */
 104         if (mspi->flags & SPI_CPM_MODE) {
 105                 fsl_spi_cpm_reinit_txrx(mspi);
 106         }
 107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 108         local_irq_restore(flags);
 109 }
 110
 111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 112 {
 113         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 114         struct fsl_spi_platform_data *pdata;
 115         bool pol = spi->mode & SPI_CS_HIGH;
 116         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 117
 118         pdata = spi->dev.parent->parent->platform_data;
 119
 120         if (value == BITBANG_CS_INACTIVE) {
 121                 if (pdata->cs_control)
 122                         pdata->cs_control(spi, !pol);
 123         }
 124
 125         if (value == BITBANG_CS_ACTIVE) {
 126                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 127                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 128                 mpc8xxx_spi->get_rx = cs->get_rx;
 129                 mpc8xxx_spi->get_tx = cs->get_tx;
 130
 131                 fsl_spi_change_mode(spi);
 132
 133                 if (pdata->cs_control)
 134                         pdata->cs_control(spi, pol);
 135         }
 136 }
 137
 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 139                                       int bits_per_word, int msb_first)
 140 {
 141         *rx_shift = 0;
 142         *tx_shift = 0;
 143         if (msb_first) {
 144                 if (bits_per_word <= 8) {
 145                         *rx_shift = 16;
 146                         *tx_shift = 24;
 147                 } else if (bits_per_word <= 16) {
 148                         *rx_shift = 16;
 149                         *tx_shift = 16;
 150                 }
 151         } else {
 152                 if (bits_per_word <= 8)
 153                         *rx_shift = 8;
 154         }
 155 }
 156
 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 158                                      int bits_per_word, int msb_first)
 159 {
 160         *rx_shift = 0;
 161         *tx_shift = 0;
 162         if (bits_per_word <= 16) {
 163                 if (msb_first) {
 164                         *rx_shift = 16; /* LSB in bit 16 */
 165                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 166                 } else {
 167                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 168                 }
 169         }
 170 }
 171
 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 173                                 struct spi_device *spi,
 174                                 struct mpc8xxx_spi *mpc8xxx_spi,
 175                                 int bits_per_word)
 176 {
 177         cs->rx_shift = 0;
 178         cs->tx_shift = 0;
 179         if (bits_per_word <= 8) {
 180                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 181                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 182         } else if (bits_per_word <= 16) {
 183                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 184                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 185         } else if (bits_per_word <= 32) {
 186                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 187                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 188         } else
 189                 return -EINVAL;
 190
 191         if (mpc8xxx_spi->set_shifts)
 192                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 193                                         bits_per_word,
 194                                         !(spi->mode & SPI_LSB_FIRST));
 195
 196         mpc8xxx_spi->rx_shift = cs->rx_shift;
 197         mpc8xxx_spi->tx_shift = cs->tx_shift;
 198         mpc8xxx_spi->get_rx = cs->get_rx;
 199         mpc8xxx_spi->get_tx = cs->get_tx;
 200
 201         return bits_per_word;
 202 }
 203
 204 static int fsl_spi_setup_transfer(struct spi_device *spi,
 205                                         struct spi_transfer *t)
 206 {
 207         struct mpc8xxx_spi *mpc8xxx_spi;
 208         int bits_per_word = 0;
 209         u8 pm;
 210         u32 hz = 0;
 211         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 212
 213         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 214
 215         if (t) {
 216                 bits_per_word = t->bits_per_word;
 217                 hz = t->speed_hz;
 218         }
 219
 220         /* spi_transfer level calls that work per-word */
 221         if (!bits_per_word)
 222                 bits_per_word = spi->bits_per_word;
 223
 224         if (!hz)
 225                 hz = spi->max_speed_hz;
 226
 227         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 228                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 229                                                            mpc8xxx_spi,
 230                                                            bits_per_word);
 231
 232         if (bits_per_word < 0)
 233                 return bits_per_word;
 234
 235         if (bits_per_word == 32)
 236                 bits_per_word = 0;
 237         else
 238                 bits_per_word = bits_per_word - 1;
 239
 240         /* mask out bits we are going to set */
 241         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 242                                   | SPMODE_PM(0xF));
 243
 244         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 245
 246         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 247                 cs->hw_mode |= SPMODE_DIV16;
 248                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 249                 WARN_ONCE(pm > 16,
 250                           "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
 251                           dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
 252                 if (pm > 16)
 253                         pm = 16;
 254         } else {
 255                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 256         }
 257         if (pm)
 258                 pm--;
 259
 260         cs->hw_mode |= SPMODE_PM(pm);
 261
 262         fsl_spi_change_mode(spi);
 263         return 0;
 264 }
 265
 266 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 267                                 struct spi_transfer *t, unsigned int len)
 268 {
 269         u32 word;
 270         struct fsl_spi_reg *reg_base = mspi->reg_base;
 271
 272         mspi->count = len;
 273
 274         /* enable rx ints */
 275         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 276
 277         /* transmit word */
 278         word = mspi->get_tx(mspi);
 279         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 280
 281         return 0;
 282 }
 283
 284 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 285                             bool is_dma_mapped)
 286 {
 287         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 288         struct fsl_spi_reg *reg_base;
 289         unsigned int len = t->len;
 290         u8 bits_per_word;
 291         int ret;
 292
 293         reg_base = mpc8xxx_spi->reg_base;
 294         bits_per_word = spi->bits_per_word;
 295         if (t->bits_per_word)
 296                 bits_per_word = t->bits_per_word;
 297
 298         if (bits_per_word > 8) {
 299                 /* invalid length? */
 300                 if (len & 1)
 301                         return -EINVAL;
 302                 len /= 2;
 303         }
 304         if (bits_per_word > 16) {
 305                 /* invalid length? */
 306                 if (len & 1)
 307                         return -EINVAL;
 308                 len /= 2;
 309         }
 310
 311         mpc8xxx_spi->tx = t->tx_buf;
 312         mpc8xxx_spi->rx = t->rx_buf;
 313
 314         reinit_completion(&mpc8xxx_spi->done);
 315
 316         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 317                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 318         else
 319                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 320         if (ret)
 321                 return ret;
 322
 323         wait_for_completion(&mpc8xxx_spi->done);
 324
 325         /* disable rx ints */
 326         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 327
 328         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 329                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 330
 331         return mpc8xxx_spi->count;
 332 }
 333
 334 static int fsl_spi_do_one_msg(struct spi_master *master,
 335                               struct spi_message *m)
 336 {
 337         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 338         struct spi_device *spi = m->spi;
 339         struct spi_transfer *t, *first;
 340         unsigned int cs_change;
 341         const int nsecs = 50;
 342         int status, last_bpw;
 343
 344         /*
 345          * In CPU mode, optimize large byte transfers to use larger
 346          * bits_per_word values to reduce number of interrupts taken.
 347          */
 348         list_for_each_entry(t, &m->transfers, transfer_list) {
 349                 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
 350                         if (t->len < 256 || t->bits_per_word != 8)
 351                                 continue;
 352                         if ((t->len & 3) == 0)
 353                                 t->bits_per_word = 32;
 354                         else if ((t->len & 1) == 0)
 355                                 t->bits_per_word = 16;
 356                 } else {
 357                         /*
 358                          * CPM/QE uses Little Endian for words > 8
 359                          * so transform 16 and 32 bits words into 8 bits
 360                          * Unfortnatly that doesn't work for LSB so
 361                          * reject these for now
 362                          * Note: 32 bits word, LSB works iff
 363                          * tfcr/rfcr is set to CPMFCR_GBL
 364                          */
 365                         if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)
 366                                 return -EINVAL;
 367                         if (t->bits_per_word == 16 || t->bits_per_word == 32)
 368                                 t->bits_per_word = 8; /* pretend its 8 bits */
 369                         if (t->bits_per_word == 8 && t->len >= 256 &&
 370                             (mpc8xxx_spi->flags & SPI_CPM1))
 371                                 t->bits_per_word = 16;
 372                 }
 373         }
 374
 375         /* Don't allow changes if CS is active */
 376         cs_change = 1;
 377         list_for_each_entry(t, &m->transfers, transfer_list) {
 378                 if (cs_change)
 379                         first = t;
 380                 cs_change = t->cs_change;
 381                 if (first->speed_hz != t->speed_hz) {
 382                         dev_err(&spi->dev,
 383                                 "speed_hz cannot change while CS is active\n");
 384                         return -EINVAL;
 385                 }
 386         }
 387
 388         last_bpw = -1;
 389         cs_change = 1;
 390         status = -EINVAL;
 391         list_for_each_entry(t, &m->transfers, transfer_list) {
 392                 if (cs_change || last_bpw != t->bits_per_word)
 393                         status = fsl_spi_setup_transfer(spi, t);
 394                 if (status < 0)
 395                         break;
 396                 last_bpw = t->bits_per_word;
 397
 398                 if (cs_change) {
 399                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 400                         ndelay(nsecs);
 401                 }
 402                 cs_change = t->cs_change;
 403                 if (t->len)
 404                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 405                 if (status) {
 406                         status = -EMSGSIZE;
 407                         break;
 408                 }
 409                 m->actual_length += t->len;
 410
 411                 if (t->delay_usecs)
 412                         udelay(t->delay_usecs);
 413
 414                 if (cs_change) {
 415                         ndelay(nsecs);
 416                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 417                         ndelay(nsecs);
 418                 }
 419         }
 420
 421         m->status = status;
 422
 423         if (status || !cs_change) {
 424                 ndelay(nsecs);
 425                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 426         }
 427
 428         fsl_spi_setup_transfer(spi, NULL);
 429         spi_finalize_current_message(master);
 430         return 0;
 431 }
 432
 433 static int fsl_spi_setup(struct spi_device *spi)
 434 {
 435         struct mpc8xxx_spi *mpc8xxx_spi;
 436         struct fsl_spi_reg *reg_base;
 437         int retval;
 438         u32 hw_mode;
 439         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 440
 441         if (!spi->max_speed_hz)
 442                 return -EINVAL;
 443
 444         if (!cs) {
 445                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 446                 if (!cs)
 447                         return -ENOMEM;
 448                 spi_set_ctldata(spi, cs);
 449         }
 450         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 451
 452         reg_base = mpc8xxx_spi->reg_base;
 453
 454         hw_mode = cs->hw_mode; /* Save original settings */
 455         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 456         /* mask out bits we are going to set */
 457         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 458                          | SPMODE_REV | SPMODE_LOOP);
 459
 460         if (spi->mode & SPI_CPHA)
 461                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 462         if (spi->mode & SPI_CPOL)
 463                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 464         if (!(spi->mode & SPI_LSB_FIRST))
 465                 cs->hw_mode |= SPMODE_REV;
 466         if (spi->mode & SPI_LOOP)
 467                 cs->hw_mode |= SPMODE_LOOP;
 468
 469         retval = fsl_spi_setup_transfer(spi, NULL);
 470         if (retval < 0) {
 471                 cs->hw_mode = hw_mode; /* Restore settings */
 472                 return retval;
 473         }
 474
 475         if (mpc8xxx_spi->type == TYPE_GRLIB) {
 476                 if (gpio_is_valid(spi->cs_gpio)) {
 477                         int desel;
 478
 479                         retval = gpio_request(spi->cs_gpio,
 480                                               dev_name(&spi->dev));
 481                         if (retval)
 482                                 return retval;
 483
 484                         desel = !(spi->mode & SPI_CS_HIGH);
 485                         retval = gpio_direction_output(spi->cs_gpio, desel);
 486                         if (retval) {
 487                                 gpio_free(spi->cs_gpio);
 488                                 return retval;
 489                         }
 490                 } else if (spi->cs_gpio != -ENOENT) {
 491                         if (spi->cs_gpio < 0)
 492                                 return spi->cs_gpio;
 493                         return -EINVAL;
 494                 }
 495                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
 496                  * indicates to use native chipselect if present, or allow for
 497                  * an always selected chip
 498                  */
 499         }
 500
 501         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 502         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 503
 504         return 0;
 505 }
 506
 507 static void fsl_spi_cleanup(struct spi_device *spi)
 508 {
 509         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 510         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 511
 512         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
 513                 gpio_free(spi->cs_gpio);
 514
 515         kfree(cs);
 516         spi_set_ctldata(spi, NULL);
 517 }
 518
 519 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 520 {
 521         struct fsl_spi_reg *reg_base = mspi->reg_base;
 522
 523         /* We need handle RX first */
 524         if (events & SPIE_NE) {
 525                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 526
 527                 if (mspi->rx)
 528                         mspi->get_rx(rx_data, mspi);
 529         }
 530
 531         if ((events & SPIE_NF) == 0)
 532                 /* spin until TX is done */
 533                 while (((events =
 534                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 535                                                 SPIE_NF) == 0)
 536                         cpu_relax();
 537
 538         /* Clear the events */
 539         mpc8xxx_spi_write_reg(&reg_base->event, events);
 540
 541         mspi->count -= 1;
 542         if (mspi->count) {
 543                 u32 word = mspi->get_tx(mspi);
 544
 545                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 546         } else {
 547                 complete(&mspi->done);
 548         }
 549 }
 550
 551 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 552 {
 553         struct mpc8xxx_spi *mspi = context_data;
 554         irqreturn_t ret = IRQ_NONE;
 555         u32 events;
 556         struct fsl_spi_reg *reg_base = mspi->reg_base;
 557
 558         /* Get interrupt events(tx/rx) */
 559         events = mpc8xxx_spi_read_reg(&reg_base->event);
 560         if (events)
 561                 ret = IRQ_HANDLED;
 562
 563         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 564
 565         if (mspi->flags & SPI_CPM_MODE)
 566                 fsl_spi_cpm_irq(mspi, events);
 567         else
 568                 fsl_spi_cpu_irq(mspi, events);
 569
 570         return ret;
 571 }
 572
 573 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 574 {
 575         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 576         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 577         u32 slvsel;
 578         u16 cs = spi->chip_select;
 579
 580         if (gpio_is_valid(spi->cs_gpio)) {
 581                 gpio_set_value(spi->cs_gpio, on);
 582         } else if (cs < mpc8xxx_spi->native_chipselects) {
 583                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 584                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 585                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 586         }
 587 }
 588
 589 static void fsl_spi_grlib_probe(struct device *dev)
 590 {
 591         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 592         struct spi_master *master = dev_get_drvdata(dev);
 593         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 594         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 595         int mbits;
 596         u32 capabilities;
 597
 598         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 599
 600         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 601         mbits = SPCAP_MAXWLEN(capabilities);
 602         if (mbits)
 603                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 604
 605         mpc8xxx_spi->native_chipselects = 0;
 606         if (SPCAP_SSEN(capabilities)) {
 607                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 608                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 609         }
 610         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 611         pdata->cs_control = fsl_spi_grlib_cs_control;
 612 }
 613
 614 static struct spi_master * fsl_spi_probe(struct device *dev,
 615                 struct resource *mem, unsigned int irq)
 616 {
 617         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 618         struct spi_master *master;
 619         struct mpc8xxx_spi *mpc8xxx_spi;
 620         struct fsl_spi_reg *reg_base;
 621         u32 regval;
 622         int ret = 0;
 623
 624         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 625         if (master == NULL) {
 626                 ret = -ENOMEM;
 627                 goto err;
 628         }
 629
 630         dev_set_drvdata(dev, master);
 631
 632         mpc8xxx_spi_probe(dev, mem, irq);
 633
 634         master->setup = fsl_spi_setup;
 635         master->cleanup = fsl_spi_cleanup;
 636         master->transfer_one_message = fsl_spi_do_one_msg;
 637
 638         mpc8xxx_spi = spi_master_get_devdata(master);
 639         mpc8xxx_spi->max_bits_per_word = 32;
 640         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 641
 642         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 643         if (ret)
 644                 goto err_cpm_init;
 645
 646         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 647         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 648                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 649                 goto err_probe;
 650         }
 651
 652         if (mpc8xxx_spi->type == TYPE_GRLIB)
 653                 fsl_spi_grlib_probe(dev);
 654
 655         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 656                 master->bits_per_word_mask =
 657                         (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));
 658         else
 659                 master->bits_per_word_mask =
 660                         (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));
 661
 662         master->bits_per_word_mask &=
 663                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 664
 665         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 666                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 667
 668         if (mpc8xxx_spi->set_shifts)
 669                 /* 8 bits per word and MSB first */
 670                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 671                                         &mpc8xxx_spi->tx_shift, 8, 1);
 672
 673         /* Register for SPI Interrupt */
 674         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 675                                0, "fsl_spi", mpc8xxx_spi);
 676
 677         if (ret != 0)
 678                 goto err_probe;
 679
 680         reg_base = mpc8xxx_spi->reg_base;
 681
 682         /* SPI controller initializations */
 683         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 684         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 685         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 686         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 687
 688         /* Enable SPI interface */
 689         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 690         if (mpc8xxx_spi->max_bits_per_word < 8) {
 691                 regval &= ~SPMODE_LEN(0xF);
 692                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 693         }
 694         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 695                 regval |= SPMODE_OP;
 696
 697         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 698
 699         ret = devm_spi_register_master(dev, master);
 700         if (ret < 0)
 701                 goto err_probe;
 702
 703         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 704                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 705
 706         return master;
 707
 708 err_probe:
 709         fsl_spi_cpm_free(mpc8xxx_spi);
 710 err_cpm_init:
 711         spi_master_put(master);
 712 err:
 713         return ERR_PTR(ret);
 714 }
 715
 716 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 717 {
 718         struct device *dev = spi->dev.parent->parent;
 719         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 720         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 721         u16 cs = spi->chip_select;
 722         int gpio = pinfo->gpios[cs];
 723         bool alow = pinfo->alow_flags[cs];
 724
 725         gpio_set_value(gpio, on ^ alow);
 726 }
 727
 728 static int of_fsl_spi_get_chipselects(struct device *dev)
 729 {
 730         struct device_node *np = dev->of_node;
 731         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 732         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 733         int ngpios;
 734         int i = 0;
 735         int ret;
 736
 737         ngpios = of_gpio_count(np);
 738         if (ngpios <= 0) {
 739                 /*
 740                  * SPI w/o chip-select line. One SPI device is still permitted
 741                  * though.
 742                  */
 743                 pdata->max_chipselect = 1;
 744                 return 0;
 745         }
 746
 747         pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios),
 748                                      GFP_KERNEL);
 749         if (!pinfo->gpios)
 750                 return -ENOMEM;
 751         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 752
 753         pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags),
 754                                     GFP_KERNEL);
 755         if (!pinfo->alow_flags) {
 756                 ret = -ENOMEM;
 757                 goto err_alloc_flags;
 758         }
 759
 760         for (; i < ngpios; i++) {
 761                 int gpio;
 762                 enum of_gpio_flags flags;
 763
 764                 gpio = of_get_gpio_flags(np, i, &flags);
 765                 if (!gpio_is_valid(gpio)) {
 766                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 767                         ret = gpio;
 768                         goto err_loop;
 769                 }
 770
 771                 ret = gpio_request(gpio, dev_name(dev));
 772                 if (ret) {
 773                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 774                         goto err_loop;
 775                 }
 776
 777                 pinfo->gpios[i] = gpio;
 778                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 779
 780                 ret = gpio_direction_output(pinfo->gpios[i],
 781                                             pinfo->alow_flags[i]);
 782                 if (ret) {
 783                         dev_err(dev,
 784                                 "can't set output direction for gpio #%d: %d\n",
 785                                 i, ret);
 786                         goto err_loop;
 787                 }
 788         }
 789
 790         pdata->max_chipselect = ngpios;
 791         pdata->cs_control = fsl_spi_cs_control;
 792
 793         return 0;
 794
 795 err_loop:
 796         while (i >= 0) {
 797                 if (gpio_is_valid(pinfo->gpios[i]))
 798                         gpio_free(pinfo->gpios[i]);
 799                 i--;
 800         }
 801
 802         kfree(pinfo->alow_flags);
 803         pinfo->alow_flags = NULL;
 804 err_alloc_flags:
 805         kfree(pinfo->gpios);
 806         pinfo->gpios = NULL;
 807         return ret;
 808 }
 809
 810 static int of_fsl_spi_free_chipselects(struct device *dev)
 811 {
 812         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 813         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 814         int i;
 815
 816         if (!pinfo->gpios)
 817                 return 0;
 818
 819         for (i = 0; i < pdata->max_chipselect; i++) {
 820                 if (gpio_is_valid(pinfo->gpios[i]))
 821                         gpio_free(pinfo->gpios[i]);
 822         }
 823
 824         kfree(pinfo->gpios);
 825         kfree(pinfo->alow_flags);
 826         return 0;
 827 }
 828
 829 static int of_fsl_spi_probe(struct platform_device *ofdev)
 830 {
 831         struct device *dev = &ofdev->dev;
 832         struct device_node *np = ofdev->dev.of_node;
 833         struct spi_master *master;
 834         struct resource mem;
 835         int irq = 0, type;
 836         int ret = -ENOMEM;
 837
 838         ret = of_mpc8xxx_spi_probe(ofdev);
 839         if (ret)
 840                 return ret;
 841
 842         type = fsl_spi_get_type(&ofdev->dev);
 843         if (type == TYPE_FSL) {
 844                 ret = of_fsl_spi_get_chipselects(dev);
 845                 if (ret)
 846                         goto err;
 847         }
 848
 849         ret = of_address_to_resource(np, 0, &mem);
 850         if (ret)
 851                 goto err;
 852
 853         irq = platform_get_irq(ofdev, 0);
 854         if (irq < 0) {
 855                 ret = irq;
 856                 goto err;
 857         }
 858
 859         master = fsl_spi_probe(dev, &mem, irq);
 860         if (IS_ERR(master)) {
 861                 ret = PTR_ERR(master);
 862                 goto err;
 863         }
 864
 865         return 0;
 866
 867 err:
 868         if (type == TYPE_FSL)
 869                 of_fsl_spi_free_chipselects(dev);
 870         return ret;
 871 }
 872
 873 static int of_fsl_spi_remove(struct platform_device *ofdev)
 874 {
 875         struct spi_master *master = platform_get_drvdata(ofdev);
 876         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 877
 878         fsl_spi_cpm_free(mpc8xxx_spi);
 879         if (mpc8xxx_spi->type == TYPE_FSL)
 880                 of_fsl_spi_free_chipselects(&ofdev->dev);
 881         return 0;
 882 }
 883
 884 static struct platform_driver of_fsl_spi_driver = {
 885         .driver = {
 886                 .name = "fsl_spi",
 887                 .of_match_table = of_fsl_spi_match,
 888         },
 889         .probe          = of_fsl_spi_probe,
 890         .remove         = of_fsl_spi_remove,
 891 };
 892
 893 #ifdef CONFIG_MPC832x_RDB
 894 /*
 895  * XXX XXX XXX
 896  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 897  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 898  * tree can work with OpenFirmware driver. But for now we support old trees
 899  * as well.
 900  */
 901 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 902 {
 903         struct resource *mem;
 904         int irq;
 905         struct spi_master *master;
 906
 907         if (!dev_get_platdata(&pdev->dev))
 908                 return -EINVAL;
 909
 910         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 911         if (!mem)
 912                 return -EINVAL;
 913
 914         irq = platform_get_irq(pdev, 0);
 915         if (irq <= 0)
 916                 return -EINVAL;
 917
 918         master = fsl_spi_probe(&pdev->dev, mem, irq);
 919         return PTR_ERR_OR_ZERO(master);
 920 }
 921
 922 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 923 {
 924         struct spi_master *master = platform_get_drvdata(pdev);
 925         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 926
 927         fsl_spi_cpm_free(mpc8xxx_spi);
 928
 929         return 0;
 930 }
 931
 932 MODULE_ALIAS("platform:mpc8xxx_spi");
 933 static struct platform_driver mpc8xxx_spi_driver = {
 934         .probe = plat_mpc8xxx_spi_probe,
 935         .remove = plat_mpc8xxx_spi_remove,
 936         .driver = {
 937                 .name = "mpc8xxx_spi",
 938         },
 939 };
 940
 941 static bool legacy_driver_failed;
 942
 943 static void __init legacy_driver_register(void)
 944 {
 945         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 946 }
 947
 948 static void __exit legacy_driver_unregister(void)
 949 {
 950         if (legacy_driver_failed)
 951                 return;
 952         platform_driver_unregister(&mpc8xxx_spi_driver);
 953 }
 954 #else
 955 static void __init legacy_driver_register(void) {}
 956 static void __exit legacy_driver_unregister(void) {}
 957 #endif /* CONFIG_MPC832x_RDB */
 958
 959 static int __init fsl_spi_init(void)
 960 {
 961         legacy_driver_register();
 962         return platform_driver_register(&of_fsl_spi_driver);
 963 }
 964 module_init(fsl_spi_init);
 965
 966 static void __exit fsl_spi_exit(void)
 967 {
 968         platform_driver_unregister(&of_fsl_spi_driver);
 969         legacy_driver_unregister();
 970 }
 971 module_exit(fsl_spi_exit);
 972
 973 MODULE_AUTHOR("Kumar Gala");
 974 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 975 MODULE_LICENSE("GPL");