drivers/spi/spi-fsl-spi.c

   1 /*
   2  * Freescale SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * GRLIB support:
  14  * Copyright (c) 2012 Aeroflex Gaisler AB.
  15  * Author: Andreas Larsson <andreas@gaisler.com>
  16  *
  17  * This program is free software; you can redistribute  it and/or modify it
  18  * under  the terms of  the GNU General  Public License as published by the
  19  * Free Software Foundation;  either version 2 of the  License, or (at your
  20  * option) any later version.
  21  */
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/fsl_devices.h>
  25 #include <linux/gpio.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/kernel.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mutex.h>
  32 #include <linux/of.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/spi/spi.h>
  39 #include <linux/spi/spi_bitbang.h>
  40 #include <linux/types.h>
  41
  42 #include "spi-fsl-lib.h"
  43 #include "spi-fsl-cpm.h"
  44 #include "spi-fsl-spi.h"
  45
  46 #define TYPE_FSL        0
  47 #define TYPE_GRLIB      1
  48
  49 struct fsl_spi_match_data {
  50         int type;
  51 };
  52
  53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  54         .type = TYPE_FSL,
  55 };
  56
  57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  58         .type = TYPE_GRLIB,
  59 };
  60
  61 static const struct of_device_id of_fsl_spi_match[] = {
  62         {
  63                 .compatible = "fsl,spi",
  64                 .data = &of_fsl_spi_fsl_config,
  65         },
  66         {
  67                 .compatible = "aeroflexgaisler,spictrl",
  68                 .data = &of_fsl_spi_grlib_config,
  69         },
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  73
  74 static int fsl_spi_get_type(struct device *dev)
  75 {
  76         const struct of_device_id *match;
  77
  78         if (dev->of_node) {
  79                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  80                 if (match && match->data)
  81                         return ((struct fsl_spi_match_data *)match->data)->type;
  82         }
  83         return TYPE_FSL;
  84 }
  85
  86 static void fsl_spi_change_mode(struct spi_device *spi)
  87 {
  88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  90         struct fsl_spi_reg *reg_base = mspi->reg_base;
  91         __be32 __iomem *mode = &reg_base->mode;
  92         unsigned long flags;
  93
  94         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  95                 return;
  96
  97         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  98         local_irq_save(flags);
  99
 100         /* Turn off SPI unit prior changing mode */
 101         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 102
 103         /* When in CPM mode, we need to reinit tx and rx. */
 104         if (mspi->flags & SPI_CPM_MODE) {
 105                 fsl_spi_cpm_reinit_txrx(mspi);
 106         }
 107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 108         local_irq_restore(flags);
 109 }
 110
 111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 112 {
 113         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 114         struct fsl_spi_platform_data *pdata;
 115         bool pol = spi->mode & SPI_CS_HIGH;
 116         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 117
 118         pdata = spi->dev.parent->parent->platform_data;
 119
 120         if (value == BITBANG_CS_INACTIVE) {
 121                 if (pdata->cs_control)
 122                         pdata->cs_control(spi, !pol);
 123         }
 124
 125         if (value == BITBANG_CS_ACTIVE) {
 126                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 127                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 128                 mpc8xxx_spi->get_rx = cs->get_rx;
 129                 mpc8xxx_spi->get_tx = cs->get_tx;
 130
 131                 fsl_spi_change_mode(spi);
 132
 133                 if (pdata->cs_control)
 134                         pdata->cs_control(spi, pol);
 135         }
 136 }
 137
 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 139                                       int bits_per_word, int msb_first)
 140 {
 141         *rx_shift = 0;
 142         *tx_shift = 0;
 143         if (msb_first) {
 144                 if (bits_per_word <= 8) {
 145                         *rx_shift = 16;
 146                         *tx_shift = 24;
 147                 } else if (bits_per_word <= 16) {
 148                         *rx_shift = 16;
 149                         *tx_shift = 16;
 150                 }
 151         } else {
 152                 if (bits_per_word <= 8)
 153                         *rx_shift = 8;
 154         }
 155 }
 156
 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 158                                      int bits_per_word, int msb_first)
 159 {
 160         *rx_shift = 0;
 161         *tx_shift = 0;
 162         if (bits_per_word <= 16) {
 163                 if (msb_first) {
 164                         *rx_shift = 16; /* LSB in bit 16 */
 165                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 166                 } else {
 167                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 168                 }
 169         }
 170 }
 171
 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 173                                 struct spi_device *spi,
 174                                 struct mpc8xxx_spi *mpc8xxx_spi,
 175                                 int bits_per_word)
 176 {
 177         cs->rx_shift = 0;
 178         cs->tx_shift = 0;
 179         if (bits_per_word <= 8) {
 180                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 181                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 182         } else if (bits_per_word <= 16) {
 183                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 184                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 185         } else if (bits_per_word <= 32) {
 186                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 187                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 188         } else
 189                 return -EINVAL;
 190
 191         if (mpc8xxx_spi->set_shifts)
 192                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 193                                         bits_per_word,
 194                                         !(spi->mode & SPI_LSB_FIRST));
 195
 196         mpc8xxx_spi->rx_shift = cs->rx_shift;
 197         mpc8xxx_spi->tx_shift = cs->tx_shift;
 198         mpc8xxx_spi->get_rx = cs->get_rx;
 199         mpc8xxx_spi->get_tx = cs->get_tx;
 200
 201         return bits_per_word;
 202 }
 203
 204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 205                                 struct spi_device *spi,
 206                                 int bits_per_word)
 207 {
 208         /* QE uses Little Endian for words > 8
 209          * so transform all words > 8 into 8 bits
 210          * Unfortnatly that doesn't work for LSB so
 211          * reject these for now */
 212         /* Note: 32 bits word, LSB works iff
 213          * tfcr/rfcr is set to CPMFCR_GBL */
 214         if (spi->mode & SPI_LSB_FIRST &&
 215             bits_per_word > 8)
 216                 return -EINVAL;
 217         if (bits_per_word > 8)
 218                 return 8; /* pretend its 8 bits */
 219         return bits_per_word;
 220 }
 221
 222 static int fsl_spi_setup_transfer(struct spi_device *spi,
 223                                         struct spi_transfer *t)
 224 {
 225         struct mpc8xxx_spi *mpc8xxx_spi;
 226         int bits_per_word = 0;
 227         u8 pm;
 228         u32 hz = 0;
 229         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 230
 231         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 232
 233         if (t) {
 234                 bits_per_word = t->bits_per_word;
 235                 hz = t->speed_hz;
 236         }
 237
 238         /* spi_transfer level calls that work per-word */
 239         if (!bits_per_word)
 240                 bits_per_word = spi->bits_per_word;
 241
 242         if (!hz)
 243                 hz = spi->max_speed_hz;
 244
 245         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 246                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 247                                                            mpc8xxx_spi,
 248                                                            bits_per_word);
 249         else if (mpc8xxx_spi->flags & SPI_QE)
 250                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 251                                                           bits_per_word);
 252
 253         if (bits_per_word < 0)
 254                 return bits_per_word;
 255
 256         if (bits_per_word == 32)
 257                 bits_per_word = 0;
 258         else
 259                 bits_per_word = bits_per_word - 1;
 260
 261         /* mask out bits we are going to set */
 262         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 263                                   | SPMODE_PM(0xF));
 264
 265         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 266
 267         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 268                 cs->hw_mode |= SPMODE_DIV16;
 269                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 270
 271                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 272                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 273                           hz, mpc8xxx_spi->spibrg / 1024);
 274                 if (pm > 16)
 275                         pm = 16;
 276         } else {
 277                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 278         }
 279         if (pm)
 280                 pm--;
 281
 282         cs->hw_mode |= SPMODE_PM(pm);
 283
 284         fsl_spi_change_mode(spi);
 285         return 0;
 286 }
 287
 288 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 289                                 struct spi_transfer *t, unsigned int len)
 290 {
 291         u32 word;
 292         struct fsl_spi_reg *reg_base = mspi->reg_base;
 293
 294         mspi->count = len;
 295
 296         /* enable rx ints */
 297         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 298
 299         /* transmit word */
 300         word = mspi->get_tx(mspi);
 301         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 302
 303         return 0;
 304 }
 305
 306 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 307                             bool is_dma_mapped)
 308 {
 309         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 310         struct fsl_spi_reg *reg_base;
 311         unsigned int len = t->len;
 312         u8 bits_per_word;
 313         int ret;
 314
 315         reg_base = mpc8xxx_spi->reg_base;
 316         bits_per_word = spi->bits_per_word;
 317         if (t->bits_per_word)
 318                 bits_per_word = t->bits_per_word;
 319
 320         if (bits_per_word > 8) {
 321                 /* invalid length? */
 322                 if (len & 1)
 323                         return -EINVAL;
 324                 len /= 2;
 325         }
 326         if (bits_per_word > 16) {
 327                 /* invalid length? */
 328                 if (len & 1)
 329                         return -EINVAL;
 330                 len /= 2;
 331         }
 332
 333         mpc8xxx_spi->tx = t->tx_buf;
 334         mpc8xxx_spi->rx = t->rx_buf;
 335
 336         reinit_completion(&mpc8xxx_spi->done);
 337
 338         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 339                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 340         else
 341                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 342         if (ret)
 343                 return ret;
 344
 345         wait_for_completion(&mpc8xxx_spi->done);
 346
 347         /* disable rx ints */
 348         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 349
 350         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 351                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 352
 353         return mpc8xxx_spi->count;
 354 }
 355
 356 static int fsl_spi_do_one_msg(struct spi_master *master,
 357                               struct spi_message *m)
 358 {
 359         struct spi_device *spi = m->spi;
 360         struct spi_transfer *t, *first;
 361         unsigned int cs_change;
 362         const int nsecs = 50;
 363         int status;
 364
 365         /* Don't allow changes if CS is active */
 366         first = list_first_entry(&m->transfers, struct spi_transfer,
 367                         transfer_list);
 368         list_for_each_entry(t, &m->transfers, transfer_list) {
 369                 if ((first->bits_per_word != t->bits_per_word) ||
 370                         (first->speed_hz != t->speed_hz)) {
 371                         dev_err(&spi->dev,
 372                                 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
 373                         return -EINVAL;
 374                 }
 375         }
 376
 377         cs_change = 1;
 378         status = -EINVAL;
 379         list_for_each_entry(t, &m->transfers, transfer_list) {
 380                 if (t->bits_per_word || t->speed_hz) {
 381                         if (cs_change)
 382                                 status = fsl_spi_setup_transfer(spi, t);
 383                         if (status < 0)
 384                                 break;
 385                 }
 386
 387                 if (cs_change) {
 388                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 389                         ndelay(nsecs);
 390                 }
 391                 cs_change = t->cs_change;
 392                 if (t->len)
 393                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 394                 if (status) {
 395                         status = -EMSGSIZE;
 396                         break;
 397                 }
 398                 m->actual_length += t->len;
 399
 400                 if (t->delay_usecs)
 401                         udelay(t->delay_usecs);
 402
 403                 if (cs_change) {
 404                         ndelay(nsecs);
 405                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 406                         ndelay(nsecs);
 407                 }
 408         }
 409
 410         m->status = status;
 411
 412         if (status || !cs_change) {
 413                 ndelay(nsecs);
 414                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 415         }
 416
 417         fsl_spi_setup_transfer(spi, NULL);
 418         spi_finalize_current_message(master);
 419         return 0;
 420 }
 421
 422 static int fsl_spi_setup(struct spi_device *spi)
 423 {
 424         struct mpc8xxx_spi *mpc8xxx_spi;
 425         struct fsl_spi_reg *reg_base;
 426         int retval;
 427         u32 hw_mode;
 428         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 429
 430         if (!spi->max_speed_hz)
 431                 return -EINVAL;
 432
 433         if (!cs) {
 434                 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 435                 if (!cs)
 436                         return -ENOMEM;
 437                 spi_set_ctldata(spi, cs);
 438         }
 439         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 440
 441         reg_base = mpc8xxx_spi->reg_base;
 442
 443         hw_mode = cs->hw_mode; /* Save original settings */
 444         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 445         /* mask out bits we are going to set */
 446         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 447                          | SPMODE_REV | SPMODE_LOOP);
 448
 449         if (spi->mode & SPI_CPHA)
 450                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 451         if (spi->mode & SPI_CPOL)
 452                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 453         if (!(spi->mode & SPI_LSB_FIRST))
 454                 cs->hw_mode |= SPMODE_REV;
 455         if (spi->mode & SPI_LOOP)
 456                 cs->hw_mode |= SPMODE_LOOP;
 457
 458         retval = fsl_spi_setup_transfer(spi, NULL);
 459         if (retval < 0) {
 460                 cs->hw_mode = hw_mode; /* Restore settings */
 461                 return retval;
 462         }
 463
 464         if (mpc8xxx_spi->type == TYPE_GRLIB) {
 465                 if (gpio_is_valid(spi->cs_gpio)) {
 466                         int desel;
 467
 468                         retval = gpio_request(spi->cs_gpio,
 469                                               dev_name(&spi->dev));
 470                         if (retval)
 471                                 return retval;
 472
 473                         desel = !(spi->mode & SPI_CS_HIGH);
 474                         retval = gpio_direction_output(spi->cs_gpio, desel);
 475                         if (retval) {
 476                                 gpio_free(spi->cs_gpio);
 477                                 return retval;
 478                         }
 479                 } else if (spi->cs_gpio != -ENOENT) {
 480                         if (spi->cs_gpio < 0)
 481                                 return spi->cs_gpio;
 482                         return -EINVAL;
 483                 }
 484                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
 485                  * indicates to use native chipselect if present, or allow for
 486                  * an always selected chip
 487                  */
 488         }
 489
 490         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 491         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 492
 493         return 0;
 494 }
 495
 496 static void fsl_spi_cleanup(struct spi_device *spi)
 497 {
 498         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 499         struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
 500
 501         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
 502                 gpio_free(spi->cs_gpio);
 503
 504         kfree(cs);
 505         spi_set_ctldata(spi, NULL);
 506 }
 507
 508 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 509 {
 510         struct fsl_spi_reg *reg_base = mspi->reg_base;
 511
 512         /* We need handle RX first */
 513         if (events & SPIE_NE) {
 514                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 515
 516                 if (mspi->rx)
 517                         mspi->get_rx(rx_data, mspi);
 518         }
 519
 520         if ((events & SPIE_NF) == 0)
 521                 /* spin until TX is done */
 522                 while (((events =
 523                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 524                                                 SPIE_NF) == 0)
 525                         cpu_relax();
 526
 527         /* Clear the events */
 528         mpc8xxx_spi_write_reg(&reg_base->event, events);
 529
 530         mspi->count -= 1;
 531         if (mspi->count) {
 532                 u32 word = mspi->get_tx(mspi);
 533
 534                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 535         } else {
 536                 complete(&mspi->done);
 537         }
 538 }
 539
 540 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 541 {
 542         struct mpc8xxx_spi *mspi = context_data;
 543         irqreturn_t ret = IRQ_NONE;
 544         u32 events;
 545         struct fsl_spi_reg *reg_base = mspi->reg_base;
 546
 547         /* Get interrupt events(tx/rx) */
 548         events = mpc8xxx_spi_read_reg(&reg_base->event);
 549         if (events)
 550                 ret = IRQ_HANDLED;
 551
 552         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 553
 554         if (mspi->flags & SPI_CPM_MODE)
 555                 fsl_spi_cpm_irq(mspi, events);
 556         else
 557                 fsl_spi_cpu_irq(mspi, events);
 558
 559         return ret;
 560 }
 561
 562 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 563 {
 564         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 565         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 566         u32 slvsel;
 567         u16 cs = spi->chip_select;
 568
 569         if (gpio_is_valid(spi->cs_gpio)) {
 570                 gpio_set_value(spi->cs_gpio, on);
 571         } else if (cs < mpc8xxx_spi->native_chipselects) {
 572                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 573                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 574                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 575         }
 576 }
 577
 578 static void fsl_spi_grlib_probe(struct device *dev)
 579 {
 580         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 581         struct spi_master *master = dev_get_drvdata(dev);
 582         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 583         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 584         int mbits;
 585         u32 capabilities;
 586
 587         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 588
 589         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 590         mbits = SPCAP_MAXWLEN(capabilities);
 591         if (mbits)
 592                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 593
 594         mpc8xxx_spi->native_chipselects = 0;
 595         if (SPCAP_SSEN(capabilities)) {
 596                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 597                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 598         }
 599         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 600         pdata->cs_control = fsl_spi_grlib_cs_control;
 601 }
 602
 603 static struct spi_master * fsl_spi_probe(struct device *dev,
 604                 struct resource *mem, unsigned int irq)
 605 {
 606         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 607         struct spi_master *master;
 608         struct mpc8xxx_spi *mpc8xxx_spi;
 609         struct fsl_spi_reg *reg_base;
 610         u32 regval;
 611         int ret = 0;
 612
 613         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 614         if (master == NULL) {
 615                 ret = -ENOMEM;
 616                 goto err;
 617         }
 618
 619         dev_set_drvdata(dev, master);
 620
 621         mpc8xxx_spi_probe(dev, mem, irq);
 622
 623         master->setup = fsl_spi_setup;
 624         master->cleanup = fsl_spi_cleanup;
 625         master->transfer_one_message = fsl_spi_do_one_msg;
 626
 627         mpc8xxx_spi = spi_master_get_devdata(master);
 628         mpc8xxx_spi->max_bits_per_word = 32;
 629         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 630
 631         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 632         if (ret)
 633                 goto err_cpm_init;
 634
 635         mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
 636         if (IS_ERR(mpc8xxx_spi->reg_base)) {
 637                 ret = PTR_ERR(mpc8xxx_spi->reg_base);
 638                 goto err_probe;
 639         }
 640
 641         if (mpc8xxx_spi->type == TYPE_GRLIB)
 642                 fsl_spi_grlib_probe(dev);
 643
 644         master->bits_per_word_mask =
 645                 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
 646                 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
 647
 648         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 649                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 650
 651         if (mpc8xxx_spi->set_shifts)
 652                 /* 8 bits per word and MSB first */
 653                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 654                                         &mpc8xxx_spi->tx_shift, 8, 1);
 655
 656         /* Register for SPI Interrupt */
 657         ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
 658                                0, "fsl_spi", mpc8xxx_spi);
 659
 660         if (ret != 0)
 661                 goto err_probe;
 662
 663         reg_base = mpc8xxx_spi->reg_base;
 664
 665         /* SPI controller initializations */
 666         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 667         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 668         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 669         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 670
 671         /* Enable SPI interface */
 672         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 673         if (mpc8xxx_spi->max_bits_per_word < 8) {
 674                 regval &= ~SPMODE_LEN(0xF);
 675                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 676         }
 677         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 678                 regval |= SPMODE_OP;
 679
 680         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 681
 682         ret = devm_spi_register_master(dev, master);
 683         if (ret < 0)
 684                 goto err_probe;
 685
 686         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 687                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 688
 689         return master;
 690
 691 err_probe:
 692         fsl_spi_cpm_free(mpc8xxx_spi);
 693 err_cpm_init:
 694         spi_master_put(master);
 695 err:
 696         return ERR_PTR(ret);
 697 }
 698
 699 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 700 {
 701         struct device *dev = spi->dev.parent->parent;
 702         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 703         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 704         u16 cs = spi->chip_select;
 705         int gpio = pinfo->gpios[cs];
 706         bool alow = pinfo->alow_flags[cs];
 707
 708         gpio_set_value(gpio, on ^ alow);
 709 }
 710
 711 static int of_fsl_spi_get_chipselects(struct device *dev)
 712 {
 713         struct device_node *np = dev->of_node;
 714         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 715         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 716         int ngpios;
 717         int i = 0;
 718         int ret;
 719
 720         ngpios = of_gpio_count(np);
 721         if (ngpios <= 0) {
 722                 /*
 723                  * SPI w/o chip-select line. One SPI device is still permitted
 724                  * though.
 725                  */
 726                 pdata->max_chipselect = 1;
 727                 return 0;
 728         }
 729
 730         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
 731         if (!pinfo->gpios)
 732                 return -ENOMEM;
 733         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 734
 735         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
 736                                     GFP_KERNEL);
 737         if (!pinfo->alow_flags) {
 738                 ret = -ENOMEM;
 739                 goto err_alloc_flags;
 740         }
 741
 742         for (; i < ngpios; i++) {
 743                 int gpio;
 744                 enum of_gpio_flags flags;
 745
 746                 gpio = of_get_gpio_flags(np, i, &flags);
 747                 if (!gpio_is_valid(gpio)) {
 748                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 749                         ret = gpio;
 750                         goto err_loop;
 751                 }
 752
 753                 ret = gpio_request(gpio, dev_name(dev));
 754                 if (ret) {
 755                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 756                         goto err_loop;
 757                 }
 758
 759                 pinfo->gpios[i] = gpio;
 760                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 761
 762                 ret = gpio_direction_output(pinfo->gpios[i],
 763                                             pinfo->alow_flags[i]);
 764                 if (ret) {
 765                         dev_err(dev, "can't set output direction for gpio "
 766                                 "#%d: %d\n", i, ret);
 767                         goto err_loop;
 768                 }
 769         }
 770
 771         pdata->max_chipselect = ngpios;
 772         pdata->cs_control = fsl_spi_cs_control;
 773
 774         return 0;
 775
 776 err_loop:
 777         while (i >= 0) {
 778                 if (gpio_is_valid(pinfo->gpios[i]))
 779                         gpio_free(pinfo->gpios[i]);
 780                 i--;
 781         }
 782
 783         kfree(pinfo->alow_flags);
 784         pinfo->alow_flags = NULL;
 785 err_alloc_flags:
 786         kfree(pinfo->gpios);
 787         pinfo->gpios = NULL;
 788         return ret;
 789 }
 790
 791 static int of_fsl_spi_free_chipselects(struct device *dev)
 792 {
 793         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 794         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 795         int i;
 796
 797         if (!pinfo->gpios)
 798                 return 0;
 799
 800         for (i = 0; i < pdata->max_chipselect; i++) {
 801                 if (gpio_is_valid(pinfo->gpios[i]))
 802                         gpio_free(pinfo->gpios[i]);
 803         }
 804
 805         kfree(pinfo->gpios);
 806         kfree(pinfo->alow_flags);
 807         return 0;
 808 }
 809
 810 static int of_fsl_spi_probe(struct platform_device *ofdev)
 811 {
 812         struct device *dev = &ofdev->dev;
 813         struct device_node *np = ofdev->dev.of_node;
 814         struct spi_master *master;
 815         struct resource mem;
 816         int irq, type;
 817         int ret = -ENOMEM;
 818
 819         ret = of_mpc8xxx_spi_probe(ofdev);
 820         if (ret)
 821                 return ret;
 822
 823         type = fsl_spi_get_type(&ofdev->dev);
 824         if (type == TYPE_FSL) {
 825                 ret = of_fsl_spi_get_chipselects(dev);
 826                 if (ret)
 827                         goto err;
 828         }
 829
 830         ret = of_address_to_resource(np, 0, &mem);
 831         if (ret)
 832                 goto err;
 833
 834         irq = irq_of_parse_and_map(np, 0);
 835         if (!irq) {
 836                 ret = -EINVAL;
 837                 goto err;
 838         }
 839
 840         master = fsl_spi_probe(dev, &mem, irq);
 841         if (IS_ERR(master)) {
 842                 ret = PTR_ERR(master);
 843                 goto err;
 844         }
 845
 846         return 0;
 847
 848 err:
 849         if (type == TYPE_FSL)
 850                 of_fsl_spi_free_chipselects(dev);
 851         return ret;
 852 }
 853
 854 static int of_fsl_spi_remove(struct platform_device *ofdev)
 855 {
 856         struct spi_master *master = platform_get_drvdata(ofdev);
 857         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 858
 859         fsl_spi_cpm_free(mpc8xxx_spi);
 860         if (mpc8xxx_spi->type == TYPE_FSL)
 861                 of_fsl_spi_free_chipselects(&ofdev->dev);
 862         return 0;
 863 }
 864
 865 static struct platform_driver of_fsl_spi_driver = {
 866         .driver = {
 867                 .name = "fsl_spi",
 868                 .of_match_table = of_fsl_spi_match,
 869         },
 870         .probe          = of_fsl_spi_probe,
 871         .remove         = of_fsl_spi_remove,
 872 };
 873
 874 #ifdef CONFIG_MPC832x_RDB
 875 /*
 876  * XXX XXX XXX
 877  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 878  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 879  * tree can work with OpenFirmware driver. But for now we support old trees
 880  * as well.
 881  */
 882 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 883 {
 884         struct resource *mem;
 885         int irq;
 886         struct spi_master *master;
 887
 888         if (!dev_get_platdata(&pdev->dev))
 889                 return -EINVAL;
 890
 891         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 892         if (!mem)
 893                 return -EINVAL;
 894
 895         irq = platform_get_irq(pdev, 0);
 896         if (irq <= 0)
 897                 return -EINVAL;
 898
 899         master = fsl_spi_probe(&pdev->dev, mem, irq);
 900         return PTR_ERR_OR_ZERO(master);
 901 }
 902
 903 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 904 {
 905         struct spi_master *master = platform_get_drvdata(pdev);
 906         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 907
 908         fsl_spi_cpm_free(mpc8xxx_spi);
 909
 910         return 0;
 911 }
 912
 913 MODULE_ALIAS("platform:mpc8xxx_spi");
 914 static struct platform_driver mpc8xxx_spi_driver = {
 915         .probe = plat_mpc8xxx_spi_probe,
 916         .remove = plat_mpc8xxx_spi_remove,
 917         .driver = {
 918                 .name = "mpc8xxx_spi",
 919         },
 920 };
 921
 922 static bool legacy_driver_failed;
 923
 924 static void __init legacy_driver_register(void)
 925 {
 926         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 927 }
 928
 929 static void __exit legacy_driver_unregister(void)
 930 {
 931         if (legacy_driver_failed)
 932                 return;
 933         platform_driver_unregister(&mpc8xxx_spi_driver);
 934 }
 935 #else
 936 static void __init legacy_driver_register(void) {}
 937 static void __exit legacy_driver_unregister(void) {}
 938 #endif /* CONFIG_MPC832x_RDB */
 939
 940 static int __init fsl_spi_init(void)
 941 {
 942         legacy_driver_register();
 943         return platform_driver_register(&of_fsl_spi_driver);
 944 }
 945 module_init(fsl_spi_init);
 946
 947 static void __exit fsl_spi_exit(void)
 948 {
 949         platform_driver_unregister(&of_fsl_spi_driver);
 950         legacy_driver_unregister();
 951 }
 952 module_exit(fsl_spi_exit);
 953
 954 MODULE_AUTHOR("Kumar Gala");
 955 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 956 MODULE_LICENSE("GPL");