1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2013 Freescale Semiconductor, Inc.
6 // Freescale DSPI driver
7 // This file contains a driver for the Freescale DSPI
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/errno.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/sched.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/spi-fsl-dspi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/time.h>
32 #define DRIVER_NAME "fsl-dspi"
35 #define DSPI_FIFO_SIZE 16
37 #define DSPI_FIFO_SIZE 4
39 #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
42 #define SPI_MCR_MASTER (1 << 31)
43 #define SPI_MCR_PCSIS (0x3F << 16)
44 #define SPI_MCR_CLR_TXF (1 << 11)
45 #define SPI_MCR_CLR_RXF (1 << 10)
46 #define SPI_MCR_XSPI (1 << 3)
47 #define SPI_MCR_DIS_TXF (1 << 13)
48 #define SPI_MCR_DIS_RXF (1 << 12)
49 #define SPI_MCR_HALT (1 << 0)
52 #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
54 #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
55 #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
56 #define SPI_CTAR_CPOL(x) ((x) << 26)
57 #define SPI_CTAR_CPHA(x) ((x) << 25)
58 #define SPI_CTAR_LSBFE(x) ((x) << 24)
59 #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
60 #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
61 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
62 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
63 #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
64 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
65 #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
66 #define SPI_CTAR_BR(x) ((x) & 0x0000000f)
67 #define SPI_CTAR_SCALE_BITS 0xf
69 #define SPI_CTAR0_SLAVE 0x0c
72 #define SPI_SR_EOQF 0x10000000
73 #define SPI_SR_TCFQF 0x80000000
74 #define SPI_SR_CLEAR 0x9aaf0000
76 #define SPI_RSER_TFFFE BIT(25)
77 #define SPI_RSER_TFFFD BIT(24)
78 #define SPI_RSER_RFDFE BIT(17)
79 #define SPI_RSER_RFDFD BIT(16)
82 #define SPI_RSER_EOQFE 0x10000000
83 #define SPI_RSER_TCFQE 0x80000000
85 #define SPI_PUSHR 0x34
86 #define SPI_PUSHR_CMD_CONT (1 << 15)
87 #define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16)
88 #define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12)
89 #define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16)
90 #define SPI_PUSHR_CMD_EOQ (1 << 11)
91 #define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16)
92 #define SPI_PUSHR_CMD_CTCNT (1 << 10)
93 #define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16)
94 #define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f)
95 #define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16)
96 #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
98 #define SPI_PUSHR_SLAVE 0x34
100 #define SPI_POPR 0x38
101 #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
103 #define SPI_TXFR0 0x3c
104 #define SPI_TXFR1 0x40
105 #define SPI_TXFR2 0x44
106 #define SPI_TXFR3 0x48
107 #define SPI_RXFR0 0x7c
108 #define SPI_RXFR1 0x80
109 #define SPI_RXFR2 0x84
110 #define SPI_RXFR3 0x88
112 #define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4))
113 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
114 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
116 #define SPI_SREX 0x13c
118 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
119 #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
120 #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
121 #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
123 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
124 #define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1)
126 /* Register offsets for regmap_pushr */
127 #define PUSHR_CMD 0x0
130 #define SPI_CS_INIT 0x01
131 #define SPI_CS_ASSERT 0x02
132 #define SPI_CS_DROP 0x04
134 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
141 enum dspi_trans_mode {
147 struct fsl_dspi_devtype_data {
148 enum dspi_trans_mode trans_mode;
153 static const struct fsl_dspi_devtype_data vf610_data = {
154 .trans_mode = DSPI_DMA_MODE,
155 .max_clock_factor = 2,
158 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
159 .trans_mode = DSPI_TCFQ_MODE,
160 .max_clock_factor = 8,
164 static const struct fsl_dspi_devtype_data ls2085a_data = {
165 .trans_mode = DSPI_TCFQ_MODE,
166 .max_clock_factor = 8,
169 static const struct fsl_dspi_devtype_data coldfire_data = {
170 .trans_mode = DSPI_EOQ_MODE,
171 .max_clock_factor = 8,
174 struct fsl_dspi_dma {
175 /* Length of transfer in words of DSPI_FIFO_SIZE */
179 struct dma_chan *chan_tx;
180 dma_addr_t tx_dma_phys;
181 struct completion cmd_tx_complete;
182 struct dma_async_tx_descriptor *tx_desc;
185 struct dma_chan *chan_rx;
186 dma_addr_t rx_dma_phys;
187 struct completion cmd_rx_complete;
188 struct dma_async_tx_descriptor *rx_desc;
192 struct spi_master *master;
193 struct platform_device *pdev;
195 struct regmap *regmap;
196 struct regmap *regmap_pushr;
200 struct spi_transfer *cur_transfer;
201 struct spi_message *cur_msg;
202 struct chip_data *cur_chip;
211 const struct fsl_dspi_devtype_data *devtype_data;
213 wait_queue_head_t waitq;
216 struct fsl_dspi_dma *dma;
219 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
224 if (dspi->bytes_per_word == 1)
225 txdata = *(u8 *)dspi->tx;
226 else if (dspi->bytes_per_word == 2)
227 txdata = *(u16 *)dspi->tx;
228 else /* dspi->bytes_per_word == 4 */
229 txdata = *(u32 *)dspi->tx;
230 dspi->tx += dspi->bytes_per_word;
232 dspi->len -= dspi->bytes_per_word;
236 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
238 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
241 cmd |= SPI_PUSHR_CMD_CONT;
242 return cmd << 16 | data;
245 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
250 /* Mask of undefined bits */
251 rxdata &= (1 << dspi->bits_per_word) - 1;
253 if (dspi->bytes_per_word == 1)
254 *(u8 *)dspi->rx = rxdata;
255 else if (dspi->bytes_per_word == 2)
256 *(u16 *)dspi->rx = rxdata;
257 else /* dspi->bytes_per_word == 4 */
258 *(u32 *)dspi->rx = rxdata;
259 dspi->rx += dspi->bytes_per_word;
262 static void dspi_tx_dma_callback(void *arg)
264 struct fsl_dspi *dspi = arg;
265 struct fsl_dspi_dma *dma = dspi->dma;
267 complete(&dma->cmd_tx_complete);
270 static void dspi_rx_dma_callback(void *arg)
272 struct fsl_dspi *dspi = arg;
273 struct fsl_dspi_dma *dma = dspi->dma;
277 for (i = 0; i < dma->curr_xfer_len; i++)
278 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
281 complete(&dma->cmd_rx_complete);
284 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
286 struct fsl_dspi_dma *dma = dspi->dma;
287 struct device *dev = &dspi->pdev->dev;
291 for (i = 0; i < dma->curr_xfer_len; i++)
292 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
294 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
297 DMA_SLAVE_BUSWIDTH_4_BYTES,
299 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
301 dev_err(dev, "Not able to get desc for DMA xfer\n");
305 dma->tx_desc->callback = dspi_tx_dma_callback;
306 dma->tx_desc->callback_param = dspi;
307 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
308 dev_err(dev, "DMA submit failed\n");
312 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
315 DMA_SLAVE_BUSWIDTH_4_BYTES,
317 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
319 dev_err(dev, "Not able to get desc for DMA xfer\n");
323 dma->rx_desc->callback = dspi_rx_dma_callback;
324 dma->rx_desc->callback_param = dspi;
325 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
326 dev_err(dev, "DMA submit failed\n");
330 reinit_completion(&dspi->dma->cmd_rx_complete);
331 reinit_completion(&dspi->dma->cmd_tx_complete);
333 dma_async_issue_pending(dma->chan_rx);
334 dma_async_issue_pending(dma->chan_tx);
336 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
337 DMA_COMPLETION_TIMEOUT);
338 if (time_left == 0) {
339 dev_err(dev, "DMA tx timeout\n");
340 dmaengine_terminate_all(dma->chan_tx);
341 dmaengine_terminate_all(dma->chan_rx);
345 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
346 DMA_COMPLETION_TIMEOUT);
347 if (time_left == 0) {
348 dev_err(dev, "DMA rx timeout\n");
349 dmaengine_terminate_all(dma->chan_tx);
350 dmaengine_terminate_all(dma->chan_rx);
357 static int dspi_dma_xfer(struct fsl_dspi *dspi)
359 struct fsl_dspi_dma *dma = dspi->dma;
360 struct device *dev = &dspi->pdev->dev;
361 struct spi_message *message = dspi->cur_msg;
362 int curr_remaining_bytes;
363 int bytes_per_buffer;
366 curr_remaining_bytes = dspi->len;
367 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
368 while (curr_remaining_bytes) {
369 /* Check if current transfer fits the DMA buffer */
370 dma->curr_xfer_len = curr_remaining_bytes
371 / dspi->bytes_per_word;
372 if (dma->curr_xfer_len > bytes_per_buffer)
373 dma->curr_xfer_len = bytes_per_buffer;
375 ret = dspi_next_xfer_dma_submit(dspi);
377 dev_err(dev, "DMA transfer failed\n");
382 dma->curr_xfer_len * dspi->bytes_per_word;
383 curr_remaining_bytes -= len;
384 message->actual_length += len;
385 if (curr_remaining_bytes < 0)
386 curr_remaining_bytes = 0;
394 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
396 struct fsl_dspi_dma *dma;
397 struct dma_slave_config cfg;
398 struct device *dev = &dspi->pdev->dev;
401 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
405 dma->chan_rx = dma_request_slave_channel(dev, "rx");
407 dev_err(dev, "rx dma channel not available\n");
412 dma->chan_tx = dma_request_slave_channel(dev, "tx");
414 dev_err(dev, "tx dma channel not available\n");
419 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
420 &dma->tx_dma_phys, GFP_KERNEL);
421 if (!dma->tx_dma_buf) {
426 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
427 &dma->rx_dma_phys, GFP_KERNEL);
428 if (!dma->rx_dma_buf) {
433 memset(&cfg, 0, sizeof(cfg));
434 cfg.src_addr = phy_addr + SPI_POPR;
435 cfg.dst_addr = phy_addr + SPI_PUSHR;
436 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
437 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
438 cfg.src_maxburst = 1;
439 cfg.dst_maxburst = 1;
441 cfg.direction = DMA_DEV_TO_MEM;
442 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
444 dev_err(dev, "can't configure rx dma channel\n");
446 goto err_slave_config;
449 cfg.direction = DMA_MEM_TO_DEV;
450 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
452 dev_err(dev, "can't configure tx dma channel\n");
454 goto err_slave_config;
458 init_completion(&dma->cmd_tx_complete);
459 init_completion(&dma->cmd_rx_complete);
464 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
465 dma->rx_dma_buf, dma->rx_dma_phys);
467 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
468 dma->tx_dma_buf, dma->tx_dma_phys);
470 dma_release_channel(dma->chan_tx);
472 dma_release_channel(dma->chan_rx);
474 devm_kfree(dev, dma);
480 static void dspi_release_dma(struct fsl_dspi *dspi)
482 struct fsl_dspi_dma *dma = dspi->dma;
483 struct device *dev = &dspi->pdev->dev;
487 dma_unmap_single(dev, dma->tx_dma_phys,
488 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
489 dma_release_channel(dma->chan_tx);
493 dma_unmap_single(dev, dma->rx_dma_phys,
494 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
495 dma_release_channel(dma->chan_rx);
500 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
501 unsigned long clkrate)
503 /* Valid baud rate pre-scaler values */
504 int pbr_tbl[4] = {2, 3, 5, 7};
505 int brs[16] = { 2, 4, 6, 8,
507 256, 512, 1024, 2048,
508 4096, 8192, 16384, 32768 };
509 int scale_needed, scale, minscale = INT_MAX;
512 scale_needed = clkrate / speed_hz;
513 if (clkrate % speed_hz)
516 for (i = 0; i < ARRAY_SIZE(brs); i++)
517 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
518 scale = brs[i] * pbr_tbl[j];
519 if (scale >= scale_needed) {
520 if (scale < minscale) {
529 if (minscale == INT_MAX) {
530 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
532 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
533 *br = ARRAY_SIZE(brs) - 1;
537 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
538 unsigned long clkrate)
540 int pscale_tbl[4] = {1, 3, 5, 7};
541 int scale_needed, scale, minscale = INT_MAX;
545 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
550 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
551 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
552 scale = pscale_tbl[i] * (2 << j);
553 if (scale >= scale_needed) {
554 if (scale < minscale) {
563 if (minscale == INT_MAX) {
564 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
566 *psc = ARRAY_SIZE(pscale_tbl) - 1;
567 *sc = SPI_CTAR_SCALE_BITS;
571 static void fifo_write(struct fsl_dspi *dspi)
573 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
576 static void cmd_fifo_write(struct fsl_dspi *dspi)
578 u16 cmd = dspi->tx_cmd;
581 cmd |= SPI_PUSHR_CMD_CONT;
582 regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
585 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
587 regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
590 static void dspi_tcfq_write(struct fsl_dspi *dspi)
592 /* Clear transfer count */
593 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
595 if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
596 /* Write two TX FIFO entries first, and then the corresponding
599 u32 data = dspi_pop_tx(dspi);
601 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) {
603 tx_fifo_write(dspi, data & 0xFFFF);
604 tx_fifo_write(dspi, data >> 16);
607 tx_fifo_write(dspi, data >> 16);
608 tx_fifo_write(dspi, data & 0xFFFF);
610 cmd_fifo_write(dspi);
612 /* Write one entry to both TX FIFO and CMD FIFO
619 static u32 fifo_read(struct fsl_dspi *dspi)
623 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
627 static void dspi_tcfq_read(struct fsl_dspi *dspi)
629 dspi_push_rx(dspi, fifo_read(dspi));
632 static void dspi_eoq_write(struct fsl_dspi *dspi)
634 int fifo_size = DSPI_FIFO_SIZE;
635 u16 xfer_cmd = dspi->tx_cmd;
637 /* Fill TX FIFO with as many transfers as possible */
638 while (dspi->len && fifo_size--) {
639 dspi->tx_cmd = xfer_cmd;
640 /* Request EOQF for last transfer in FIFO */
641 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
642 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
643 /* Clear transfer count for first transfer in FIFO */
644 if (fifo_size == (DSPI_FIFO_SIZE - 1))
645 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
646 /* Write combined TX FIFO and CMD FIFO entry */
651 static void dspi_eoq_read(struct fsl_dspi *dspi)
653 int fifo_size = DSPI_FIFO_SIZE;
655 /* Read one FIFO entry at and push to rx buffer */
656 while ((dspi->rx < dspi->rx_end) && fifo_size--)
657 dspi_push_rx(dspi, fifo_read(dspi));
660 static int dspi_transfer_one_message(struct spi_master *master,
661 struct spi_message *message)
663 struct fsl_dspi *dspi = spi_master_get_devdata(master);
664 struct spi_device *spi = message->spi;
665 struct spi_transfer *transfer;
667 enum dspi_trans_mode trans_mode;
669 message->actual_length = 0;
671 list_for_each_entry(transfer, &message->transfers, transfer_list) {
672 dspi->cur_transfer = transfer;
673 dspi->cur_msg = message;
674 dspi->cur_chip = spi_get_ctldata(spi);
675 /* Prepare command word for CMD FIFO */
676 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
677 SPI_PUSHR_CMD_PCS(spi->chip_select);
678 if (list_is_last(&dspi->cur_transfer->transfer_list,
679 &dspi->cur_msg->transfers)) {
680 /* Leave PCS activated after last transfer when
683 if (transfer->cs_change)
684 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
686 /* Keep PCS active between transfers in same message
687 * when cs_change is not set, and de-activate PCS
688 * between transfers in the same message when
691 if (!transfer->cs_change)
692 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
695 dspi->void_write_data = dspi->cur_chip->void_write_data;
697 dspi->tx = transfer->tx_buf;
698 dspi->rx = transfer->rx_buf;
699 dspi->rx_end = dspi->rx + transfer->len;
700 dspi->len = transfer->len;
701 /* Validated transfer specific frame size (defaults applied) */
702 dspi->bits_per_word = transfer->bits_per_word;
703 if (transfer->bits_per_word <= 8)
704 dspi->bytes_per_word = 1;
705 else if (transfer->bits_per_word <= 16)
706 dspi->bytes_per_word = 2;
708 dspi->bytes_per_word = 4;
710 regmap_update_bits(dspi->regmap, SPI_MCR,
711 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
712 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
713 regmap_write(dspi->regmap, SPI_CTAR(0),
714 dspi->cur_chip->ctar_val |
715 SPI_FRAME_BITS(transfer->bits_per_word));
716 if (dspi->devtype_data->xspi_mode)
717 regmap_write(dspi->regmap, SPI_CTARE(0),
718 SPI_FRAME_EBITS(transfer->bits_per_word)
719 | SPI_CTARE_DTCP(1));
721 trans_mode = dspi->devtype_data->trans_mode;
722 switch (trans_mode) {
724 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
725 dspi_eoq_write(dspi);
728 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
729 dspi_tcfq_write(dspi);
732 regmap_write(dspi->regmap, SPI_RSER,
733 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
734 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
735 status = dspi_dma_xfer(dspi);
738 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
744 if (trans_mode != DSPI_DMA_MODE) {
745 if (wait_event_interruptible(dspi->waitq,
747 dev_err(&dspi->pdev->dev,
748 "wait transfer complete fail!\n");
752 if (transfer->delay_usecs)
753 udelay(transfer->delay_usecs);
757 message->status = status;
758 spi_finalize_current_message(master);
763 static int dspi_setup(struct spi_device *spi)
765 struct chip_data *chip;
766 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
767 struct fsl_dspi_platform_data *pdata;
768 u32 cs_sck_delay = 0, sck_cs_delay = 0;
769 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
770 unsigned char pasc = 0, asc = 0;
771 unsigned long clkrate;
773 /* Only alloc on first setup */
774 chip = spi_get_ctldata(spi);
776 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
781 pdata = dev_get_platdata(&dspi->pdev->dev);
784 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
787 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
790 cs_sck_delay = pdata->cs_sck_delay;
791 sck_cs_delay = pdata->sck_cs_delay;
794 chip->void_write_data = 0;
796 clkrate = clk_get_rate(dspi->clk);
797 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
799 /* Set PCS to SCK delay scale values */
800 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
802 /* Set After SCK delay scale values */
803 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
805 chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
806 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
807 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
808 | SPI_CTAR_PCSSCK(pcssck)
809 | SPI_CTAR_CSSCK(cssck)
810 | SPI_CTAR_PASC(pasc)
815 spi_set_ctldata(spi, chip);
820 static void dspi_cleanup(struct spi_device *spi)
822 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
824 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
825 spi->master->bus_num, spi->chip_select);
830 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
832 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
833 struct spi_message *msg = dspi->cur_msg;
834 enum dspi_trans_mode trans_mode;
838 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
839 regmap_write(dspi->regmap, SPI_SR, spi_sr);
842 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
843 /* Get transfer counter (in number of SPI transfers). It was
844 * reset to 0 when transfer(s) were started.
846 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
847 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
848 /* Update total number of bytes that were transferred */
849 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
851 trans_mode = dspi->devtype_data->trans_mode;
852 switch (trans_mode) {
857 dspi_tcfq_read(dspi);
860 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
867 wake_up_interruptible(&dspi->waitq);
869 switch (trans_mode) {
871 dspi_eoq_write(dspi);
874 dspi_tcfq_write(dspi);
877 dev_err(&dspi->pdev->dev,
878 "unsupported trans_mode %u\n",
889 static const struct of_device_id fsl_dspi_dt_ids[] = {
890 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
891 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
892 { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
895 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
897 #ifdef CONFIG_PM_SLEEP
898 static int dspi_suspend(struct device *dev)
900 struct spi_master *master = dev_get_drvdata(dev);
901 struct fsl_dspi *dspi = spi_master_get_devdata(master);
904 disable_irq(dspi->irq);
905 spi_master_suspend(master);
906 clk_disable_unprepare(dspi->clk);
908 pinctrl_pm_select_sleep_state(dev);
913 static int dspi_resume(struct device *dev)
915 struct spi_master *master = dev_get_drvdata(dev);
916 struct fsl_dspi *dspi = spi_master_get_devdata(master);
919 pinctrl_pm_select_default_state(dev);
921 ret = clk_prepare_enable(dspi->clk);
924 spi_master_resume(master);
926 enable_irq(dspi->irq);
930 #endif /* CONFIG_PM_SLEEP */
932 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
934 static const struct regmap_range dspi_volatile_ranges[] = {
935 regmap_reg_range(SPI_MCR, SPI_TCR),
936 regmap_reg_range(SPI_SR, SPI_SR),
937 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
940 static const struct regmap_access_table dspi_volatile_table = {
941 .yes_ranges = dspi_volatile_ranges,
942 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
945 static const struct regmap_config dspi_regmap_config = {
949 .max_register = 0x88,
950 .volatile_table = &dspi_volatile_table,
953 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
954 regmap_reg_range(SPI_MCR, SPI_TCR),
955 regmap_reg_range(SPI_SR, SPI_SR),
956 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
957 regmap_reg_range(SPI_SREX, SPI_SREX),
960 static const struct regmap_access_table dspi_xspi_volatile_table = {
961 .yes_ranges = dspi_xspi_volatile_ranges,
962 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
965 static const struct regmap_config dspi_xspi_regmap_config[] = {
970 .max_register = 0x13c,
971 .volatile_table = &dspi_xspi_volatile_table,
982 static void dspi_init(struct fsl_dspi *dspi)
984 regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS |
985 (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0));
986 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
987 if (dspi->devtype_data->xspi_mode)
988 regmap_write(dspi->regmap, SPI_CTARE(0),
989 SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
992 static int dspi_probe(struct platform_device *pdev)
994 struct device_node *np = pdev->dev.of_node;
995 struct spi_master *master;
996 struct fsl_dspi *dspi;
997 struct resource *res;
998 const struct regmap_config *regmap_config;
1000 struct fsl_dspi_platform_data *pdata;
1001 int ret = 0, cs_num, bus_num;
1003 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1007 dspi = spi_master_get_devdata(master);
1009 dspi->master = master;
1011 master->transfer = NULL;
1012 master->setup = dspi_setup;
1013 master->transfer_one_message = dspi_transfer_one_message;
1014 master->dev.of_node = pdev->dev.of_node;
1016 master->cleanup = dspi_cleanup;
1017 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1019 pdata = dev_get_platdata(&pdev->dev);
1021 master->num_chipselect = pdata->cs_num;
1022 master->bus_num = pdata->bus_num;
1024 dspi->devtype_data = &coldfire_data;
1027 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1029 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1030 goto out_master_put;
1032 master->num_chipselect = cs_num;
1034 ret = of_property_read_u32(np, "bus-num", &bus_num);
1036 dev_err(&pdev->dev, "can't get bus-num\n");
1037 goto out_master_put;
1039 master->bus_num = bus_num;
1041 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1042 if (!dspi->devtype_data) {
1043 dev_err(&pdev->dev, "can't get devtype_data\n");
1045 goto out_master_put;
1049 if (dspi->devtype_data->xspi_mode)
1050 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1052 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1054 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1055 base = devm_ioremap_resource(&pdev->dev, res);
1057 ret = PTR_ERR(base);
1058 goto out_master_put;
1061 if (dspi->devtype_data->xspi_mode)
1062 regmap_config = &dspi_xspi_regmap_config[0];
1064 regmap_config = &dspi_regmap_config;
1065 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1066 if (IS_ERR(dspi->regmap)) {
1067 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1068 PTR_ERR(dspi->regmap));
1069 ret = PTR_ERR(dspi->regmap);
1070 goto out_master_put;
1073 if (dspi->devtype_data->xspi_mode) {
1074 dspi->regmap_pushr = devm_regmap_init_mmio(
1075 &pdev->dev, base + SPI_PUSHR,
1076 &dspi_xspi_regmap_config[1]);
1077 if (IS_ERR(dspi->regmap_pushr)) {
1079 "failed to init pushr regmap: %ld\n",
1080 PTR_ERR(dspi->regmap_pushr));
1081 ret = PTR_ERR(dspi->regmap_pushr);
1082 goto out_master_put;
1086 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1087 if (IS_ERR(dspi->clk)) {
1088 ret = PTR_ERR(dspi->clk);
1089 dev_err(&pdev->dev, "unable to get clock\n");
1090 goto out_master_put;
1092 ret = clk_prepare_enable(dspi->clk);
1094 goto out_master_put;
1097 dspi->irq = platform_get_irq(pdev, 0);
1098 if (dspi->irq < 0) {
1099 dev_err(&pdev->dev, "can't get platform irq\n");
1104 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1105 IRQF_SHARED, pdev->name, dspi);
1107 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1111 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1112 ret = dspi_request_dma(dspi, res->start);
1114 dev_err(&pdev->dev, "can't get dma channels\n");
1119 master->max_speed_hz =
1120 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1122 init_waitqueue_head(&dspi->waitq);
1123 platform_set_drvdata(pdev, master);
1125 ret = spi_register_master(master);
1127 dev_err(&pdev->dev, "Problem registering DSPI master\n");
1128 goto out_release_dma;
1134 dspi_release_dma(dspi);
1137 free_irq(dspi->irq, dspi);
1139 clk_disable_unprepare(dspi->clk);
1141 spi_master_put(master);
1146 static int dspi_remove(struct platform_device *pdev)
1148 struct spi_master *master = platform_get_drvdata(pdev);
1149 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1151 /* Disconnect from the SPI framework */
1152 spi_unregister_controller(dspi->master);
1154 /* Disable RX and TX */
1155 regmap_update_bits(dspi->regmap, SPI_MCR,
1156 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1157 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1160 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1162 dspi_release_dma(dspi);
1164 free_irq(dspi->irq, dspi);
1165 clk_disable_unprepare(dspi->clk);
1170 static void dspi_shutdown(struct platform_device *pdev)
1175 static struct platform_driver fsl_dspi_driver = {
1176 .driver.name = DRIVER_NAME,
1177 .driver.of_match_table = fsl_dspi_dt_ids,
1178 .driver.owner = THIS_MODULE,
1179 .driver.pm = &dspi_pm,
1180 .probe = dspi_probe,
1181 .remove = dspi_remove,
1182 .shutdown = dspi_shutdown,
1184 module_platform_driver(fsl_dspi_driver);
1186 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1187 MODULE_LICENSE("GPL");
1188 MODULE_ALIAS("platform:" DRIVER_NAME);