1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DW_SPI_HEADER_H
3 #define DW_SPI_HEADER_H
6 #include <linux/scatterlist.h>
7 #include <linux/gpio.h>
10 #define DW_SPI_CTRL0 0x00
11 #define DW_SPI_CTRL1 0x04
12 #define DW_SPI_SSIENR 0x08
13 #define DW_SPI_MWCR 0x0c
14 #define DW_SPI_SER 0x10
15 #define DW_SPI_BAUDR 0x14
16 #define DW_SPI_TXFLTR 0x18
17 #define DW_SPI_RXFLTR 0x1c
18 #define DW_SPI_TXFLR 0x20
19 #define DW_SPI_RXFLR 0x24
20 #define DW_SPI_SR 0x28
21 #define DW_SPI_IMR 0x2c
22 #define DW_SPI_ISR 0x30
23 #define DW_SPI_RISR 0x34
24 #define DW_SPI_TXOICR 0x38
25 #define DW_SPI_RXOICR 0x3c
26 #define DW_SPI_RXUICR 0x40
27 #define DW_SPI_MSTICR 0x44
28 #define DW_SPI_ICR 0x48
29 #define DW_SPI_DMACR 0x4c
30 #define DW_SPI_DMATDLR 0x50
31 #define DW_SPI_DMARDLR 0x54
32 #define DW_SPI_IDR 0x58
33 #define DW_SPI_VERSION 0x5c
34 #define DW_SPI_DR 0x60
36 /* Bit fields in CTRLR0 */
37 #define SPI_DFS_OFFSET 0
39 #define SPI_FRF_OFFSET 4
40 #define SPI_FRF_SPI 0x0
41 #define SPI_FRF_SSP 0x1
42 #define SPI_FRF_MICROWIRE 0x2
43 #define SPI_FRF_RESV 0x3
45 #define SPI_MODE_OFFSET 6
46 #define SPI_SCPH_OFFSET 6
47 #define SPI_SCOL_OFFSET 7
49 #define SPI_TMOD_OFFSET 8
50 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
51 #define SPI_TMOD_TR 0x0 /* xmit & recv */
52 #define SPI_TMOD_TO 0x1 /* xmit only */
53 #define SPI_TMOD_RO 0x2 /* recv only */
54 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
56 #define SPI_SLVOE_OFFSET 10
57 #define SPI_SRL_OFFSET 11
58 #define SPI_CFS_OFFSET 12
60 /* Bit fields in SR, 7 bits */
61 #define SR_MASK 0x7f /* cover 7 bits */
62 #define SR_BUSY (1 << 0)
63 #define SR_TF_NOT_FULL (1 << 1)
64 #define SR_TF_EMPT (1 << 2)
65 #define SR_RF_NOT_EMPT (1 << 3)
66 #define SR_RF_FULL (1 << 4)
67 #define SR_TX_ERR (1 << 5)
68 #define SR_DCOL (1 << 6)
70 /* Bit fields in ISR, IMR, RISR, 7 bits */
71 #define SPI_INT_TXEI (1 << 0)
72 #define SPI_INT_TXOI (1 << 1)
73 #define SPI_INT_RXUI (1 << 2)
74 #define SPI_INT_RXOI (1 << 3)
75 #define SPI_INT_RXFI (1 << 4)
76 #define SPI_INT_MSTI (1 << 5)
78 /* Bit fields in DMACR */
79 #define SPI_DMA_RDMAE (1 << 0)
80 #define SPI_DMA_TDMAE (1 << 1)
82 /* TX RX interrupt level threshold, max can be 256 */
83 #define SPI_INT_THRESHOLD 32
92 struct dw_spi_dma_ops {
93 int (*dma_init)(struct dw_spi *dws);
94 void (*dma_exit)(struct dw_spi *dws);
95 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
96 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
97 struct spi_transfer *xfer);
98 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
99 void (*dma_stop)(struct dw_spi *dws);
103 struct spi_controller *master;
104 enum dw_ssi_type type;
109 u32 fifo_len; /* depth of the FIFO buffer */
110 u32 max_freq; /* max bus freq supported */
112 u32 reg_io_width; /* DR I/O width in bytes */
114 u16 num_cs; /* supported slave numbers */
115 void (*set_cs)(struct spi_device *spi, bool enable);
117 /* Current message transfer state info */
125 u8 n_bytes; /* current is a 1/2 bytes op */
127 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
128 u32 current_freq; /* frequency in hz */
132 struct dma_chan *txchan;
133 struct dma_chan *rxchan;
134 unsigned long dma_chan_busy;
135 dma_addr_t dma_addr; /* phy address of the Data register */
136 const struct dw_spi_dma_ops *dma_ops;
140 /* Bus interface info */
142 #ifdef CONFIG_DEBUG_FS
143 struct dentry *debugfs;
147 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
149 return __raw_readl(dws->regs + offset);
152 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
154 return __raw_readw(dws->regs + offset);
157 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
159 __raw_writel(val, dws->regs + offset);
162 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
164 __raw_writew(val, dws->regs + offset);
167 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
169 switch (dws->reg_io_width) {
171 return dw_readw(dws, offset);
174 return dw_readl(dws, offset);
178 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
180 switch (dws->reg_io_width) {
182 dw_writew(dws, offset, val);
186 dw_writel(dws, offset, val);
191 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
193 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
196 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
198 dw_writel(dws, DW_SPI_BAUDR, div);
201 /* Disable IRQ bits */
202 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
206 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
207 dw_writel(dws, DW_SPI_IMR, new_mask);
210 /* Enable IRQ bits */
211 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
215 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
216 dw_writel(dws, DW_SPI_IMR, new_mask);
220 * This does disable the SPI controller, interrupts, and re-enable the
221 * controller back. Transmit and receive FIFO buffers are cleared when the
222 * device is disabled.
224 static inline void spi_reset_chip(struct dw_spi *dws)
226 spi_enable_chip(dws, 0);
227 spi_mask_intr(dws, 0xff);
228 spi_enable_chip(dws, 1);
231 static inline void spi_shutdown_chip(struct dw_spi *dws)
233 spi_enable_chip(dws, 0);
238 * Each SPI slave device to work with dw_api controller should
239 * has such a structure claiming its working mode (poll or PIO/DMA),
240 * which can be save in the "controller_data" member of the
244 u8 poll_mode; /* 1 for controller polling mode */
245 u8 type; /* SPI/SSP/MicroWire */
246 void (*cs_control)(u32 command);
249 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
250 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
251 extern void dw_spi_remove_host(struct dw_spi *dws);
252 extern int dw_spi_suspend_host(struct dw_spi *dws);
253 extern int dw_spi_resume_host(struct dw_spi *dws);
255 /* platform related setup */
256 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
257 #endif /* DW_SPI_HEADER_H */