2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/highmem.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spi/spi.h>
23 #include <linux/gpio.h>
27 #ifdef CONFIG_DEBUG_FS
28 #include <linux/debugfs.h>
31 /* Slave spi_dev related */
33 u8 cs; /* chip select pin */
34 u8 tmode; /* TR/TO/RO/EEPROM */
35 u8 type; /* SPI/SSP/MicroWire */
37 u8 poll_mode; /* 1 means use poll mode */
40 u16 clk_div; /* baud rate divider */
41 u32 speed_hz; /* baud rate */
42 void (*cs_control)(u32 command);
45 #ifdef CONFIG_DEBUG_FS
46 #define SPI_REGS_BUFSIZE 1024
47 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos)
50 struct dw_spi *dws = file->private_data;
55 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
59 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
60 "%s registers:\n", dev_name(&dws->master->dev));
61 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
62 "=================================\n");
63 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
64 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
65 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
66 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
67 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
68 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
69 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
70 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
71 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
72 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
73 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
74 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
75 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
76 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
77 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
78 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
79 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
80 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "=================================\n");
96 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
101 static const struct file_operations dw_spi_regs_ops = {
102 .owner = THIS_MODULE,
104 .read = dw_spi_show_regs,
105 .llseek = default_llseek,
108 static int dw_spi_debugfs_init(struct dw_spi *dws)
112 snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
113 dws->debugfs = debugfs_create_dir(name, NULL);
117 debugfs_create_file("registers", S_IFREG | S_IRUGO,
118 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
122 static void dw_spi_debugfs_remove(struct dw_spi *dws)
124 debugfs_remove_recursive(dws->debugfs);
128 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
133 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
136 #endif /* CONFIG_DEBUG_FS */
138 static void dw_spi_set_cs(struct spi_device *spi, bool enable)
140 struct dw_spi *dws = spi_master_get_devdata(spi->master);
141 struct chip_data *chip = spi_get_ctldata(spi);
143 /* Chip select logic is inverted from spi_set_cs() */
144 if (chip && chip->cs_control)
145 chip->cs_control(!enable);
148 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
151 /* Return the max entries we can fill into tx fifo */
152 static inline u32 tx_max(struct dw_spi *dws)
154 u32 tx_left, tx_room, rxtx_gap;
156 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
157 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
160 * Another concern is about the tx/rx mismatch, we
161 * though to use (dws->fifo_len - rxflr - txflr) as
162 * one maximum value for tx, but it doesn't cover the
163 * data which is out of tx/rx fifo and inside the
164 * shift registers. So a control from sw point of
167 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
170 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
173 /* Return the max entries we should read out of rx fifo */
174 static inline u32 rx_max(struct dw_spi *dws)
176 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
178 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
181 static void dw_writer(struct dw_spi *dws)
186 spin_lock(&dws->buf_lock);
189 /* Set the tx word if the transfer's original "tx" is not null */
190 if (dws->tx_end - dws->len) {
191 if (dws->n_bytes == 1)
192 txw = *(u8 *)(dws->tx);
194 txw = *(u16 *)(dws->tx);
196 dw_write_io_reg(dws, DW_SPI_DR, txw);
197 dws->tx += dws->n_bytes;
199 spin_unlock(&dws->buf_lock);
202 static void dw_reader(struct dw_spi *dws)
207 spin_lock(&dws->buf_lock);
210 rxw = dw_read_io_reg(dws, DW_SPI_DR);
211 /* Care rx only if the transfer's original "rx" is not null */
212 if (dws->rx_end - dws->len) {
213 if (dws->n_bytes == 1)
214 *(u8 *)(dws->rx) = rxw;
216 *(u16 *)(dws->rx) = rxw;
218 dws->rx += dws->n_bytes;
220 spin_unlock(&dws->buf_lock);
223 static void int_error_stop(struct dw_spi *dws, const char *msg)
227 dev_err(&dws->master->dev, "%s\n", msg);
228 dws->master->cur_msg->status = -EIO;
229 spi_finalize_current_transfer(dws->master);
232 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
234 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
237 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
238 dw_readl(dws, DW_SPI_ICR);
239 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
244 if (dws->rx_end == dws->rx) {
245 spi_mask_intr(dws, SPI_INT_TXEI);
246 spi_finalize_current_transfer(dws->master);
249 if (irq_status & SPI_INT_TXEI) {
250 spi_mask_intr(dws, SPI_INT_TXEI);
252 /* Enable TX irq always, it will be disabled when RX finished */
253 spi_umask_intr(dws, SPI_INT_TXEI);
259 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
261 struct spi_master *master = dev_id;
262 struct dw_spi *dws = spi_master_get_devdata(master);
263 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
268 if (!master->cur_msg) {
269 spi_mask_intr(dws, SPI_INT_TXEI);
273 return dws->transfer_handler(dws);
276 /* Must be called inside pump_transfers() */
277 static int poll_transfer(struct dw_spi *dws)
283 } while (dws->rx_end > dws->rx);
288 static int dw_spi_transfer_one(struct spi_master *master,
289 struct spi_device *spi, struct spi_transfer *transfer)
291 struct dw_spi *dws = spi_master_get_devdata(master);
292 struct chip_data *chip = spi_get_ctldata(spi);
300 spin_lock_irqsave(&dws->buf_lock, flags);
301 dws->tx = (void *)transfer->tx_buf;
302 dws->tx_end = dws->tx + transfer->len;
303 dws->rx = transfer->rx_buf;
304 dws->rx_end = dws->rx + transfer->len;
305 dws->len = transfer->len;
306 spin_unlock_irqrestore(&dws->buf_lock, flags);
308 /* Ensure dw->rx and dw->rx_end are visible */
311 spi_enable_chip(dws, 0);
313 /* Handle per transfer options for bpw and speed */
314 if (transfer->speed_hz != dws->current_freq) {
315 if (transfer->speed_hz != chip->speed_hz) {
316 /* clk_div doesn't support odd number */
317 chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
318 chip->speed_hz = transfer->speed_hz;
320 dws->current_freq = transfer->speed_hz;
321 spi_set_clk(dws, chip->clk_div);
323 if (transfer->bits_per_word == 8) {
326 } else if (transfer->bits_per_word == 16) {
332 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
333 cr0 = (transfer->bits_per_word - 1)
334 | (chip->type << SPI_FRF_OFFSET)
335 | (spi->mode << SPI_MODE_OFFSET)
336 | (chip->tmode << SPI_TMOD_OFFSET);
339 * Adjust transfer mode if necessary. Requires platform dependent
340 * chipselect mechanism.
342 if (chip->cs_control) {
343 if (dws->rx && dws->tx)
344 chip->tmode = SPI_TMOD_TR;
346 chip->tmode = SPI_TMOD_RO;
348 chip->tmode = SPI_TMOD_TO;
350 cr0 &= ~SPI_TMOD_MASK;
351 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
354 dw_writel(dws, DW_SPI_CTRL0, cr0);
356 /* Check if current transfer is a DMA transaction */
357 if (master->can_dma && master->can_dma(master, spi, transfer))
358 dws->dma_mapped = master->cur_msg_mapped;
360 /* For poll mode just disable all interrupts */
361 spi_mask_intr(dws, 0xff);
365 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
367 if (dws->dma_mapped) {
368 ret = dws->dma_ops->dma_setup(dws, transfer);
370 spi_enable_chip(dws, 1);
373 } else if (!chip->poll_mode) {
374 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
375 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
377 /* Set the interrupt mask */
378 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
379 SPI_INT_RXUI | SPI_INT_RXOI;
380 spi_umask_intr(dws, imask);
382 dws->transfer_handler = interrupt_transfer;
385 spi_enable_chip(dws, 1);
388 return dws->dma_ops->dma_transfer(dws, transfer);
391 return poll_transfer(dws);
396 static void dw_spi_handle_err(struct spi_master *master,
397 struct spi_message *msg)
399 struct dw_spi *dws = spi_master_get_devdata(master);
402 dws->dma_ops->dma_stop(dws);
407 /* This may be called twice for each spi dev */
408 static int dw_spi_setup(struct spi_device *spi)
410 struct dw_spi_chip *chip_info = NULL;
411 struct chip_data *chip;
414 /* Only alloc on first setup */
415 chip = spi_get_ctldata(spi);
417 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
420 spi_set_ctldata(spi, chip);
424 * Protocol drivers may change the chip settings, so...
425 * if chip_info exists, use it
427 chip_info = spi->controller_data;
429 /* chip_info doesn't always exist */
431 if (chip_info->cs_control)
432 chip->cs_control = chip_info->cs_control;
434 chip->poll_mode = chip_info->poll_mode;
435 chip->type = chip_info->type;
438 chip->tmode = SPI_TMOD_TR;
440 if (gpio_is_valid(spi->cs_gpio)) {
441 ret = gpio_direction_output(spi->cs_gpio,
442 !(spi->mode & SPI_CS_HIGH));
450 static void dw_spi_cleanup(struct spi_device *spi)
452 struct chip_data *chip = spi_get_ctldata(spi);
455 spi_set_ctldata(spi, NULL);
458 /* Restart the controller, disable all interrupts, clean rx fifo */
459 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
464 * Try to detect the FIFO depth if not set by interface driver,
465 * the depth could be from 2 to 256 from HW spec
467 if (!dws->fifo_len) {
470 for (fifo = 1; fifo < 256; fifo++) {
471 dw_writel(dws, DW_SPI_TXFLTR, fifo);
472 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
475 dw_writel(dws, DW_SPI_TXFLTR, 0);
477 dws->fifo_len = (fifo == 1) ? 0 : fifo;
478 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
482 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
484 struct spi_master *master;
489 master = spi_alloc_master(dev, 0);
493 dws->master = master;
494 dws->type = SSI_MOTO_SPI;
496 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
497 spin_lock_init(&dws->buf_lock);
499 spi_master_set_devdata(master, dws);
501 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
504 dev_err(dev, "can not get IRQ\n");
505 goto err_free_master;
508 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
509 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
510 master->bus_num = dws->bus_num;
511 master->num_chipselect = dws->num_cs;
512 master->setup = dw_spi_setup;
513 master->cleanup = dw_spi_cleanup;
514 master->set_cs = dw_spi_set_cs;
515 master->transfer_one = dw_spi_transfer_one;
516 master->handle_err = dw_spi_handle_err;
517 master->max_speed_hz = dws->max_freq;
518 master->dev.of_node = dev->of_node;
519 master->flags = SPI_MASTER_GPIO_SS;
522 spi_hw_init(dev, dws);
524 if (dws->dma_ops && dws->dma_ops->dma_init) {
525 ret = dws->dma_ops->dma_init(dws);
527 dev_warn(dev, "DMA init failed\n");
530 master->can_dma = dws->dma_ops->can_dma;
531 master->flags |= SPI_CONTROLLER_MUST_TX;
535 ret = spi_register_master(master);
537 dev_err(&master->dev, "problem registering spi master\n");
541 dw_spi_debugfs_init(dws);
545 if (dws->dma_ops && dws->dma_ops->dma_exit)
546 dws->dma_ops->dma_exit(dws);
547 spi_enable_chip(dws, 0);
548 free_irq(dws->irq, master);
550 spi_master_put(master);
553 EXPORT_SYMBOL_GPL(dw_spi_add_host);
555 void dw_spi_remove_host(struct dw_spi *dws)
557 dw_spi_debugfs_remove(dws);
559 spi_unregister_master(dws->master);
561 if (dws->dma_ops && dws->dma_ops->dma_exit)
562 dws->dma_ops->dma_exit(dws);
564 spi_shutdown_chip(dws);
566 free_irq(dws->irq, dws->master);
568 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
570 int dw_spi_suspend_host(struct dw_spi *dws)
574 ret = spi_master_suspend(dws->master);
578 spi_shutdown_chip(dws);
581 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
583 int dw_spi_resume_host(struct dw_spi *dws)
587 spi_hw_init(&dws->master->dev, dws);
588 ret = spi_master_resume(dws->master);
590 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
593 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
595 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
596 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
597 MODULE_LICENSE("GPL v2");