drivers/spi/spi-dw-mid.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/types.h>
  22
  23 #include "spi-dw.h"
  24
  25 #ifdef CONFIG_SPI_DW_MID_DMA
  26 #include <linux/pci.h>
  27 #include <linux/platform_data/dma-dw.h>
  28
  29 #define RX_BUSY         0
  30 #define TX_BUSY         1
  31
  32 static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
  33 static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
  34
  35 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  36 {
  37         struct dw_dma_slave *s = param;
  38
  39         if (s->dma_dev != chan->device->dev)
  40                 return false;
  41
  42         chan->private = s;
  43         return true;
  44 }
  45
  46 static int mid_spi_dma_init(struct dw_spi *dws)
  47 {
  48         struct pci_dev *dma_dev;
  49         struct dw_dma_slave *tx = dws->dma_tx;
  50         struct dw_dma_slave *rx = dws->dma_rx;
  51         dma_cap_mask_t mask;
  52
  53         /*
  54          * Get pci device for DMA controller, currently it could only
  55          * be the DMA controller of Medfield
  56          */
  57         dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  58         if (!dma_dev)
  59                 return -ENODEV;
  60
  61         dma_cap_zero(mask);
  62         dma_cap_set(DMA_SLAVE, mask);
  63
  64         /* 1. Init rx channel */
  65         rx->dma_dev = &dma_dev->dev;
  66         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx);
  67         if (!dws->rxchan)
  68                 goto err_exit;
  69         dws->master->dma_rx = dws->rxchan;
  70
  71         /* 2. Init tx channel */
  72         tx->dma_dev = &dma_dev->dev;
  73         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx);
  74         if (!dws->txchan)
  75                 goto free_rxchan;
  76         dws->master->dma_tx = dws->txchan;
  77
  78         dws->dma_inited = 1;
  79         return 0;
  80
  81 free_rxchan:
  82         dma_release_channel(dws->rxchan);
  83 err_exit:
  84         return -EBUSY;
  85 }
  86
  87 static void mid_spi_dma_exit(struct dw_spi *dws)
  88 {
  89         if (!dws->dma_inited)
  90                 return;
  91
  92         dmaengine_terminate_all(dws->txchan);
  93         dma_release_channel(dws->txchan);
  94
  95         dmaengine_terminate_all(dws->rxchan);
  96         dma_release_channel(dws->rxchan);
  97 }
  98
  99 static irqreturn_t dma_transfer(struct dw_spi *dws)
 100 {
 101         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 102
 103         if (!irq_status)
 104                 return IRQ_NONE;
 105
 106         dw_readl(dws, DW_SPI_ICR);
 107         spi_reset_chip(dws);
 108
 109         dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
 110         dws->master->cur_msg->status = -EIO;
 111         spi_finalize_current_transfer(dws->master);
 112         return IRQ_HANDLED;
 113 }
 114
 115 static bool mid_spi_can_dma(struct spi_master *master, struct spi_device *spi,
 116                 struct spi_transfer *xfer)
 117 {
 118         struct dw_spi *dws = spi_master_get_devdata(master);
 119
 120         if (!dws->dma_inited)
 121                 return false;
 122
 123         return xfer->len > dws->fifo_len;
 124 }
 125
 126 static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
 127         if (dma_width == 1)
 128                 return DMA_SLAVE_BUSWIDTH_1_BYTE;
 129         else if (dma_width == 2)
 130                 return DMA_SLAVE_BUSWIDTH_2_BYTES;
 131
 132         return DMA_SLAVE_BUSWIDTH_UNDEFINED;
 133 }
 134
 135 /*
 136  * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 137  * channel will clear a corresponding bit.
 138  */
 139 static void dw_spi_dma_tx_done(void *arg)
 140 {
 141         struct dw_spi *dws = arg;
 142
 143         clear_bit(TX_BUSY, &dws->dma_chan_busy);
 144         if (test_bit(RX_BUSY, &dws->dma_chan_busy))
 145                 return;
 146         spi_finalize_current_transfer(dws->master);
 147 }
 148
 149 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
 150                 struct spi_transfer *xfer)
 151 {
 152         struct dma_slave_config txconf;
 153         struct dma_async_tx_descriptor *txdesc;
 154
 155         if (!xfer->tx_buf)
 156                 return NULL;
 157
 158         memset(&txconf, 0, sizeof(txconf));
 159         txconf.direction = DMA_MEM_TO_DEV;
 160         txconf.dst_addr = dws->dma_addr;
 161         txconf.dst_maxburst = 16;
 162         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 163         txconf.dst_addr_width = convert_dma_width(dws->dma_width);
 164         txconf.device_fc = false;
 165
 166         dmaengine_slave_config(dws->txchan, &txconf);
 167
 168         txdesc = dmaengine_prep_slave_sg(dws->txchan,
 169                                 xfer->tx_sg.sgl,
 170                                 xfer->tx_sg.nents,
 171                                 DMA_MEM_TO_DEV,
 172                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 173         if (!txdesc)
 174                 return NULL;
 175
 176         txdesc->callback = dw_spi_dma_tx_done;
 177         txdesc->callback_param = dws;
 178
 179         return txdesc;
 180 }
 181
 182 /*
 183  * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 184  * channel will clear a corresponding bit.
 185  */
 186 static void dw_spi_dma_rx_done(void *arg)
 187 {
 188         struct dw_spi *dws = arg;
 189
 190         clear_bit(RX_BUSY, &dws->dma_chan_busy);
 191         if (test_bit(TX_BUSY, &dws->dma_chan_busy))
 192                 return;
 193         spi_finalize_current_transfer(dws->master);
 194 }
 195
 196 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
 197                 struct spi_transfer *xfer)
 198 {
 199         struct dma_slave_config rxconf;
 200         struct dma_async_tx_descriptor *rxdesc;
 201
 202         if (!xfer->rx_buf)
 203                 return NULL;
 204
 205         memset(&rxconf, 0, sizeof(rxconf));
 206         rxconf.direction = DMA_DEV_TO_MEM;
 207         rxconf.src_addr = dws->dma_addr;
 208         rxconf.src_maxburst = 16;
 209         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 210         rxconf.src_addr_width = convert_dma_width(dws->dma_width);
 211         rxconf.device_fc = false;
 212
 213         dmaengine_slave_config(dws->rxchan, &rxconf);
 214
 215         rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
 216                                 xfer->rx_sg.sgl,
 217                                 xfer->rx_sg.nents,
 218                                 DMA_DEV_TO_MEM,
 219                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 220         if (!rxdesc)
 221                 return NULL;
 222
 223         rxdesc->callback = dw_spi_dma_rx_done;
 224         rxdesc->callback_param = dws;
 225
 226         return rxdesc;
 227 }
 228
 229 static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
 230 {
 231         u16 imr = 0, dma_ctrl = 0;
 232
 233         dw_writel(dws, DW_SPI_DMARDLR, 0xf);
 234         dw_writel(dws, DW_SPI_DMATDLR, 0x10);
 235
 236         if (xfer->tx_buf) {
 237                 dma_ctrl |= SPI_DMA_TDMAE;
 238                 imr |= SPI_INT_TXOI;
 239         }
 240         if (xfer->rx_buf) {
 241                 dma_ctrl |= SPI_DMA_RDMAE;
 242                 imr |= SPI_INT_RXUI | SPI_INT_RXOI;
 243         }
 244         dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
 245
 246         /* Set the interrupt mask */
 247         spi_umask_intr(dws, imr);
 248
 249         dws->transfer_handler = dma_transfer;
 250
 251         return 0;
 252 }
 253
 254 static int mid_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
 255 {
 256         struct dma_async_tx_descriptor *txdesc, *rxdesc;
 257
 258         /* Prepare the TX dma transfer */
 259         txdesc = dw_spi_dma_prepare_tx(dws, xfer);
 260
 261         /* Prepare the RX dma transfer */
 262         rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
 263
 264         /* rx must be started before tx due to spi instinct */
 265         if (rxdesc) {
 266                 set_bit(RX_BUSY, &dws->dma_chan_busy);
 267                 dmaengine_submit(rxdesc);
 268                 dma_async_issue_pending(dws->rxchan);
 269         }
 270
 271         if (txdesc) {
 272                 set_bit(TX_BUSY, &dws->dma_chan_busy);
 273                 dmaengine_submit(txdesc);
 274                 dma_async_issue_pending(dws->txchan);
 275         }
 276
 277         return 1;
 278 }
 279
 280 static void mid_spi_dma_stop(struct dw_spi *dws)
 281 {
 282         if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
 283                 dmaengine_terminate_all(dws->txchan);
 284                 clear_bit(TX_BUSY, &dws->dma_chan_busy);
 285         }
 286         if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
 287                 dmaengine_terminate_all(dws->rxchan);
 288                 clear_bit(RX_BUSY, &dws->dma_chan_busy);
 289         }
 290 }
 291
 292 static struct dw_spi_dma_ops mid_dma_ops = {
 293         .dma_init       = mid_spi_dma_init,
 294         .dma_exit       = mid_spi_dma_exit,
 295         .dma_setup      = mid_spi_dma_setup,
 296         .can_dma        = mid_spi_can_dma,
 297         .dma_transfer   = mid_spi_dma_transfer,
 298         .dma_stop       = mid_spi_dma_stop,
 299 };
 300 #endif
 301
 302 /* Some specific info for SPI0 controller on Intel MID */
 303
 304 /* HW info for MRST Clk Control Unit, 32b reg per controller */
 305 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 306 #define MRST_CLK_SPI_REG        0xff11d86c
 307 #define CLK_SPI_BDIV_OFFSET     0
 308 #define CLK_SPI_BDIV_MASK       0x00000007
 309 #define CLK_SPI_CDIV_OFFSET     9
 310 #define CLK_SPI_CDIV_MASK       0x00000e00
 311 #define CLK_SPI_DISABLE_OFFSET  8
 312
 313 int dw_spi_mid_init(struct dw_spi *dws)
 314 {
 315         void __iomem *clk_reg;
 316         u32 clk_cdiv;
 317
 318         clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
 319         if (!clk_reg)
 320                 return -ENOMEM;
 321
 322         /* Get SPI controller operating freq info */
 323         clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
 324         clk_cdiv &= CLK_SPI_CDIV_MASK;
 325         clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
 326         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 327
 328         iounmap(clk_reg);
 329
 330 #ifdef CONFIG_SPI_DW_MID_DMA
 331         dws->dma_tx = &mid_dma_tx;
 332         dws->dma_rx = &mid_dma_rx;
 333         dws->dma_ops = &mid_dma_ops;
 334 #endif
 335         return 0;
 336 }