2 * Cadence SPI controller driver (master mode only)
4 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/spi/spi.h>
25 /* Name of this driver */
26 #define CDNS_SPI_NAME "cdns-spi"
28 /* Register offset definitions */
29 #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
30 #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
31 #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
32 #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
33 #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
34 #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
35 #define CDNS_SPI_DR 0x18 /* Delay Register, RW */
36 #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
37 #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
38 #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
39 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
41 #define SPI_AUTOSUSPEND_TIMEOUT 3000
43 * SPI Configuration Register bit Masks
45 * This register contains various control bits that affect the operation
46 * of the SPI controller
48 #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
49 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
50 #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
51 #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
52 #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
53 #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
54 #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
55 #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
56 #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
57 #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
58 #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
59 CDNS_SPI_CR_SSCTRL | \
60 CDNS_SPI_CR_SSFORCE | \
61 CDNS_SPI_CR_BAUD_DIV_4)
64 * SPI Configuration Register - Baud rate and slave select
66 * These are the values used in the calculation of baud rate divisor and
67 * setting the slave select.
70 #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
71 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
72 #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
73 #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
74 #define CDNS_SPI_SS0 0x1 /* Slave Select zero */
77 * SPI Interrupt Registers bit Masks
79 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
82 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83 #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
84 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
85 #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
87 #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
88 #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
91 * SPI Enable Register bit Masks
93 * This register is used to enable or disable the SPI controller
95 #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
96 #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
98 /* SPI FIFO depth in bytes */
99 #define CDNS_SPI_FIFO_DEPTH 128
101 /* Default number of chip select lines */
102 #define CDNS_SPI_DEFAULT_NUM_CS 4
105 * struct cdns_spi - This definition defines spi driver instance
106 * @regs: Virtual address of the SPI controller registers
107 * @ref_clk: Pointer to the peripheral clock
108 * @pclk: Pointer to the APB clock
109 * @speed_hz: Current SPI bus clock speed in Hz
110 * @txbuf: Pointer to the TX buffer
111 * @rxbuf: Pointer to the RX buffer
112 * @tx_bytes: Number of bytes left to transfer
113 * @rx_bytes: Number of bytes requested
114 * @dev_busy: Device busy flag
115 * @is_decoded_cs: Flag for decoder property set or not
121 unsigned int clk_rate;
131 /* Macros for the SPI controller read/write */
132 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
134 return readl_relaxed(xspi->regs + offset);
137 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
139 writel_relaxed(val, xspi->regs + offset);
143 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
144 * @xspi: Pointer to the cdns_spi structure
146 * On reset the SPI controller is configured to be in master mode, baud rate
147 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
148 * to 1 and size of the word to be transferred as 8 bit.
149 * This function initializes the SPI controller to disable and clear all the
150 * interrupts, enable manual slave select and manual start, deselect all the
151 * chip select lines, and enable the SPI controller.
153 static void cdns_spi_init_hw(struct cdns_spi *xspi)
155 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
157 if (xspi->is_decoded_cs)
158 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
160 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
161 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
163 /* Clear the RX FIFO */
164 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
165 cdns_spi_read(xspi, CDNS_SPI_RXD);
167 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
168 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
169 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
173 * cdns_spi_chipselect - Select or deselect the chip select line
174 * @spi: Pointer to the spi_device structure
175 * @is_high: Select(0) or deselect (1) the chip select line
177 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
179 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
182 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
185 /* Deselect the slave */
186 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
188 /* Select the slave */
189 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
190 if (!(xspi->is_decoded_cs))
191 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
195 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
199 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
203 * cdns_spi_config_clock_mode - Sets clock polarity and phase
204 * @spi: Pointer to the spi_device structure
206 * Sets the requested clock polarity and phase.
208 static void cdns_spi_config_clock_mode(struct spi_device *spi)
210 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
211 u32 ctrl_reg, new_ctrl_reg;
213 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
214 ctrl_reg = new_ctrl_reg;
216 /* Set the SPI clock phase and clock polarity */
217 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
218 if (spi->mode & SPI_CPHA)
219 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
220 if (spi->mode & SPI_CPOL)
221 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
223 if (new_ctrl_reg != ctrl_reg) {
225 * Just writing the CR register does not seem to apply the clock
226 * setting changes. This is problematic when changing the clock
227 * polarity as it will cause the SPI slave to see spurious clock
228 * transitions. To workaround the issue toggle the ER register.
230 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
231 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
232 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
237 * cdns_spi_config_clock_freq - Sets clock frequency
238 * @spi: Pointer to the spi_device structure
239 * @transfer: Pointer to the spi_transfer structure which provides
240 * information about next transfer setup parameters
242 * Sets the requested clock frequency.
243 * Note: If the requested frequency is not an exact match with what can be
244 * obtained using the prescalar value the driver sets the clock frequency which
245 * is lower than the requested frequency (maximum lower) for the transfer. If
246 * the requested frequency is higher or lower than that is supported by the SPI
247 * controller the driver will set the highest or lowest frequency supported by
250 static void cdns_spi_config_clock_freq(struct spi_device *spi,
251 struct spi_transfer *transfer)
253 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
254 u32 ctrl_reg, baud_rate_val;
255 unsigned long frequency;
257 frequency = xspi->clk_rate;
259 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
261 /* Set the clock frequency */
262 if (xspi->speed_hz != transfer->speed_hz) {
263 /* first valid value is 1 */
264 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
265 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
266 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
269 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
270 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
272 xspi->speed_hz = frequency / (2 << baud_rate_val);
274 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
278 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
279 * @spi: Pointer to the spi_device structure
280 * @transfer: Pointer to the spi_transfer structure which provides
281 * information about next transfer setup parameters
283 * Sets the operational mode of SPI controller for the next SPI transfer and
284 * sets the requested clock frequency.
288 static int cdns_spi_setup_transfer(struct spi_device *spi,
289 struct spi_transfer *transfer)
291 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
293 cdns_spi_config_clock_freq(spi, transfer);
295 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
296 __func__, spi->mode, spi->bits_per_word,
303 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
304 * @xspi: Pointer to the cdns_spi structure
306 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
308 unsigned long trans_cnt = 0;
310 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
311 (xspi->tx_bytes > 0)) {
313 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
315 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
323 * cdns_spi_irq - Interrupt service routine of the SPI controller
325 * @dev_id: Pointer to the xspi structure
327 * This function handles TX empty and Mode Fault interrupts only.
328 * On TX empty interrupt this function reads the received data from RX FIFO and
329 * fills the TX FIFO if there is any data remaining to be transferred.
330 * On Mode Fault interrupt this function indicates that transfer is completed,
331 * the SPI subsystem will identify the error as the remaining bytes to be
332 * transferred is non-zero.
334 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
336 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
338 struct spi_master *master = dev_id;
339 struct cdns_spi *xspi = spi_master_get_devdata(master);
340 u32 intr_status, status;
343 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
344 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
346 if (intr_status & CDNS_SPI_IXR_MODF) {
347 /* Indicate that transfer is completed, the SPI subsystem will
348 * identify the error as the remaining bytes to be
349 * transferred is non-zero
351 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
352 spi_finalize_current_transfer(master);
353 status = IRQ_HANDLED;
354 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
355 unsigned long trans_cnt;
357 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
359 /* Read out the data from the RX FIFO */
363 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
365 *xspi->rxbuf++ = data;
371 if (xspi->tx_bytes) {
372 /* There is more data to send */
373 cdns_spi_fill_tx_fifo(xspi);
375 /* Transfer is completed */
376 cdns_spi_write(xspi, CDNS_SPI_IDR,
377 CDNS_SPI_IXR_DEFAULT);
378 spi_finalize_current_transfer(master);
380 status = IRQ_HANDLED;
386 static int cdns_prepare_message(struct spi_master *master,
387 struct spi_message *msg)
389 cdns_spi_config_clock_mode(msg->spi);
394 * cdns_transfer_one - Initiates the SPI transfer
395 * @master: Pointer to spi_master structure
396 * @spi: Pointer to the spi_device structure
397 * @transfer: Pointer to the spi_transfer structure which provides
398 * information about next transfer parameters
400 * This function fills the TX FIFO, starts the SPI transfer and
401 * returns a positive transfer count so that core will wait for completion.
403 * Return: Number of bytes transferred in the last transfer
405 static int cdns_transfer_one(struct spi_master *master,
406 struct spi_device *spi,
407 struct spi_transfer *transfer)
409 struct cdns_spi *xspi = spi_master_get_devdata(master);
411 xspi->txbuf = transfer->tx_buf;
412 xspi->rxbuf = transfer->rx_buf;
413 xspi->tx_bytes = transfer->len;
414 xspi->rx_bytes = transfer->len;
416 cdns_spi_setup_transfer(spi, transfer);
418 cdns_spi_fill_tx_fifo(xspi);
420 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
421 return transfer->len;
425 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
426 * @master: Pointer to the spi_master structure which provides
427 * information about the controller.
429 * This function enables SPI master controller.
433 static int cdns_prepare_transfer_hardware(struct spi_master *master)
435 struct cdns_spi *xspi = spi_master_get_devdata(master);
437 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
443 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
444 * @master: Pointer to the spi_master structure which provides
445 * information about the controller.
447 * This function disables the SPI master controller.
451 static int cdns_unprepare_transfer_hardware(struct spi_master *master)
453 struct cdns_spi *xspi = spi_master_get_devdata(master);
455 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
461 * cdns_spi_probe - Probe method for the SPI driver
462 * @pdev: Pointer to the platform_device structure
464 * This function initializes the driver data structures and the hardware.
466 * Return: 0 on success and error value on error
468 static int cdns_spi_probe(struct platform_device *pdev)
471 struct spi_master *master;
472 struct cdns_spi *xspi;
473 struct resource *res;
476 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
480 xspi = spi_master_get_devdata(master);
481 master->dev.of_node = pdev->dev.of_node;
482 platform_set_drvdata(pdev, master);
484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
486 if (IS_ERR(xspi->regs)) {
487 ret = PTR_ERR(xspi->regs);
491 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
492 if (IS_ERR(xspi->pclk)) {
493 dev_err(&pdev->dev, "pclk clock not found.\n");
494 ret = PTR_ERR(xspi->pclk);
498 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
499 if (IS_ERR(xspi->ref_clk)) {
500 dev_err(&pdev->dev, "ref_clk clock not found.\n");
501 ret = PTR_ERR(xspi->ref_clk);
505 ret = clk_prepare_enable(xspi->pclk);
507 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
511 ret = clk_prepare_enable(xspi->ref_clk);
513 dev_err(&pdev->dev, "Unable to enable device clock.\n");
517 pm_runtime_enable(&pdev->dev);
518 pm_runtime_use_autosuspend(&pdev->dev);
519 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
520 pm_runtime_set_active(&pdev->dev);
522 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
524 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
526 master->num_chipselect = num_cs;
528 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
529 &xspi->is_decoded_cs);
531 xspi->is_decoded_cs = 0;
533 /* SPI controller initializations */
534 cdns_spi_init_hw(xspi);
536 pm_runtime_mark_last_busy(&pdev->dev);
537 pm_runtime_put_autosuspend(&pdev->dev);
539 irq = platform_get_irq(pdev, 0);
542 dev_err(&pdev->dev, "irq number is invalid\n");
546 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
547 0, pdev->name, master);
550 dev_err(&pdev->dev, "request_irq failed\n");
554 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
555 master->prepare_message = cdns_prepare_message;
556 master->transfer_one = cdns_transfer_one;
557 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
558 master->set_cs = cdns_spi_chipselect;
559 master->auto_runtime_pm = true;
560 master->mode_bits = SPI_CPOL | SPI_CPHA;
562 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
563 /* Set to default valid value */
564 master->max_speed_hz = xspi->clk_rate / 4;
565 xspi->speed_hz = master->max_speed_hz;
567 master->bits_per_word_mask = SPI_BPW_MASK(8);
569 ret = spi_register_master(master);
571 dev_err(&pdev->dev, "spi_register_master failed\n");
578 pm_runtime_set_suspended(&pdev->dev);
579 pm_runtime_disable(&pdev->dev);
580 clk_disable_unprepare(xspi->ref_clk);
582 clk_disable_unprepare(xspi->pclk);
584 spi_master_put(master);
589 * cdns_spi_remove - Remove method for the SPI driver
590 * @pdev: Pointer to the platform_device structure
592 * This function is called if a device is physically removed from the system or
593 * if the driver module is being unloaded. It frees all resources allocated to
596 * Return: 0 on success and error value on error
598 static int cdns_spi_remove(struct platform_device *pdev)
600 struct spi_master *master = platform_get_drvdata(pdev);
601 struct cdns_spi *xspi = spi_master_get_devdata(master);
603 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
605 clk_disable_unprepare(xspi->ref_clk);
606 clk_disable_unprepare(xspi->pclk);
607 pm_runtime_set_suspended(&pdev->dev);
608 pm_runtime_disable(&pdev->dev);
610 spi_unregister_master(master);
616 * cdns_spi_suspend - Suspend method for the SPI driver
617 * @dev: Address of the platform_device structure
619 * This function disables the SPI controller and
620 * changes the driver state to "suspend"
622 * Return: 0 on success and error value on error
624 static int __maybe_unused cdns_spi_suspend(struct device *dev)
626 struct platform_device *pdev = to_platform_device(dev);
627 struct spi_master *master = platform_get_drvdata(pdev);
629 return spi_master_suspend(master);
633 * cdns_spi_resume - Resume method for the SPI driver
634 * @dev: Address of the platform_device structure
636 * This function changes the driver state to "ready"
638 * Return: 0 on success and error value on error
640 static int __maybe_unused cdns_spi_resume(struct device *dev)
642 struct platform_device *pdev = to_platform_device(dev);
643 struct spi_master *master = platform_get_drvdata(pdev);
645 return spi_master_resume(master);
649 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
650 * @dev: Address of the platform_device structure
652 * This function enables the clocks
654 * Return: 0 on success and error value on error
656 static int __maybe_unused cnds_runtime_resume(struct device *dev)
658 struct spi_master *master = dev_get_drvdata(dev);
659 struct cdns_spi *xspi = spi_master_get_devdata(master);
662 ret = clk_prepare_enable(xspi->pclk);
664 dev_err(dev, "Cannot enable APB clock.\n");
668 ret = clk_prepare_enable(xspi->ref_clk);
670 dev_err(dev, "Cannot enable device clock.\n");
671 clk_disable(xspi->pclk);
678 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
679 * @dev: Address of the platform_device structure
681 * This function disables the clocks
685 static int __maybe_unused cnds_runtime_suspend(struct device *dev)
687 struct spi_master *master = dev_get_drvdata(dev);
688 struct cdns_spi *xspi = spi_master_get_devdata(master);
690 clk_disable_unprepare(xspi->ref_clk);
691 clk_disable_unprepare(xspi->pclk);
696 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
697 SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
698 cnds_runtime_resume, NULL)
699 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
702 static const struct of_device_id cdns_spi_of_match[] = {
703 { .compatible = "xlnx,zynq-spi-r1p6" },
704 { .compatible = "cdns,spi-r1p6" },
705 { /* end of table */ }
707 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
709 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
710 static struct platform_driver cdns_spi_driver = {
711 .probe = cdns_spi_probe,
712 .remove = cdns_spi_remove,
714 .name = CDNS_SPI_NAME,
715 .of_match_table = cdns_spi_of_match,
716 .pm = &cdns_spi_dev_pm_ops,
720 module_platform_driver(cdns_spi_driver);
722 MODULE_AUTHOR("Xilinx, Inc.");
723 MODULE_DESCRIPTION("Cadence SPI driver");
724 MODULE_LICENSE("GPL");