drivers/spi/spi-bcm63xx-hsspi.c

   1 /*
   2  * Broadcom BCM63XX High Speed SPI Controller driver
   3  *
   4  * Copyright 2000-2010 Broadcom Corporation
   5  * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
   6  *
   7  * Licensed under the GNU/GPL. See COPYING for details.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/mutex.h>
  22 #include <linux/of.h>
  23
  24 #define HSSPI_GLOBAL_CTRL_REG                   0x0
  25 #define GLOBAL_CTRL_CS_POLARITY_SHIFT           0
  26 #define GLOBAL_CTRL_CS_POLARITY_MASK            0x000000ff
  27 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT          8
  28 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK           0x0000ff00
  29 #define GLOBAL_CTRL_CLK_GATE_SSOFF              BIT(16)
  30 #define GLOBAL_CTRL_CLK_POLARITY                BIT(17)
  31 #define GLOBAL_CTRL_MOSI_IDLE                   BIT(18)
  32
  33 #define HSSPI_GLOBAL_EXT_TRIGGER_REG            0x4
  34
  35 #define HSSPI_INT_STATUS_REG                    0x8
  36 #define HSSPI_INT_STATUS_MASKED_REG             0xc
  37 #define HSSPI_INT_MASK_REG                      0x10
  38
  39 #define HSSPI_PINGx_CMD_DONE(i)                 BIT((i * 8) + 0)
  40 #define HSSPI_PINGx_RX_OVER(i)                  BIT((i * 8) + 1)
  41 #define HSSPI_PINGx_TX_UNDER(i)                 BIT((i * 8) + 2)
  42 #define HSSPI_PINGx_POLL_TIMEOUT(i)             BIT((i * 8) + 3)
  43 #define HSSPI_PINGx_CTRL_INVAL(i)               BIT((i * 8) + 4)
  44
  45 #define HSSPI_INT_CLEAR_ALL                     0xff001f1f
  46
  47 #define HSSPI_PINGPONG_COMMAND_REG(x)           (0x80 + (x) * 0x40)
  48 #define PINGPONG_CMD_COMMAND_MASK               0xf
  49 #define PINGPONG_COMMAND_NOOP                   0
  50 #define PINGPONG_COMMAND_START_NOW              1
  51 #define PINGPONG_COMMAND_START_TRIGGER          2
  52 #define PINGPONG_COMMAND_HALT                   3
  53 #define PINGPONG_COMMAND_FLUSH                  4
  54 #define PINGPONG_CMD_PROFILE_SHIFT              8
  55 #define PINGPONG_CMD_SS_SHIFT                   12
  56
  57 #define HSSPI_PINGPONG_STATUS_REG(x)            (0x84 + (x) * 0x40)
  58
  59 #define HSSPI_PROFILE_CLK_CTRL_REG(x)           (0x100 + (x) * 0x20)
  60 #define CLK_CTRL_FREQ_CTRL_MASK                 0x0000ffff
  61 #define CLK_CTRL_SPI_CLK_2X_SEL                 BIT(14)
  62 #define CLK_CTRL_ACCUM_RST_ON_LOOP              BIT(15)
  63
  64 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)        (0x104 + (x) * 0x20)
  65 #define SIGNAL_CTRL_LATCH_RISING                BIT(12)
  66 #define SIGNAL_CTRL_LAUNCH_RISING               BIT(13)
  67 #define SIGNAL_CTRL_ASYNC_INPUT_PATH            BIT(16)
  68
  69 #define HSSPI_PROFILE_MODE_CTRL_REG(x)          (0x108 + (x) * 0x20)
  70 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT       8
  71 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT       12
  72 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT       16
  73 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT       18
  74 #define MODE_CTRL_MODE_3WIRE                    BIT(20)
  75 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT         24
  76
  77 #define HSSPI_FIFO_REG(x)                       (0x200 + (x) * 0x200)
  78
  79
  80 #define HSSPI_OP_MULTIBIT                       BIT(11)
  81 #define HSSPI_OP_CODE_SHIFT                     13
  82 #define HSSPI_OP_SLEEP                          (0 << HSSPI_OP_CODE_SHIFT)
  83 #define HSSPI_OP_READ_WRITE                     (1 << HSSPI_OP_CODE_SHIFT)
  84 #define HSSPI_OP_WRITE                          (2 << HSSPI_OP_CODE_SHIFT)
  85 #define HSSPI_OP_READ                           (3 << HSSPI_OP_CODE_SHIFT)
  86 #define HSSPI_OP_SETIRQ                         (4 << HSSPI_OP_CODE_SHIFT)
  87
  88 #define HSSPI_BUFFER_LEN                        512
  89 #define HSSPI_OPCODE_LEN                        2
  90
  91 #define HSSPI_MAX_PREPEND_LEN                   15
  92
  93 #define HSSPI_MAX_SYNC_CLOCK                    30000000
  94
  95 #define HSSPI_SPI_MAX_CS                        8
  96 #define HSSPI_BUS_NUM                           1 /* 0 is legacy SPI */
  97
  98 struct bcm63xx_hsspi {
  99         struct completion done;
 100         struct mutex bus_mutex;
 101
 102         struct platform_device *pdev;
 103         struct clk *clk;
 104         void __iomem *regs;
 105         u8 __iomem *fifo;
 106
 107         u32 speed_hz;
 108         u8 cs_polarity;
 109 };
 110
 111 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
 112                                  bool active)
 113 {
 114         u32 reg;
 115
 116         mutex_lock(&bs->bus_mutex);
 117         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 118
 119         reg &= ~BIT(cs);
 120         if (active == !(bs->cs_polarity & BIT(cs)))
 121                 reg |= BIT(cs);
 122
 123         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 124         mutex_unlock(&bs->bus_mutex);
 125 }
 126
 127 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
 128                                   struct spi_device *spi, int hz)
 129 {
 130         unsigned int profile = spi->chip_select;
 131         u32 reg;
 132
 133         reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
 134         __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
 135                      bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
 136
 137         reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 138         if (hz > HSSPI_MAX_SYNC_CLOCK)
 139                 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
 140         else
 141                 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
 142         __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
 143
 144         mutex_lock(&bs->bus_mutex);
 145         /* setup clock polarity */
 146         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 147         reg &= ~GLOBAL_CTRL_CLK_POLARITY;
 148         if (spi->mode & SPI_CPOL)
 149                 reg |= GLOBAL_CTRL_CLK_POLARITY;
 150         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 151         mutex_unlock(&bs->bus_mutex);
 152 }
 153
 154 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
 155 {
 156         struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 157         unsigned int chip_select = spi->chip_select;
 158         u16 opcode = 0;
 159         int pending = t->len;
 160         int step_size = HSSPI_BUFFER_LEN;
 161         const u8 *tx = t->tx_buf;
 162         u8 *rx = t->rx_buf;
 163         u32 val = 0;
 164
 165         bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
 166         bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
 167
 168         if (tx && rx)
 169                 opcode = HSSPI_OP_READ_WRITE;
 170         else if (tx)
 171                 opcode = HSSPI_OP_WRITE;
 172         else if (rx)
 173                 opcode = HSSPI_OP_READ;
 174
 175         if (opcode != HSSPI_OP_READ)
 176                 step_size -= HSSPI_OPCODE_LEN;
 177
 178         if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
 179             (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
 180                 opcode |= HSSPI_OP_MULTIBIT;
 181
 182                 if (t->rx_nbits == SPI_NBITS_DUAL)
 183                         val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
 184                 if (t->tx_nbits == SPI_NBITS_DUAL)
 185                         val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
 186         }
 187
 188         __raw_writel(val | 0xff,
 189                      bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
 190
 191         while (pending > 0) {
 192                 int curr_step = min_t(int, step_size, pending);
 193
 194                 reinit_completion(&bs->done);
 195                 if (tx) {
 196                         memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
 197                         tx += curr_step;
 198                 }
 199
 200                 __raw_writew(opcode | curr_step, bs->fifo);
 201
 202                 /* enable interrupt */
 203                 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
 204                              bs->regs + HSSPI_INT_MASK_REG);
 205
 206                 /* start the transfer */
 207                 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
 208                              chip_select << PINGPONG_CMD_PROFILE_SHIFT |
 209                              PINGPONG_COMMAND_START_NOW,
 210                              bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
 211
 212                 if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
 213                         dev_err(&bs->pdev->dev, "transfer timed out!\n");
 214                         return -ETIMEDOUT;
 215                 }
 216
 217                 if (rx) {
 218                         memcpy_fromio(rx, bs->fifo, curr_step);
 219                         rx += curr_step;
 220                 }
 221
 222                 pending -= curr_step;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int bcm63xx_hsspi_setup(struct spi_device *spi)
 229 {
 230         struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
 231         u32 reg;
 232
 233         reg = __raw_readl(bs->regs +
 234                           HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 235         reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
 236         if (spi->mode & SPI_CPHA)
 237                 reg |= SIGNAL_CTRL_LAUNCH_RISING;
 238         else
 239                 reg |= SIGNAL_CTRL_LATCH_RISING;
 240         __raw_writel(reg, bs->regs +
 241                      HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
 242
 243         mutex_lock(&bs->bus_mutex);
 244         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 245
 246         /* only change actual polarities if there is no transfer */
 247         if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
 248                 if (spi->mode & SPI_CS_HIGH)
 249                         reg |= BIT(spi->chip_select);
 250                 else
 251                         reg &= ~BIT(spi->chip_select);
 252                 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 253         }
 254
 255         if (spi->mode & SPI_CS_HIGH)
 256                 bs->cs_polarity |= BIT(spi->chip_select);
 257         else
 258                 bs->cs_polarity &= ~BIT(spi->chip_select);
 259
 260         mutex_unlock(&bs->bus_mutex);
 261
 262         return 0;
 263 }
 264
 265 static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
 266                                       struct spi_message *msg)
 267 {
 268         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 269         struct spi_transfer *t;
 270         struct spi_device *spi = msg->spi;
 271         int status = -EINVAL;
 272         int dummy_cs;
 273         u32 reg;
 274
 275         /* This controller does not support keeping CS active during idle.
 276          * To work around this, we use the following ugly hack:
 277          *
 278          * a. Invert the target chip select's polarity so it will be active.
 279          * b. Select a "dummy" chip select to use as the hardware target.
 280          * c. Invert the dummy chip select's polarity so it will be inactive
 281          *    during the actual transfers.
 282          * d. Tell the hardware to send to the dummy chip select. Thanks to
 283          *    the multiplexed nature of SPI the actual target will receive
 284          *    the transfer and we see its response.
 285          *
 286          * e. At the end restore the polarities again to their default values.
 287          */
 288
 289         dummy_cs = !spi->chip_select;
 290         bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
 291
 292         list_for_each_entry(t, &msg->transfers, transfer_list) {
 293                 status = bcm63xx_hsspi_do_txrx(spi, t);
 294                 if (status)
 295                         break;
 296
 297                 msg->actual_length += t->len;
 298
 299                 if (t->delay_usecs)
 300                         udelay(t->delay_usecs);
 301
 302                 if (t->cs_change)
 303                         bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
 304         }
 305
 306         mutex_lock(&bs->bus_mutex);
 307         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 308         reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
 309         reg |= bs->cs_polarity;
 310         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
 311         mutex_unlock(&bs->bus_mutex);
 312
 313         msg->status = status;
 314         spi_finalize_current_message(master);
 315
 316         return 0;
 317 }
 318
 319 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
 320 {
 321         struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
 322
 323         if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
 324                 return IRQ_NONE;
 325
 326         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 327         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 328
 329         complete(&bs->done);
 330
 331         return IRQ_HANDLED;
 332 }
 333
 334 static int bcm63xx_hsspi_probe(struct platform_device *pdev)
 335 {
 336         struct spi_master *master;
 337         struct bcm63xx_hsspi *bs;
 338         struct resource *res_mem;
 339         void __iomem *regs;
 340         struct device *dev = &pdev->dev;
 341         struct clk *clk;
 342         int irq, ret;
 343         u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
 344
 345         irq = platform_get_irq(pdev, 0);
 346         if (irq < 0) {
 347                 dev_err(dev, "no irq: %d\n", irq);
 348                 return irq;
 349         }
 350
 351         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 352         regs = devm_ioremap_resource(dev, res_mem);
 353         if (IS_ERR(regs))
 354                 return PTR_ERR(regs);
 355
 356         clk = devm_clk_get(dev, "hsspi");
 357
 358         if (IS_ERR(clk))
 359                 return PTR_ERR(clk);
 360
 361         rate = clk_get_rate(clk);
 362         if (!rate) {
 363                 struct clk *pll_clk = devm_clk_get(dev, "pll");
 364
 365                 if (IS_ERR(pll_clk))
 366                         return PTR_ERR(pll_clk);
 367
 368                 rate = clk_get_rate(pll_clk);
 369                 if (!rate)
 370                         return -EINVAL;
 371         }
 372
 373         ret = clk_prepare_enable(clk);
 374         if (ret)
 375                 return ret;
 376
 377         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 378         if (!master) {
 379                 ret = -ENOMEM;
 380                 goto out_disable_clk;
 381         }
 382
 383         bs = spi_master_get_devdata(master);
 384         bs->pdev = pdev;
 385         bs->clk = clk;
 386         bs->regs = regs;
 387         bs->speed_hz = rate;
 388         bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
 389
 390         mutex_init(&bs->bus_mutex);
 391         init_completion(&bs->done);
 392
 393         master->dev.of_node = dev->of_node;
 394         if (!dev->of_node)
 395                 master->bus_num = HSSPI_BUS_NUM;
 396
 397         of_property_read_u32(dev->of_node, "num-cs", &num_cs);
 398         if (num_cs > 8) {
 399                 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
 400                          num_cs);
 401                 num_cs = HSSPI_SPI_MAX_CS;
 402         }
 403         master->num_chipselect = num_cs;
 404         master->setup = bcm63xx_hsspi_setup;
 405         master->transfer_one_message = bcm63xx_hsspi_transfer_one;
 406         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
 407                             SPI_RX_DUAL | SPI_TX_DUAL;
 408         master->bits_per_word_mask = SPI_BPW_MASK(8);
 409         master->auto_runtime_pm = true;
 410
 411         platform_set_drvdata(pdev, master);
 412
 413         /* Initialize the hardware */
 414         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 415
 416         /* clean up any pending interrupts */
 417         __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
 418
 419         /* read out default CS polarities */
 420         reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
 421         bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
 422         __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
 423                      bs->regs + HSSPI_GLOBAL_CTRL_REG);
 424
 425         ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
 426                                pdev->name, bs);
 427
 428         if (ret)
 429                 goto out_put_master;
 430
 431         /* register and we are done */
 432         ret = devm_spi_register_master(dev, master);
 433         if (ret)
 434                 goto out_put_master;
 435
 436         return 0;
 437
 438 out_put_master:
 439         spi_master_put(master);
 440 out_disable_clk:
 441         clk_disable_unprepare(clk);
 442         return ret;
 443 }
 444
 445
 446 static int bcm63xx_hsspi_remove(struct platform_device *pdev)
 447 {
 448         struct spi_master *master = platform_get_drvdata(pdev);
 449         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 450
 451         /* reset the hardware and block queue progress */
 452         __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
 453         clk_disable_unprepare(bs->clk);
 454
 455         return 0;
 456 }
 457
 458 #ifdef CONFIG_PM_SLEEP
 459 static int bcm63xx_hsspi_suspend(struct device *dev)
 460 {
 461         struct spi_master *master = dev_get_drvdata(dev);
 462         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 463
 464         spi_master_suspend(master);
 465         clk_disable_unprepare(bs->clk);
 466
 467         return 0;
 468 }
 469
 470 static int bcm63xx_hsspi_resume(struct device *dev)
 471 {
 472         struct spi_master *master = dev_get_drvdata(dev);
 473         struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
 474         int ret;
 475
 476         ret = clk_prepare_enable(bs->clk);
 477         if (ret)
 478                 return ret;
 479
 480         spi_master_resume(master);
 481
 482         return 0;
 483 }
 484 #endif
 485
 486 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
 487                          bcm63xx_hsspi_resume);
 488
 489 static const struct of_device_id bcm63xx_hsspi_of_match[] = {
 490         { .compatible = "brcm,bcm6328-hsspi", },
 491         { },
 492 };
 493 MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
 494
 495 static struct platform_driver bcm63xx_hsspi_driver = {
 496         .driver = {
 497                 .name   = "bcm63xx-hsspi",
 498                 .pm     = &bcm63xx_hsspi_pm_ops,
 499                 .of_match_table = bcm63xx_hsspi_of_match,
 500         },
 501         .probe          = bcm63xx_hsspi_probe,
 502         .remove         = bcm63xx_hsspi_remove,
 503 };
 504
 505 module_platform_driver(bcm63xx_hsspi_driver);
 506
 507 MODULE_ALIAS("platform:bcm63xx_hsspi");
 508 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
 509 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
 510 MODULE_LICENSE("GPL");