2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/dma-atmel.h>
26 #include <linux/gpio.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pm_runtime.h>
31 /* SPI register offsets */
34 #define SPI_RDR 0x0008
35 #define SPI_TDR 0x000c
37 #define SPI_IER 0x0014
38 #define SPI_IDR 0x0018
39 #define SPI_IMR 0x001c
40 #define SPI_CSR0 0x0030
41 #define SPI_CSR1 0x0034
42 #define SPI_CSR2 0x0038
43 #define SPI_CSR3 0x003c
44 #define SPI_FMR 0x0040
45 #define SPI_FLR 0x0044
46 #define SPI_VERSION 0x00fc
47 #define SPI_RPR 0x0100
48 #define SPI_RCR 0x0104
49 #define SPI_TPR 0x0108
50 #define SPI_TCR 0x010c
51 #define SPI_RNPR 0x0110
52 #define SPI_RNCR 0x0114
53 #define SPI_TNPR 0x0118
54 #define SPI_TNCR 0x011c
55 #define SPI_PTCR 0x0120
56 #define SPI_PTSR 0x0124
59 #define SPI_SPIEN_OFFSET 0
60 #define SPI_SPIEN_SIZE 1
61 #define SPI_SPIDIS_OFFSET 1
62 #define SPI_SPIDIS_SIZE 1
63 #define SPI_SWRST_OFFSET 7
64 #define SPI_SWRST_SIZE 1
65 #define SPI_LASTXFER_OFFSET 24
66 #define SPI_LASTXFER_SIZE 1
67 #define SPI_TXFCLR_OFFSET 16
68 #define SPI_TXFCLR_SIZE 1
69 #define SPI_RXFCLR_OFFSET 17
70 #define SPI_RXFCLR_SIZE 1
71 #define SPI_FIFOEN_OFFSET 30
72 #define SPI_FIFOEN_SIZE 1
73 #define SPI_FIFODIS_OFFSET 31
74 #define SPI_FIFODIS_SIZE 1
77 #define SPI_MSTR_OFFSET 0
78 #define SPI_MSTR_SIZE 1
79 #define SPI_PS_OFFSET 1
81 #define SPI_PCSDEC_OFFSET 2
82 #define SPI_PCSDEC_SIZE 1
83 #define SPI_FDIV_OFFSET 3
84 #define SPI_FDIV_SIZE 1
85 #define SPI_MODFDIS_OFFSET 4
86 #define SPI_MODFDIS_SIZE 1
87 #define SPI_WDRBT_OFFSET 5
88 #define SPI_WDRBT_SIZE 1
89 #define SPI_LLB_OFFSET 7
90 #define SPI_LLB_SIZE 1
91 #define SPI_PCS_OFFSET 16
92 #define SPI_PCS_SIZE 4
93 #define SPI_DLYBCS_OFFSET 24
94 #define SPI_DLYBCS_SIZE 8
96 /* Bitfields in RDR */
97 #define SPI_RD_OFFSET 0
98 #define SPI_RD_SIZE 16
100 /* Bitfields in TDR */
101 #define SPI_TD_OFFSET 0
102 #define SPI_TD_SIZE 16
104 /* Bitfields in SR */
105 #define SPI_RDRF_OFFSET 0
106 #define SPI_RDRF_SIZE 1
107 #define SPI_TDRE_OFFSET 1
108 #define SPI_TDRE_SIZE 1
109 #define SPI_MODF_OFFSET 2
110 #define SPI_MODF_SIZE 1
111 #define SPI_OVRES_OFFSET 3
112 #define SPI_OVRES_SIZE 1
113 #define SPI_ENDRX_OFFSET 4
114 #define SPI_ENDRX_SIZE 1
115 #define SPI_ENDTX_OFFSET 5
116 #define SPI_ENDTX_SIZE 1
117 #define SPI_RXBUFF_OFFSET 6
118 #define SPI_RXBUFF_SIZE 1
119 #define SPI_TXBUFE_OFFSET 7
120 #define SPI_TXBUFE_SIZE 1
121 #define SPI_NSSR_OFFSET 8
122 #define SPI_NSSR_SIZE 1
123 #define SPI_TXEMPTY_OFFSET 9
124 #define SPI_TXEMPTY_SIZE 1
125 #define SPI_SPIENS_OFFSET 16
126 #define SPI_SPIENS_SIZE 1
127 #define SPI_TXFEF_OFFSET 24
128 #define SPI_TXFEF_SIZE 1
129 #define SPI_TXFFF_OFFSET 25
130 #define SPI_TXFFF_SIZE 1
131 #define SPI_TXFTHF_OFFSET 26
132 #define SPI_TXFTHF_SIZE 1
133 #define SPI_RXFEF_OFFSET 27
134 #define SPI_RXFEF_SIZE 1
135 #define SPI_RXFFF_OFFSET 28
136 #define SPI_RXFFF_SIZE 1
137 #define SPI_RXFTHF_OFFSET 29
138 #define SPI_RXFTHF_SIZE 1
139 #define SPI_TXFPTEF_OFFSET 30
140 #define SPI_TXFPTEF_SIZE 1
141 #define SPI_RXFPTEF_OFFSET 31
142 #define SPI_RXFPTEF_SIZE 1
144 /* Bitfields in CSR0 */
145 #define SPI_CPOL_OFFSET 0
146 #define SPI_CPOL_SIZE 1
147 #define SPI_NCPHA_OFFSET 1
148 #define SPI_NCPHA_SIZE 1
149 #define SPI_CSAAT_OFFSET 3
150 #define SPI_CSAAT_SIZE 1
151 #define SPI_BITS_OFFSET 4
152 #define SPI_BITS_SIZE 4
153 #define SPI_SCBR_OFFSET 8
154 #define SPI_SCBR_SIZE 8
155 #define SPI_DLYBS_OFFSET 16
156 #define SPI_DLYBS_SIZE 8
157 #define SPI_DLYBCT_OFFSET 24
158 #define SPI_DLYBCT_SIZE 8
160 /* Bitfields in RCR */
161 #define SPI_RXCTR_OFFSET 0
162 #define SPI_RXCTR_SIZE 16
164 /* Bitfields in TCR */
165 #define SPI_TXCTR_OFFSET 0
166 #define SPI_TXCTR_SIZE 16
168 /* Bitfields in RNCR */
169 #define SPI_RXNCR_OFFSET 0
170 #define SPI_RXNCR_SIZE 16
172 /* Bitfields in TNCR */
173 #define SPI_TXNCR_OFFSET 0
174 #define SPI_TXNCR_SIZE 16
176 /* Bitfields in PTCR */
177 #define SPI_RXTEN_OFFSET 0
178 #define SPI_RXTEN_SIZE 1
179 #define SPI_RXTDIS_OFFSET 1
180 #define SPI_RXTDIS_SIZE 1
181 #define SPI_TXTEN_OFFSET 8
182 #define SPI_TXTEN_SIZE 1
183 #define SPI_TXTDIS_OFFSET 9
184 #define SPI_TXTDIS_SIZE 1
186 /* Bitfields in FMR */
187 #define SPI_TXRDYM_OFFSET 0
188 #define SPI_TXRDYM_SIZE 2
189 #define SPI_RXRDYM_OFFSET 4
190 #define SPI_RXRDYM_SIZE 2
191 #define SPI_TXFTHRES_OFFSET 16
192 #define SPI_TXFTHRES_SIZE 6
193 #define SPI_RXFTHRES_OFFSET 24
194 #define SPI_RXFTHRES_SIZE 6
196 /* Bitfields in FLR */
197 #define SPI_TXFL_OFFSET 0
198 #define SPI_TXFL_SIZE 6
199 #define SPI_RXFL_OFFSET 16
200 #define SPI_RXFL_SIZE 6
202 /* Constants for BITS */
203 #define SPI_BITS_8_BPT 0
204 #define SPI_BITS_9_BPT 1
205 #define SPI_BITS_10_BPT 2
206 #define SPI_BITS_11_BPT 3
207 #define SPI_BITS_12_BPT 4
208 #define SPI_BITS_13_BPT 5
209 #define SPI_BITS_14_BPT 6
210 #define SPI_BITS_15_BPT 7
211 #define SPI_BITS_16_BPT 8
212 #define SPI_ONE_DATA 0
213 #define SPI_TWO_DATA 1
214 #define SPI_FOUR_DATA 2
216 /* Bit manipulation macros */
217 #define SPI_BIT(name) \
218 (1 << SPI_##name##_OFFSET)
219 #define SPI_BF(name, value) \
220 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
221 #define SPI_BFEXT(name, value) \
222 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
223 #define SPI_BFINS(name, value, old) \
224 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225 | SPI_BF(name, value))
227 /* Register access macros */
229 #define spi_readl(port, reg) \
230 __raw_readl((port)->regs + SPI_##reg)
231 #define spi_writel(port, reg, value) \
232 __raw_writel((value), (port)->regs + SPI_##reg)
234 #define spi_readw(port, reg) \
235 __raw_readw((port)->regs + SPI_##reg)
236 #define spi_writew(port, reg, value) \
237 __raw_writew((value), (port)->regs + SPI_##reg)
239 #define spi_readb(port, reg) \
240 __raw_readb((port)->regs + SPI_##reg)
241 #define spi_writeb(port, reg, value) \
242 __raw_writeb((value), (port)->regs + SPI_##reg)
244 #define spi_readl(port, reg) \
245 readl_relaxed((port)->regs + SPI_##reg)
246 #define spi_writel(port, reg, value) \
247 writel_relaxed((value), (port)->regs + SPI_##reg)
249 #define spi_readw(port, reg) \
250 readw_relaxed((port)->regs + SPI_##reg)
251 #define spi_writew(port, reg, value) \
252 writew_relaxed((value), (port)->regs + SPI_##reg)
254 #define spi_readb(port, reg) \
255 readb_relaxed((port)->regs + SPI_##reg)
256 #define spi_writeb(port, reg, value) \
257 writeb_relaxed((value), (port)->regs + SPI_##reg)
259 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
260 * cache operations; better heuristics consider wordsize and bitrate.
262 #define DMA_MIN_BYTES 16
264 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
266 #define AUTOSUSPEND_TIMEOUT 2000
268 struct atmel_spi_caps {
271 bool has_dma_support;
272 bool has_pdc_support;
276 * The core SPI transfer engine just talks to a register bank to set up
277 * DMA transfers; transfer queue progress is driven by IRQs. The clock
278 * framework provides the base clock, subdivided for each spi_device.
288 struct platform_device *pdev;
289 unsigned long spi_clk;
291 struct spi_transfer *current_transfer;
292 int current_remaining_bytes;
295 struct completion xfer_completion;
297 struct atmel_spi_caps caps;
308 /* Controller-specific per-slave state */
309 struct atmel_spi_device {
310 unsigned int npcs_pin;
314 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
315 #define INVALID_DMA_ADDRESS 0xffffffff
318 * Version 2 of the SPI controller has
320 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
321 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
323 * - SPI_CSRx.SBCR allows faster clocking
325 static bool atmel_spi_is_v2(struct atmel_spi *as)
327 return as->caps.is_spi2;
331 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
332 * they assume that spi slave device state will not change on deselect, so
333 * that automagic deselection is OK. ("NPCSx rises if no data is to be
334 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
335 * controllers have CSAAT and friends.
337 * Since the CSAAT functionality is a bit weird on newer controllers as
338 * well, we use GPIO to control nCSx pins on all controllers, updating
339 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
340 * support active-high chipselects despite the controller's belief that
341 * only active-low devices/systems exists.
343 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
344 * right when driven with GPIO. ("Mode Fault does not allow more than one
345 * Master on Chip Select 0.") No workaround exists for that ... so for
346 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
347 * and (c) will trigger that first erratum in some cases.
350 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
352 struct atmel_spi_device *asd = spi->controller_state;
353 unsigned active = spi->mode & SPI_CS_HIGH;
356 if (atmel_spi_is_v2(as)) {
357 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
358 /* For the low SPI version, there is a issue that PDC transfer
359 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
361 spi_writel(as, CSR0, asd->csr);
362 if (as->caps.has_wdrbt) {
364 SPI_BF(PCS, ~(0x01 << spi->chip_select))
370 SPI_BF(PCS, ~(0x01 << spi->chip_select))
375 mr = spi_readl(as, MR);
376 if (as->use_cs_gpios)
377 gpio_set_value(asd->npcs_pin, active);
379 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
383 /* Make sure clock polarity is correct */
384 for (i = 0; i < spi->master->num_chipselect; i++) {
385 csr = spi_readl(as, CSR0 + 4 * i);
386 if ((csr ^ cpol) & SPI_BIT(CPOL))
387 spi_writel(as, CSR0 + 4 * i,
388 csr ^ SPI_BIT(CPOL));
391 mr = spi_readl(as, MR);
392 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
393 if (as->use_cs_gpios && spi->chip_select != 0)
394 gpio_set_value(asd->npcs_pin, active);
395 spi_writel(as, MR, mr);
398 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
399 asd->npcs_pin, active ? " (high)" : "",
403 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
405 struct atmel_spi_device *asd = spi->controller_state;
406 unsigned active = spi->mode & SPI_CS_HIGH;
409 /* only deactivate *this* device; sometimes transfers to
410 * another device may be active when this routine is called.
412 mr = spi_readl(as, MR);
413 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
414 mr = SPI_BFINS(PCS, 0xf, mr);
415 spi_writel(as, MR, mr);
418 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
419 asd->npcs_pin, active ? " (low)" : "",
422 if (!as->use_cs_gpios)
423 spi_writel(as, CR, SPI_BIT(LASTXFER));
424 else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
425 gpio_set_value(asd->npcs_pin, !active);
428 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
430 spin_lock_irqsave(&as->lock, as->flags);
433 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
435 spin_unlock_irqrestore(&as->lock, as->flags);
438 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
439 struct spi_transfer *xfer)
441 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
444 static bool atmel_spi_can_dma(struct spi_master *master,
445 struct spi_device *spi,
446 struct spi_transfer *xfer)
448 struct atmel_spi *as = spi_master_get_devdata(master);
450 return atmel_spi_use_dma(as, xfer);
453 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
454 struct dma_slave_config *slave_config,
457 struct spi_master *master = platform_get_drvdata(as->pdev);
460 if (bits_per_word > 8) {
461 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
462 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
464 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
465 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
468 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
469 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
470 slave_config->src_maxburst = 1;
471 slave_config->dst_maxburst = 1;
472 slave_config->device_fc = false;
475 * This driver uses fixed peripheral select mode (PS bit set to '0' in
476 * the Mode Register).
477 * So according to the datasheet, when FIFOs are available (and
478 * enabled), the Transmit FIFO operates in Multiple Data Mode.
479 * In this mode, up to 2 data, not 4, can be written into the Transmit
480 * Data Register in a single access.
481 * However, the first data has to be written into the lowest 16 bits and
482 * the second data into the highest 16 bits of the Transmit
483 * Data Register. For 8bit data (the most frequent case), it would
484 * require to rework tx_buf so each data would actualy fit 16 bits.
485 * So we'd rather write only one data at the time. Hence the transmit
486 * path works the same whether FIFOs are available (and enabled) or not.
488 slave_config->direction = DMA_MEM_TO_DEV;
489 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
490 dev_err(&as->pdev->dev,
491 "failed to configure tx dma channel\n");
496 * This driver configures the spi controller for master mode (MSTR bit
497 * set to '1' in the Mode Register).
498 * So according to the datasheet, when FIFOs are available (and
499 * enabled), the Receive FIFO operates in Single Data Mode.
500 * So the receive path works the same whether FIFOs are available (and
503 slave_config->direction = DMA_DEV_TO_MEM;
504 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
505 dev_err(&as->pdev->dev,
506 "failed to configure rx dma channel\n");
513 static int atmel_spi_configure_dma(struct spi_master *master,
514 struct atmel_spi *as)
516 struct dma_slave_config slave_config;
517 struct device *dev = &as->pdev->dev;
522 dma_cap_set(DMA_SLAVE, mask);
524 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
525 if (IS_ERR(master->dma_tx)) {
526 err = PTR_ERR(master->dma_tx);
527 if (err == -EPROBE_DEFER) {
528 dev_warn(dev, "no DMA channel available at the moment\n");
532 "DMA TX channel not available, SPI unable to use DMA\n");
538 * No reason to check EPROBE_DEFER here since we have already requested
539 * tx channel. If it fails here, it's for another reason.
541 master->dma_rx = dma_request_slave_channel(dev, "rx");
543 if (!master->dma_rx) {
545 "DMA RX channel not available, SPI unable to use DMA\n");
550 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
554 dev_info(&as->pdev->dev,
555 "Using %s (tx) and %s (rx) for DMA transfers\n",
556 dma_chan_name(master->dma_tx),
557 dma_chan_name(master->dma_rx));
562 dma_release_channel(master->dma_rx);
563 if (!IS_ERR(master->dma_tx))
564 dma_release_channel(master->dma_tx);
566 master->dma_tx = master->dma_rx = NULL;
570 static void atmel_spi_stop_dma(struct spi_master *master)
573 dmaengine_terminate_all(master->dma_rx);
575 dmaengine_terminate_all(master->dma_tx);
578 static void atmel_spi_release_dma(struct spi_master *master)
580 if (master->dma_rx) {
581 dma_release_channel(master->dma_rx);
582 master->dma_rx = NULL;
584 if (master->dma_tx) {
585 dma_release_channel(master->dma_tx);
586 master->dma_tx = NULL;
590 /* This function is called by the DMA driver from tasklet context */
591 static void dma_callback(void *data)
593 struct spi_master *master = data;
594 struct atmel_spi *as = spi_master_get_devdata(master);
596 complete(&as->xfer_completion);
600 * Next transfer using PIO without FIFO.
602 static void atmel_spi_next_xfer_single(struct spi_master *master,
603 struct spi_transfer *xfer)
605 struct atmel_spi *as = spi_master_get_devdata(master);
606 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
608 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
610 /* Make sure data is not remaining in RDR */
612 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
617 if (xfer->bits_per_word > 8)
618 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
620 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
622 dev_dbg(master->dev.parent,
623 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
624 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
625 xfer->bits_per_word);
627 /* Enable relevant interrupts */
628 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
632 * Next transfer using PIO with FIFO.
634 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
635 struct spi_transfer *xfer)
637 struct atmel_spi *as = spi_master_get_devdata(master);
638 u32 current_remaining_data, num_data;
639 u32 offset = xfer->len - as->current_remaining_bytes;
640 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
641 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
645 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
647 /* Compute the number of data to transfer in the current iteration */
648 current_remaining_data = ((xfer->bits_per_word > 8) ?
649 ((u32)as->current_remaining_bytes >> 1) :
650 (u32)as->current_remaining_bytes);
651 num_data = min(current_remaining_data, as->fifo_size);
653 /* Flush RX and TX FIFOs */
654 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
655 while (spi_readl(as, FLR))
658 /* Set RX FIFO Threshold to the number of data to transfer */
659 fifomr = spi_readl(as, FMR);
660 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
662 /* Clear FIFO flags in the Status Register, especially RXFTHF */
663 (void)spi_readl(as, SR);
666 while (num_data >= 2) {
667 if (xfer->bits_per_word > 8) {
675 spi_writel(as, TDR, (td1 << 16) | td0);
680 if (xfer->bits_per_word > 8)
685 spi_writew(as, TDR, td0);
689 dev_dbg(master->dev.parent,
690 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
691 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
692 xfer->bits_per_word);
695 * Enable RX FIFO Threshold Flag interrupt to be notified about
696 * transfer completion.
698 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
702 * Next transfer using PIO.
704 static void atmel_spi_next_xfer_pio(struct spi_master *master,
705 struct spi_transfer *xfer)
707 struct atmel_spi *as = spi_master_get_devdata(master);
710 atmel_spi_next_xfer_fifo(master, xfer);
712 atmel_spi_next_xfer_single(master, xfer);
716 * Submit next transfer for DMA.
718 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
719 struct spi_transfer *xfer,
722 struct atmel_spi *as = spi_master_get_devdata(master);
723 struct dma_chan *rxchan = master->dma_rx;
724 struct dma_chan *txchan = master->dma_tx;
725 struct dma_async_tx_descriptor *rxdesc;
726 struct dma_async_tx_descriptor *txdesc;
727 struct dma_slave_config slave_config;
730 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
732 /* Check that the channels are available */
733 if (!rxchan || !txchan)
736 /* release lock for DMA operations */
737 atmel_spi_unlock(as);
741 if (atmel_spi_dma_slave_config(as, &slave_config,
742 xfer->bits_per_word))
745 /* Send both scatterlists */
746 rxdesc = dmaengine_prep_slave_sg(rxchan,
747 xfer->rx_sg.sgl, xfer->rx_sg.nents,
749 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
753 txdesc = dmaengine_prep_slave_sg(txchan,
754 xfer->tx_sg.sgl, xfer->tx_sg.nents,
756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
760 dev_dbg(master->dev.parent,
761 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
762 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
763 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
765 /* Enable relevant interrupts */
766 spi_writel(as, IER, SPI_BIT(OVRES));
768 /* Put the callback on the RX transfer only, that should finish last */
769 rxdesc->callback = dma_callback;
770 rxdesc->callback_param = master;
772 /* Submit and fire RX and TX with TX last so we're ready to read! */
773 cookie = rxdesc->tx_submit(rxdesc);
774 if (dma_submit_error(cookie))
776 cookie = txdesc->tx_submit(txdesc);
777 if (dma_submit_error(cookie))
779 rxchan->device->device_issue_pending(rxchan);
780 txchan->device->device_issue_pending(txchan);
787 spi_writel(as, IDR, SPI_BIT(OVRES));
788 atmel_spi_stop_dma(master);
794 static void atmel_spi_next_xfer_data(struct spi_master *master,
795 struct spi_transfer *xfer,
800 *rx_dma = xfer->rx_dma + xfer->len - *plen;
801 *tx_dma = xfer->tx_dma + xfer->len - *plen;
802 if (*plen > master->max_dma_len)
803 *plen = master->max_dma_len;
806 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
807 struct spi_device *spi,
808 struct spi_transfer *xfer)
811 unsigned long bus_hz;
813 /* v1 chips start out at half the peripheral bus speed. */
814 bus_hz = as->spi_clk;
815 if (!atmel_spi_is_v2(as))
819 * Calculate the lowest divider that satisfies the
820 * constraint, assuming div32/fdiv/mbz == 0.
822 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
825 * If the resulting divider doesn't fit into the
826 * register bitfield, we can't satisfy the constraint.
828 if (scbr >= (1 << SPI_SCBR_SIZE)) {
830 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
831 xfer->speed_hz, scbr, bus_hz/255);
836 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
837 xfer->speed_hz, scbr, bus_hz);
840 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
841 csr = SPI_BFINS(SCBR, scbr, csr);
842 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
848 * Submit next transfer for PDC.
849 * lock is held, spi irq is blocked
851 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
852 struct spi_message *msg,
853 struct spi_transfer *xfer)
855 struct atmel_spi *as = spi_master_get_devdata(master);
857 dma_addr_t tx_dma, rx_dma;
859 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
861 len = as->current_remaining_bytes;
862 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
863 as->current_remaining_bytes -= len;
865 spi_writel(as, RPR, rx_dma);
866 spi_writel(as, TPR, tx_dma);
868 if (msg->spi->bits_per_word > 8)
870 spi_writel(as, RCR, len);
871 spi_writel(as, TCR, len);
873 dev_dbg(&msg->spi->dev,
874 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
875 xfer, xfer->len, xfer->tx_buf,
876 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
877 (unsigned long long)xfer->rx_dma);
879 if (as->current_remaining_bytes) {
880 len = as->current_remaining_bytes;
881 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
882 as->current_remaining_bytes -= len;
884 spi_writel(as, RNPR, rx_dma);
885 spi_writel(as, TNPR, tx_dma);
887 if (msg->spi->bits_per_word > 8)
889 spi_writel(as, RNCR, len);
890 spi_writel(as, TNCR, len);
892 dev_dbg(&msg->spi->dev,
893 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
894 xfer, xfer->len, xfer->tx_buf,
895 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
896 (unsigned long long)xfer->rx_dma);
899 /* REVISIT: We're waiting for RXBUFF before we start the next
900 * transfer because we need to handle some difficult timing
901 * issues otherwise. If we wait for TXBUFE in one transfer and
902 * then starts waiting for RXBUFF in the next, it's difficult
903 * to tell the difference between the RXBUFF interrupt we're
904 * actually waiting for and the RXBUFF interrupt of the
907 * It should be doable, though. Just not now...
909 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
910 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
914 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
915 * - The buffer is either valid for CPU access, else NULL
916 * - If the buffer is valid, so is its DMA address
918 * This driver manages the dma address unless message->is_dma_mapped.
921 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
923 struct device *dev = &as->pdev->dev;
925 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
927 /* tx_buf is a const void* where we need a void * for the dma
929 void *nonconst_tx = (void *)xfer->tx_buf;
931 xfer->tx_dma = dma_map_single(dev,
932 nonconst_tx, xfer->len,
934 if (dma_mapping_error(dev, xfer->tx_dma))
938 xfer->rx_dma = dma_map_single(dev,
939 xfer->rx_buf, xfer->len,
941 if (dma_mapping_error(dev, xfer->rx_dma)) {
943 dma_unmap_single(dev,
944 xfer->tx_dma, xfer->len,
952 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
953 struct spi_transfer *xfer)
955 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
956 dma_unmap_single(master->dev.parent, xfer->tx_dma,
957 xfer->len, DMA_TO_DEVICE);
958 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
959 dma_unmap_single(master->dev.parent, xfer->rx_dma,
960 xfer->len, DMA_FROM_DEVICE);
963 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
965 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
969 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
973 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
975 if (xfer->bits_per_word > 8) {
976 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
977 *rxp16 = spi_readl(as, RDR);
979 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
980 *rxp = spi_readl(as, RDR);
982 if (xfer->bits_per_word > 8) {
983 if (as->current_remaining_bytes > 2)
984 as->current_remaining_bytes -= 2;
986 as->current_remaining_bytes = 0;
988 as->current_remaining_bytes--;
993 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
995 u32 fifolr = spi_readl(as, FLR);
996 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
997 u32 offset = xfer->len - as->current_remaining_bytes;
998 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
999 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1000 u16 rd; /* RD field is the lowest 16 bits of RDR */
1002 /* Update the number of remaining bytes to transfer */
1003 num_bytes = ((xfer->bits_per_word > 8) ?
1007 if (as->current_remaining_bytes > num_bytes)
1008 as->current_remaining_bytes -= num_bytes;
1010 as->current_remaining_bytes = 0;
1012 /* Handle odd number of bytes when data are more than 8bit width */
1013 if (xfer->bits_per_word > 8)
1014 as->current_remaining_bytes &= ~0x1;
1018 rd = spi_readl(as, RDR);
1019 if (xfer->bits_per_word > 8)
1029 * Must update "current_remaining_bytes" to keep track of data
1033 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1036 atmel_spi_pump_fifo_data(as, xfer);
1038 atmel_spi_pump_single_data(as, xfer);
1043 * No need for locking in this Interrupt handler: done_status is the
1044 * only information modified.
1047 atmel_spi_pio_interrupt(int irq, void *dev_id)
1049 struct spi_master *master = dev_id;
1050 struct atmel_spi *as = spi_master_get_devdata(master);
1051 u32 status, pending, imr;
1052 struct spi_transfer *xfer;
1055 imr = spi_readl(as, IMR);
1056 status = spi_readl(as, SR);
1057 pending = status & imr;
1059 if (pending & SPI_BIT(OVRES)) {
1061 spi_writel(as, IDR, SPI_BIT(OVRES));
1062 dev_warn(master->dev.parent, "overrun\n");
1065 * When we get an overrun, we disregard the current
1066 * transfer. Data will not be copied back from any
1067 * bounce buffer and msg->actual_len will not be
1068 * updated with the last xfer.
1070 * We will also not process any remaning transfers in
1073 as->done_status = -EIO;
1076 /* Clear any overrun happening while cleaning up */
1079 complete(&as->xfer_completion);
1081 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1084 if (as->current_remaining_bytes) {
1086 xfer = as->current_transfer;
1087 atmel_spi_pump_pio_data(as, xfer);
1088 if (!as->current_remaining_bytes)
1089 spi_writel(as, IDR, pending);
1091 complete(&as->xfer_completion);
1094 atmel_spi_unlock(as);
1096 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1098 spi_writel(as, IDR, pending);
1105 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1107 struct spi_master *master = dev_id;
1108 struct atmel_spi *as = spi_master_get_devdata(master);
1109 u32 status, pending, imr;
1112 imr = spi_readl(as, IMR);
1113 status = spi_readl(as, SR);
1114 pending = status & imr;
1116 if (pending & SPI_BIT(OVRES)) {
1120 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1123 /* Clear any overrun happening while cleaning up */
1126 as->done_status = -EIO;
1128 complete(&as->xfer_completion);
1130 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1133 spi_writel(as, IDR, pending);
1135 complete(&as->xfer_completion);
1141 static int atmel_spi_setup(struct spi_device *spi)
1143 struct atmel_spi *as;
1144 struct atmel_spi_device *asd;
1146 unsigned int bits = spi->bits_per_word;
1147 unsigned int npcs_pin;
1149 as = spi_master_get_devdata(spi->master);
1151 /* see notes above re chipselect */
1152 if (!as->use_cs_gpios && (spi->mode & SPI_CS_HIGH)) {
1153 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1157 csr = SPI_BF(BITS, bits - 8);
1158 if (spi->mode & SPI_CPOL)
1159 csr |= SPI_BIT(CPOL);
1160 if (!(spi->mode & SPI_CPHA))
1161 csr |= SPI_BIT(NCPHA);
1162 if (!as->use_cs_gpios)
1163 csr |= SPI_BIT(CSAAT);
1165 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1167 * DLYBCT would add delays between words, slowing down transfers.
1168 * It could potentially be useful to cope with DMA bottlenecks, but
1169 * in those cases it's probably best to just use a lower bitrate.
1171 csr |= SPI_BF(DLYBS, 0);
1172 csr |= SPI_BF(DLYBCT, 0);
1174 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1175 npcs_pin = (unsigned long)spi->controller_data;
1177 if (!as->use_cs_gpios)
1178 npcs_pin = spi->chip_select;
1179 else if (gpio_is_valid(spi->cs_gpio))
1180 npcs_pin = spi->cs_gpio;
1182 asd = spi->controller_state;
1184 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1188 if (as->use_cs_gpios)
1189 gpio_direction_output(npcs_pin,
1190 !(spi->mode & SPI_CS_HIGH));
1192 asd->npcs_pin = npcs_pin;
1193 spi->controller_state = asd;
1199 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1200 bits, spi->mode, spi->chip_select, csr);
1202 if (!atmel_spi_is_v2(as))
1203 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1208 static int atmel_spi_one_transfer(struct spi_master *master,
1209 struct spi_message *msg,
1210 struct spi_transfer *xfer)
1212 struct atmel_spi *as;
1213 struct spi_device *spi = msg->spi;
1216 struct atmel_spi_device *asd;
1219 unsigned long dma_timeout;
1221 as = spi_master_get_devdata(master);
1223 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1224 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1228 asd = spi->controller_state;
1229 bits = (asd->csr >> 4) & 0xf;
1230 if (bits != xfer->bits_per_word - 8) {
1232 "you can't yet change bits_per_word in transfers\n");
1233 return -ENOPROTOOPT;
1237 * DMA map early, for performance (empties dcache ASAP) and
1238 * better fault reporting.
1240 if ((!msg->is_dma_mapped)
1242 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1246 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1248 as->done_status = 0;
1249 as->current_transfer = xfer;
1250 as->current_remaining_bytes = xfer->len;
1251 while (as->current_remaining_bytes) {
1252 reinit_completion(&as->xfer_completion);
1255 atmel_spi_pdc_next_xfer(master, msg, xfer);
1256 } else if (atmel_spi_use_dma(as, xfer)) {
1257 len = as->current_remaining_bytes;
1258 ret = atmel_spi_next_xfer_dma_submit(master,
1262 "unable to use DMA, fallback to PIO\n");
1263 atmel_spi_next_xfer_pio(master, xfer);
1265 as->current_remaining_bytes -= len;
1266 if (as->current_remaining_bytes < 0)
1267 as->current_remaining_bytes = 0;
1270 atmel_spi_next_xfer_pio(master, xfer);
1273 /* interrupts are disabled, so free the lock for schedule */
1274 atmel_spi_unlock(as);
1275 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1278 if (WARN_ON(dma_timeout == 0)) {
1279 dev_err(&spi->dev, "spi transfer timeout\n");
1280 as->done_status = -EIO;
1283 if (as->done_status)
1287 if (as->done_status) {
1289 dev_warn(master->dev.parent,
1290 "overrun (%u/%u remaining)\n",
1291 spi_readl(as, TCR), spi_readl(as, RCR));
1294 * Clean up DMA registers and make sure the data
1295 * registers are empty.
1297 spi_writel(as, RNCR, 0);
1298 spi_writel(as, TNCR, 0);
1299 spi_writel(as, RCR, 0);
1300 spi_writel(as, TCR, 0);
1301 for (timeout = 1000; timeout; timeout--)
1302 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1305 dev_warn(master->dev.parent,
1306 "timeout waiting for TXEMPTY");
1307 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1310 /* Clear any overrun happening while cleaning up */
1313 } else if (atmel_spi_use_dma(as, xfer)) {
1314 atmel_spi_stop_dma(master);
1317 if (!msg->is_dma_mapped
1319 atmel_spi_dma_unmap_xfer(master, xfer);
1324 /* only update length if no error */
1325 msg->actual_length += xfer->len;
1328 if (!msg->is_dma_mapped
1330 atmel_spi_dma_unmap_xfer(master, xfer);
1332 if (xfer->delay_usecs)
1333 udelay(xfer->delay_usecs);
1335 if (xfer->cs_change) {
1336 if (list_is_last(&xfer->transfer_list,
1340 cs_deactivate(as, msg->spi);
1342 cs_activate(as, msg->spi);
1349 static int atmel_spi_transfer_one_message(struct spi_master *master,
1350 struct spi_message *msg)
1352 struct atmel_spi *as;
1353 struct spi_transfer *xfer;
1354 struct spi_device *spi = msg->spi;
1357 as = spi_master_get_devdata(master);
1359 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1360 msg, dev_name(&spi->dev));
1363 cs_activate(as, spi);
1365 as->keep_cs = false;
1368 msg->actual_length = 0;
1370 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1371 ret = atmel_spi_one_transfer(master, msg, xfer);
1377 atmel_spi_disable_pdc_transfer(as);
1379 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1381 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1383 xfer->tx_buf, &xfer->tx_dma,
1384 xfer->rx_buf, &xfer->rx_dma);
1389 cs_deactivate(as, msg->spi);
1391 atmel_spi_unlock(as);
1393 msg->status = as->done_status;
1394 spi_finalize_current_message(spi->master);
1399 static void atmel_spi_cleanup(struct spi_device *spi)
1401 struct atmel_spi_device *asd = spi->controller_state;
1406 spi->controller_state = NULL;
1410 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1412 return spi_readl(as, VERSION) & 0x00000fff;
1415 static void atmel_get_caps(struct atmel_spi *as)
1417 unsigned int version;
1419 version = atmel_get_version(as);
1421 as->caps.is_spi2 = version > 0x121;
1422 as->caps.has_wdrbt = version >= 0x210;
1423 #ifdef CONFIG_SOC_SAM_V4_V5
1425 * Atmel SoCs based on ARM9 (SAM9x) cores should not use spi_map_buf()
1426 * since this later function tries to map buffers with dma_map_sg()
1427 * even if they have not been allocated inside DMA-safe areas.
1428 * On SoCs based on Cortex A5 (SAMA5Dx), it works anyway because for
1429 * those ARM cores, the data cache follows the PIPT model.
1430 * Also the L2 cache controller of SAMA5D2 uses the PIPT model too.
1431 * In case of PIPT caches, there cannot be cache aliases.
1432 * However on ARM9 cores, the data cache follows the VIVT model, hence
1433 * the cache aliases issue can occur when buffers are allocated from
1434 * DMA-unsafe areas, by vmalloc() for instance, where cache coherency is
1435 * not taken into account or at least not handled completely (cache
1436 * lines of aliases are not invalidated).
1437 * This is not a theorical issue: it was reproduced when trying to mount
1438 * a UBI file-system on a at91sam9g35ek board.
1440 as->caps.has_dma_support = false;
1442 as->caps.has_dma_support = version >= 0x212;
1444 as->caps.has_pdc_support = version < 0x212;
1447 /*-------------------------------------------------------------------------*/
1448 static int atmel_spi_gpio_cs(struct platform_device *pdev)
1450 struct spi_master *master = platform_get_drvdata(pdev);
1451 struct atmel_spi *as = spi_master_get_devdata(master);
1452 struct device_node *np = master->dev.of_node;
1457 if (!as->use_cs_gpios)
1463 nb = of_gpio_named_count(np, "cs-gpios");
1464 for (i = 0; i < nb; i++) {
1465 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1468 if (cs_gpio == -EPROBE_DEFER)
1471 if (gpio_is_valid(cs_gpio)) {
1472 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1473 dev_name(&pdev->dev));
1482 static void atmel_spi_init(struct atmel_spi *as)
1484 spi_writel(as, CR, SPI_BIT(SWRST));
1485 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1487 /* It is recommended to enable FIFOs first thing after reset */
1489 spi_writel(as, CR, SPI_BIT(FIFOEN));
1491 if (as->caps.has_wdrbt) {
1492 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1495 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1499 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1500 spi_writel(as, CR, SPI_BIT(SPIEN));
1503 static int atmel_spi_probe(struct platform_device *pdev)
1505 struct resource *regs;
1509 struct spi_master *master;
1510 struct atmel_spi *as;
1512 /* Select default pin state */
1513 pinctrl_pm_select_default_state(&pdev->dev);
1515 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1519 irq = platform_get_irq(pdev, 0);
1523 clk = devm_clk_get(&pdev->dev, "spi_clk");
1525 return PTR_ERR(clk);
1527 /* setup spi core then atmel-specific driver state */
1529 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1533 /* the spi->mode bits understood by this driver: */
1534 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1535 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1536 master->dev.of_node = pdev->dev.of_node;
1537 master->bus_num = pdev->id;
1538 master->num_chipselect = master->dev.of_node ? 0 : 4;
1539 master->setup = atmel_spi_setup;
1540 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1541 master->transfer_one_message = atmel_spi_transfer_one_message;
1542 master->cleanup = atmel_spi_cleanup;
1543 master->auto_runtime_pm = true;
1544 master->max_dma_len = SPI_MAX_DMA_XFER;
1545 master->can_dma = atmel_spi_can_dma;
1546 platform_set_drvdata(pdev, master);
1548 as = spi_master_get_devdata(master);
1550 spin_lock_init(&as->lock);
1553 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1554 if (IS_ERR(as->regs)) {
1555 ret = PTR_ERR(as->regs);
1556 goto out_unmap_regs;
1558 as->phybase = regs->start;
1562 init_completion(&as->xfer_completion);
1566 as->use_cs_gpios = true;
1567 if (atmel_spi_is_v2(as) &&
1568 pdev->dev.of_node &&
1569 !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1570 as->use_cs_gpios = false;
1571 master->num_chipselect = 4;
1574 ret = atmel_spi_gpio_cs(pdev);
1576 goto out_unmap_regs;
1578 as->use_dma = false;
1579 as->use_pdc = false;
1580 if (as->caps.has_dma_support) {
1581 ret = atmel_spi_configure_dma(master, as);
1584 } else if (ret == -EPROBE_DEFER) {
1585 goto out_unmap_regs;
1587 } else if (as->caps.has_pdc_support) {
1591 if (as->caps.has_dma_support && !as->use_dma)
1592 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1595 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1596 0, dev_name(&pdev->dev), master);
1598 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1599 0, dev_name(&pdev->dev), master);
1602 goto out_unmap_regs;
1604 /* Initialize the hardware */
1605 ret = clk_prepare_enable(clk);
1609 as->spi_clk = clk_get_rate(clk);
1612 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1614 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1619 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1620 pm_runtime_use_autosuspend(&pdev->dev);
1621 pm_runtime_set_active(&pdev->dev);
1622 pm_runtime_enable(&pdev->dev);
1624 ret = devm_spi_register_master(&pdev->dev, master);
1629 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1630 atmel_get_version(as), (unsigned long)regs->start,
1636 pm_runtime_disable(&pdev->dev);
1637 pm_runtime_set_suspended(&pdev->dev);
1640 atmel_spi_release_dma(master);
1642 spi_writel(as, CR, SPI_BIT(SWRST));
1643 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1644 clk_disable_unprepare(clk);
1648 spi_master_put(master);
1652 static int atmel_spi_remove(struct platform_device *pdev)
1654 struct spi_master *master = platform_get_drvdata(pdev);
1655 struct atmel_spi *as = spi_master_get_devdata(master);
1657 pm_runtime_get_sync(&pdev->dev);
1659 /* reset the hardware and block queue progress */
1661 atmel_spi_stop_dma(master);
1662 atmel_spi_release_dma(master);
1665 spin_lock_irq(&as->lock);
1666 spi_writel(as, CR, SPI_BIT(SWRST));
1667 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1669 spin_unlock_irq(&as->lock);
1671 clk_disable_unprepare(as->clk);
1673 pm_runtime_put_noidle(&pdev->dev);
1674 pm_runtime_disable(&pdev->dev);
1680 static int atmel_spi_runtime_suspend(struct device *dev)
1682 struct spi_master *master = dev_get_drvdata(dev);
1683 struct atmel_spi *as = spi_master_get_devdata(master);
1685 clk_disable_unprepare(as->clk);
1686 pinctrl_pm_select_sleep_state(dev);
1691 static int atmel_spi_runtime_resume(struct device *dev)
1693 struct spi_master *master = dev_get_drvdata(dev);
1694 struct atmel_spi *as = spi_master_get_devdata(master);
1696 pinctrl_pm_select_default_state(dev);
1698 return clk_prepare_enable(as->clk);
1701 #ifdef CONFIG_PM_SLEEP
1702 static int atmel_spi_suspend(struct device *dev)
1704 struct spi_master *master = dev_get_drvdata(dev);
1707 /* Stop the queue running */
1708 ret = spi_master_suspend(master);
1710 dev_warn(dev, "cannot suspend master\n");
1714 if (!pm_runtime_suspended(dev))
1715 atmel_spi_runtime_suspend(dev);
1720 static int atmel_spi_resume(struct device *dev)
1722 struct spi_master *master = dev_get_drvdata(dev);
1723 struct atmel_spi *as = spi_master_get_devdata(master);
1726 ret = clk_prepare_enable(as->clk);
1732 clk_disable_unprepare(as->clk);
1734 if (!pm_runtime_suspended(dev)) {
1735 ret = atmel_spi_runtime_resume(dev);
1740 /* Start the queue running */
1741 ret = spi_master_resume(master);
1743 dev_err(dev, "problem starting queue (%d)\n", ret);
1749 static const struct dev_pm_ops atmel_spi_pm_ops = {
1750 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1751 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1752 atmel_spi_runtime_resume, NULL)
1754 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1756 #define ATMEL_SPI_PM_OPS NULL
1759 #if defined(CONFIG_OF)
1760 static const struct of_device_id atmel_spi_dt_ids[] = {
1761 { .compatible = "atmel,at91rm9200-spi" },
1765 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1768 static struct platform_driver atmel_spi_driver = {
1770 .name = "atmel_spi",
1771 .pm = ATMEL_SPI_PM_OPS,
1772 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1774 .probe = atmel_spi_probe,
1775 .remove = atmel_spi_remove,
1777 module_platform_driver(atmel_spi_driver);
1779 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1780 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1781 MODULE_LICENSE("GPL");
1782 MODULE_ALIAS("platform:atmel_spi");