drivers/spi/spi-atmel.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_data/dma-atmel.h>
  23 #include <linux/of.h>
  24
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/pm_runtime.h>
  29
  30 /* SPI register offsets */
  31 #define SPI_CR                                  0x0000
  32 #define SPI_MR                                  0x0004
  33 #define SPI_RDR                                 0x0008
  34 #define SPI_TDR                                 0x000c
  35 #define SPI_SR                                  0x0010
  36 #define SPI_IER                                 0x0014
  37 #define SPI_IDR                                 0x0018
  38 #define SPI_IMR                                 0x001c
  39 #define SPI_CSR0                                0x0030
  40 #define SPI_CSR1                                0x0034
  41 #define SPI_CSR2                                0x0038
  42 #define SPI_CSR3                                0x003c
  43 #define SPI_FMR                                 0x0040
  44 #define SPI_FLR                                 0x0044
  45 #define SPI_VERSION                             0x00fc
  46 #define SPI_RPR                                 0x0100
  47 #define SPI_RCR                                 0x0104
  48 #define SPI_TPR                                 0x0108
  49 #define SPI_TCR                                 0x010c
  50 #define SPI_RNPR                                0x0110
  51 #define SPI_RNCR                                0x0114
  52 #define SPI_TNPR                                0x0118
  53 #define SPI_TNCR                                0x011c
  54 #define SPI_PTCR                                0x0120
  55 #define SPI_PTSR                                0x0124
  56
  57 /* Bitfields in CR */
  58 #define SPI_SPIEN_OFFSET                        0
  59 #define SPI_SPIEN_SIZE                          1
  60 #define SPI_SPIDIS_OFFSET                       1
  61 #define SPI_SPIDIS_SIZE                         1
  62 #define SPI_SWRST_OFFSET                        7
  63 #define SPI_SWRST_SIZE                          1
  64 #define SPI_LASTXFER_OFFSET                     24
  65 #define SPI_LASTXFER_SIZE                       1
  66 #define SPI_TXFCLR_OFFSET                       16
  67 #define SPI_TXFCLR_SIZE                         1
  68 #define SPI_RXFCLR_OFFSET                       17
  69 #define SPI_RXFCLR_SIZE                         1
  70 #define SPI_FIFOEN_OFFSET                       30
  71 #define SPI_FIFOEN_SIZE                         1
  72 #define SPI_FIFODIS_OFFSET                      31
  73 #define SPI_FIFODIS_SIZE                        1
  74
  75 /* Bitfields in MR */
  76 #define SPI_MSTR_OFFSET                         0
  77 #define SPI_MSTR_SIZE                           1
  78 #define SPI_PS_OFFSET                           1
  79 #define SPI_PS_SIZE                             1
  80 #define SPI_PCSDEC_OFFSET                       2
  81 #define SPI_PCSDEC_SIZE                         1
  82 #define SPI_FDIV_OFFSET                         3
  83 #define SPI_FDIV_SIZE                           1
  84 #define SPI_MODFDIS_OFFSET                      4
  85 #define SPI_MODFDIS_SIZE                        1
  86 #define SPI_WDRBT_OFFSET                        5
  87 #define SPI_WDRBT_SIZE                          1
  88 #define SPI_LLB_OFFSET                          7
  89 #define SPI_LLB_SIZE                            1
  90 #define SPI_PCS_OFFSET                          16
  91 #define SPI_PCS_SIZE                            4
  92 #define SPI_DLYBCS_OFFSET                       24
  93 #define SPI_DLYBCS_SIZE                         8
  94
  95 /* Bitfields in RDR */
  96 #define SPI_RD_OFFSET                           0
  97 #define SPI_RD_SIZE                             16
  98
  99 /* Bitfields in TDR */
 100 #define SPI_TD_OFFSET                           0
 101 #define SPI_TD_SIZE                             16
 102
 103 /* Bitfields in SR */
 104 #define SPI_RDRF_OFFSET                         0
 105 #define SPI_RDRF_SIZE                           1
 106 #define SPI_TDRE_OFFSET                         1
 107 #define SPI_TDRE_SIZE                           1
 108 #define SPI_MODF_OFFSET                         2
 109 #define SPI_MODF_SIZE                           1
 110 #define SPI_OVRES_OFFSET                        3
 111 #define SPI_OVRES_SIZE                          1
 112 #define SPI_ENDRX_OFFSET                        4
 113 #define SPI_ENDRX_SIZE                          1
 114 #define SPI_ENDTX_OFFSET                        5
 115 #define SPI_ENDTX_SIZE                          1
 116 #define SPI_RXBUFF_OFFSET                       6
 117 #define SPI_RXBUFF_SIZE                         1
 118 #define SPI_TXBUFE_OFFSET                       7
 119 #define SPI_TXBUFE_SIZE                         1
 120 #define SPI_NSSR_OFFSET                         8
 121 #define SPI_NSSR_SIZE                           1
 122 #define SPI_TXEMPTY_OFFSET                      9
 123 #define SPI_TXEMPTY_SIZE                        1
 124 #define SPI_SPIENS_OFFSET                       16
 125 #define SPI_SPIENS_SIZE                         1
 126 #define SPI_TXFEF_OFFSET                        24
 127 #define SPI_TXFEF_SIZE                          1
 128 #define SPI_TXFFF_OFFSET                        25
 129 #define SPI_TXFFF_SIZE                          1
 130 #define SPI_TXFTHF_OFFSET                       26
 131 #define SPI_TXFTHF_SIZE                         1
 132 #define SPI_RXFEF_OFFSET                        27
 133 #define SPI_RXFEF_SIZE                          1
 134 #define SPI_RXFFF_OFFSET                        28
 135 #define SPI_RXFFF_SIZE                          1
 136 #define SPI_RXFTHF_OFFSET                       29
 137 #define SPI_RXFTHF_SIZE                         1
 138 #define SPI_TXFPTEF_OFFSET                      30
 139 #define SPI_TXFPTEF_SIZE                        1
 140 #define SPI_RXFPTEF_OFFSET                      31
 141 #define SPI_RXFPTEF_SIZE                        1
 142
 143 /* Bitfields in CSR0 */
 144 #define SPI_CPOL_OFFSET                         0
 145 #define SPI_CPOL_SIZE                           1
 146 #define SPI_NCPHA_OFFSET                        1
 147 #define SPI_NCPHA_SIZE                          1
 148 #define SPI_CSAAT_OFFSET                        3
 149 #define SPI_CSAAT_SIZE                          1
 150 #define SPI_BITS_OFFSET                         4
 151 #define SPI_BITS_SIZE                           4
 152 #define SPI_SCBR_OFFSET                         8
 153 #define SPI_SCBR_SIZE                           8
 154 #define SPI_DLYBS_OFFSET                        16
 155 #define SPI_DLYBS_SIZE                          8
 156 #define SPI_DLYBCT_OFFSET                       24
 157 #define SPI_DLYBCT_SIZE                         8
 158
 159 /* Bitfields in RCR */
 160 #define SPI_RXCTR_OFFSET                        0
 161 #define SPI_RXCTR_SIZE                          16
 162
 163 /* Bitfields in TCR */
 164 #define SPI_TXCTR_OFFSET                        0
 165 #define SPI_TXCTR_SIZE                          16
 166
 167 /* Bitfields in RNCR */
 168 #define SPI_RXNCR_OFFSET                        0
 169 #define SPI_RXNCR_SIZE                          16
 170
 171 /* Bitfields in TNCR */
 172 #define SPI_TXNCR_OFFSET                        0
 173 #define SPI_TXNCR_SIZE                          16
 174
 175 /* Bitfields in PTCR */
 176 #define SPI_RXTEN_OFFSET                        0
 177 #define SPI_RXTEN_SIZE                          1
 178 #define SPI_RXTDIS_OFFSET                       1
 179 #define SPI_RXTDIS_SIZE                         1
 180 #define SPI_TXTEN_OFFSET                        8
 181 #define SPI_TXTEN_SIZE                          1
 182 #define SPI_TXTDIS_OFFSET                       9
 183 #define SPI_TXTDIS_SIZE                         1
 184
 185 /* Bitfields in FMR */
 186 #define SPI_TXRDYM_OFFSET                       0
 187 #define SPI_TXRDYM_SIZE                         2
 188 #define SPI_RXRDYM_OFFSET                       4
 189 #define SPI_RXRDYM_SIZE                         2
 190 #define SPI_TXFTHRES_OFFSET                     16
 191 #define SPI_TXFTHRES_SIZE                       6
 192 #define SPI_RXFTHRES_OFFSET                     24
 193 #define SPI_RXFTHRES_SIZE                       6
 194
 195 /* Bitfields in FLR */
 196 #define SPI_TXFL_OFFSET                         0
 197 #define SPI_TXFL_SIZE                           6
 198 #define SPI_RXFL_OFFSET                         16
 199 #define SPI_RXFL_SIZE                           6
 200
 201 /* Constants for BITS */
 202 #define SPI_BITS_8_BPT                          0
 203 #define SPI_BITS_9_BPT                          1
 204 #define SPI_BITS_10_BPT                         2
 205 #define SPI_BITS_11_BPT                         3
 206 #define SPI_BITS_12_BPT                         4
 207 #define SPI_BITS_13_BPT                         5
 208 #define SPI_BITS_14_BPT                         6
 209 #define SPI_BITS_15_BPT                         7
 210 #define SPI_BITS_16_BPT                         8
 211 #define SPI_ONE_DATA                            0
 212 #define SPI_TWO_DATA                            1
 213 #define SPI_FOUR_DATA                           2
 214
 215 /* Bit manipulation macros */
 216 #define SPI_BIT(name) \
 217         (1 << SPI_##name##_OFFSET)
 218 #define SPI_BF(name, value) \
 219         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 220 #define SPI_BFEXT(name, value) \
 221         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 222 #define SPI_BFINS(name, value, old) \
 223         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 224           | SPI_BF(name, value))
 225
 226 /* Register access macros */
 227 #ifdef CONFIG_AVR32
 228 #define spi_readl(port, reg) \
 229         __raw_readl((port)->regs + SPI_##reg)
 230 #define spi_writel(port, reg, value) \
 231         __raw_writel((value), (port)->regs + SPI_##reg)
 232
 233 #define spi_readw(port, reg) \
 234         __raw_readw((port)->regs + SPI_##reg)
 235 #define spi_writew(port, reg, value) \
 236         __raw_writew((value), (port)->regs + SPI_##reg)
 237
 238 #define spi_readb(port, reg) \
 239         __raw_readb((port)->regs + SPI_##reg)
 240 #define spi_writeb(port, reg, value) \
 241         __raw_writeb((value), (port)->regs + SPI_##reg)
 242 #else
 243 #define spi_readl(port, reg) \
 244         readl_relaxed((port)->regs + SPI_##reg)
 245 #define spi_writel(port, reg, value) \
 246         writel_relaxed((value), (port)->regs + SPI_##reg)
 247
 248 #define spi_readw(port, reg) \
 249         readw_relaxed((port)->regs + SPI_##reg)
 250 #define spi_writew(port, reg, value) \
 251         writew_relaxed((value), (port)->regs + SPI_##reg)
 252
 253 #define spi_readb(port, reg) \
 254         readb_relaxed((port)->regs + SPI_##reg)
 255 #define spi_writeb(port, reg, value) \
 256         writeb_relaxed((value), (port)->regs + SPI_##reg)
 257 #endif
 258 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 259  * cache operations; better heuristics consider wordsize and bitrate.
 260  */
 261 #define DMA_MIN_BYTES   16
 262
 263 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 264
 265 #define AUTOSUSPEND_TIMEOUT     2000
 266
 267 struct atmel_spi_dma {
 268         struct dma_chan                 *chan_rx;
 269         struct dma_chan                 *chan_tx;
 270         struct scatterlist              sgrx;
 271         struct scatterlist              sgtx;
 272         struct dma_async_tx_descriptor  *data_desc_rx;
 273         struct dma_async_tx_descriptor  *data_desc_tx;
 274
 275         struct at_dma_slave     dma_slave;
 276 };
 277
 278 struct atmel_spi_caps {
 279         bool    is_spi2;
 280         bool    has_wdrbt;
 281         bool    has_dma_support;
 282 };
 283
 284 /*
 285  * The core SPI transfer engine just talks to a register bank to set up
 286  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 287  * framework provides the base clock, subdivided for each spi_device.
 288  */
 289 struct atmel_spi {
 290         spinlock_t              lock;
 291         unsigned long           flags;
 292
 293         phys_addr_t             phybase;
 294         void __iomem            *regs;
 295         int                     irq;
 296         struct clk              *clk;
 297         struct platform_device  *pdev;
 298
 299         struct spi_transfer     *current_transfer;
 300         int                     current_remaining_bytes;
 301         int                     done_status;
 302
 303         struct completion       xfer_completion;
 304
 305         /* scratch buffer */
 306         void                    *buffer;
 307         dma_addr_t              buffer_dma;
 308
 309         struct atmel_spi_caps   caps;
 310
 311         bool                    use_dma;
 312         bool                    use_pdc;
 313         bool                    use_cs_gpios;
 314         /* dmaengine data */
 315         struct atmel_spi_dma    dma;
 316
 317         bool                    keep_cs;
 318
 319         u32                     fifo_size;
 320 };
 321
 322 /* Controller-specific per-slave state */
 323 struct atmel_spi_device {
 324         unsigned int            npcs_pin;
 325         u32                     csr;
 326 };
 327
 328 #define BUFFER_SIZE             PAGE_SIZE
 329 #define INVALID_DMA_ADDRESS     0xffffffff
 330
 331 /*
 332  * Version 2 of the SPI controller has
 333  *  - CR.LASTXFER
 334  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 335  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 336  *  - SPI_CSRx.CSAAT
 337  *  - SPI_CSRx.SBCR allows faster clocking
 338  */
 339 static bool atmel_spi_is_v2(struct atmel_spi *as)
 340 {
 341         return as->caps.is_spi2;
 342 }
 343
 344 /*
 345  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 346  * they assume that spi slave device state will not change on deselect, so
 347  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 348  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 349  * controllers have CSAAT and friends.
 350  *
 351  * Since the CSAAT functionality is a bit weird on newer controllers as
 352  * well, we use GPIO to control nCSx pins on all controllers, updating
 353  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 354  * support active-high chipselects despite the controller's belief that
 355  * only active-low devices/systems exists.
 356  *
 357  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 358  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 359  * Master on Chip Select 0.")  No workaround exists for that ... so for
 360  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 361  * and (c) will trigger that first erratum in some cases.
 362  */
 363
 364 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 365 {
 366         struct atmel_spi_device *asd = spi->controller_state;
 367         unsigned active = spi->mode & SPI_CS_HIGH;
 368         u32 mr;
 369
 370         if (atmel_spi_is_v2(as)) {
 371                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 372                 /* For the low SPI version, there is a issue that PDC transfer
 373                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 374                  */
 375                 spi_writel(as, CSR0, asd->csr);
 376                 if (as->caps.has_wdrbt) {
 377                         spi_writel(as, MR,
 378                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 379                                         | SPI_BIT(WDRBT)
 380                                         | SPI_BIT(MODFDIS)
 381                                         | SPI_BIT(MSTR));
 382                 } else {
 383                         spi_writel(as, MR,
 384                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 385                                         | SPI_BIT(MODFDIS)
 386                                         | SPI_BIT(MSTR));
 387                 }
 388
 389                 mr = spi_readl(as, MR);
 390                 if (as->use_cs_gpios)
 391                         gpio_set_value(asd->npcs_pin, active);
 392         } else {
 393                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 394                 int i;
 395                 u32 csr;
 396
 397                 /* Make sure clock polarity is correct */
 398                 for (i = 0; i < spi->master->num_chipselect; i++) {
 399                         csr = spi_readl(as, CSR0 + 4 * i);
 400                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 401                                 spi_writel(as, CSR0 + 4 * i,
 402                                                 csr ^ SPI_BIT(CPOL));
 403                 }
 404
 405                 mr = spi_readl(as, MR);
 406                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 407                 if (as->use_cs_gpios && spi->chip_select != 0)
 408                         gpio_set_value(asd->npcs_pin, active);
 409                 spi_writel(as, MR, mr);
 410         }
 411
 412         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 413                         asd->npcs_pin, active ? " (high)" : "",
 414                         mr);
 415 }
 416
 417 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 418 {
 419         struct atmel_spi_device *asd = spi->controller_state;
 420         unsigned active = spi->mode & SPI_CS_HIGH;
 421         u32 mr;
 422
 423         /* only deactivate *this* device; sometimes transfers to
 424          * another device may be active when this routine is called.
 425          */
 426         mr = spi_readl(as, MR);
 427         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 428                 mr = SPI_BFINS(PCS, 0xf, mr);
 429                 spi_writel(as, MR, mr);
 430         }
 431
 432         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 433                         asd->npcs_pin, active ? " (low)" : "",
 434                         mr);
 435
 436         if (!as->use_cs_gpios)
 437                 spi_writel(as, CR, SPI_BIT(LASTXFER));
 438         else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 439                 gpio_set_value(asd->npcs_pin, !active);
 440 }
 441
 442 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 443 {
 444         spin_lock_irqsave(&as->lock, as->flags);
 445 }
 446
 447 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 448 {
 449         spin_unlock_irqrestore(&as->lock, as->flags);
 450 }
 451
 452 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 453                                 struct spi_transfer *xfer)
 454 {
 455         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 456 }
 457
 458 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 459                                 struct dma_slave_config *slave_config,
 460                                 u8 bits_per_word)
 461 {
 462         int err = 0;
 463
 464         if (bits_per_word > 8) {
 465                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 466                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 467         } else {
 468                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 469                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 470         }
 471
 472         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 473         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 474         slave_config->src_maxburst = 1;
 475         slave_config->dst_maxburst = 1;
 476         slave_config->device_fc = false;
 477
 478         /*
 479          * This driver uses fixed peripheral select mode (PS bit set to '0' in
 480          * the Mode Register).
 481          * So according to the datasheet, when FIFOs are available (and
 482          * enabled), the Transmit FIFO operates in Multiple Data Mode.
 483          * In this mode, up to 2 data, not 4, can be written into the Transmit
 484          * Data Register in a single access.
 485          * However, the first data has to be written into the lowest 16 bits and
 486          * the second data into the highest 16 bits of the Transmit
 487          * Data Register. For 8bit data (the most frequent case), it would
 488          * require to rework tx_buf so each data would actualy fit 16 bits.
 489          * So we'd rather write only one data at the time. Hence the transmit
 490          * path works the same whether FIFOs are available (and enabled) or not.
 491          */
 492         slave_config->direction = DMA_MEM_TO_DEV;
 493         if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
 494                 dev_err(&as->pdev->dev,
 495                         "failed to configure tx dma channel\n");
 496                 err = -EINVAL;
 497         }
 498
 499         /*
 500          * This driver configures the spi controller for master mode (MSTR bit
 501          * set to '1' in the Mode Register).
 502          * So according to the datasheet, when FIFOs are available (and
 503          * enabled), the Receive FIFO operates in Single Data Mode.
 504          * So the receive path works the same whether FIFOs are available (and
 505          * enabled) or not.
 506          */
 507         slave_config->direction = DMA_DEV_TO_MEM;
 508         if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
 509                 dev_err(&as->pdev->dev,
 510                         "failed to configure rx dma channel\n");
 511                 err = -EINVAL;
 512         }
 513
 514         return err;
 515 }
 516
 517 static int atmel_spi_configure_dma(struct atmel_spi *as)
 518 {
 519         struct dma_slave_config slave_config;
 520         struct device *dev = &as->pdev->dev;
 521         int err;
 522
 523         dma_cap_mask_t mask;
 524         dma_cap_zero(mask);
 525         dma_cap_set(DMA_SLAVE, mask);
 526
 527         as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx");
 528         if (IS_ERR(as->dma.chan_tx)) {
 529                 err = PTR_ERR(as->dma.chan_tx);
 530                 if (err == -EPROBE_DEFER) {
 531                         dev_warn(dev, "no DMA channel available at the moment\n");
 532                         return err;
 533                 }
 534                 dev_err(dev,
 535                         "DMA TX channel not available, SPI unable to use DMA\n");
 536                 err = -EBUSY;
 537                 goto error;
 538         }
 539
 540         /*
 541          * No reason to check EPROBE_DEFER here since we have already requested
 542          * tx channel. If it fails here, it's for another reason.
 543          */
 544         as->dma.chan_rx = dma_request_slave_channel(dev, "rx");
 545
 546         if (!as->dma.chan_rx) {
 547                 dev_err(dev,
 548                         "DMA RX channel not available, SPI unable to use DMA\n");
 549                 err = -EBUSY;
 550                 goto error;
 551         }
 552
 553         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 554         if (err)
 555                 goto error;
 556
 557         dev_info(&as->pdev->dev,
 558                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 559                         dma_chan_name(as->dma.chan_tx),
 560                         dma_chan_name(as->dma.chan_rx));
 561         return 0;
 562 error:
 563         if (as->dma.chan_rx)
 564                 dma_release_channel(as->dma.chan_rx);
 565         if (!IS_ERR(as->dma.chan_tx))
 566                 dma_release_channel(as->dma.chan_tx);
 567         return err;
 568 }
 569
 570 static void atmel_spi_stop_dma(struct atmel_spi *as)
 571 {
 572         if (as->dma.chan_rx)
 573                 dmaengine_terminate_all(as->dma.chan_rx);
 574         if (as->dma.chan_tx)
 575                 dmaengine_terminate_all(as->dma.chan_tx);
 576 }
 577
 578 static void atmel_spi_release_dma(struct atmel_spi *as)
 579 {
 580         if (as->dma.chan_rx)
 581                 dma_release_channel(as->dma.chan_rx);
 582         if (as->dma.chan_tx)
 583                 dma_release_channel(as->dma.chan_tx);
 584 }
 585
 586 /* This function is called by the DMA driver from tasklet context */
 587 static void dma_callback(void *data)
 588 {
 589         struct spi_master       *master = data;
 590         struct atmel_spi        *as = spi_master_get_devdata(master);
 591
 592         complete(&as->xfer_completion);
 593 }
 594
 595 /*
 596  * Next transfer using PIO without FIFO.
 597  */
 598 static void atmel_spi_next_xfer_single(struct spi_master *master,
 599                                        struct spi_transfer *xfer)
 600 {
 601         struct atmel_spi        *as = spi_master_get_devdata(master);
 602         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 603
 604         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 605
 606         /* Make sure data is not remaining in RDR */
 607         spi_readl(as, RDR);
 608         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 609                 spi_readl(as, RDR);
 610                 cpu_relax();
 611         }
 612
 613         if (xfer->tx_buf) {
 614                 if (xfer->bits_per_word > 8)
 615                         spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 616                 else
 617                         spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 618         } else {
 619                 spi_writel(as, TDR, 0);
 620         }
 621
 622         dev_dbg(master->dev.parent,
 623                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 624                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 625                 xfer->bits_per_word);
 626
 627         /* Enable relevant interrupts */
 628         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 629 }
 630
 631 /*
 632  * Next transfer using PIO with FIFO.
 633  */
 634 static void atmel_spi_next_xfer_fifo(struct spi_master *master,
 635                                      struct spi_transfer *xfer)
 636 {
 637         struct atmel_spi *as = spi_master_get_devdata(master);
 638         u32 current_remaining_data, num_data;
 639         u32 offset = xfer->len - as->current_remaining_bytes;
 640         const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
 641         const u8  *bytes = (const u8  *)((u8 *)xfer->tx_buf + offset);
 642         u16 td0, td1;
 643         u32 fifomr;
 644
 645         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
 646
 647         /* Compute the number of data to transfer in the current iteration */
 648         current_remaining_data = ((xfer->bits_per_word > 8) ?
 649                                   ((u32)as->current_remaining_bytes >> 1) :
 650                                   (u32)as->current_remaining_bytes);
 651         num_data = min(current_remaining_data, as->fifo_size);
 652
 653         /* Flush RX and TX FIFOs */
 654         spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
 655         while (spi_readl(as, FLR))
 656                 cpu_relax();
 657
 658         /* Set RX FIFO Threshold to the number of data to transfer */
 659         fifomr = spi_readl(as, FMR);
 660         spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
 661
 662         /* Clear FIFO flags in the Status Register, especially RXFTHF */
 663         (void)spi_readl(as, SR);
 664
 665         /* Fill TX FIFO */
 666         while (num_data >= 2) {
 667                 if (xfer->tx_buf) {
 668                         if (xfer->bits_per_word > 8) {
 669                                 td0 = *words++;
 670                                 td1 = *words++;
 671                         } else {
 672                                 td0 = *bytes++;
 673                                 td1 = *bytes++;
 674                         }
 675                 } else {
 676                         td0 = 0;
 677                         td1 = 0;
 678                 }
 679
 680                 spi_writel(as, TDR, (td1 << 16) | td0);
 681                 num_data -= 2;
 682         }
 683
 684         if (num_data) {
 685                 if (xfer->tx_buf) {
 686                         if (xfer->bits_per_word > 8)
 687                                 td0 = *words++;
 688                         else
 689                                 td0 = *bytes++;
 690                 } else {
 691                         td0 = 0;
 692                 }
 693
 694                 spi_writew(as, TDR, td0);
 695                 num_data--;
 696         }
 697
 698         dev_dbg(master->dev.parent,
 699                 "  start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
 700                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 701                 xfer->bits_per_word);
 702
 703         /*
 704          * Enable RX FIFO Threshold Flag interrupt to be notified about
 705          * transfer completion.
 706          */
 707         spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
 708 }
 709
 710 /*
 711  * Next transfer using PIO.
 712  */
 713 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 714                                     struct spi_transfer *xfer)
 715 {
 716         struct atmel_spi *as = spi_master_get_devdata(master);
 717
 718         if (as->fifo_size)
 719                 atmel_spi_next_xfer_fifo(master, xfer);
 720         else
 721                 atmel_spi_next_xfer_single(master, xfer);
 722 }
 723
 724 /*
 725  * Submit next transfer for DMA.
 726  */
 727 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 728                                 struct spi_transfer *xfer,
 729                                 u32 *plen)
 730 {
 731         struct atmel_spi        *as = spi_master_get_devdata(master);
 732         struct dma_chan         *rxchan = as->dma.chan_rx;
 733         struct dma_chan         *txchan = as->dma.chan_tx;
 734         struct dma_async_tx_descriptor *rxdesc;
 735         struct dma_async_tx_descriptor *txdesc;
 736         struct dma_slave_config slave_config;
 737         dma_cookie_t            cookie;
 738         u32     len = *plen;
 739
 740         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 741
 742         /* Check that the channels are available */
 743         if (!rxchan || !txchan)
 744                 return -ENODEV;
 745
 746         /* release lock for DMA operations */
 747         atmel_spi_unlock(as);
 748
 749         /* prepare the RX dma transfer */
 750         sg_init_table(&as->dma.sgrx, 1);
 751         if (xfer->rx_buf) {
 752                 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
 753         } else {
 754                 as->dma.sgrx.dma_address = as->buffer_dma;
 755                 if (len > BUFFER_SIZE)
 756                         len = BUFFER_SIZE;
 757         }
 758
 759         /* prepare the TX dma transfer */
 760         sg_init_table(&as->dma.sgtx, 1);
 761         if (xfer->tx_buf) {
 762                 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
 763         } else {
 764                 as->dma.sgtx.dma_address = as->buffer_dma;
 765                 if (len > BUFFER_SIZE)
 766                         len = BUFFER_SIZE;
 767                 memset(as->buffer, 0, len);
 768         }
 769
 770         sg_dma_len(&as->dma.sgtx) = len;
 771         sg_dma_len(&as->dma.sgrx) = len;
 772
 773         *plen = len;
 774
 775         if (atmel_spi_dma_slave_config(as, &slave_config,
 776                                        xfer->bits_per_word))
 777                 goto err_exit;
 778
 779         /* Send both scatterlists */
 780         rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
 781                                          DMA_FROM_DEVICE,
 782                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 783         if (!rxdesc)
 784                 goto err_dma;
 785
 786         txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
 787                                          DMA_TO_DEVICE,
 788                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 789         if (!txdesc)
 790                 goto err_dma;
 791
 792         dev_dbg(master->dev.parent,
 793                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 794                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 795                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 796
 797         /* Enable relevant interrupts */
 798         spi_writel(as, IER, SPI_BIT(OVRES));
 799
 800         /* Put the callback on the RX transfer only, that should finish last */
 801         rxdesc->callback = dma_callback;
 802         rxdesc->callback_param = master;
 803
 804         /* Submit and fire RX and TX with TX last so we're ready to read! */
 805         cookie = rxdesc->tx_submit(rxdesc);
 806         if (dma_submit_error(cookie))
 807                 goto err_dma;
 808         cookie = txdesc->tx_submit(txdesc);
 809         if (dma_submit_error(cookie))
 810                 goto err_dma;
 811         rxchan->device->device_issue_pending(rxchan);
 812         txchan->device->device_issue_pending(txchan);
 813
 814         /* take back lock */
 815         atmel_spi_lock(as);
 816         return 0;
 817
 818 err_dma:
 819         spi_writel(as, IDR, SPI_BIT(OVRES));
 820         atmel_spi_stop_dma(as);
 821 err_exit:
 822         atmel_spi_lock(as);
 823         return -ENOMEM;
 824 }
 825
 826 static void atmel_spi_next_xfer_data(struct spi_master *master,
 827                                 struct spi_transfer *xfer,
 828                                 dma_addr_t *tx_dma,
 829                                 dma_addr_t *rx_dma,
 830                                 u32 *plen)
 831 {
 832         struct atmel_spi        *as = spi_master_get_devdata(master);
 833         u32                     len = *plen;
 834
 835         /* use scratch buffer only when rx or tx data is unspecified */
 836         if (xfer->rx_buf)
 837                 *rx_dma = xfer->rx_dma + xfer->len - *plen;
 838         else {
 839                 *rx_dma = as->buffer_dma;
 840                 if (len > BUFFER_SIZE)
 841                         len = BUFFER_SIZE;
 842         }
 843
 844         if (xfer->tx_buf)
 845                 *tx_dma = xfer->tx_dma + xfer->len - *plen;
 846         else {
 847                 *tx_dma = as->buffer_dma;
 848                 if (len > BUFFER_SIZE)
 849                         len = BUFFER_SIZE;
 850                 memset(as->buffer, 0, len);
 851                 dma_sync_single_for_device(&as->pdev->dev,
 852                                 as->buffer_dma, len, DMA_TO_DEVICE);
 853         }
 854
 855         *plen = len;
 856 }
 857
 858 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 859                                     struct spi_device *spi,
 860                                     struct spi_transfer *xfer)
 861 {
 862         u32                     scbr, csr;
 863         unsigned long           bus_hz;
 864
 865         /* v1 chips start out at half the peripheral bus speed. */
 866         bus_hz = clk_get_rate(as->clk);
 867         if (!atmel_spi_is_v2(as))
 868                 bus_hz /= 2;
 869
 870         /*
 871          * Calculate the lowest divider that satisfies the
 872          * constraint, assuming div32/fdiv/mbz == 0.
 873          */
 874         scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 875
 876         /*
 877          * If the resulting divider doesn't fit into the
 878          * register bitfield, we can't satisfy the constraint.
 879          */
 880         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 881                 dev_err(&spi->dev,
 882                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 883                         xfer->speed_hz, scbr, bus_hz/255);
 884                 return -EINVAL;
 885         }
 886         if (scbr == 0) {
 887                 dev_err(&spi->dev,
 888                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 889                         xfer->speed_hz, scbr, bus_hz);
 890                 return -EINVAL;
 891         }
 892         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 893         csr = SPI_BFINS(SCBR, scbr, csr);
 894         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 895
 896         return 0;
 897 }
 898
 899 /*
 900  * Submit next transfer for PDC.
 901  * lock is held, spi irq is blocked
 902  */
 903 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 904                                         struct spi_message *msg,
 905                                         struct spi_transfer *xfer)
 906 {
 907         struct atmel_spi        *as = spi_master_get_devdata(master);
 908         u32                     len;
 909         dma_addr_t              tx_dma, rx_dma;
 910
 911         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 912
 913         len = as->current_remaining_bytes;
 914         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 915         as->current_remaining_bytes -= len;
 916
 917         spi_writel(as, RPR, rx_dma);
 918         spi_writel(as, TPR, tx_dma);
 919
 920         if (msg->spi->bits_per_word > 8)
 921                 len >>= 1;
 922         spi_writel(as, RCR, len);
 923         spi_writel(as, TCR, len);
 924
 925         dev_dbg(&msg->spi->dev,
 926                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 927                 xfer, xfer->len, xfer->tx_buf,
 928                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 929                 (unsigned long long)xfer->rx_dma);
 930
 931         if (as->current_remaining_bytes) {
 932                 len = as->current_remaining_bytes;
 933                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 934                 as->current_remaining_bytes -= len;
 935
 936                 spi_writel(as, RNPR, rx_dma);
 937                 spi_writel(as, TNPR, tx_dma);
 938
 939                 if (msg->spi->bits_per_word > 8)
 940                         len >>= 1;
 941                 spi_writel(as, RNCR, len);
 942                 spi_writel(as, TNCR, len);
 943
 944                 dev_dbg(&msg->spi->dev,
 945                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 946                         xfer, xfer->len, xfer->tx_buf,
 947                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 948                         (unsigned long long)xfer->rx_dma);
 949         }
 950
 951         /* REVISIT: We're waiting for RXBUFF before we start the next
 952          * transfer because we need to handle some difficult timing
 953          * issues otherwise. If we wait for TXBUFE in one transfer and
 954          * then starts waiting for RXBUFF in the next, it's difficult
 955          * to tell the difference between the RXBUFF interrupt we're
 956          * actually waiting for and the RXBUFF interrupt of the
 957          * previous transfer.
 958          *
 959          * It should be doable, though. Just not now...
 960          */
 961         spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
 962         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 963 }
 964
 965 /*
 966  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 967  *  - The buffer is either valid for CPU access, else NULL
 968  *  - If the buffer is valid, so is its DMA address
 969  *
 970  * This driver manages the dma address unless message->is_dma_mapped.
 971  */
 972 static int
 973 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 974 {
 975         struct device   *dev = &as->pdev->dev;
 976
 977         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 978         if (xfer->tx_buf) {
 979                 /* tx_buf is a const void* where we need a void * for the dma
 980                  * mapping */
 981                 void *nonconst_tx = (void *)xfer->tx_buf;
 982
 983                 xfer->tx_dma = dma_map_single(dev,
 984                                 nonconst_tx, xfer->len,
 985                                 DMA_TO_DEVICE);
 986                 if (dma_mapping_error(dev, xfer->tx_dma))
 987                         return -ENOMEM;
 988         }
 989         if (xfer->rx_buf) {
 990                 xfer->rx_dma = dma_map_single(dev,
 991                                 xfer->rx_buf, xfer->len,
 992                                 DMA_FROM_DEVICE);
 993                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 994                         if (xfer->tx_buf)
 995                                 dma_unmap_single(dev,
 996                                                 xfer->tx_dma, xfer->len,
 997                                                 DMA_TO_DEVICE);
 998                         return -ENOMEM;
 999                 }
1000         }
1001         return 0;
1002 }
1003
1004 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
1005                                      struct spi_transfer *xfer)
1006 {
1007         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
1008                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
1009                                  xfer->len, DMA_TO_DEVICE);
1010         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
1011                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
1012                                  xfer->len, DMA_FROM_DEVICE);
1013 }
1014
1015 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
1016 {
1017         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1018 }
1019
1020 static void
1021 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
1022 {
1023         u8              *rxp;
1024         u16             *rxp16;
1025         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
1026
1027         if (xfer->rx_buf) {
1028                 if (xfer->bits_per_word > 8) {
1029                         rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
1030                         *rxp16 = spi_readl(as, RDR);
1031                 } else {
1032                         rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
1033                         *rxp = spi_readl(as, RDR);
1034                 }
1035         } else {
1036                 spi_readl(as, RDR);
1037         }
1038         if (xfer->bits_per_word > 8) {
1039                 if (as->current_remaining_bytes > 2)
1040                         as->current_remaining_bytes -= 2;
1041                 else
1042                         as->current_remaining_bytes = 0;
1043         } else {
1044                 as->current_remaining_bytes--;
1045         }
1046 }
1047
1048 static void
1049 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
1050 {
1051         u32 fifolr = spi_readl(as, FLR);
1052         u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
1053         u32 offset = xfer->len - as->current_remaining_bytes;
1054         u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
1055         u8  *bytes = (u8  *)((u8 *)xfer->rx_buf + offset);
1056         u16 rd; /* RD field is the lowest 16 bits of RDR */
1057
1058         /* Update the number of remaining bytes to transfer */
1059         num_bytes = ((xfer->bits_per_word > 8) ?
1060                      (num_data << 1) :
1061                      num_data);
1062
1063         if (as->current_remaining_bytes > num_bytes)
1064                 as->current_remaining_bytes -= num_bytes;
1065         else
1066                 as->current_remaining_bytes = 0;
1067
1068         /* Handle odd number of bytes when data are more than 8bit width */
1069         if (xfer->bits_per_word > 8)
1070                 as->current_remaining_bytes &= ~0x1;
1071
1072         /* Read data */
1073         while (num_data) {
1074                 rd = spi_readl(as, RDR);
1075                 if (xfer->rx_buf) {
1076                         if (xfer->bits_per_word > 8)
1077                                 *words++ = rd;
1078                         else
1079                                 *bytes++ = rd;
1080                 }
1081                 num_data--;
1082         }
1083 }
1084
1085 /* Called from IRQ
1086  *
1087  * Must update "current_remaining_bytes" to keep track of data
1088  * to transfer.
1089  */
1090 static void
1091 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1092 {
1093         if (as->fifo_size)
1094                 atmel_spi_pump_fifo_data(as, xfer);
1095         else
1096                 atmel_spi_pump_single_data(as, xfer);
1097 }
1098
1099 /* Interrupt
1100  *
1101  * No need for locking in this Interrupt handler: done_status is the
1102  * only information modified.
1103  */
1104 static irqreturn_t
1105 atmel_spi_pio_interrupt(int irq, void *dev_id)
1106 {
1107         struct spi_master       *master = dev_id;
1108         struct atmel_spi        *as = spi_master_get_devdata(master);
1109         u32                     status, pending, imr;
1110         struct spi_transfer     *xfer;
1111         int                     ret = IRQ_NONE;
1112
1113         imr = spi_readl(as, IMR);
1114         status = spi_readl(as, SR);
1115         pending = status & imr;
1116
1117         if (pending & SPI_BIT(OVRES)) {
1118                 ret = IRQ_HANDLED;
1119                 spi_writel(as, IDR, SPI_BIT(OVRES));
1120                 dev_warn(master->dev.parent, "overrun\n");
1121
1122                 /*
1123                  * When we get an overrun, we disregard the current
1124                  * transfer. Data will not be copied back from any
1125                  * bounce buffer and msg->actual_len will not be
1126                  * updated with the last xfer.
1127                  *
1128                  * We will also not process any remaning transfers in
1129                  * the message.
1130                  */
1131                 as->done_status = -EIO;
1132                 smp_wmb();
1133
1134                 /* Clear any overrun happening while cleaning up */
1135                 spi_readl(as, SR);
1136
1137                 complete(&as->xfer_completion);
1138
1139         } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1140                 atmel_spi_lock(as);
1141
1142                 if (as->current_remaining_bytes) {
1143                         ret = IRQ_HANDLED;
1144                         xfer = as->current_transfer;
1145                         atmel_spi_pump_pio_data(as, xfer);
1146                         if (!as->current_remaining_bytes)
1147                                 spi_writel(as, IDR, pending);
1148
1149                         complete(&as->xfer_completion);
1150                 }
1151
1152                 atmel_spi_unlock(as);
1153         } else {
1154                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1155                 ret = IRQ_HANDLED;
1156                 spi_writel(as, IDR, pending);
1157         }
1158
1159         return ret;
1160 }
1161
1162 static irqreturn_t
1163 atmel_spi_pdc_interrupt(int irq, void *dev_id)
1164 {
1165         struct spi_master       *master = dev_id;
1166         struct atmel_spi        *as = spi_master_get_devdata(master);
1167         u32                     status, pending, imr;
1168         int                     ret = IRQ_NONE;
1169
1170         imr = spi_readl(as, IMR);
1171         status = spi_readl(as, SR);
1172         pending = status & imr;
1173
1174         if (pending & SPI_BIT(OVRES)) {
1175
1176                 ret = IRQ_HANDLED;
1177
1178                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1179                                      | SPI_BIT(OVRES)));
1180
1181                 /* Clear any overrun happening while cleaning up */
1182                 spi_readl(as, SR);
1183
1184                 as->done_status = -EIO;
1185
1186                 complete(&as->xfer_completion);
1187
1188         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1189                 ret = IRQ_HANDLED;
1190
1191                 spi_writel(as, IDR, pending);
1192
1193                 complete(&as->xfer_completion);
1194         }
1195
1196         return ret;
1197 }
1198
1199 static int atmel_spi_setup(struct spi_device *spi)
1200 {
1201         struct atmel_spi        *as;
1202         struct atmel_spi_device *asd;
1203         u32                     csr;
1204         unsigned int            bits = spi->bits_per_word;
1205         unsigned int            npcs_pin;
1206         int                     ret;
1207
1208         as = spi_master_get_devdata(spi->master);
1209
1210         /* see notes above re chipselect */
1211         if (!as->use_cs_gpios && (spi->mode & SPI_CS_HIGH)) {
1212                 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
1213                 return -EINVAL;
1214         }
1215
1216         csr = SPI_BF(BITS, bits - 8);
1217         if (spi->mode & SPI_CPOL)
1218                 csr |= SPI_BIT(CPOL);
1219         if (!(spi->mode & SPI_CPHA))
1220                 csr |= SPI_BIT(NCPHA);
1221         if (!as->use_cs_gpios)
1222                 csr |= SPI_BIT(CSAAT);
1223
1224         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1225          *
1226          * DLYBCT would add delays between words, slowing down transfers.
1227          * It could potentially be useful to cope with DMA bottlenecks, but
1228          * in those cases it's probably best to just use a lower bitrate.
1229          */
1230         csr |= SPI_BF(DLYBS, 0);
1231         csr |= SPI_BF(DLYBCT, 0);
1232
1233         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1234         npcs_pin = (unsigned long)spi->controller_data;
1235
1236         if (!as->use_cs_gpios)
1237                 npcs_pin = spi->chip_select;
1238         else if (gpio_is_valid(spi->cs_gpio))
1239                 npcs_pin = spi->cs_gpio;
1240
1241         asd = spi->controller_state;
1242         if (!asd) {
1243                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1244                 if (!asd)
1245                         return -ENOMEM;
1246
1247                 if (as->use_cs_gpios) {
1248                         ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1249                         if (ret) {
1250                                 kfree(asd);
1251                                 return ret;
1252                         }
1253
1254                         gpio_direction_output(npcs_pin,
1255                                               !(spi->mode & SPI_CS_HIGH));
1256                 }
1257
1258                 asd->npcs_pin = npcs_pin;
1259                 spi->controller_state = asd;
1260         }
1261
1262         asd->csr = csr;
1263
1264         dev_dbg(&spi->dev,
1265                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1266                 bits, spi->mode, spi->chip_select, csr);
1267
1268         if (!atmel_spi_is_v2(as))
1269                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1270
1271         return 0;
1272 }
1273
1274 static int atmel_spi_one_transfer(struct spi_master *master,
1275                                         struct spi_message *msg,
1276                                         struct spi_transfer *xfer)
1277 {
1278         struct atmel_spi        *as;
1279         struct spi_device       *spi = msg->spi;
1280         u8                      bits;
1281         u32                     len;
1282         struct atmel_spi_device *asd;
1283         int                     timeout;
1284         int                     ret;
1285         unsigned long           dma_timeout;
1286
1287         as = spi_master_get_devdata(master);
1288
1289         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1290                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1291                 return -EINVAL;
1292         }
1293
1294         asd = spi->controller_state;
1295         bits = (asd->csr >> 4) & 0xf;
1296         if (bits != xfer->bits_per_word - 8) {
1297                 dev_dbg(&spi->dev,
1298                         "you can't yet change bits_per_word in transfers\n");
1299                 return -ENOPROTOOPT;
1300         }
1301
1302         /*
1303          * DMA map early, for performance (empties dcache ASAP) and
1304          * better fault reporting.
1305          */
1306         if ((!msg->is_dma_mapped)
1307                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1308                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1309                         return -ENOMEM;
1310         }
1311
1312         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1313
1314         as->done_status = 0;
1315         as->current_transfer = xfer;
1316         as->current_remaining_bytes = xfer->len;
1317         while (as->current_remaining_bytes) {
1318                 reinit_completion(&as->xfer_completion);
1319
1320                 if (as->use_pdc) {
1321                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1322                 } else if (atmel_spi_use_dma(as, xfer)) {
1323                         len = as->current_remaining_bytes;
1324                         ret = atmel_spi_next_xfer_dma_submit(master,
1325                                                                 xfer, &len);
1326                         if (ret) {
1327                                 dev_err(&spi->dev,
1328                                         "unable to use DMA, fallback to PIO\n");
1329                                 atmel_spi_next_xfer_pio(master, xfer);
1330                         } else {
1331                                 as->current_remaining_bytes -= len;
1332                                 if (as->current_remaining_bytes < 0)
1333                                         as->current_remaining_bytes = 0;
1334                         }
1335                 } else {
1336                         atmel_spi_next_xfer_pio(master, xfer);
1337                 }
1338
1339                 /* interrupts are disabled, so free the lock for schedule */
1340                 atmel_spi_unlock(as);
1341                 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1342                                                           SPI_DMA_TIMEOUT);
1343                 atmel_spi_lock(as);
1344                 if (WARN_ON(dma_timeout == 0)) {
1345                         dev_err(&spi->dev, "spi transfer timeout\n");
1346                         as->done_status = -EIO;
1347                 }
1348
1349                 if (as->done_status)
1350                         break;
1351         }
1352
1353         if (as->done_status) {
1354                 if (as->use_pdc) {
1355                         dev_warn(master->dev.parent,
1356                                 "overrun (%u/%u remaining)\n",
1357                                 spi_readl(as, TCR), spi_readl(as, RCR));
1358
1359                         /*
1360                          * Clean up DMA registers and make sure the data
1361                          * registers are empty.
1362                          */
1363                         spi_writel(as, RNCR, 0);
1364                         spi_writel(as, TNCR, 0);
1365                         spi_writel(as, RCR, 0);
1366                         spi_writel(as, TCR, 0);
1367                         for (timeout = 1000; timeout; timeout--)
1368                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1369                                         break;
1370                         if (!timeout)
1371                                 dev_warn(master->dev.parent,
1372                                          "timeout waiting for TXEMPTY");
1373                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1374                                 spi_readl(as, RDR);
1375
1376                         /* Clear any overrun happening while cleaning up */
1377                         spi_readl(as, SR);
1378
1379                 } else if (atmel_spi_use_dma(as, xfer)) {
1380                         atmel_spi_stop_dma(as);
1381                 }
1382
1383                 if (!msg->is_dma_mapped
1384                         && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1385                         atmel_spi_dma_unmap_xfer(master, xfer);
1386
1387                 return 0;
1388
1389         } else {
1390                 /* only update length if no error */
1391                 msg->actual_length += xfer->len;
1392         }
1393
1394         if (!msg->is_dma_mapped
1395                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1396                 atmel_spi_dma_unmap_xfer(master, xfer);
1397
1398         if (xfer->delay_usecs)
1399                 udelay(xfer->delay_usecs);
1400
1401         if (xfer->cs_change) {
1402                 if (list_is_last(&xfer->transfer_list,
1403                                  &msg->transfers)) {
1404                         as->keep_cs = true;
1405                 } else {
1406                         cs_deactivate(as, msg->spi);
1407                         udelay(10);
1408                         cs_activate(as, msg->spi);
1409                 }
1410         }
1411
1412         return 0;
1413 }
1414
1415 static int atmel_spi_transfer_one_message(struct spi_master *master,
1416                                                 struct spi_message *msg)
1417 {
1418         struct atmel_spi *as;
1419         struct spi_transfer *xfer;
1420         struct spi_device *spi = msg->spi;
1421         int ret = 0;
1422
1423         as = spi_master_get_devdata(master);
1424
1425         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1426                                         msg, dev_name(&spi->dev));
1427
1428         atmel_spi_lock(as);
1429         cs_activate(as, spi);
1430
1431         as->keep_cs = false;
1432
1433         msg->status = 0;
1434         msg->actual_length = 0;
1435
1436         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1437                 ret = atmel_spi_one_transfer(master, msg, xfer);
1438                 if (ret)
1439                         goto msg_done;
1440         }
1441
1442         if (as->use_pdc)
1443                 atmel_spi_disable_pdc_transfer(as);
1444
1445         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1446                 dev_dbg(&spi->dev,
1447                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1448                         xfer, xfer->len,
1449                         xfer->tx_buf, &xfer->tx_dma,
1450                         xfer->rx_buf, &xfer->rx_dma);
1451         }
1452
1453 msg_done:
1454         if (!as->keep_cs)
1455                 cs_deactivate(as, msg->spi);
1456
1457         atmel_spi_unlock(as);
1458
1459         msg->status = as->done_status;
1460         spi_finalize_current_message(spi->master);
1461
1462         return ret;
1463 }
1464
1465 static void atmel_spi_cleanup(struct spi_device *spi)
1466 {
1467         struct atmel_spi_device *asd = spi->controller_state;
1468         unsigned                gpio = (unsigned long) spi->controller_data;
1469
1470         if (!asd)
1471                 return;
1472
1473         spi->controller_state = NULL;
1474         gpio_free(gpio);
1475         kfree(asd);
1476 }
1477
1478 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1479 {
1480         return spi_readl(as, VERSION) & 0x00000fff;
1481 }
1482
1483 static void atmel_get_caps(struct atmel_spi *as)
1484 {
1485         unsigned int version;
1486
1487         version = atmel_get_version(as);
1488         dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1489
1490         as->caps.is_spi2 = version > 0x121;
1491         as->caps.has_wdrbt = version >= 0x210;
1492         as->caps.has_dma_support = version >= 0x212;
1493 }
1494
1495 /*-------------------------------------------------------------------------*/
1496
1497 static int atmel_spi_probe(struct platform_device *pdev)
1498 {
1499         struct resource         *regs;
1500         int                     irq;
1501         struct clk              *clk;
1502         int                     ret;
1503         struct spi_master       *master;
1504         struct atmel_spi        *as;
1505
1506         /* Select default pin state */
1507         pinctrl_pm_select_default_state(&pdev->dev);
1508
1509         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1510         if (!regs)
1511                 return -ENXIO;
1512
1513         irq = platform_get_irq(pdev, 0);
1514         if (irq < 0)
1515                 return irq;
1516
1517         clk = devm_clk_get(&pdev->dev, "spi_clk");
1518         if (IS_ERR(clk))
1519                 return PTR_ERR(clk);
1520
1521         /* setup spi core then atmel-specific driver state */
1522         ret = -ENOMEM;
1523         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1524         if (!master)
1525                 goto out_free;
1526
1527         /* the spi->mode bits understood by this driver: */
1528         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1529         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1530         master->dev.of_node = pdev->dev.of_node;
1531         master->bus_num = pdev->id;
1532         master->num_chipselect = master->dev.of_node ? 0 : 4;
1533         master->setup = atmel_spi_setup;
1534         master->transfer_one_message = atmel_spi_transfer_one_message;
1535         master->cleanup = atmel_spi_cleanup;
1536         master->auto_runtime_pm = true;
1537         platform_set_drvdata(pdev, master);
1538
1539         as = spi_master_get_devdata(master);
1540
1541         /*
1542          * Scratch buffer is used for throwaway rx and tx data.
1543          * It's coherent to minimize dcache pollution.
1544          */
1545         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1546                                         &as->buffer_dma, GFP_KERNEL);
1547         if (!as->buffer)
1548                 goto out_free;
1549
1550         spin_lock_init(&as->lock);
1551
1552         as->pdev = pdev;
1553         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1554         if (IS_ERR(as->regs)) {
1555                 ret = PTR_ERR(as->regs);
1556                 goto out_free_buffer;
1557         }
1558         as->phybase = regs->start;
1559         as->irq = irq;
1560         as->clk = clk;
1561
1562         init_completion(&as->xfer_completion);
1563
1564         atmel_get_caps(as);
1565
1566         as->use_cs_gpios = true;
1567         if (atmel_spi_is_v2(as) &&
1568             pdev->dev.of_node &&
1569             !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1570                 as->use_cs_gpios = false;
1571                 master->num_chipselect = 4;
1572         }
1573
1574         as->use_dma = false;
1575         as->use_pdc = false;
1576         if (as->caps.has_dma_support) {
1577                 ret = atmel_spi_configure_dma(as);
1578                 if (ret == 0)
1579                         as->use_dma = true;
1580                 else if (ret == -EPROBE_DEFER)
1581                         return ret;
1582         } else {
1583                 as->use_pdc = true;
1584         }
1585
1586         if (as->caps.has_dma_support && !as->use_dma)
1587                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1588
1589         if (as->use_pdc) {
1590                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1591                                         0, dev_name(&pdev->dev), master);
1592         } else {
1593                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1594                                         0, dev_name(&pdev->dev), master);
1595         }
1596         if (ret)
1597                 goto out_unmap_regs;
1598
1599         /* Initialize the hardware */
1600         ret = clk_prepare_enable(clk);
1601         if (ret)
1602                 goto out_free_irq;
1603         spi_writel(as, CR, SPI_BIT(SWRST));
1604         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1605         if (as->caps.has_wdrbt) {
1606                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1607                                 | SPI_BIT(MSTR));
1608         } else {
1609                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1610         }
1611
1612         if (as->use_pdc)
1613                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1614         spi_writel(as, CR, SPI_BIT(SPIEN));
1615
1616         as->fifo_size = 0;
1617         if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1618                                   &as->fifo_size)) {
1619                 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1620                 spi_writel(as, CR, SPI_BIT(FIFOEN));
1621         }
1622
1623         /* go! */
1624         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1625                         (unsigned long)regs->start, irq);
1626
1627         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1628         pm_runtime_use_autosuspend(&pdev->dev);
1629         pm_runtime_set_active(&pdev->dev);
1630         pm_runtime_enable(&pdev->dev);
1631
1632         ret = devm_spi_register_master(&pdev->dev, master);
1633         if (ret)
1634                 goto out_free_dma;
1635
1636         return 0;
1637
1638 out_free_dma:
1639         pm_runtime_disable(&pdev->dev);
1640         pm_runtime_set_suspended(&pdev->dev);
1641
1642         if (as->use_dma)
1643                 atmel_spi_release_dma(as);
1644
1645         spi_writel(as, CR, SPI_BIT(SWRST));
1646         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1647         clk_disable_unprepare(clk);
1648 out_free_irq:
1649 out_unmap_regs:
1650 out_free_buffer:
1651         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1652                         as->buffer_dma);
1653 out_free:
1654         spi_master_put(master);
1655         return ret;
1656 }
1657
1658 static int atmel_spi_remove(struct platform_device *pdev)
1659 {
1660         struct spi_master       *master = platform_get_drvdata(pdev);
1661         struct atmel_spi        *as = spi_master_get_devdata(master);
1662
1663         pm_runtime_get_sync(&pdev->dev);
1664
1665         /* reset the hardware and block queue progress */
1666         if (as->use_dma) {
1667                 atmel_spi_stop_dma(as);
1668                 atmel_spi_release_dma(as);
1669         }
1670
1671         spin_lock_irq(&as->lock);
1672         spi_writel(as, CR, SPI_BIT(SWRST));
1673         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1674         spi_readl(as, SR);
1675         spin_unlock_irq(&as->lock);
1676
1677         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1678                         as->buffer_dma);
1679
1680         clk_disable_unprepare(as->clk);
1681
1682         pm_runtime_put_noidle(&pdev->dev);
1683         pm_runtime_disable(&pdev->dev);
1684
1685         return 0;
1686 }
1687
1688 #ifdef CONFIG_PM
1689 static int atmel_spi_runtime_suspend(struct device *dev)
1690 {
1691         struct spi_master *master = dev_get_drvdata(dev);
1692         struct atmel_spi *as = spi_master_get_devdata(master);
1693
1694         clk_disable_unprepare(as->clk);
1695         pinctrl_pm_select_sleep_state(dev);
1696
1697         return 0;
1698 }
1699
1700 static int atmel_spi_runtime_resume(struct device *dev)
1701 {
1702         struct spi_master *master = dev_get_drvdata(dev);
1703         struct atmel_spi *as = spi_master_get_devdata(master);
1704
1705         pinctrl_pm_select_default_state(dev);
1706
1707         return clk_prepare_enable(as->clk);
1708 }
1709
1710 #ifdef CONFIG_PM_SLEEP
1711 static int atmel_spi_suspend(struct device *dev)
1712 {
1713         struct spi_master *master = dev_get_drvdata(dev);
1714         int ret;
1715
1716         /* Stop the queue running */
1717         ret = spi_master_suspend(master);
1718         if (ret) {
1719                 dev_warn(dev, "cannot suspend master\n");
1720                 return ret;
1721         }
1722
1723         if (!pm_runtime_suspended(dev))
1724                 atmel_spi_runtime_suspend(dev);
1725
1726         return 0;
1727 }
1728
1729 static int atmel_spi_resume(struct device *dev)
1730 {
1731         struct spi_master *master = dev_get_drvdata(dev);
1732         int ret;
1733
1734         if (!pm_runtime_suspended(dev)) {
1735                 ret = atmel_spi_runtime_resume(dev);
1736                 if (ret)
1737                         return ret;
1738         }
1739
1740         /* Start the queue running */
1741         ret = spi_master_resume(master);
1742         if (ret)
1743                 dev_err(dev, "problem starting queue (%d)\n", ret);
1744
1745         return ret;
1746 }
1747 #endif
1748
1749 static const struct dev_pm_ops atmel_spi_pm_ops = {
1750         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1751         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1752                            atmel_spi_runtime_resume, NULL)
1753 };
1754 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1755 #else
1756 #define ATMEL_SPI_PM_OPS        NULL
1757 #endif
1758
1759 #if defined(CONFIG_OF)
1760 static const struct of_device_id atmel_spi_dt_ids[] = {
1761         { .compatible = "atmel,at91rm9200-spi" },
1762         { /* sentinel */ }
1763 };
1764
1765 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1766 #endif
1767
1768 static struct platform_driver atmel_spi_driver = {
1769         .driver         = {
1770                 .name   = "atmel_spi",
1771                 .pm     = ATMEL_SPI_PM_OPS,
1772                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1773         },
1774         .probe          = atmel_spi_probe,
1775         .remove         = atmel_spi_remove,
1776 };
1777 module_platform_driver(atmel_spi_driver);
1778
1779 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1780 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1781 MODULE_LICENSE("GPL");
1782 MODULE_ALIAS("platform:atmel_spi");