drivers/spi/spi-amd.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 //
   3 // AMD SPI controller driver
   4 //
   5 // Copyright (c) 2020, Advanced Micro Devices, Inc.
   6 //
   7 // Author: Sanjay R Mehta <sanju.mehta@amd.com>
   8
   9 #include <linux/acpi.h>
  10 #include <linux/init.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/delay.h>
  14 #include <linux/spi/spi.h>
  15
  16 #define AMD_SPI_CTRL0_REG       0x00
  17 #define AMD_SPI_EXEC_CMD        BIT(16)
  18 #define AMD_SPI_FIFO_CLEAR      BIT(20)
  19 #define AMD_SPI_BUSY            BIT(31)
  20
  21 #define AMD_SPI_OPCODE_MASK     0xFF
  22
  23 #define AMD_SPI_ALT_CS_REG      0x1D
  24 #define AMD_SPI_ALT_CS_MASK     0x3
  25
  26 #define AMD_SPI_FIFO_BASE       0x80
  27 #define AMD_SPI_TX_COUNT_REG    0x48
  28 #define AMD_SPI_RX_COUNT_REG    0x4B
  29 #define AMD_SPI_STATUS_REG      0x4C
  30
  31 #define AMD_SPI_FIFO_SIZE       70
  32 #define AMD_SPI_MEM_SIZE        200
  33
  34 /* M_CMD OP codes for SPI */
  35 #define AMD_SPI_XFER_TX         1
  36 #define AMD_SPI_XFER_RX         2
  37
  38 struct amd_spi {
  39         void __iomem *io_remap_addr;
  40         unsigned long io_base_addr;
  41         u32 rom_addr;
  42         u8 chip_select;
  43 };
  44
  45 static inline u8 amd_spi_readreg8(struct spi_master *master, int idx)
  46 {
  47         struct amd_spi *amd_spi = spi_master_get_devdata(master);
  48
  49         return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
  50 }
  51
  52 static inline void amd_spi_writereg8(struct spi_master *master, int idx,
  53                                      u8 val)
  54 {
  55         struct amd_spi *amd_spi = spi_master_get_devdata(master);
  56
  57         iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
  58 }
  59
  60 static inline void amd_spi_setclear_reg8(struct spi_master *master, int idx,
  61                                          u8 set, u8 clear)
  62 {
  63         u8 tmp = amd_spi_readreg8(master, idx);
  64
  65         tmp = (tmp & ~clear) | set;
  66         amd_spi_writereg8(master, idx, tmp);
  67 }
  68
  69 static inline u32 amd_spi_readreg32(struct spi_master *master, int idx)
  70 {
  71         struct amd_spi *amd_spi = spi_master_get_devdata(master);
  72
  73         return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
  74 }
  75
  76 static inline void amd_spi_writereg32(struct spi_master *master, int idx,
  77                                       u32 val)
  78 {
  79         struct amd_spi *amd_spi = spi_master_get_devdata(master);
  80
  81         iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
  82 }
  83
  84 static inline void amd_spi_setclear_reg32(struct spi_master *master, int idx,
  85                                           u32 set, u32 clear)
  86 {
  87         u32 tmp = amd_spi_readreg32(master, idx);
  88
  89         tmp = (tmp & ~clear) | set;
  90         amd_spi_writereg32(master, idx, tmp);
  91 }
  92
  93 static void amd_spi_select_chip(struct spi_master *master)
  94 {
  95         struct amd_spi *amd_spi = spi_master_get_devdata(master);
  96         u8 chip_select = amd_spi->chip_select;
  97
  98         amd_spi_setclear_reg8(master, AMD_SPI_ALT_CS_REG, chip_select,
  99                               AMD_SPI_ALT_CS_MASK);
 100 }
 101
 102 static void amd_spi_clear_fifo_ptr(struct spi_master *master)
 103 {
 104         amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR,
 105                                AMD_SPI_FIFO_CLEAR);
 106 }
 107
 108 static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode)
 109 {
 110         amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode,
 111                                AMD_SPI_OPCODE_MASK);
 112 }
 113
 114 static inline void amd_spi_set_rx_count(struct spi_master *master,
 115                                         u8 rx_count)
 116 {
 117         amd_spi_setclear_reg8(master, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
 118 }
 119
 120 static inline void amd_spi_set_tx_count(struct spi_master *master,
 121                                         u8 tx_count)
 122 {
 123         amd_spi_setclear_reg8(master, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
 124 }
 125
 126 static inline int amd_spi_busy_wait(struct amd_spi *amd_spi)
 127 {
 128         bool spi_busy;
 129         int timeout = 100000;
 130
 131         /* poll for SPI bus to become idle */
 132         spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr +
 133                     AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
 134         while (spi_busy) {
 135                 usleep_range(10, 20);
 136                 if (timeout-- < 0)
 137                         return -ETIMEDOUT;
 138
 139                 spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr +
 140                             AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY;
 141         }
 142
 143         return 0;
 144 }
 145
 146 static void amd_spi_execute_opcode(struct spi_master *master)
 147 {
 148         struct amd_spi *amd_spi = spi_master_get_devdata(master);
 149
 150         /* Set ExecuteOpCode bit in the CTRL0 register */
 151         amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
 152                                AMD_SPI_EXEC_CMD);
 153
 154         amd_spi_busy_wait(amd_spi);
 155 }
 156
 157 static int amd_spi_master_setup(struct spi_device *spi)
 158 {
 159         struct spi_master *master = spi->master;
 160
 161         amd_spi_clear_fifo_ptr(master);
 162
 163         return 0;
 164 }
 165
 166 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
 167                                     struct spi_master *master,
 168                                     struct spi_message *message)
 169 {
 170         struct spi_transfer *xfer = NULL;
 171         u8 cmd_opcode;
 172         u8 *buf = NULL;
 173         u32 m_cmd = 0;
 174         u32 i = 0;
 175         u32 tx_len = 0, rx_len = 0;
 176
 177         list_for_each_entry(xfer, &message->transfers,
 178                             transfer_list) {
 179                 if (xfer->rx_buf)
 180                         m_cmd = AMD_SPI_XFER_RX;
 181                 if (xfer->tx_buf)
 182                         m_cmd = AMD_SPI_XFER_TX;
 183
 184                 if (m_cmd & AMD_SPI_XFER_TX) {
 185                         buf = (u8 *)xfer->tx_buf;
 186                         tx_len = xfer->len - 1;
 187                         cmd_opcode = *(u8 *)xfer->tx_buf;
 188                         buf++;
 189                         amd_spi_set_opcode(master, cmd_opcode);
 190
 191                         /* Write data into the FIFO. */
 192                         for (i = 0; i < tx_len; i++) {
 193                                 iowrite8(buf[i],
 194                                          ((u8 __iomem *)amd_spi->io_remap_addr +
 195                                          AMD_SPI_FIFO_BASE + i));
 196                         }
 197
 198                         amd_spi_set_tx_count(master, tx_len);
 199                         amd_spi_clear_fifo_ptr(master);
 200                         /* Execute command */
 201                         amd_spi_execute_opcode(master);
 202                 }
 203                 if (m_cmd & AMD_SPI_XFER_RX) {
 204                         /*
 205                          * Store no. of bytes to be received from
 206                          * FIFO
 207                          */
 208                         rx_len = xfer->len;
 209                         buf = (u8 *)xfer->rx_buf;
 210                         amd_spi_set_rx_count(master, rx_len);
 211                         amd_spi_clear_fifo_ptr(master);
 212                         /* Execute command */
 213                         amd_spi_execute_opcode(master);
 214                         /* Read data from FIFO to receive buffer  */
 215                         for (i = 0; i < rx_len; i++)
 216                                 buf[i] = amd_spi_readreg8(master,
 217                                                           AMD_SPI_FIFO_BASE +
 218                                                           tx_len + i);
 219                 }
 220         }
 221
 222         /* Update statistics */
 223         message->actual_length = tx_len + rx_len + 1;
 224         /* complete the transaction */
 225         message->status = 0;
 226         spi_finalize_current_message(master);
 227
 228         return 0;
 229 }
 230
 231 static int amd_spi_master_transfer(struct spi_master *master,
 232                                    struct spi_message *msg)
 233 {
 234         struct amd_spi *amd_spi = spi_master_get_devdata(master);
 235         struct spi_device *spi = msg->spi;
 236
 237         amd_spi->chip_select = spi->chip_select;
 238         amd_spi_select_chip(master);
 239
 240         /*
 241          * Extract spi_transfers from the spi message and
 242          * program the controller.
 243          */
 244         amd_spi_fifo_xfer(amd_spi, master, msg);
 245
 246         return 0;
 247 }
 248
 249 static size_t amd_spi_max_transfer_size(struct spi_device *spi)
 250 {
 251         return AMD_SPI_FIFO_SIZE;
 252 }
 253
 254 static int amd_spi_probe(struct platform_device *pdev)
 255 {
 256         struct device *dev = &pdev->dev;
 257         struct spi_master *master;
 258         struct amd_spi *amd_spi;
 259         struct resource *res;
 260         int err = 0;
 261
 262         /* Allocate storage for spi_master and driver private data */
 263         master = spi_alloc_master(dev, sizeof(struct amd_spi));
 264         if (!master) {
 265                 dev_err(dev, "Error allocating SPI master\n");
 266                 return -ENOMEM;
 267         }
 268
 269         amd_spi = spi_master_get_devdata(master);
 270
 271         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 272         amd_spi->io_remap_addr = devm_ioremap_resource(&pdev->dev, res);
 273         if (IS_ERR(amd_spi->io_remap_addr)) {
 274                 err = PTR_ERR(amd_spi->io_remap_addr);
 275                 dev_err(dev, "error %d ioremap of SPI registers failed\n", err);
 276                 goto err_free_master;
 277         }
 278         dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
 279
 280         /* Initialize the spi_master fields */
 281         master->bus_num = 0;
 282         master->num_chipselect = 4;
 283         master->mode_bits = 0;
 284         master->flags = SPI_MASTER_HALF_DUPLEX;
 285         master->setup = amd_spi_master_setup;
 286         master->transfer_one_message = amd_spi_master_transfer;
 287         master->max_transfer_size = amd_spi_max_transfer_size;
 288         master->max_message_size = amd_spi_max_transfer_size;
 289
 290         /* Register the controller with SPI framework */
 291         err = devm_spi_register_master(dev, master);
 292         if (err) {
 293                 dev_err(dev, "error %d registering SPI controller\n", err);
 294                 goto err_free_master;
 295         }
 296
 297         return 0;
 298
 299 err_free_master:
 300         spi_master_put(master);
 301
 302         return err;
 303 }
 304
 305 #ifdef CONFIG_ACPI
 306 static const struct acpi_device_id spi_acpi_match[] = {
 307         { "AMDI0061", 0 },
 308         {},
 309 };
 310 MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
 311 #endif
 312
 313 static struct platform_driver amd_spi_driver = {
 314         .driver = {
 315                 .name = "amd_spi",
 316                 .acpi_match_table = ACPI_PTR(spi_acpi_match),
 317         },
 318         .probe = amd_spi_probe,
 319 };
 320
 321 module_platform_driver(amd_spi_driver);
 322
 323 MODULE_LICENSE("Dual BSD/GPL");
 324 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
 325 MODULE_DESCRIPTION("AMD SPI Master Controller Driver");