1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/debugfs.h>
12 #include <linux/of_irq.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 #include <linux/slab.h>
17 #include <linux/pm_wakeirq.h>
18 #include <linux/slimbus.h>
19 #include <linux/soundwire/sdw.h>
20 #include <linux/soundwire/sdw_registers.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
25 #define SWRM_COMP_SW_RESET 0x008
26 #define SWRM_COMP_STATUS 0x014
27 #define SWRM_LINK_MANAGER_EE 0x018
29 #define SWRM_FRM_GEN_ENABLED BIT(0)
30 #define SWRM_VERSION_1_3_0 0x01030000
31 #define SWRM_VERSION_1_5_1 0x01050001
32 #define SWRM_VERSION_1_7_0 0x01070000
33 #define SWRM_VERSION_2_0_0 0x02000000
34 #define SWRM_COMP_HW_VERSION 0x00
35 #define SWRM_COMP_CFG_ADDR 0x04
36 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
37 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
38 #define SWRM_COMP_PARAMS 0x100
39 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
40 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
42 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
43 #define SWRM_COMP_MASTER_ID 0x104
44 #define SWRM_V1_3_INTERRUPT_STATUS 0x200
45 #define SWRM_V2_0_INTERRUPT_STATUS 0x5000
46 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
48 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
49 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
50 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
51 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
53 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
54 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
55 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
56 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
57 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
58 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11)
59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12)
60 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
61 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
62 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
63 #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED BIT(19)
64 #define SWRM_INTERRUPT_MAX 17
65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204
66 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208
67 #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008
68 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210
69 #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004
70 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300
71 #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020
72 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304
73 #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024
74 #define SWRM_CMD_FIFO_CMD 0x308
75 #define SWRM_CMD_FIFO_FLUSH 0x1
76 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C
77 #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050
78 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
79 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
80 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
81 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
82 #define SWRM_RD_WR_CMD_RETRIES 0x7
83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318
84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040
85 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
86 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
91 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
92 #define SWRM_MCP_BUS_CTRL 0x1044
93 #define SWRM_MCP_BUS_CLK_START BIT(1)
94 #define SWRM_MCP_CFG_ADDR 0x1048
95 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
96 #define SWRM_DEF_CMD_NO_PINGS 0x1f
97 #define SWRM_MCP_STATUS 0x104C
98 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
99 #define SWRM_MCP_SLV_STATUS 0x1090
100 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
101 #define SWRM_MCP_SLV_STATUS_SZ 2
102 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
110 #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
111 #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
113 #define SWRM_V2_0_CLK_CTRL 0x5060
114 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0)
115 #define SWRM_V2_0_LINK_STATUS 0x5064
117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
120 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
121 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
122 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
123 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
125 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
126 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
128 #define MAX_FREQ_NUM 1
129 #define TIMEOUT_MS 100
130 #define QCOM_SWRM_MAX_RD_LEN 0x1
131 #define QCOM_SDW_MAX_PORTS 14
132 #define DEFAULT_CLK_FREQ 9600000
133 #define SWRM_MAX_DAIS 0xF
134 #define SWR_INVALID_PARAM 0xFF
135 #define SWR_HSTOP_MAX_VAL 0xF
136 #define SWR_HSTART_MIN_VAL 0x0
137 #define SWR_BROADCAST_CMD_ID 0x0F
138 #define SWR_MAX_CMD_ID 14
139 #define MAX_FIFO_RD_RETRY 3
140 #define SWR_OVERFLOW_RETRY_COUNT 30
141 #define SWRM_LINK_STATUS_RETRY_CNT 100
149 struct qcom_swrm_port_config {
162 * Internal IDs for different register layouts. Only few registers differ per
163 * each variant, so the list of IDs below does not include all of registers.
166 SWRM_REG_FRAME_GEN_ENABLED,
167 SWRM_REG_INTERRUPT_STATUS,
168 SWRM_REG_INTERRUPT_MASK_ADDR,
169 SWRM_REG_INTERRUPT_CLEAR,
170 SWRM_REG_INTERRUPT_CPU_EN,
171 SWRM_REG_CMD_FIFO_WR_CMD,
172 SWRM_REG_CMD_FIFO_RD_CMD,
173 SWRM_REG_CMD_FIFO_STATUS,
174 SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
177 struct qcom_swrm_ctrl {
180 struct regmap *regmap;
182 const unsigned int *reg_layout;
184 struct reset_control *audio_cgcr;
185 #ifdef CONFIG_DEBUG_FS
186 struct dentry *debugfs;
188 struct completion broadcast;
189 struct completion enumeration;
190 /* Port alloc/free lock */
191 struct mutex port_lock;
194 unsigned int version;
200 unsigned long dout_port_mask;
201 unsigned long din_port_mask;
205 /* Port numbers are 1 - 14 */
206 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1];
207 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
208 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
209 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
210 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
214 bool clock_stop_not_supported;
217 struct qcom_swrm_data {
220 bool sw_clk_gate_required;
222 const unsigned int *reg_layout;
225 static const unsigned int swrm_v1_3_reg_layout[] = {
226 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
227 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
228 [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
229 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
230 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
231 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
232 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
233 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
234 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
237 static const struct qcom_swrm_data swrm_v1_3_data = {
240 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
241 .reg_layout = swrm_v1_3_reg_layout,
244 static const struct qcom_swrm_data swrm_v1_5_data = {
247 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
248 .reg_layout = swrm_v1_3_reg_layout,
251 static const struct qcom_swrm_data swrm_v1_6_data = {
254 .sw_clk_gate_required = true,
255 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
256 .reg_layout = swrm_v1_3_reg_layout,
259 static const unsigned int swrm_v2_0_reg_layout[] = {
260 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
261 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
262 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
263 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
264 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
265 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
266 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
267 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
268 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
271 static const struct qcom_swrm_data swrm_v2_0_data = {
274 .sw_clk_gate_required = true,
275 .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
276 .reg_layout = swrm_v2_0_reg_layout,
279 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
281 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
284 struct regmap *wcd_regmap = ctrl->regmap;
287 /* pg register + offset */
288 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
293 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
301 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
304 struct regmap *wcd_regmap = ctrl->regmap;
306 /* pg register + offset */
307 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
312 /* write address register */
313 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
321 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
324 *val = readl(ctrl->mmio + reg);
328 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
331 writel(val, ctrl->mmio + reg);
335 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
336 u8 dev_addr, u16 reg_addr)
341 if (id != SWR_BROADCAST_CMD_ID) {
342 if (id < SWR_MAX_CMD_ID)
348 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
353 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
355 u32 fifo_outstanding_data, value;
356 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
359 /* Check for fifo underflow during read */
360 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
362 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
364 /* Check if read data is available in read fifo */
365 if (fifo_outstanding_data > 0)
368 usleep_range(500, 510);
369 } while (fifo_retry_count--);
371 if (fifo_outstanding_data == 0) {
372 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
379 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
381 u32 fifo_outstanding_cmds, value;
382 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
385 /* Check for fifo overflow during write */
386 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
388 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
390 /* Check for space in write fifo before writing */
391 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
394 usleep_range(500, 510);
395 } while (fifo_retry_count--);
397 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
398 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
405 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
407 u32 fifo_outstanding_cmds, value;
408 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
410 /* Check for fifo overflow during write */
411 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
412 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
414 if (fifo_outstanding_cmds) {
415 while (fifo_retry_count) {
416 usleep_range(500, 510);
417 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
418 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
420 if (fifo_outstanding_cmds == 0)
431 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
432 u8 dev_addr, u16 reg_addr)
439 if (dev_addr == SDW_BROADCAST_DEV_NUM) {
440 cmd_id = SWR_BROADCAST_CMD_ID;
441 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
444 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
448 if (swrm_wait_for_wr_fifo_avail(ctrl))
449 return SDW_CMD_FAIL_OTHER;
451 if (cmd_id == SWR_BROADCAST_CMD_ID)
452 reinit_completion(&ctrl->broadcast);
454 /* Its assumed that write is okay as we do not get any status back */
455 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
457 if (ctrl->version <= SWRM_VERSION_1_3_0)
458 usleep_range(150, 155);
460 if (cmd_id == SWR_BROADCAST_CMD_ID) {
461 swrm_wait_for_wr_fifo_done(ctrl);
463 * sleep for 10ms for MSM soundwire variant to allow broadcast
464 * command to complete.
466 ret = wait_for_completion_timeout(&ctrl->broadcast,
467 msecs_to_jiffies(TIMEOUT_MS));
469 ret = SDW_CMD_IGNORED;
479 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
480 u8 dev_addr, u16 reg_addr,
483 u32 cmd_data, cmd_id, val, retry_attempt = 0;
485 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
488 * Check for outstanding cmd wrt. write fifo depth to avoid
489 * overflow as read will also increase write fifo cnt.
491 swrm_wait_for_wr_fifo_avail(ctrl);
493 /* wait for FIFO RD to complete to avoid overflow */
494 usleep_range(100, 105);
495 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
496 /* wait for FIFO RD CMD complete to avoid overflow */
497 usleep_range(250, 255);
499 if (swrm_wait_for_rd_fifo_avail(ctrl))
500 return SDW_CMD_FAIL_OTHER;
503 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
505 rval[0] = cmd_data & 0xFF;
506 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
508 if (cmd_id != ctrl->rcmd_id) {
509 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
510 /* wait 500 us before retry on fifo read failure */
511 usleep_range(500, 505);
512 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
513 SWRM_CMD_FIFO_FLUSH);
514 ctrl->reg_write(ctrl,
515 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
523 } while (retry_attempt < MAX_FIFO_RD_RETRY);
525 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
526 dev_num: 0x%x, cmd_data: 0x%x\n",
527 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
529 return SDW_CMD_IGNORED;
532 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
537 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
539 for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
540 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
542 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
543 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
551 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
556 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
557 ctrl->slave_status = val;
559 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
562 s = (val >> (i * 2));
563 s &= SWRM_MCP_SLV_STATUS_MASK;
568 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
569 struct sdw_slave *slave, int devnum)
571 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
574 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
575 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
576 status &= SWRM_MCP_SLV_STATUS_MASK;
578 if (status == SDW_SLAVE_ATTACHED) {
580 slave->dev_num = devnum;
581 mutex_lock(&bus->bus_lock);
582 set_bit(devnum, bus->assigned);
583 mutex_unlock(&bus->bus_lock);
587 static int qcom_swrm_enumerate(struct sdw_bus *bus)
589 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
590 struct sdw_slave *slave, *_s;
591 struct sdw_slave_id id;
596 char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
598 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
599 /* do not continue if the status is Not Present */
600 if (!ctrl->status[i])
603 /*SCP_Devid5 - Devid 4*/
604 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
606 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
607 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
612 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
613 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
614 ((u64)buf1[0] << 40);
616 sdw_extract_slave_id(bus, addr, &id);
618 ctrl->clock_stop_not_supported = false;
619 /* Now compare with entries */
620 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
621 if (sdw_compare_devid(slave, id) == 0) {
622 qcom_swrm_set_slave_dev_num(bus, slave, i);
623 if (slave->prop.clk_stop_mode1)
624 ctrl->clock_stop_not_supported = true;
632 qcom_swrm_set_slave_dev_num(bus, NULL, i);
633 sdw_slave_add(bus, &id, NULL);
637 complete(&ctrl->enumeration);
641 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
643 struct qcom_swrm_ctrl *ctrl = dev_id;
646 ret = pm_runtime_get_sync(ctrl->dev);
647 if (ret < 0 && ret != -EACCES) {
648 dev_err_ratelimited(ctrl->dev,
649 "pm_runtime_get_sync failed in %s, ret %d\n",
651 pm_runtime_put_noidle(ctrl->dev);
655 if (ctrl->wake_irq > 0) {
656 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
657 disable_irq_nosync(ctrl->wake_irq);
660 pm_runtime_mark_last_busy(ctrl->dev);
661 pm_runtime_put_autosuspend(ctrl->dev);
666 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
668 struct qcom_swrm_ctrl *ctrl = dev_id;
669 u32 value, intr_sts, intr_sts_masked, slave_status;
672 int ret = IRQ_HANDLED;
673 clk_prepare_enable(ctrl->hclk);
675 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
677 intr_sts_masked = intr_sts & ctrl->intr_mask;
680 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
681 value = intr_sts_masked & BIT(i);
686 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
687 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
689 dev_err_ratelimited(ctrl->dev,
690 "no slave alert found.spurious interrupt\n");
692 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
696 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
697 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
698 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
699 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
700 if (ctrl->slave_status == slave_status) {
701 dev_dbg(ctrl->dev, "Slave status not changed %x\n",
704 qcom_swrm_get_device_status(ctrl);
705 qcom_swrm_enumerate(&ctrl->bus);
706 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
709 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
710 dev_err_ratelimited(ctrl->dev,
711 "%s: SWR bus clsh detected\n",
713 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
714 ctrl->reg_write(ctrl,
715 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
718 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
720 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
722 dev_err_ratelimited(ctrl->dev,
723 "%s: SWR read FIFO overflow fifo status 0x%x\n",
726 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
728 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
730 dev_err_ratelimited(ctrl->dev,
731 "%s: SWR read FIFO underflow fifo status 0x%x\n",
734 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
736 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
739 "%s: SWR write FIFO overflow fifo status %x\n",
741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
743 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
745 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
747 dev_err_ratelimited(ctrl->dev,
748 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
752 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
753 dev_err_ratelimited(ctrl->dev,
754 "%s: SWR Port collision detected\n",
756 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
757 ctrl->reg_write(ctrl,
758 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
761 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
762 dev_err_ratelimited(ctrl->dev,
763 "%s: SWR read enable valid mismatch\n",
766 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
767 ctrl->reg_write(ctrl,
768 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
771 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
772 complete(&ctrl->broadcast);
774 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
776 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
778 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
780 case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED:
782 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
785 "%s: SWR CMD ignored, fifo status %x\n",
788 /* Wait 3.5ms to clear */
789 usleep_range(3500, 3505);
792 dev_err_ratelimited(ctrl->dev,
793 "%s: SWR unknown interrupt value: %d\n",
799 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
801 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
803 intr_sts_masked = intr_sts & ctrl->intr_mask;
804 } while (intr_sts_masked);
806 clk_disable_unprepare(ctrl->hclk);
810 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
812 int retry = SWRM_LINK_STATUS_RETRY_CNT;
816 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],
818 if (comp_sts & SWRM_FRM_GEN_ENABLED)
821 usleep_range(500, 510);
824 dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
825 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
830 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
834 /* Clear Rows and Cols */
835 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
836 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
838 reset_control_reset(ctrl->audio_cgcr);
840 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
842 /* Enable Auto enumeration */
843 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
845 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
846 /* Mask soundwire interrupts */
847 if (ctrl->version < SWRM_VERSION_2_0_0)
848 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
849 SWRM_INTERRUPT_STATUS_RMSK);
851 /* Configure No pings */
852 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
853 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
854 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
856 if (ctrl->version == SWRM_VERSION_1_7_0) {
857 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
858 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
859 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
860 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
861 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
862 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
863 SWRM_V2_0_CLK_CTRL_CLK_START);
865 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
868 /* Configure number of retries of a read/write cmd */
869 if (ctrl->version >= SWRM_VERSION_1_5_1) {
870 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
871 SWRM_RD_WR_CMD_RETRIES |
872 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
874 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
875 SWRM_RD_WR_CMD_RETRIES);
879 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
881 /* Set IRQ to PULSE */
882 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
883 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK);
885 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
888 /* enable CPU IRQs */
890 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
891 SWRM_INTERRUPT_STATUS_RMSK);
894 /* Set IRQ to PULSE */
895 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
896 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
897 SWRM_COMP_CFG_ENABLE_MSK);
899 swrm_wait_for_frame_gen_enabled(ctrl);
900 ctrl->slave_status = 0;
901 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
902 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
903 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
908 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
911 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
914 if (msg->flags == SDW_MSG_FLAG_READ) {
915 for (i = 0; i < msg->len;) {
916 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
919 len = QCOM_SWRM_MAX_RD_LEN;
921 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
929 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
930 for (i = 0; i < msg->len; i++) {
931 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
935 return SDW_CMD_IGNORED;
942 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
944 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
945 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
948 ctrl->reg_read(ctrl, reg, &val);
950 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
951 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
953 return ctrl->reg_write(ctrl, reg, val);
956 static int qcom_swrm_port_params(struct sdw_bus *bus,
957 struct sdw_port_params *p_params,
960 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
962 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
967 static int qcom_swrm_transport_params(struct sdw_bus *bus,
968 struct sdw_transport_params *params,
969 enum sdw_reg_bank bank)
971 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
972 struct qcom_swrm_port_config *pcfg;
974 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
977 pcfg = &ctrl->pconfig[params->port_num];
979 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
980 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
981 value |= pcfg->si & 0xff;
983 ret = ctrl->reg_write(ctrl, reg, value);
987 if (pcfg->si > 0xff) {
988 value = (pcfg->si >> 8) & 0xff;
989 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
990 ret = ctrl->reg_write(ctrl, reg, value);
995 if (pcfg->lane_control != SWR_INVALID_PARAM) {
996 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
997 value = pcfg->lane_control;
998 ret = ctrl->reg_write(ctrl, reg, value);
1003 if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1004 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
1005 value = pcfg->blk_group_count;
1006 ret = ctrl->reg_write(ctrl, reg, value);
1011 if (pcfg->hstart != SWR_INVALID_PARAM
1012 && pcfg->hstop != SWR_INVALID_PARAM) {
1013 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1014 value = (pcfg->hstop << 4) | pcfg->hstart;
1015 ret = ctrl->reg_write(ctrl, reg, value);
1017 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1018 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
1019 ret = ctrl->reg_write(ctrl, reg, value);
1025 if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1026 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
1027 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1034 static int qcom_swrm_port_enable(struct sdw_bus *bus,
1035 struct sdw_enable_ch *enable_ch,
1038 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
1039 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1042 ctrl->reg_read(ctrl, reg, &val);
1044 if (enable_ch->enable)
1045 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1047 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1049 return ctrl->reg_write(ctrl, reg, val);
1052 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
1053 .dpn_set_port_params = qcom_swrm_port_params,
1054 .dpn_set_port_transport_params = qcom_swrm_transport_params,
1055 .dpn_port_enable_ch = qcom_swrm_port_enable,
1058 static const struct sdw_master_ops qcom_swrm_ops = {
1059 .xfer_msg = qcom_swrm_xfer_msg,
1060 .pre_bank_switch = qcom_swrm_pre_bank_switch,
1063 static int qcom_swrm_compute_params(struct sdw_bus *bus)
1065 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1066 struct sdw_master_runtime *m_rt;
1067 struct sdw_slave_runtime *s_rt;
1068 struct sdw_port_runtime *p_rt;
1069 struct qcom_swrm_port_config *pcfg;
1070 struct sdw_slave *slave;
1071 unsigned int m_port;
1074 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
1075 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1076 pcfg = &ctrl->pconfig[p_rt->num];
1077 p_rt->transport_params.port_num = p_rt->num;
1078 if (pcfg->word_length != SWR_INVALID_PARAM) {
1079 sdw_fill_port_params(&p_rt->port_params,
1080 p_rt->num, pcfg->word_length + 1,
1081 SDW_PORT_FLOW_MODE_ISOCH,
1082 SDW_PORT_DATA_MODE_NORMAL);
1087 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1088 slave = s_rt->slave;
1089 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1090 m_port = slave->m_port_map[p_rt->num];
1091 /* port config starts at offset 0 so -1 from actual port number */
1093 pcfg = &ctrl->pconfig[m_port];
1095 pcfg = &ctrl->pconfig[i];
1096 p_rt->transport_params.port_num = p_rt->num;
1097 p_rt->transport_params.sample_interval =
1099 p_rt->transport_params.offset1 = pcfg->off1;
1100 p_rt->transport_params.offset2 = pcfg->off2;
1101 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1102 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1104 p_rt->transport_params.hstart = pcfg->hstart;
1105 p_rt->transport_params.hstop = pcfg->hstop;
1106 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1107 if (pcfg->word_length != SWR_INVALID_PARAM) {
1108 sdw_fill_port_params(&p_rt->port_params,
1110 pcfg->word_length + 1,
1111 SDW_PORT_FLOW_MODE_ISOCH,
1112 SDW_PORT_DATA_MODE_NORMAL);
1122 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1126 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1127 struct sdw_stream_runtime *stream)
1129 struct sdw_master_runtime *m_rt;
1130 struct sdw_port_runtime *p_rt;
1131 unsigned long *port_mask;
1133 mutex_lock(&ctrl->port_lock);
1135 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1136 if (m_rt->direction == SDW_DATA_DIR_RX)
1137 port_mask = &ctrl->dout_port_mask;
1139 port_mask = &ctrl->din_port_mask;
1141 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1142 clear_bit(p_rt->num, port_mask);
1145 mutex_unlock(&ctrl->port_lock);
1148 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1149 struct sdw_stream_runtime *stream,
1150 struct snd_pcm_hw_params *params,
1153 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
1154 struct sdw_stream_config sconfig;
1155 struct sdw_master_runtime *m_rt;
1156 struct sdw_slave_runtime *s_rt;
1157 struct sdw_port_runtime *p_rt;
1158 struct sdw_slave *slave;
1159 unsigned long *port_mask;
1160 int i, maxport, pn, nports = 0, ret = 0;
1161 unsigned int m_port;
1163 mutex_lock(&ctrl->port_lock);
1164 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1165 if (m_rt->direction == SDW_DATA_DIR_RX) {
1166 maxport = ctrl->num_dout_ports;
1167 port_mask = &ctrl->dout_port_mask;
1169 maxport = ctrl->num_din_ports;
1170 port_mask = &ctrl->din_port_mask;
1173 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1174 slave = s_rt->slave;
1175 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1176 m_port = slave->m_port_map[p_rt->num];
1177 /* Port numbers start from 1 - 14*/
1181 pn = find_first_zero_bit(port_mask, maxport);
1184 dev_err(ctrl->dev, "All ports busy\n");
1188 set_bit(pn, port_mask);
1189 pconfig[nports].num = pn;
1190 pconfig[nports].ch_mask = p_rt->ch_mask;
1196 if (direction == SNDRV_PCM_STREAM_CAPTURE)
1197 sconfig.direction = SDW_DATA_DIR_TX;
1199 sconfig.direction = SDW_DATA_DIR_RX;
1201 /* hw parameters wil be ignored as we only support PDM */
1202 sconfig.ch_count = 1;
1203 sconfig.frame_rate = params_rate(params);
1204 sconfig.type = stream->type;
1206 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1210 for (i = 0; i < nports; i++)
1211 clear_bit(pconfig[i].num, port_mask);
1214 mutex_unlock(&ctrl->port_lock);
1219 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1220 struct snd_pcm_hw_params *params,
1221 struct snd_soc_dai *dai)
1223 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1224 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1227 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1230 qcom_swrm_stream_free_ports(ctrl, sruntime);
1235 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1236 struct snd_soc_dai *dai)
1238 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1239 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1241 qcom_swrm_stream_free_ports(ctrl, sruntime);
1242 sdw_stream_remove_master(&ctrl->bus, sruntime);
1247 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1248 void *stream, int direction)
1250 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1252 ctrl->sruntime[dai->id] = stream;
1257 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1259 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1261 return ctrl->sruntime[dai->id];
1264 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1265 struct snd_soc_dai *dai)
1267 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1268 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1269 struct sdw_stream_runtime *sruntime;
1270 struct snd_soc_dai *codec_dai;
1273 ret = pm_runtime_get_sync(ctrl->dev);
1274 if (ret < 0 && ret != -EACCES) {
1275 dev_err_ratelimited(ctrl->dev,
1276 "pm_runtime_get_sync failed in %s, ret %d\n",
1278 pm_runtime_put_noidle(ctrl->dev);
1282 sruntime = sdw_alloc_stream(dai->name);
1288 ctrl->sruntime[dai->id] = sruntime;
1290 for_each_rtd_codec_dais(rtd, i, codec_dai) {
1291 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1293 if (ret < 0 && ret != -ENOTSUPP) {
1294 dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1296 goto err_set_stream;
1303 sdw_release_stream(sruntime);
1305 pm_runtime_mark_last_busy(ctrl->dev);
1306 pm_runtime_put_autosuspend(ctrl->dev);
1311 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1312 struct snd_soc_dai *dai)
1314 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1316 swrm_wait_for_wr_fifo_done(ctrl);
1317 sdw_release_stream(ctrl->sruntime[dai->id]);
1318 ctrl->sruntime[dai->id] = NULL;
1319 pm_runtime_mark_last_busy(ctrl->dev);
1320 pm_runtime_put_autosuspend(ctrl->dev);
1324 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1325 .hw_params = qcom_swrm_hw_params,
1326 .hw_free = qcom_swrm_hw_free,
1327 .startup = qcom_swrm_startup,
1328 .shutdown = qcom_swrm_shutdown,
1329 .set_stream = qcom_swrm_set_sdw_stream,
1330 .get_stream = qcom_swrm_get_sdw_stream,
1333 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1334 .name = "soundwire",
1337 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1339 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1340 struct snd_soc_dai_driver *dais;
1341 struct snd_soc_pcm_stream *stream;
1342 struct device *dev = ctrl->dev;
1345 /* PDM dais are only tested for now */
1346 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1350 for (i = 0; i < num_dais; i++) {
1351 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1355 if (i < ctrl->num_dout_ports)
1356 stream = &dais[i].playback;
1358 stream = &dais[i].capture;
1360 stream->channels_min = 1;
1361 stream->channels_max = 1;
1362 stream->rates = SNDRV_PCM_RATE_48000;
1363 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1365 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1369 return devm_snd_soc_register_component(ctrl->dev,
1370 &qcom_swrm_dai_component,
1374 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1376 struct device_node *np = ctrl->dev->of_node;
1377 u8 off1[QCOM_SDW_MAX_PORTS];
1378 u8 off2[QCOM_SDW_MAX_PORTS];
1379 u16 si[QCOM_SDW_MAX_PORTS];
1380 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1381 u8 hstart[QCOM_SDW_MAX_PORTS];
1382 u8 hstop[QCOM_SDW_MAX_PORTS];
1383 u8 word_length[QCOM_SDW_MAX_PORTS];
1384 u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1385 u8 lane_control[QCOM_SDW_MAX_PORTS];
1386 int i, ret, nports, val;
1389 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1391 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1392 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1394 ret = of_property_read_u32(np, "qcom,din-ports", &val);
1398 if (val > ctrl->num_din_ports)
1401 ctrl->num_din_ports = val;
1403 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1407 if (val > ctrl->num_dout_ports)
1410 ctrl->num_dout_ports = val;
1412 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1413 if (nports > QCOM_SDW_MAX_PORTS)
1416 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1417 set_bit(0, &ctrl->dout_port_mask);
1418 set_bit(0, &ctrl->din_port_mask);
1420 ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1425 ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1430 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1433 ret = of_property_read_u16_array(np, "qcom,ports-sinterval",
1440 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1443 if (ctrl->version <= SWRM_VERSION_1_3_0)
1444 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1449 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1450 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1452 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1453 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1455 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1456 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1458 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1459 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1461 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1462 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1464 for (i = 0; i < nports; i++) {
1465 /* Valid port number range is from 1-14 */
1467 ctrl->pconfig[i + 1].si = si[i];
1469 ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1470 ctrl->pconfig[i + 1].off1 = off1[i];
1471 ctrl->pconfig[i + 1].off2 = off2[i];
1472 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1473 ctrl->pconfig[i + 1].hstart = hstart[i];
1474 ctrl->pconfig[i + 1].hstop = hstop[i];
1475 ctrl->pconfig[i + 1].word_length = word_length[i];
1476 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1477 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1483 #ifdef CONFIG_DEBUG_FS
1484 static int swrm_reg_show(struct seq_file *s_file, void *data)
1486 struct qcom_swrm_ctrl *ctrl = s_file->private;
1487 int reg, reg_val, ret;
1489 ret = pm_runtime_get_sync(ctrl->dev);
1490 if (ret < 0 && ret != -EACCES) {
1491 dev_err_ratelimited(ctrl->dev,
1492 "pm_runtime_get_sync failed in %s, ret %d\n",
1494 pm_runtime_put_noidle(ctrl->dev);
1498 for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1499 ctrl->reg_read(ctrl, reg, ®_val);
1500 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1502 pm_runtime_mark_last_busy(ctrl->dev);
1503 pm_runtime_put_autosuspend(ctrl->dev);
1508 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1511 static int qcom_swrm_probe(struct platform_device *pdev)
1513 struct device *dev = &pdev->dev;
1514 struct sdw_master_prop *prop;
1515 struct sdw_bus_params *params;
1516 struct qcom_swrm_ctrl *ctrl;
1517 const struct qcom_swrm_data *data;
1521 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1525 data = of_device_get_match_data(dev);
1526 ctrl->max_reg = data->max_reg;
1527 ctrl->reg_layout = data->reg_layout;
1528 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1529 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1530 #if IS_REACHABLE(CONFIG_SLIMBUS)
1531 if (dev->parent->bus == &slimbus_bus) {
1535 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1536 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1537 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1541 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1542 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1543 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1544 if (IS_ERR(ctrl->mmio))
1545 return PTR_ERR(ctrl->mmio);
1548 if (data->sw_clk_gate_required) {
1549 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1550 if (IS_ERR(ctrl->audio_cgcr)) {
1551 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1552 ret = PTR_ERR(ctrl->audio_cgcr);
1557 ctrl->irq = of_irq_get(dev->of_node, 0);
1558 if (ctrl->irq < 0) {
1563 ctrl->hclk = devm_clk_get(dev, "iface");
1564 if (IS_ERR(ctrl->hclk)) {
1565 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1569 clk_prepare_enable(ctrl->hclk);
1572 dev_set_drvdata(&pdev->dev, ctrl);
1573 mutex_init(&ctrl->port_lock);
1574 init_completion(&ctrl->broadcast);
1575 init_completion(&ctrl->enumeration);
1577 ctrl->bus.ops = &qcom_swrm_ops;
1578 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1579 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1580 ctrl->bus.clk_stop_timeout = 300;
1582 ret = qcom_swrm_get_port_config(ctrl);
1586 params = &ctrl->bus.params;
1587 params->max_dr_freq = DEFAULT_CLK_FREQ;
1588 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1589 params->col = data->default_cols;
1590 params->row = data->default_rows;
1591 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1592 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1593 params->next_bank = !params->curr_bank;
1595 prop = &ctrl->bus.prop;
1596 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1597 prop->num_clk_gears = 0;
1598 prop->num_clk_freq = MAX_FREQ_NUM;
1599 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1600 prop->default_col = data->default_cols;
1601 prop->default_row = data->default_rows;
1603 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1605 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1606 qcom_swrm_irq_handler,
1607 IRQF_TRIGGER_RISING |
1611 dev_err(dev, "Failed to request soundwire irq\n");
1615 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1616 if (ctrl->wake_irq > 0) {
1617 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1618 qcom_swrm_wake_irq_handler,
1619 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1620 "swr_wake_irq", ctrl);
1622 dev_err(dev, "Failed to request soundwire wake irq\n");
1627 /* FIXME: is there a DT-defined value to use ? */
1628 ctrl->bus.controller_id = -1;
1630 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1632 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1637 qcom_swrm_init(ctrl);
1638 wait_for_completion_timeout(&ctrl->enumeration,
1639 msecs_to_jiffies(TIMEOUT_MS));
1640 ret = qcom_swrm_register_dais(ctrl);
1642 goto err_master_add;
1644 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1645 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1646 ctrl->version & 0xffff);
1648 pm_runtime_set_autosuspend_delay(dev, 3000);
1649 pm_runtime_use_autosuspend(dev);
1650 pm_runtime_mark_last_busy(dev);
1651 pm_runtime_set_active(dev);
1652 pm_runtime_enable(dev);
1654 #ifdef CONFIG_DEBUG_FS
1655 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1656 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1663 sdw_bus_master_delete(&ctrl->bus);
1665 clk_disable_unprepare(ctrl->hclk);
1670 static int qcom_swrm_remove(struct platform_device *pdev)
1672 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1674 sdw_bus_master_delete(&ctrl->bus);
1675 clk_disable_unprepare(ctrl->hclk);
1680 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1682 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1685 if (ctrl->wake_irq > 0) {
1686 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1687 disable_irq_nosync(ctrl->wake_irq);
1690 clk_prepare_enable(ctrl->hclk);
1692 if (ctrl->clock_stop_not_supported) {
1693 reinit_completion(&ctrl->enumeration);
1694 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1695 usleep_range(100, 105);
1697 qcom_swrm_init(ctrl);
1699 usleep_range(100, 105);
1700 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1701 dev_err(ctrl->dev, "link failed to connect\n");
1703 /* wait for hw enumeration to complete */
1704 wait_for_completion_timeout(&ctrl->enumeration,
1705 msecs_to_jiffies(TIMEOUT_MS));
1706 qcom_swrm_get_device_status(ctrl);
1707 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1709 reset_control_reset(ctrl->audio_cgcr);
1711 if (ctrl->version == SWRM_VERSION_1_7_0) {
1712 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1713 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1714 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1715 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1716 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1717 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1718 SWRM_V2_0_CLK_CTRL_CLK_START);
1720 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1722 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1723 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1725 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1726 if (ctrl->version < SWRM_VERSION_2_0_0)
1727 ctrl->reg_write(ctrl,
1728 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1730 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1733 usleep_range(100, 105);
1734 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1735 dev_err(ctrl->dev, "link failed to connect\n");
1737 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1739 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1745 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1747 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1750 swrm_wait_for_wr_fifo_done(ctrl);
1751 if (!ctrl->clock_stop_not_supported) {
1752 /* Mask bus clash interrupt */
1753 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1754 if (ctrl->version < SWRM_VERSION_2_0_0)
1755 ctrl->reg_write(ctrl,
1756 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1758 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1760 /* Prepare slaves for clock stop */
1761 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1762 if (ret < 0 && ret != -ENODATA) {
1763 dev_err(dev, "prepare clock stop failed %d", ret);
1767 ret = sdw_bus_clk_stop(&ctrl->bus);
1768 if (ret < 0 && ret != -ENODATA) {
1769 dev_err(dev, "bus clock stop failed %d", ret);
1774 clk_disable_unprepare(ctrl->hclk);
1776 usleep_range(300, 305);
1778 if (ctrl->wake_irq > 0) {
1779 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1780 enable_irq(ctrl->wake_irq);
1786 static const struct dev_pm_ops swrm_dev_pm_ops = {
1787 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1790 static const struct of_device_id qcom_swrm_of_match[] = {
1791 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1792 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1793 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1794 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1795 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1799 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1801 static struct platform_driver qcom_swrm_driver = {
1802 .probe = &qcom_swrm_probe,
1803 .remove = &qcom_swrm_remove,
1805 .name = "qcom-soundwire",
1806 .of_match_table = qcom_swrm_of_match,
1807 .pm = &swrm_dev_pm_ops,
1810 module_platform_driver(qcom_swrm_driver);
1812 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1813 MODULE_LICENSE("GPL v2");