drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17 #include <linux/pm_wakeirq.h>
  18 #include <linux/slimbus.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_registers.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/soc.h>
  23 #include "bus.h"
  24
  25 #define SWRM_COMP_SW_RESET                                      0x008
  26 #define SWRM_COMP_STATUS                                        0x014
  27 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  28 #define SWRM_COMP_HW_VERSION                                    0x00
  29 #define SWRM_COMP_CFG_ADDR                                      0x04
  30 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  31 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  32 #define SWRM_COMP_PARAMS                                        0x100
  33 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  34 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  35 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  36 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  37 #define SWRM_COMP_MASTER_ID                                     0x104
  38 #define SWRM_INTERRUPT_STATUS                                   0x200
  39 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  40 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  41 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  42 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  43 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  44 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  45 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  46 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  47 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  48 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  49 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  50 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  51 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  52 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  53 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  54 #define SWRM_INTERRUPT_MAX                                      17
  55 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  56 #define SWRM_INTERRUPT_CLEAR                                    0x208
  57 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  58 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  59 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  60 #define SWRM_CMD_FIFO_CMD                                       0x308
  61 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  62 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  63 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  64 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  65 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  66 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  67 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  68 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  69 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  70 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  71 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  72 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  73 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  74 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  75 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  76 #define SWRM_MCP_BUS_CTRL                                       0x1044
  77 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  78 #define SWRM_MCP_CFG_ADDR                                       0x1048
  79 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  80 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  81 #define SWRM_MCP_STATUS                                         0x104C
  82 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  83 #define SWRM_MCP_SLV_STATUS                                     0x1090
  84 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  85 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  86 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  87 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  88 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  89 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  90 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  91 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  92 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  93 #define SWR_MSTR_MAX_REG_ADDR           (0x1740)
  94
  95 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
  96 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
  97 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
  98 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
  99 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 100 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 101 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 102
 103 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 104                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 105
 106 #define SWRM_SPECIAL_CMD_ID     0xF
 107 #define MAX_FREQ_NUM            1
 108 #define TIMEOUT_MS              100
 109 #define QCOM_SWRM_MAX_RD_LEN    0x1
 110 #define QCOM_SDW_MAX_PORTS      14
 111 #define DEFAULT_CLK_FREQ        9600000
 112 #define SWRM_MAX_DAIS           0xF
 113 #define SWR_INVALID_PARAM 0xFF
 114 #define SWR_HSTOP_MAX_VAL 0xF
 115 #define SWR_HSTART_MIN_VAL 0x0
 116 #define SWR_BROADCAST_CMD_ID    0x0F
 117 #define SWR_MAX_CMD_ID  14
 118 #define MAX_FIFO_RD_RETRY 3
 119 #define SWR_OVERFLOW_RETRY_COUNT 30
 120 #define SWRM_LINK_STATUS_RETRY_CNT 100
 121
 122 enum {
 123         MASTER_ID_WSA = 1,
 124         MASTER_ID_RX,
 125         MASTER_ID_TX
 126 };
 127
 128 struct qcom_swrm_port_config {
 129         u8 si;
 130         u8 off1;
 131         u8 off2;
 132         u8 bp_mode;
 133         u8 hstart;
 134         u8 hstop;
 135         u8 word_length;
 136         u8 blk_group_count;
 137         u8 lane_control;
 138 };
 139
 140 struct qcom_swrm_ctrl {
 141         struct sdw_bus bus;
 142         struct device *dev;
 143         struct regmap *regmap;
 144         void __iomem *mmio;
 145 #ifdef CONFIG_DEBUG_FS
 146         struct dentry *debugfs;
 147 #endif
 148         struct completion broadcast;
 149         struct completion enumeration;
 150         struct work_struct slave_work;
 151         /* Port alloc/free lock */
 152         struct mutex port_lock;
 153         struct clk *hclk;
 154         u8 wr_cmd_id;
 155         u8 rd_cmd_id;
 156         int irq;
 157         unsigned int version;
 158         int wake_irq;
 159         int num_din_ports;
 160         int num_dout_ports;
 161         int cols_index;
 162         int rows_index;
 163         unsigned long dout_port_mask;
 164         unsigned long din_port_mask;
 165         u32 intr_mask;
 166         u8 rcmd_id;
 167         u8 wcmd_id;
 168         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 169         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 170         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 171         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 172         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 173         u32 slave_status;
 174         u32 wr_fifo_depth;
 175         u32 rd_fifo_depth;
 176         bool clock_stop_not_supported;
 177 };
 178
 179 struct qcom_swrm_data {
 180         u32 default_cols;
 181         u32 default_rows;
 182 };
 183
 184 static const struct qcom_swrm_data swrm_v1_3_data = {
 185         .default_rows = 48,
 186         .default_cols = 16,
 187 };
 188
 189 static const struct qcom_swrm_data swrm_v1_5_data = {
 190         .default_rows = 50,
 191         .default_cols = 16,
 192 };
 193
 194 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 195
 196 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 197                                   u32 *val)
 198 {
 199         struct regmap *wcd_regmap = ctrl->regmap;
 200         int ret;
 201
 202         /* pg register + offset */
 203         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 204                           (u8 *)&reg, 4);
 205         if (ret < 0)
 206                 return SDW_CMD_FAIL;
 207
 208         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 209                                val, 4);
 210         if (ret < 0)
 211                 return SDW_CMD_FAIL;
 212
 213         return SDW_CMD_OK;
 214 }
 215
 216 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 217                                    int reg, int val)
 218 {
 219         struct regmap *wcd_regmap = ctrl->regmap;
 220         int ret;
 221         /* pg register + offset */
 222         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 223                           (u8 *)&val, 4);
 224         if (ret)
 225                 return SDW_CMD_FAIL;
 226
 227         /* write address register */
 228         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 229                           (u8 *)&reg, 4);
 230         if (ret)
 231                 return SDW_CMD_FAIL;
 232
 233         return SDW_CMD_OK;
 234 }
 235
 236 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 237                                   u32 *val)
 238 {
 239         *val = readl(ctrl->mmio + reg);
 240         return SDW_CMD_OK;
 241 }
 242
 243 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 244                                    int val)
 245 {
 246         writel(val, ctrl->mmio + reg);
 247         return SDW_CMD_OK;
 248 }
 249
 250 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 251                                    u8 dev_addr, u16 reg_addr)
 252 {
 253         u32 val;
 254         u8 id = *cmd_id;
 255
 256         if (id != SWR_BROADCAST_CMD_ID) {
 257                 if (id < SWR_MAX_CMD_ID)
 258                         id += 1;
 259                 else
 260                         id = 0;
 261                 *cmd_id = id;
 262         }
 263         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 264
 265         return val;
 266 }
 267
 268 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 269 {
 270         u32 fifo_outstanding_data, value;
 271         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 272
 273         do {
 274                 /* Check for fifo underflow during read */
 275                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 276                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 277
 278                 /* Check if read data is available in read fifo */
 279                 if (fifo_outstanding_data > 0)
 280                         return 0;
 281
 282                 usleep_range(500, 510);
 283         } while (fifo_retry_count--);
 284
 285         if (fifo_outstanding_data == 0) {
 286                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 287                 return -EIO;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 294 {
 295         u32 fifo_outstanding_cmds, value;
 296         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 297
 298         do {
 299                 /* Check for fifo overflow during write */
 300                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 301                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 302
 303                 /* Check for space in write fifo before writing */
 304                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 305                         return 0;
 306
 307                 usleep_range(500, 510);
 308         } while (fifo_retry_count--);
 309
 310         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 311                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 312                 return -EIO;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 319                                      u8 dev_addr, u16 reg_addr)
 320 {
 321
 322         u32 val;
 323         int ret = 0;
 324         u8 cmd_id = 0x0;
 325
 326         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 327                 cmd_id = SWR_BROADCAST_CMD_ID;
 328                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 329                                               dev_addr, reg_addr);
 330         } else {
 331                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 332                                               dev_addr, reg_addr);
 333         }
 334
 335         if (swrm_wait_for_wr_fifo_avail(swrm))
 336                 return SDW_CMD_FAIL_OTHER;
 337
 338         /* Its assumed that write is okay as we do not get any status back */
 339         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 340
 341         /* version 1.3 or less */
 342         if (swrm->version <= 0x01030000)
 343                 usleep_range(150, 155);
 344
 345         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 346                 /*
 347                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 348                  * command to complete.
 349                  */
 350                 ret = wait_for_completion_timeout(&swrm->broadcast,
 351                                                   msecs_to_jiffies(TIMEOUT_MS));
 352                 if (!ret)
 353                         ret = SDW_CMD_IGNORED;
 354                 else
 355                         ret = SDW_CMD_OK;
 356
 357         } else {
 358                 ret = SDW_CMD_OK;
 359         }
 360         return ret;
 361 }
 362
 363 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 364                                      u8 dev_addr, u16 reg_addr,
 365                                      u32 len, u8 *rval)
 366 {
 367         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 368
 369         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 370
 371         /* wait for FIFO RD to complete to avoid overflow */
 372         usleep_range(100, 105);
 373         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 374         /* wait for FIFO RD CMD complete to avoid overflow */
 375         usleep_range(250, 255);
 376
 377         if (swrm_wait_for_rd_fifo_avail(swrm))
 378                 return SDW_CMD_FAIL_OTHER;
 379
 380         do {
 381                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 382                 rval[0] = cmd_data & 0xFF;
 383                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 384
 385                 if (cmd_id != swrm->rcmd_id) {
 386                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 387                                 /* wait 500 us before retry on fifo read failure */
 388                                 usleep_range(500, 505);
 389                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 390                                                 SWRM_CMD_FIFO_FLUSH);
 391                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 392                         }
 393                         retry_attempt++;
 394                 } else {
 395                         return SDW_CMD_OK;
 396                 }
 397
 398         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 399
 400         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 401                 dev_num: 0x%x, cmd_data: 0x%x\n",
 402                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 403
 404         return SDW_CMD_IGNORED;
 405 }
 406
 407 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 408 {
 409         u32 val, status;
 410         int dev_num;
 411
 412         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 413
 414         for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 415                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 416
 417                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 418                         ctrl->status[dev_num] = status;
 419                         return dev_num;
 420                 }
 421         }
 422
 423         return -EINVAL;
 424 }
 425
 426 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 427 {
 428         u32 val;
 429         int i;
 430
 431         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 432         ctrl->slave_status = val;
 433
 434         for (i = 0; i <= SDW_MAX_DEVICES; i++) {
 435                 u32 s;
 436
 437                 s = (val >> (i * 2));
 438                 s &= SWRM_MCP_SLV_STATUS_MASK;
 439                 ctrl->status[i] = s;
 440         }
 441 }
 442
 443 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 444                                         struct sdw_slave *slave, int devnum)
 445 {
 446         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 447         u32 status;
 448
 449         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 450         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 451         status &= SWRM_MCP_SLV_STATUS_MASK;
 452
 453         if (status == SDW_SLAVE_ATTACHED) {
 454                 if (slave)
 455                         slave->dev_num = devnum;
 456                 mutex_lock(&bus->bus_lock);
 457                 set_bit(devnum, bus->assigned);
 458                 mutex_unlock(&bus->bus_lock);
 459         }
 460 }
 461
 462 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 463 {
 464         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 465         struct sdw_slave *slave, *_s;
 466         struct sdw_slave_id id;
 467         u32 val1, val2;
 468         bool found;
 469         u64 addr;
 470         int i;
 471         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 472
 473         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 474                 /* do not continue if the status is Not Present  */
 475                 if (!ctrl->status[i])
 476                         continue;
 477
 478                 /*SCP_Devid5 - Devid 4*/
 479                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 480
 481                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 482                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 483
 484                 if (!val1 && !val2)
 485                         break;
 486
 487                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 488                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 489                         ((u64)buf1[0] << 40);
 490
 491                 sdw_extract_slave_id(bus, addr, &id);
 492                 found = false;
 493                 /* Now compare with entries */
 494                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 495                         if (sdw_compare_devid(slave, id) == 0) {
 496                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 497                                 found = true;
 498                                 break;
 499                         }
 500                 }
 501
 502                 if (!found) {
 503                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 504                         sdw_slave_add(bus, &id, NULL);
 505                 }
 506         }
 507
 508         complete(&ctrl->enumeration);
 509         return 0;
 510 }
 511
 512 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 513 {
 514         struct qcom_swrm_ctrl *swrm = dev_id;
 515         int ret;
 516
 517         ret = pm_runtime_resume_and_get(swrm->dev);
 518         if (ret < 0 && ret != -EACCES) {
 519                 dev_err_ratelimited(swrm->dev,
 520                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
 521                                     __func__, ret);
 522                 return ret;
 523         }
 524
 525         if (swrm->wake_irq > 0) {
 526                 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
 527                         disable_irq_nosync(swrm->wake_irq);
 528         }
 529
 530         pm_runtime_mark_last_busy(swrm->dev);
 531         pm_runtime_put_autosuspend(swrm->dev);
 532
 533         return IRQ_HANDLED;
 534 }
 535
 536 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 537 {
 538         struct qcom_swrm_ctrl *swrm = dev_id;
 539         u32 value, intr_sts, intr_sts_masked, slave_status;
 540         u32 i;
 541         int devnum;
 542         int ret = IRQ_HANDLED;
 543         clk_prepare_enable(swrm->hclk);
 544
 545         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 546         intr_sts_masked = intr_sts & swrm->intr_mask;
 547
 548         do {
 549                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 550                         value = intr_sts_masked & BIT(i);
 551                         if (!value)
 552                                 continue;
 553
 554                         switch (value) {
 555                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 556                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 557                                 if (devnum < 0) {
 558                                         dev_err_ratelimited(swrm->dev,
 559                                             "no slave alert found.spurious interrupt\n");
 560                                 } else {
 561                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 562                                 }
 563
 564                                 break;
 565                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 566                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 567                                 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
 568                                         __func__);
 569                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 570                                 if (swrm->slave_status == slave_status) {
 571                                         dev_err(swrm->dev, "Slave status not changed %x\n",
 572                                                 slave_status);
 573                                 } else {
 574                                         qcom_swrm_get_device_status(swrm);
 575                                         qcom_swrm_enumerate(&swrm->bus);
 576                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 577                                 }
 578                                 break;
 579                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 580                                 dev_err_ratelimited(swrm->dev,
 581                                                 "%s: SWR bus clsh detected\n",
 582                                                 __func__);
 583                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 584                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 585                                 break;
 586                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 587                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 588                                 dev_err_ratelimited(swrm->dev,
 589                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 590                                         __func__, value);
 591                                 break;
 592                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 593                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 594                                 dev_err_ratelimited(swrm->dev,
 595                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 596                                         __func__, value);
 597                                 break;
 598                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 599                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 600                                 dev_err(swrm->dev,
 601                                         "%s: SWR write FIFO overflow fifo status %x\n",
 602                                         __func__, value);
 603                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 604                                 break;
 605                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 606                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 607                                 dev_err_ratelimited(swrm->dev,
 608                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 609                                         __func__, value);
 610                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 611                                 break;
 612                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 613                                 dev_err_ratelimited(swrm->dev,
 614                                                 "%s: SWR Port collision detected\n",
 615                                                 __func__);
 616                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 617                                 swrm->reg_write(swrm,
 618                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 619                                 break;
 620                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 621                                 dev_err_ratelimited(swrm->dev,
 622                                         "%s: SWR read enable valid mismatch\n",
 623                                         __func__);
 624                                 swrm->intr_mask &=
 625                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 626                                 swrm->reg_write(swrm,
 627                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 628                                 break;
 629                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 630                                 complete(&swrm->broadcast);
 631                                 break;
 632                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 633                                 break;
 634                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 635                                 break;
 636                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 637                                 break;
 638                         default:
 639                                 dev_err_ratelimited(swrm->dev,
 640                                                 "%s: SWR unknown interrupt value: %d\n",
 641                                                 __func__, value);
 642                                 ret = IRQ_NONE;
 643                                 break;
 644                         }
 645                 }
 646                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 647                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 648                 intr_sts_masked = intr_sts & swrm->intr_mask;
 649         } while (intr_sts_masked);
 650
 651         clk_disable_unprepare(swrm->hclk);
 652         return ret;
 653 }
 654
 655 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 656 {
 657         u32 val;
 658
 659         /* Clear Rows and Cols */
 660         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 661         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 662
 663         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 664
 665         /* Enable Auto enumeration */
 666         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 667
 668         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 669         /* Mask soundwire interrupts */
 670         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 671                         SWRM_INTERRUPT_STATUS_RMSK);
 672
 673         /* Configure No pings */
 674         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 675         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 676         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 677
 678         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 679         /* Configure number of retries of a read/write cmd */
 680         if (ctrl->version > 0x01050001) {
 681                 /* Only for versions >= 1.5.1 */
 682                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 683                                 SWRM_RD_WR_CMD_RETRIES |
 684                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 685         } else {
 686                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 687                                 SWRM_RD_WR_CMD_RETRIES);
 688         }
 689
 690         /* Set IRQ to PULSE */
 691         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 692                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 693                         SWRM_COMP_CFG_ENABLE_MSK);
 694
 695         /* enable CPU IRQs */
 696         if (ctrl->mmio) {
 697                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 698                                 SWRM_INTERRUPT_STATUS_RMSK);
 699         }
 700         ctrl->slave_status = 0;
 701         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 702         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 703         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 704
 705         return 0;
 706 }
 707
 708 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 709                                                     struct sdw_msg *msg)
 710 {
 711         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 712         int ret, i, len;
 713
 714         if (msg->flags == SDW_MSG_FLAG_READ) {
 715                 for (i = 0; i < msg->len;) {
 716                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 717                                 len = msg->len - i;
 718                         else
 719                                 len = QCOM_SWRM_MAX_RD_LEN;
 720
 721                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 722                                                         msg->addr + i, len,
 723                                                        &msg->buf[i]);
 724                         if (ret)
 725                                 return ret;
 726
 727                         i = i + len;
 728                 }
 729         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 730                 for (i = 0; i < msg->len; i++) {
 731                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 732                                                         msg->dev_num,
 733                                                        msg->addr + i);
 734                         if (ret)
 735                                 return SDW_CMD_IGNORED;
 736                 }
 737         }
 738
 739         return SDW_CMD_OK;
 740 }
 741
 742 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 743 {
 744         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 745         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 746         u32 val;
 747
 748         ctrl->reg_read(ctrl, reg, &val);
 749
 750         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 751         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 752
 753         return ctrl->reg_write(ctrl, reg, val);
 754 }
 755
 756 static int qcom_swrm_port_params(struct sdw_bus *bus,
 757                                  struct sdw_port_params *p_params,
 758                                  unsigned int bank)
 759 {
 760         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 761
 762         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 763                                p_params->bps - 1);
 764
 765 }
 766
 767 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 768                                       struct sdw_transport_params *params,
 769                                       enum sdw_reg_bank bank)
 770 {
 771         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 772         struct qcom_swrm_port_config *pcfg;
 773         u32 value;
 774         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 775         int ret;
 776
 777         pcfg = &ctrl->pconfig[params->port_num];
 778
 779         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 780         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 781         value |= pcfg->si;
 782
 783         ret = ctrl->reg_write(ctrl, reg, value);
 784         if (ret)
 785                 goto err;
 786
 787         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 788                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 789                 value = pcfg->lane_control;
 790                 ret = ctrl->reg_write(ctrl, reg, value);
 791                 if (ret)
 792                         goto err;
 793         }
 794
 795         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 796                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 797                 value = pcfg->blk_group_count;
 798                 ret = ctrl->reg_write(ctrl, reg, value);
 799                 if (ret)
 800                         goto err;
 801         }
 802
 803         if (pcfg->hstart != SWR_INVALID_PARAM
 804                         && pcfg->hstop != SWR_INVALID_PARAM) {
 805                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 806                 value = (pcfg->hstop << 4) | pcfg->hstart;
 807                 ret = ctrl->reg_write(ctrl, reg, value);
 808         } else {
 809                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 810                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 811                 ret = ctrl->reg_write(ctrl, reg, value);
 812         }
 813
 814         if (ret)
 815                 goto err;
 816
 817         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 818                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 819                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 820         }
 821
 822 err:
 823         return ret;
 824 }
 825
 826 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 827                                  struct sdw_enable_ch *enable_ch,
 828                                  unsigned int bank)
 829 {
 830         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 831         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 832         u32 val;
 833
 834         ctrl->reg_read(ctrl, reg, &val);
 835
 836         if (enable_ch->enable)
 837                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 838         else
 839                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 840
 841         return ctrl->reg_write(ctrl, reg, val);
 842 }
 843
 844 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 845         .dpn_set_port_params = qcom_swrm_port_params,
 846         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 847         .dpn_port_enable_ch = qcom_swrm_port_enable,
 848 };
 849
 850 static const struct sdw_master_ops qcom_swrm_ops = {
 851         .xfer_msg = qcom_swrm_xfer_msg,
 852         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 853 };
 854
 855 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 856 {
 857         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 858         struct sdw_master_runtime *m_rt;
 859         struct sdw_slave_runtime *s_rt;
 860         struct sdw_port_runtime *p_rt;
 861         struct qcom_swrm_port_config *pcfg;
 862         struct sdw_slave *slave;
 863         unsigned int m_port;
 864         int i = 1;
 865
 866         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 867                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 868                         pcfg = &ctrl->pconfig[p_rt->num];
 869                         p_rt->transport_params.port_num = p_rt->num;
 870                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 871                                 sdw_fill_port_params(&p_rt->port_params,
 872                                              p_rt->num,  pcfg->word_length + 1,
 873                                              SDW_PORT_FLOW_MODE_ISOCH,
 874                                              SDW_PORT_DATA_MODE_NORMAL);
 875                         }
 876
 877                 }
 878
 879                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 880                         slave = s_rt->slave;
 881                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 882                                 m_port = slave->m_port_map[p_rt->num];
 883                                 /* port config starts at offset 0 so -1 from actual port number */
 884                                 if (m_port)
 885                                         pcfg = &ctrl->pconfig[m_port];
 886                                 else
 887                                         pcfg = &ctrl->pconfig[i];
 888                                 p_rt->transport_params.port_num = p_rt->num;
 889                                 p_rt->transport_params.sample_interval =
 890                                         pcfg->si + 1;
 891                                 p_rt->transport_params.offset1 = pcfg->off1;
 892                                 p_rt->transport_params.offset2 = pcfg->off2;
 893                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 894                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 895
 896                                 p_rt->transport_params.hstart = pcfg->hstart;
 897                                 p_rt->transport_params.hstop = pcfg->hstop;
 898                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 899                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 900                                         sdw_fill_port_params(&p_rt->port_params,
 901                                                      p_rt->num,
 902                                                      pcfg->word_length + 1,
 903                                                      SDW_PORT_FLOW_MODE_ISOCH,
 904                                                      SDW_PORT_DATA_MODE_NORMAL);
 905                                 }
 906                                 i++;
 907                         }
 908                 }
 909         }
 910
 911         return 0;
 912 }
 913
 914 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 915         DEFAULT_CLK_FREQ,
 916 };
 917
 918 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 919                                         struct sdw_stream_runtime *stream)
 920 {
 921         struct sdw_master_runtime *m_rt;
 922         struct sdw_port_runtime *p_rt;
 923         unsigned long *port_mask;
 924
 925         mutex_lock(&ctrl->port_lock);
 926
 927         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 928                 if (m_rt->direction == SDW_DATA_DIR_RX)
 929                         port_mask = &ctrl->dout_port_mask;
 930                 else
 931                         port_mask = &ctrl->din_port_mask;
 932
 933                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 934                         clear_bit(p_rt->num, port_mask);
 935         }
 936
 937         mutex_unlock(&ctrl->port_lock);
 938 }
 939
 940 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 941                                         struct sdw_stream_runtime *stream,
 942                                        struct snd_pcm_hw_params *params,
 943                                        int direction)
 944 {
 945         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 946         struct sdw_stream_config sconfig;
 947         struct sdw_master_runtime *m_rt;
 948         struct sdw_slave_runtime *s_rt;
 949         struct sdw_port_runtime *p_rt;
 950         struct sdw_slave *slave;
 951         unsigned long *port_mask;
 952         int i, maxport, pn, nports = 0, ret = 0;
 953         unsigned int m_port;
 954
 955         mutex_lock(&ctrl->port_lock);
 956         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 957                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 958                         maxport = ctrl->num_dout_ports;
 959                         port_mask = &ctrl->dout_port_mask;
 960                 } else {
 961                         maxport = ctrl->num_din_ports;
 962                         port_mask = &ctrl->din_port_mask;
 963                 }
 964
 965                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 966                         slave = s_rt->slave;
 967                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 968                                 m_port = slave->m_port_map[p_rt->num];
 969                                 /* Port numbers start from 1 - 14*/
 970                                 if (m_port)
 971                                         pn = m_port;
 972                                 else
 973                                         pn = find_first_zero_bit(port_mask, maxport);
 974
 975                                 if (pn > maxport) {
 976                                         dev_err(ctrl->dev, "All ports busy\n");
 977                                         ret = -EBUSY;
 978                                         goto err;
 979                                 }
 980                                 set_bit(pn, port_mask);
 981                                 pconfig[nports].num = pn;
 982                                 pconfig[nports].ch_mask = p_rt->ch_mask;
 983                                 nports++;
 984                         }
 985                 }
 986         }
 987
 988         if (direction == SNDRV_PCM_STREAM_CAPTURE)
 989                 sconfig.direction = SDW_DATA_DIR_TX;
 990         else
 991                 sconfig.direction = SDW_DATA_DIR_RX;
 992
 993         /* hw parameters wil be ignored as we only support PDM */
 994         sconfig.ch_count = 1;
 995         sconfig.frame_rate = params_rate(params);
 996         sconfig.type = stream->type;
 997         sconfig.bps = 1;
 998         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
 999                               nports, stream);
1000 err:
1001         if (ret) {
1002                 for (i = 0; i < nports; i++)
1003                         clear_bit(pconfig[i].num, port_mask);
1004         }
1005
1006         mutex_unlock(&ctrl->port_lock);
1007
1008         return ret;
1009 }
1010
1011 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1012                                struct snd_pcm_hw_params *params,
1013                               struct snd_soc_dai *dai)
1014 {
1015         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1016         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1017         int ret;
1018
1019         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1020                                            substream->stream);
1021         if (ret)
1022                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1023
1024         return ret;
1025 }
1026
1027 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1028                              struct snd_soc_dai *dai)
1029 {
1030         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1031         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1032
1033         qcom_swrm_stream_free_ports(ctrl, sruntime);
1034         sdw_stream_remove_master(&ctrl->bus, sruntime);
1035
1036         return 0;
1037 }
1038
1039 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1040                                     void *stream, int direction)
1041 {
1042         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1043
1044         ctrl->sruntime[dai->id] = stream;
1045
1046         return 0;
1047 }
1048
1049 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1050 {
1051         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1052
1053         return ctrl->sruntime[dai->id];
1054 }
1055
1056 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1057                              struct snd_soc_dai *dai)
1058 {
1059         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1060         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1061         struct sdw_stream_runtime *sruntime;
1062         struct snd_soc_dai *codec_dai;
1063         int ret, i;
1064
1065         ret = pm_runtime_resume_and_get(ctrl->dev);
1066         if (ret < 0 && ret != -EACCES) {
1067                 dev_err_ratelimited(ctrl->dev,
1068                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1069                                     __func__, ret);
1070                 return ret;
1071         }
1072
1073         sruntime = sdw_alloc_stream(dai->name);
1074         if (!sruntime)
1075                 return -ENOMEM;
1076
1077         ctrl->sruntime[dai->id] = sruntime;
1078
1079         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1080                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1081                                              substream->stream);
1082                 if (ret < 0 && ret != -ENOTSUPP) {
1083                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1084                                 codec_dai->name);
1085                         sdw_release_stream(sruntime);
1086                         return ret;
1087                 }
1088         }
1089
1090         return 0;
1091 }
1092
1093 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1094                                struct snd_soc_dai *dai)
1095 {
1096         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1097
1098         sdw_release_stream(ctrl->sruntime[dai->id]);
1099         ctrl->sruntime[dai->id] = NULL;
1100         pm_runtime_mark_last_busy(ctrl->dev);
1101         pm_runtime_put_autosuspend(ctrl->dev);
1102
1103 }
1104
1105 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1106         .hw_params = qcom_swrm_hw_params,
1107         .hw_free = qcom_swrm_hw_free,
1108         .startup = qcom_swrm_startup,
1109         .shutdown = qcom_swrm_shutdown,
1110         .set_stream = qcom_swrm_set_sdw_stream,
1111         .get_stream = qcom_swrm_get_sdw_stream,
1112 };
1113
1114 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1115         .name = "soundwire",
1116 };
1117
1118 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1119 {
1120         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1121         struct snd_soc_dai_driver *dais;
1122         struct snd_soc_pcm_stream *stream;
1123         struct device *dev = ctrl->dev;
1124         int i;
1125
1126         /* PDM dais are only tested for now */
1127         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1128         if (!dais)
1129                 return -ENOMEM;
1130
1131         for (i = 0; i < num_dais; i++) {
1132                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1133                 if (!dais[i].name)
1134                         return -ENOMEM;
1135
1136                 if (i < ctrl->num_dout_ports)
1137                         stream = &dais[i].playback;
1138                 else
1139                         stream = &dais[i].capture;
1140
1141                 stream->channels_min = 1;
1142                 stream->channels_max = 1;
1143                 stream->rates = SNDRV_PCM_RATE_48000;
1144                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1145
1146                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1147                 dais[i].id = i;
1148         }
1149
1150         return devm_snd_soc_register_component(ctrl->dev,
1151                                                 &qcom_swrm_dai_component,
1152                                                 dais, num_dais);
1153 }
1154
1155 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1156 {
1157         struct device_node *np = ctrl->dev->of_node;
1158         u8 off1[QCOM_SDW_MAX_PORTS];
1159         u8 off2[QCOM_SDW_MAX_PORTS];
1160         u8 si[QCOM_SDW_MAX_PORTS];
1161         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1162         u8 hstart[QCOM_SDW_MAX_PORTS];
1163         u8 hstop[QCOM_SDW_MAX_PORTS];
1164         u8 word_length[QCOM_SDW_MAX_PORTS];
1165         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1166         u8 lane_control[QCOM_SDW_MAX_PORTS];
1167         int i, ret, nports, val;
1168
1169         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1170
1171         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1172         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1173
1174         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1175         if (ret)
1176                 return ret;
1177
1178         if (val > ctrl->num_din_ports)
1179                 return -EINVAL;
1180
1181         ctrl->num_din_ports = val;
1182
1183         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1184         if (ret)
1185                 return ret;
1186
1187         if (val > ctrl->num_dout_ports)
1188                 return -EINVAL;
1189
1190         ctrl->num_dout_ports = val;
1191
1192         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1193         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1194         set_bit(0, &ctrl->dout_port_mask);
1195         set_bit(0, &ctrl->din_port_mask);
1196
1197         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1198                                         off1, nports);
1199         if (ret)
1200                 return ret;
1201
1202         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1203                                         off2, nports);
1204         if (ret)
1205                 return ret;
1206
1207         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1208                                         si, nports);
1209         if (ret)
1210                 return ret;
1211
1212         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1213                                         bp_mode, nports);
1214         if (ret) {
1215                 if (ctrl->version <= 0x01030000)
1216                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1217                 else
1218                         return ret;
1219         }
1220
1221         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1222         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1223
1224         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1225         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1226
1227         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1228         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1229
1230         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1231         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1232
1233         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1234         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1235
1236         for (i = 0; i < nports; i++) {
1237                 /* Valid port number range is from 1-14 */
1238                 ctrl->pconfig[i + 1].si = si[i];
1239                 ctrl->pconfig[i + 1].off1 = off1[i];
1240                 ctrl->pconfig[i + 1].off2 = off2[i];
1241                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1242                 ctrl->pconfig[i + 1].hstart = hstart[i];
1243                 ctrl->pconfig[i + 1].hstop = hstop[i];
1244                 ctrl->pconfig[i + 1].word_length = word_length[i];
1245                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1246                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1247         }
1248
1249         return 0;
1250 }
1251
1252 #ifdef CONFIG_DEBUG_FS
1253 static int swrm_reg_show(struct seq_file *s_file, void *data)
1254 {
1255         struct qcom_swrm_ctrl *swrm = s_file->private;
1256         int reg, reg_val, ret;
1257
1258         ret = pm_runtime_resume_and_get(swrm->dev);
1259         if (ret < 0 && ret != -EACCES) {
1260                 dev_err_ratelimited(swrm->dev,
1261                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1262                                     __func__, ret);
1263                 return ret;
1264         }
1265
1266         for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1267                 swrm->reg_read(swrm, reg, &reg_val);
1268                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1269         }
1270         pm_runtime_mark_last_busy(swrm->dev);
1271         pm_runtime_put_autosuspend(swrm->dev);
1272
1273
1274         return 0;
1275 }
1276 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1277 #endif
1278
1279 static int qcom_swrm_probe(struct platform_device *pdev)
1280 {
1281         struct device *dev = &pdev->dev;
1282         struct sdw_master_prop *prop;
1283         struct sdw_bus_params *params;
1284         struct qcom_swrm_ctrl *ctrl;
1285         const struct qcom_swrm_data *data;
1286         int ret;
1287         u32 val;
1288
1289         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1290         if (!ctrl)
1291                 return -ENOMEM;
1292
1293         data = of_device_get_match_data(dev);
1294         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1295         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1296 #if IS_REACHABLE(CONFIG_SLIMBUS)
1297         if (dev->parent->bus == &slimbus_bus) {
1298 #else
1299         if (false) {
1300 #endif
1301                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1302                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1303                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1304                 if (!ctrl->regmap)
1305                         return -EINVAL;
1306         } else {
1307                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1308                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1309                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1310                 if (IS_ERR(ctrl->mmio))
1311                         return PTR_ERR(ctrl->mmio);
1312         }
1313
1314         ctrl->irq = of_irq_get(dev->of_node, 0);
1315         if (ctrl->irq < 0) {
1316                 ret = ctrl->irq;
1317                 goto err_init;
1318         }
1319
1320         ctrl->hclk = devm_clk_get(dev, "iface");
1321         if (IS_ERR(ctrl->hclk)) {
1322                 ret = PTR_ERR(ctrl->hclk);
1323                 goto err_init;
1324         }
1325
1326         clk_prepare_enable(ctrl->hclk);
1327
1328         ctrl->dev = dev;
1329         dev_set_drvdata(&pdev->dev, ctrl);
1330         mutex_init(&ctrl->port_lock);
1331         init_completion(&ctrl->broadcast);
1332         init_completion(&ctrl->enumeration);
1333
1334         ctrl->bus.ops = &qcom_swrm_ops;
1335         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1336         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1337         ctrl->bus.clk_stop_timeout = 300;
1338
1339         ret = qcom_swrm_get_port_config(ctrl);
1340         if (ret)
1341                 goto err_clk;
1342
1343         params = &ctrl->bus.params;
1344         params->max_dr_freq = DEFAULT_CLK_FREQ;
1345         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1346         params->col = data->default_cols;
1347         params->row = data->default_rows;
1348         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1349         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1350         params->next_bank = !params->curr_bank;
1351
1352         prop = &ctrl->bus.prop;
1353         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1354         prop->num_clk_gears = 0;
1355         prop->num_clk_freq = MAX_FREQ_NUM;
1356         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1357         prop->default_col = data->default_cols;
1358         prop->default_row = data->default_rows;
1359
1360         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1361
1362         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1363                                         qcom_swrm_irq_handler,
1364                                         IRQF_TRIGGER_RISING |
1365                                         IRQF_ONESHOT,
1366                                         "soundwire", ctrl);
1367         if (ret) {
1368                 dev_err(dev, "Failed to request soundwire irq\n");
1369                 goto err_clk;
1370         }
1371
1372         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1373         if (ctrl->wake_irq > 0) {
1374                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1375                                                 qcom_swrm_wake_irq_handler,
1376                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1377                                                 "swr_wake_irq", ctrl);
1378                 if (ret) {
1379                         dev_err(dev, "Failed to request soundwire wake irq\n");
1380                         goto err_init;
1381                 }
1382         }
1383
1384         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1385         if (ret) {
1386                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1387                         ret);
1388                 goto err_clk;
1389         }
1390
1391         qcom_swrm_init(ctrl);
1392         wait_for_completion_timeout(&ctrl->enumeration,
1393                                     msecs_to_jiffies(TIMEOUT_MS));
1394         ret = qcom_swrm_register_dais(ctrl);
1395         if (ret)
1396                 goto err_master_add;
1397
1398         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1399                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1400                  ctrl->version & 0xffff);
1401
1402         pm_runtime_set_autosuspend_delay(dev, 3000);
1403         pm_runtime_use_autosuspend(dev);
1404         pm_runtime_mark_last_busy(dev);
1405         pm_runtime_set_active(dev);
1406         pm_runtime_enable(dev);
1407
1408         /* Clk stop is not supported on WSA Soundwire masters */
1409         if (ctrl->version <= 0x01030000) {
1410                 ctrl->clock_stop_not_supported = true;
1411         } else {
1412                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1413                 if (val == MASTER_ID_WSA)
1414                         ctrl->clock_stop_not_supported = true;
1415         }
1416
1417 #ifdef CONFIG_DEBUG_FS
1418         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1419         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1420                             &swrm_reg_fops);
1421 #endif
1422
1423         return 0;
1424
1425 err_master_add:
1426         sdw_bus_master_delete(&ctrl->bus);
1427 err_clk:
1428         clk_disable_unprepare(ctrl->hclk);
1429 err_init:
1430         return ret;
1431 }
1432
1433 static int qcom_swrm_remove(struct platform_device *pdev)
1434 {
1435         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1436
1437         sdw_bus_master_delete(&ctrl->bus);
1438         clk_disable_unprepare(ctrl->hclk);
1439
1440         return 0;
1441 }
1442
1443 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1444 {
1445         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1446         int comp_sts;
1447
1448         do {
1449                 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1450
1451                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1452                         return true;
1453
1454                 usleep_range(500, 510);
1455         } while (retry--);
1456
1457         dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1458                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1459
1460         return false;
1461 }
1462
1463 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1464 {
1465         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1466         int ret;
1467
1468         if (ctrl->wake_irq > 0) {
1469                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1470                         disable_irq_nosync(ctrl->wake_irq);
1471         }
1472
1473         clk_prepare_enable(ctrl->hclk);
1474
1475         if (ctrl->clock_stop_not_supported) {
1476                 reinit_completion(&ctrl->enumeration);
1477                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1478                 usleep_range(100, 105);
1479
1480                 qcom_swrm_init(ctrl);
1481
1482                 usleep_range(100, 105);
1483                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1484                         dev_err(ctrl->dev, "link failed to connect\n");
1485
1486                 /* wait for hw enumeration to complete */
1487                 wait_for_completion_timeout(&ctrl->enumeration,
1488                                             msecs_to_jiffies(TIMEOUT_MS));
1489                 qcom_swrm_get_device_status(ctrl);
1490                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1491         } else {
1492                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1493                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1494                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1495
1496                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1497                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1498                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1499
1500                 usleep_range(100, 105);
1501                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1502                         dev_err(ctrl->dev, "link failed to connect\n");
1503
1504                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1505                 if (ret < 0)
1506                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1507         }
1508
1509         return 0;
1510 }
1511
1512 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1513 {
1514         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1515         int ret;
1516
1517         if (!ctrl->clock_stop_not_supported) {
1518                 /* Mask bus clash interrupt */
1519                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1520                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1521                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1522                 /* Prepare slaves for clock stop */
1523                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1524                 if (ret < 0 && ret != -ENODATA) {
1525                         dev_err(dev, "prepare clock stop failed %d", ret);
1526                         return ret;
1527                 }
1528
1529                 ret = sdw_bus_clk_stop(&ctrl->bus);
1530                 if (ret < 0 && ret != -ENODATA) {
1531                         dev_err(dev, "bus clock stop failed %d", ret);
1532                         return ret;
1533                 }
1534         }
1535
1536         clk_disable_unprepare(ctrl->hclk);
1537
1538         usleep_range(300, 305);
1539
1540         if (ctrl->wake_irq > 0) {
1541                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1542                         enable_irq(ctrl->wake_irq);
1543         }
1544
1545         return 0;
1546 }
1547
1548 static const struct dev_pm_ops swrm_dev_pm_ops = {
1549         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1550 };
1551
1552 static const struct of_device_id qcom_swrm_of_match[] = {
1553         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1554         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1555         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_5_data },
1556         {/* sentinel */},
1557 };
1558
1559 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1560
1561 static struct platform_driver qcom_swrm_driver = {
1562         .probe  = &qcom_swrm_probe,
1563         .remove = &qcom_swrm_remove,
1564         .driver = {
1565                 .name   = "qcom-soundwire",
1566                 .of_match_table = qcom_swrm_of_match,
1567                 .pm = &swrm_dev_pm_ops,
1568         }
1569 };
1570 module_platform_driver(qcom_swrm_driver);
1571
1572 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1573 MODULE_LICENSE("GPL v2");