2 * AMx3 Wkup M3 IPC driver
4 * Copyright (C) 2015 Texas Instruments, Inc.
6 * Dave Gerlach <d-gerlach@ti.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/err.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
25 #include <linux/omap-mailbox.h>
26 #include <linux/platform_device.h>
27 #include <linux/remoteproc.h>
28 #include <linux/suspend.h>
29 #include <linux/wkup_m3_ipc.h>
31 #define AM33XX_CTRL_IPC_REG_COUNT 0x8
32 #define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m))
34 /* AM33XX M3_TXEV_EOI register */
35 #define AM33XX_CONTROL_M3_TXEV_EOI 0x00
37 #define AM33XX_M3_TXEV_ACK (0x1 << 0)
38 #define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
40 #define IPC_CMD_DS0 0x4
41 #define IPC_CMD_STANDBY 0xc
42 #define IPC_CMD_IDLE 0x10
43 #define IPC_CMD_RESET 0xe
44 #define DS_IPC_DEFAULT 0xffffffff
45 #define M3_VERSION_UNKNOWN 0x0000ffff
46 #define M3_BASELINE_VERSION 0x191
47 #define M3_STATUS_RESP_MASK (0xffff << 16)
48 #define M3_FW_VERSION_MASK 0xffff
49 #define M3_WAKE_SRC_MASK 0xff
51 #define M3_STATE_UNKNOWN 0
52 #define M3_STATE_RESET 1
53 #define M3_STATE_INITED 2
54 #define M3_STATE_MSG_FOR_LP 3
55 #define M3_STATE_MSG_FOR_RESET 4
57 static struct wkup_m3_ipc *m3_ipc_state;
59 static const struct wkup_m3_wakeup_src wakeups[] = {
60 {.irq_nr = 35, .src = "USB0_PHY"},
61 {.irq_nr = 36, .src = "USB1_PHY"},
62 {.irq_nr = 40, .src = "I2C0"},
63 {.irq_nr = 41, .src = "RTC Timer"},
64 {.irq_nr = 42, .src = "RTC Alarm"},
65 {.irq_nr = 43, .src = "Timer0"},
66 {.irq_nr = 44, .src = "Timer1"},
67 {.irq_nr = 45, .src = "UART"},
68 {.irq_nr = 46, .src = "GPIO0"},
69 {.irq_nr = 48, .src = "MPU_WAKE"},
70 {.irq_nr = 49, .src = "WDT0"},
71 {.irq_nr = 50, .src = "WDT1"},
72 {.irq_nr = 51, .src = "ADC_TSC"},
73 {.irq_nr = 0, .src = "Unknown"},
76 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
78 writel(AM33XX_M3_TXEV_ACK,
79 m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
82 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
84 writel(AM33XX_M3_TXEV_ENABLE,
85 m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
88 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
89 u32 val, int ipc_reg_num)
91 if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
92 "ipc register operation out of range"))
95 writel(val, m3_ipc->ipc_mem_base +
96 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
99 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
102 if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
103 "ipc register operation out of range"))
106 return readl(m3_ipc->ipc_mem_base +
107 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
110 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
114 val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
116 return val & M3_FW_VERSION_MASK;
119 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
121 struct wkup_m3_ipc *m3_ipc = ipc_data;
122 struct device *dev = m3_ipc->dev;
125 am33xx_txev_eoi(m3_ipc);
127 switch (m3_ipc->state) {
129 ver = wkup_m3_fw_version_read(m3_ipc);
131 if (ver == M3_VERSION_UNKNOWN ||
132 ver < M3_BASELINE_VERSION) {
133 dev_warn(dev, "CM3 Firmware Version %x not supported\n",
136 dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
139 m3_ipc->state = M3_STATE_INITED;
140 complete(&m3_ipc->sync_complete);
142 case M3_STATE_MSG_FOR_RESET:
143 m3_ipc->state = M3_STATE_INITED;
144 complete(&m3_ipc->sync_complete);
146 case M3_STATE_MSG_FOR_LP:
147 complete(&m3_ipc->sync_complete);
149 case M3_STATE_UNKNOWN:
150 dev_warn(dev, "Unknown CM3 State\n");
153 am33xx_txev_enable(m3_ipc);
158 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
160 struct device *dev = m3_ipc->dev;
161 mbox_msg_t dummy_msg = 0;
166 "No IPC channel to communicate with wkup_m3!\n");
171 * Write a dummy message to the mailbox in order to trigger the RX
172 * interrupt to alert the M3 that data is available in the IPC
173 * registers. We must enable the IRQ here and disable it after in
174 * the RX callback to avoid multiple interrupts being received
177 ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
179 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
184 ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
185 msecs_to_jiffies(500));
187 dev_err(dev, "MPU<->CM3 sync failure\n");
188 m3_ipc->state = M3_STATE_UNKNOWN;
192 mbox_client_txdone(m3_ipc->mbox, 0);
196 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
198 struct device *dev = m3_ipc->dev;
199 mbox_msg_t dummy_msg = 0;
204 "No IPC channel to communicate with wkup_m3!\n");
208 ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
210 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
215 mbox_client_txdone(m3_ipc->mbox, 0);
219 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
221 return ((m3_ipc->state != M3_STATE_RESET) &&
222 (m3_ipc->state != M3_STATE_UNKNOWN));
225 /* Public functions */
227 * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
228 * @mem_type: memory type value read directly from emif
230 * wkup_m3 must know what memory type is in use to properly suspend
233 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
235 m3_ipc->mem_type = mem_type;
239 * wkup_m3_set_resume_address - Pass wkup_m3 resume address
240 * @addr: Physical address from which resume code should execute
242 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
244 m3_ipc->resume_addr = (unsigned long)addr;
248 * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
250 * Returns code representing the status of a low power mode transition.
251 * 0 - Successful transition
252 * 1 - Failure to transition to low power state
254 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
259 val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
261 i = M3_STATUS_RESP_MASK & val;
262 i >>= __ffs(M3_STATUS_RESP_MASK);
268 * wkup_m3_prepare_low_power - Request preparation for transition to
270 * @state: A kernel suspend state to enter, either MEM or STANDBY
272 * Returns 0 if preparation was successful, otherwise returns error code
274 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
276 struct device *dev = m3_ipc->dev;
280 if (!wkup_m3_is_available(m3_ipc))
284 case WKUP_M3_DEEPSLEEP:
285 m3_power_state = IPC_CMD_DS0;
287 case WKUP_M3_STANDBY:
288 m3_power_state = IPC_CMD_STANDBY;
291 m3_power_state = IPC_CMD_IDLE;
297 /* Program each required IPC register then write defaults to others */
298 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
299 wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
300 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type, 4);
302 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
303 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
304 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
305 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
306 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
308 m3_ipc->state = M3_STATE_MSG_FOR_LP;
310 if (state == WKUP_M3_IDLE)
311 ret = wkup_m3_ping_noirq(m3_ipc);
313 ret = wkup_m3_ping(m3_ipc);
316 dev_err(dev, "Unable to ping CM3\n");
324 * wkup_m3_finish_low_power - Return m3 to reset state
326 * Returns 0 if reset was successful, otherwise returns error code
328 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
330 struct device *dev = m3_ipc->dev;
333 if (!wkup_m3_is_available(m3_ipc))
336 wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
337 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
339 m3_ipc->state = M3_STATE_MSG_FOR_RESET;
341 ret = wkup_m3_ping(m3_ipc);
343 dev_err(dev, "Unable to ping CM3\n");
351 * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
352 * @m3_ipc: Pointer to wkup_m3_ipc context
354 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
356 unsigned int wakeup_src_idx;
359 val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
361 wakeup_src_idx = val & M3_WAKE_SRC_MASK;
363 for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
364 if (wakeups[j].irq_nr == wakeup_src_idx)
365 return wakeups[j].src;
367 return wakeups[j].src;
371 * wkup_m3_set_rtc_only - Set the rtc_only flag
372 * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the
375 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
378 m3_ipc_state->is_rtc_only = true;
381 static struct wkup_m3_ipc_ops ipc_ops = {
382 .set_mem_type = wkup_m3_set_mem_type,
383 .set_resume_address = wkup_m3_set_resume_address,
384 .prepare_low_power = wkup_m3_prepare_low_power,
385 .finish_low_power = wkup_m3_finish_low_power,
386 .request_pm_status = wkup_m3_request_pm_status,
387 .request_wake_src = wkup_m3_request_wake_src,
388 .set_rtc_only = wkup_m3_set_rtc_only,
392 * wkup_m3_ipc_get - Return handle to wkup_m3_ipc
394 * Returns NULL if the wkup_m3 is not yet available, otherwise returns
395 * pointer to wkup_m3_ipc struct.
397 struct wkup_m3_ipc *wkup_m3_ipc_get(void)
400 get_device(m3_ipc_state->dev);
406 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
409 * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
410 * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
412 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
415 put_device(m3_ipc_state->dev);
417 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
419 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc)
421 struct device *dev = m3_ipc->dev;
424 init_completion(&m3_ipc->sync_complete);
426 ret = rproc_boot(m3_ipc->rproc);
428 dev_err(dev, "rproc_boot failed\n");
430 m3_ipc_state = m3_ipc;
435 static int wkup_m3_ipc_probe(struct platform_device *pdev)
437 struct device *dev = &pdev->dev;
439 phandle rproc_phandle;
440 struct rproc *m3_rproc;
441 struct resource *res;
442 struct task_struct *task;
443 struct wkup_m3_ipc *m3_ipc;
445 m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
449 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
450 m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
451 if (IS_ERR(m3_ipc->ipc_mem_base)) {
452 dev_err(dev, "could not ioremap ipc_mem\n");
453 return PTR_ERR(m3_ipc->ipc_mem_base);
456 irq = platform_get_irq(pdev, 0);
458 dev_err(&pdev->dev, "no irq resource\n");
462 ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
463 0, "wkup_m3_txev", m3_ipc);
465 dev_err(dev, "request_irq failed\n");
469 m3_ipc->mbox_client.dev = dev;
470 m3_ipc->mbox_client.tx_done = NULL;
471 m3_ipc->mbox_client.tx_prepare = NULL;
472 m3_ipc->mbox_client.rx_callback = NULL;
473 m3_ipc->mbox_client.tx_block = false;
474 m3_ipc->mbox_client.knows_txdone = false;
476 m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
478 if (IS_ERR(m3_ipc->mbox)) {
479 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
480 PTR_ERR(m3_ipc->mbox));
481 return PTR_ERR(m3_ipc->mbox);
484 if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
485 dev_err(&pdev->dev, "could not get rproc phandle\n");
490 m3_rproc = rproc_get_by_phandle(rproc_phandle);
492 dev_err(&pdev->dev, "could not get rproc handle\n");
497 m3_ipc->rproc = m3_rproc;
499 m3_ipc->state = M3_STATE_RESET;
501 m3_ipc->ops = &ipc_ops;
504 * Wait for firmware loading completion in a thread so we
505 * can boot the wkup_m3 as soon as it's ready without holding
508 task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc,
509 "wkup_m3_rproc_loader");
512 dev_err(dev, "can't create rproc_boot thread\n");
522 mbox_free_channel(m3_ipc->mbox);
526 static int wkup_m3_ipc_remove(struct platform_device *pdev)
528 mbox_free_channel(m3_ipc_state->mbox);
530 rproc_shutdown(m3_ipc_state->rproc);
531 rproc_put(m3_ipc_state->rproc);
538 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
541 * Nothing needs to be done on suspend even with rtc_only flag set
546 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
548 if (m3_ipc_state->is_rtc_only) {
549 rproc_shutdown(m3_ipc_state->rproc);
550 rproc_boot(m3_ipc_state->rproc);
553 m3_ipc_state->is_rtc_only = false;
558 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
559 SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
562 static const struct of_device_id wkup_m3_ipc_of_match[] = {
563 { .compatible = "ti,am3352-wkup-m3-ipc", },
564 { .compatible = "ti,am4372-wkup-m3-ipc", },
567 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
569 static struct platform_driver wkup_m3_ipc_driver = {
570 .probe = wkup_m3_ipc_probe,
571 .remove = wkup_m3_ipc_remove,
573 .name = "wkup_m3_ipc",
574 .of_match_table = wkup_m3_ipc_of_match,
575 .pm = &wkup_m3_ipc_pm_ops,
579 module_platform_driver(wkup_m3_ipc_driver);
581 MODULE_LICENSE("GPL v2");
582 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
583 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");