1 // SPDX-License-Identifier: GPL-2.0+
3 * Voltage regulators coupler for NVIDIA Tegra30
4 * Copyright (C) 2019 GRATE-DRIVER project
6 * Voltage constraints borrowed from downstream kernel sources
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
12 #include <linux/init.h>
13 #include <linux/kernel.h>
15 #include <linux/reboot.h>
16 #include <linux/regulator/coupler.h>
17 #include <linux/regulator/driver.h>
18 #include <linux/regulator/machine.h>
19 #include <linux/suspend.h>
21 #include <soc/tegra/fuse.h>
22 #include <soc/tegra/pmc.h>
24 struct tegra_regulator_coupler {
25 struct regulator_coupler coupler;
26 struct regulator_dev *core_rdev;
27 struct regulator_dev *cpu_rdev;
28 struct notifier_block reboot_notifier;
29 struct notifier_block suspend_notifier;
30 int core_min_uV, cpu_min_uV;
31 bool sys_reboot_mode_req;
33 bool sys_suspend_mode_req;
34 bool sys_suspend_mode;
37 static inline struct tegra_regulator_coupler *
38 to_tegra_coupler(struct regulator_coupler *coupler)
40 return container_of(coupler, struct tegra_regulator_coupler, coupler);
43 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra,
44 struct regulator_dev *core_rdev)
52 * Tegra30 SoC has critical DVFS-capable devices that are
53 * permanently-active or active at a boot time, like EMC
54 * (DRAM controller) or Display controller for example.
56 * The voltage of a CORE SoC power domain shall not be dropped below
57 * a minimum level, which is determined by device's clock rate.
58 * This means that we can't fully allow CORE voltage scaling until
59 * the state of all DVFS-critical CORE devices is synced.
61 if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) {
62 pr_info_once("voltage state synced\n");
66 if (tegra->core_min_uV > 0)
67 return tegra->core_min_uV;
69 core_cur_uV = regulator_get_voltage_rdev(core_rdev);
73 core_max_uV = max(core_cur_uV, 1200000);
75 err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV);
80 * Limit minimum CORE voltage to a value left from bootloader or,
81 * if it's unreasonably low value, to the most common 1.2v or to
82 * whatever maximum value defined via board's device-tree.
84 tegra->core_min_uV = core_max_uV;
86 pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);
88 return tegra->core_min_uV;
91 static int tegra30_core_cpu_limit(int cpu_uV)
102 if (cpu_uV < 1100000)
105 if (cpu_uV < 1250000) {
106 switch (tegra_sku_info.cpu_speedo_id) {
120 static int tegra30_cpu_nominal_uV(void)
122 switch (tegra_sku_info.cpu_speedo_id) {
142 static int tegra30_core_nominal_uV(void)
144 switch (tegra_sku_info.soc_speedo_id) {
149 if (tegra_sku_info.cpu_speedo_id != 7 &&
150 tegra_sku_info.cpu_speedo_id != 8)
156 if (tegra_sku_info.cpu_speedo_id != 13)
166 static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra,
167 struct regulator_dev *cpu_rdev,
168 struct regulator_dev *core_rdev)
170 int core_min_uV, core_max_uV = INT_MAX;
171 int cpu_min_uV, cpu_max_uV = INT_MAX;
172 int cpu_min_uV_consumers = 0;
173 int core_min_limited_uV;
184 * CPU voltage should not got lower than 300mV from the CORE.
185 * CPU voltage should stay below the CORE by 100mV+, depending
186 * by the CORE voltage. This applies to all Tegra30 SoC's.
188 max_spread = cpu_rdev->constraints->max_spread[0];
189 cpu_max_step = cpu_rdev->constraints->max_uV_step;
190 core_max_step = core_rdev->constraints->max_uV_step;
193 pr_err_once("cpu-core max-spread is undefined in device-tree\n");
198 pr_err_once("cpu max-step is undefined in device-tree\n");
199 cpu_max_step = 150000;
202 if (!core_max_step) {
203 pr_err_once("core max-step is undefined in device-tree\n");
204 core_max_step = 150000;
208 * The CORE voltage scaling is currently not hooked up in drivers,
209 * hence we will limit the minimum CORE voltage to a reasonable value.
210 * This should be good enough for the time being.
212 core_min_uV = tegra30_core_limit(tegra, core_rdev);
216 err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV,
221 /* prepare voltage level for suspend */
222 if (tegra->sys_suspend_mode)
223 core_min_uV = clamp(tegra30_core_nominal_uV(),
224 core_min_uV, core_max_uV);
226 core_uV = regulator_get_voltage_rdev(core_rdev);
230 cpu_min_uV = core_min_uV - max_spread;
232 err = regulator_check_consumers(cpu_rdev, &cpu_min_uV, &cpu_max_uV,
237 err = regulator_check_consumers(cpu_rdev, &cpu_min_uV_consumers,
238 &cpu_max_uV, PM_SUSPEND_ON);
242 err = regulator_check_voltage(cpu_rdev, &cpu_min_uV, &cpu_max_uV);
246 cpu_uV = regulator_get_voltage_rdev(cpu_rdev);
250 /* store boot voltage level */
251 if (!tegra->cpu_min_uV)
252 tegra->cpu_min_uV = cpu_uV;
255 * CPU's regulator may not have any consumers, hence the voltage
256 * must not be changed in that case because CPU simply won't
257 * survive the voltage drop if it's running on a higher frequency.
259 if (!cpu_min_uV_consumers)
260 cpu_min_uV = max(cpu_uV, cpu_min_uV);
263 * Bootloader shall set up voltages correctly, but if it
264 * happens that there is a violation, then try to fix it
267 core_min_limited_uV = tegra30_core_cpu_limit(cpu_uV);
268 if (core_min_limited_uV < 0)
269 return core_min_limited_uV;
271 core_min_uV = max(core_min_uV, tegra30_core_cpu_limit(cpu_min_uV));
273 err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV);
277 /* restore boot voltage level */
278 if (tegra->sys_reboot_mode)
279 cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV);
281 /* prepare voltage level for suspend */
282 if (tegra->sys_suspend_mode)
283 cpu_min_uV = clamp(tegra30_cpu_nominal_uV(),
284 cpu_min_uV, cpu_max_uV);
286 if (core_min_limited_uV > core_uV) {
287 pr_err("core voltage constraint violated: %d %d %d\n",
288 core_uV, core_min_limited_uV, cpu_uV);
292 while (cpu_uV != cpu_min_uV || core_uV != core_min_uV) {
293 if (cpu_uV < cpu_min_uV) {
294 cpu_target_uV = min(cpu_uV + cpu_max_step, cpu_min_uV);
296 cpu_target_uV = max(cpu_uV - cpu_max_step, cpu_min_uV);
297 cpu_target_uV = max(core_uV - max_spread, cpu_target_uV);
300 if (cpu_uV == cpu_target_uV)
303 err = regulator_set_voltage_rdev(cpu_rdev,
310 cpu_uV = cpu_target_uV;
312 core_min_limited_uV = tegra30_core_cpu_limit(cpu_uV);
313 if (core_min_limited_uV < 0)
314 return core_min_limited_uV;
316 core_target_uV = max(core_min_limited_uV, core_min_uV);
318 if (core_uV < core_target_uV) {
319 core_target_uV = min(core_target_uV, core_uV + core_max_step);
320 core_target_uV = min(core_target_uV, cpu_uV + max_spread);
322 core_target_uV = max(core_target_uV, core_uV - core_max_step);
325 if (core_uV == core_target_uV)
328 err = regulator_set_voltage_rdev(core_rdev,
335 core_uV = core_target_uV;
341 static int tegra30_regulator_balance_voltage(struct regulator_coupler *coupler,
342 struct regulator_dev *rdev,
343 suspend_state_t state)
345 struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
346 struct regulator_dev *core_rdev = tegra->core_rdev;
347 struct regulator_dev *cpu_rdev = tegra->cpu_rdev;
349 if ((core_rdev != rdev && cpu_rdev != rdev) || state != PM_SUSPEND_ON) {
350 pr_err("regulators are not coupled properly\n");
354 tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req);
355 tegra->sys_suspend_mode = READ_ONCE(tegra->sys_suspend_mode_req);
357 return tegra30_voltage_update(tegra, cpu_rdev, core_rdev);
360 static int tegra30_regulator_prepare_suspend(struct tegra_regulator_coupler *tegra,
361 bool sys_suspend_mode)
365 if (!tegra->core_rdev || !tegra->cpu_rdev)
369 * All power domains are enabled early during resume from suspend
370 * by GENPD core. Domains like VENC may require a higher voltage
371 * when enabled during resume from suspend. This also prepares
372 * hardware for resuming from LP0.
375 WRITE_ONCE(tegra->sys_suspend_mode_req, sys_suspend_mode);
377 err = regulator_sync_voltage_rdev(tegra->cpu_rdev);
381 err = regulator_sync_voltage_rdev(tegra->core_rdev);
388 static int tegra30_regulator_suspend(struct notifier_block *notifier,
389 unsigned long mode, void *arg)
391 struct tegra_regulator_coupler *tegra;
394 tegra = container_of(notifier, struct tegra_regulator_coupler,
398 case PM_HIBERNATION_PREPARE:
399 case PM_RESTORE_PREPARE:
400 case PM_SUSPEND_PREPARE:
401 ret = tegra30_regulator_prepare_suspend(tegra, true);
404 case PM_POST_HIBERNATION:
405 case PM_POST_RESTORE:
406 case PM_POST_SUSPEND:
407 ret = tegra30_regulator_prepare_suspend(tegra, false);
412 pr_err("failed to prepare regulators: %d\n", ret);
414 return notifier_from_errno(ret);
417 static int tegra30_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra,
418 bool sys_reboot_mode)
422 if (!tegra->core_rdev || !tegra->cpu_rdev)
425 WRITE_ONCE(tegra->sys_reboot_mode_req, true);
428 * Some devices use CPU soft-reboot method and in this case we
429 * should ensure that voltages are sane for the reboot by restoring
430 * the minimum boot levels.
432 err = regulator_sync_voltage_rdev(tegra->cpu_rdev);
436 err = regulator_sync_voltage_rdev(tegra->core_rdev);
440 WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode);
445 static int tegra30_regulator_reboot(struct notifier_block *notifier,
446 unsigned long event, void *cmd)
448 struct tegra_regulator_coupler *tegra;
451 if (event != SYS_RESTART)
454 tegra = container_of(notifier, struct tegra_regulator_coupler,
457 ret = tegra30_regulator_prepare_reboot(tegra, true);
459 return notifier_from_errno(ret);
462 static int tegra30_regulator_attach(struct regulator_coupler *coupler,
463 struct regulator_dev *rdev)
465 struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
466 struct device_node *np = rdev->dev.of_node;
468 if (of_property_read_bool(np, "nvidia,tegra-core-regulator") &&
470 tegra->core_rdev = rdev;
474 if (of_property_read_bool(np, "nvidia,tegra-cpu-regulator") &&
476 tegra->cpu_rdev = rdev;
483 static int tegra30_regulator_detach(struct regulator_coupler *coupler,
484 struct regulator_dev *rdev)
486 struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
489 * We don't expect regulators to be decoupled during reboot,
490 * this may race with the reboot handler and shouldn't ever
491 * happen in practice.
493 if (WARN_ON_ONCE(system_state > SYSTEM_RUNNING))
496 if (tegra->core_rdev == rdev) {
497 tegra->core_rdev = NULL;
501 if (tegra->cpu_rdev == rdev) {
502 tegra->cpu_rdev = NULL;
509 static struct tegra_regulator_coupler tegra30_coupler = {
511 .attach_regulator = tegra30_regulator_attach,
512 .detach_regulator = tegra30_regulator_detach,
513 .balance_voltage = tegra30_regulator_balance_voltage,
515 .reboot_notifier.notifier_call = tegra30_regulator_reboot,
516 .suspend_notifier.notifier_call = tegra30_regulator_suspend,
519 static int __init tegra_regulator_coupler_init(void)
523 if (!of_machine_is_compatible("nvidia,tegra30"))
526 err = register_reboot_notifier(&tegra30_coupler.reboot_notifier);
529 err = register_pm_notifier(&tegra30_coupler.suspend_notifier);
532 return regulator_coupler_register(&tegra30_coupler.coupler);
534 arch_initcall(tegra_regulator_coupler_init);