1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/iopoll.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/of_address.h>
33 #include <linux/of_clk.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_platform.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/platform_device.h>
41 #include <linux/pm_domain.h>
42 #include <linux/pm_opp.h>
43 #include <linux/power_supply.h>
44 #include <linux/reboot.h>
45 #include <linux/regmap.h>
46 #include <linux/reset.h>
47 #include <linux/seq_file.h>
48 #include <linux/slab.h>
49 #include <linux/spinlock.h>
50 #include <linux/syscore_ops.h>
52 #include <soc/tegra/common.h>
53 #include <soc/tegra/fuse.h>
54 #include <soc/tegra/pmc.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
59 #include <dt-bindings/gpio/tegra194-gpio.h>
60 #include <dt-bindings/gpio/tegra234-gpio.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
64 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
65 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
66 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
67 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
68 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
69 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
70 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
71 #define PMC_CNTRL_BLINK_EN 7
72 #define PMC_CNTRL_MAIN_RST BIT(4)
74 #define PMC_WAKE_MASK 0x0c
75 #define PMC_WAKE_LEVEL 0x10
76 #define PMC_WAKE_STATUS 0x14
77 #define PMC_SW_WAKE_STATUS 0x18
78 #define PMC_DPD_PADS_ORIDE 0x1c
79 #define PMC_DPD_PADS_ORIDE_BLINK 20
81 #define DPD_SAMPLE 0x020
82 #define DPD_SAMPLE_ENABLE BIT(0)
83 #define DPD_SAMPLE_DISABLE (0 << 0)
85 #define PWRGATE_TOGGLE 0x30
86 #define PWRGATE_TOGGLE_START BIT(8)
88 #define REMOVE_CLAMPING 0x34
90 #define PWRGATE_STATUS 0x38
92 #define PMC_BLINK_TIMER 0x40
93 #define PMC_IMPL_E_33V_PWR 0x40
95 #define PMC_PWR_DET 0x48
97 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
98 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
99 #define PMC_SCRATCH0_MODE_RCM BIT(1)
100 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
101 PMC_SCRATCH0_MODE_BOOTLOADER | \
102 PMC_SCRATCH0_MODE_RCM)
104 #define PMC_CPUPWRGOOD_TIMER 0xc8
105 #define PMC_CPUPWROFF_TIMER 0xcc
106 #define PMC_COREPWRGOOD_TIMER 0x3c
107 #define PMC_COREPWROFF_TIMER 0xe0
109 #define PMC_PWR_DET_VALUE 0xe4
111 #define PMC_USB_DEBOUNCE_DEL 0xec
112 #define PMC_USB_AO 0xf0
114 #define PMC_SCRATCH37 0x130
115 #define PMC_SCRATCH41 0x140
117 #define PMC_WAKE2_MASK 0x160
118 #define PMC_WAKE2_LEVEL 0x164
119 #define PMC_WAKE2_STATUS 0x168
120 #define PMC_SW_WAKE2_STATUS 0x16c
122 #define PMC_CLK_OUT_CNTRL 0x1a8
123 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
124 #define PMC_SENSOR_CTRL 0x1b0
125 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
126 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
128 #define PMC_RST_STATUS_POR 0
129 #define PMC_RST_STATUS_WATCHDOG 1
130 #define PMC_RST_STATUS_SENSOR 2
131 #define PMC_RST_STATUS_SW_MAIN 3
132 #define PMC_RST_STATUS_LP0 4
133 #define PMC_RST_STATUS_AOTAG 5
135 #define IO_DPD_REQ 0x1b8
136 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
137 #define IO_DPD_REQ_CODE_OFF (1U << 30)
138 #define IO_DPD_REQ_CODE_ON (2U << 30)
139 #define IO_DPD_REQ_CODE_MASK (3U << 30)
141 #define IO_DPD_STATUS 0x1bc
142 #define IO_DPD2_REQ 0x1c0
143 #define IO_DPD2_STATUS 0x1c4
144 #define SEL_DPD_TIM 0x1c8
146 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
147 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
149 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
150 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
151 #define PMC_UTMIP_UHSIC_FAKE 0x218
153 #define PMC_SCRATCH54 0x258
154 #define PMC_SCRATCH54_DATA_SHIFT 8
155 #define PMC_SCRATCH54_ADDR_SHIFT 0
157 #define PMC_SCRATCH55 0x25c
158 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
159 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
160 #define PMC_SCRATCH55_PINMUX_SHIFT 24
161 #define PMC_SCRATCH55_16BITOP BIT(15)
162 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
163 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
165 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
167 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
168 #define PMC_UTMIP_MASTER_CONFIG 0x274
169 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
170 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
172 #define GPU_RG_CNTRL 0x2d4
174 #define PMC_UTMIP_PAD_CFG0 0x4c0
175 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
176 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
177 /* Tegra186 and later */
178 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
179 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
180 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1)
181 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
182 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
183 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
184 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
185 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
186 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
187 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
188 #define WAKE_AOWAKE_SW_STATUS_W_0 0x49c
189 #define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2))
190 #define WAKE_LATCH_SW 0x498
192 #define WAKE_AOWAKE_CTRL 0x4f4
193 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
195 #define SW_WAKE_ID 83 /* wake83 */
198 #define TEGRA_SMC_PMC 0xc2fffe00
199 #define TEGRA_SMC_PMC_READ 0xaa
200 #define TEGRA_SMC_PMC_WRITE 0xbb
209 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
211 struct pmc_clk_gate {
217 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
219 struct pmc_clk_init_data {
221 const char *const *parents;
228 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
229 "osc_div4", "extern1",
232 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
233 "osc_div4", "extern2",
236 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
237 "osc_div4", "extern3",
240 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
242 .name = "pmc_clk_out_1",
243 .parents = clk_out1_parents,
244 .num_parents = ARRAY_SIZE(clk_out1_parents),
245 .clk_id = TEGRA_PMC_CLK_OUT_1,
250 .name = "pmc_clk_out_2",
251 .parents = clk_out2_parents,
252 .num_parents = ARRAY_SIZE(clk_out2_parents),
253 .clk_id = TEGRA_PMC_CLK_OUT_2,
255 .force_en_shift = 10,
258 .name = "pmc_clk_out_3",
259 .parents = clk_out3_parents,
260 .num_parents = ARRAY_SIZE(clk_out3_parents),
261 .clk_id = TEGRA_PMC_CLK_OUT_3,
263 .force_en_shift = 18,
267 struct tegra_powergate {
268 struct generic_pm_domain genpd;
269 struct tegra_pmc *pmc;
272 unsigned int num_clks;
273 unsigned long *clk_rates;
274 struct reset_control *reset;
277 struct tegra_io_pad_soc {
278 enum tegra_io_pad id;
280 unsigned int request;
282 unsigned int voltage;
286 struct tegra_pmc_regs {
287 unsigned int scratch0;
288 unsigned int rst_status;
289 unsigned int rst_source_shift;
290 unsigned int rst_source_mask;
291 unsigned int rst_level_shift;
292 unsigned int rst_level_mask;
295 struct tegra_wake_event {
300 unsigned int instance;
305 #define TEGRA_WAKE_SIMPLE(_name, _id) \
311 .instance = UINT_MAX, \
316 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
322 .instance = UINT_MAX, \
327 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
333 .instance = _instance, \
338 struct tegra_pmc_soc {
339 unsigned int num_powergates;
340 const char *const *powergates;
341 unsigned int num_cpu_powergates;
342 const u8 *cpu_powergates;
344 bool has_tsense_reset;
346 bool needs_mbist_war;
347 bool has_impl_33v_pwr;
350 const struct tegra_io_pad_soc *io_pads;
351 unsigned int num_io_pads;
353 const struct pinctrl_pin_desc *pin_descs;
354 unsigned int num_pin_descs;
356 const struct tegra_pmc_regs *regs;
357 void (*init)(struct tegra_pmc *pmc);
358 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
359 struct device_node *np,
361 void (*set_wake_filters)(struct tegra_pmc *pmc);
362 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
363 int (*irq_set_type)(struct irq_data *data, unsigned int type);
364 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
367 const char * const *reset_sources;
368 unsigned int num_reset_sources;
369 const char * const *reset_levels;
370 unsigned int num_reset_levels;
373 * These describe events that can wake the system from sleep (i.e.
374 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
375 * are dealt with in the LIC.
377 const struct tegra_wake_event *wake_events;
378 unsigned int num_wake_events;
379 unsigned int max_wake_events;
380 unsigned int max_wake_vectors;
382 const struct pmc_clk_init_data *pmc_clks_data;
383 unsigned int num_pmc_clks;
384 bool has_blink_output;
385 bool has_usb_sleepwalk;
386 bool supports_core_domain;
387 bool has_single_mmio_aperture;
391 * struct tegra_pmc - NVIDIA Tegra PMC
392 * @dev: pointer to PMC device structure
393 * @base: pointer to I/O remapped register region
394 * @wake: pointer to I/O remapped region for WAKE registers
395 * @aotag: pointer to I/O remapped region for AOTAG registers
396 * @scratch: pointer to I/O remapped region for scratch registers
397 * @clk: pointer to pclk clock
398 * @soc: pointer to SoC data structure
399 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
400 * @rate: currently configured rate of pclk
401 * @suspend_mode: lowest suspend mode available
402 * @cpu_good_time: CPU power good time (in microseconds)
403 * @cpu_off_time: CPU power off time (in microsecends)
404 * @core_osc_time: core power good OSC time (in microseconds)
405 * @core_pmu_time: core power good PMU time (in microseconds)
406 * @core_off_time: core power off time (in microseconds)
407 * @corereq_high: core power request is active-high
408 * @sysclkreq_high: system clock request is active-high
409 * @combined_req: combined power request for CPU & core
410 * @cpu_pwr_good_en: CPU power good signal is enabled
411 * @lp0_vec_phys: physical base address of the LP0 warm boot code
412 * @lp0_vec_size: size of the LP0 warm boot code
413 * @powergates_available: Bitmap of available power gates
414 * @powergates_lock: mutex for power gate register access
415 * @pctl_dev: pin controller exposed by the PMC
416 * @domain: IRQ domain provided by the PMC
417 * @irq: chip implementation for the IRQ domain
418 * @clk_nb: pclk clock changes handler
419 * @core_domain_state_synced: flag marking the core domain's state as synced
420 * @core_domain_registered: flag marking the core domain as registered
421 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes
422 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not
423 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask
424 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in
425 * cntrl register associated with each wake during system suspend.
432 void __iomem *scratch;
435 const struct tegra_pmc_soc *soc;
440 enum tegra_suspend_mode suspend_mode;
449 bool cpu_pwr_good_en;
452 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
454 struct mutex powergates_lock;
456 struct pinctrl_dev *pctl_dev;
458 struct irq_domain *domain;
461 struct notifier_block clk_nb;
463 bool core_domain_state_synced;
464 bool core_domain_registered;
466 unsigned long *wake_type_level_map;
467 unsigned long *wake_type_dual_edge_map;
468 unsigned long *wake_sw_status_map;
469 unsigned long *wake_cntrl_level_map;
470 struct syscore_ops syscore;
473 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
475 .suspend_mode = TEGRA_SUSPEND_NOT_READY,
478 static inline struct tegra_powergate *
479 to_powergate(struct generic_pm_domain *domain)
481 return container_of(domain, struct tegra_powergate, genpd);
484 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
486 struct arm_smccc_res res;
489 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
493 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
496 pr_warn("%s(): SMC failed: %lu\n", __func__,
503 return readl(pmc->base + offset);
506 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
507 unsigned long offset)
509 struct arm_smccc_res res;
512 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
513 value, 0, 0, 0, 0, &res);
516 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
519 pr_warn("%s(): SMC failed: %lu\n", __func__,
523 writel(value, pmc->base + offset);
527 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
530 return tegra_pmc_readl(pmc, offset);
532 return readl(pmc->scratch + offset);
535 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
536 unsigned long offset)
539 tegra_pmc_writel(pmc, value, offset);
541 writel(value, pmc->scratch + offset);
545 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
546 * This currently doesn't work because readx_poll_timeout() can only operate
547 * on functions that take a single argument.
549 static inline bool tegra_powergate_state(int id)
551 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
552 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
554 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
557 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
559 return (pmc->soc && pmc->soc->powergates[id]);
562 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
564 return test_bit(id, pmc->powergates_available);
567 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
571 if (!pmc || !pmc->soc || !name)
574 for (i = 0; i < pmc->soc->num_powergates; i++) {
575 if (!tegra_powergate_is_valid(pmc, i))
578 if (!strcmp(name, pmc->soc->powergates[i]))
585 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
588 unsigned int retries = 100;
593 * As per TRM documentation, the toggle command will be dropped by PMC
594 * if there is contention with a HW-initiated toggling (i.e. CPU core
595 * power-gated), the command should be retried in that case.
598 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
600 /* wait for PMC to execute the command */
601 ret = readx_poll_timeout(tegra_powergate_state, id, status,
602 status == new_state, 1, 10);
603 } while (ret == -ETIMEDOUT && retries--);
608 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
610 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
613 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
619 /* wait while PMC power gating is contended */
620 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
621 status == true, 1, 100);
625 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
627 /* wait for PMC to accept the command */
628 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
629 status == true, 1, 100);
633 /* wait for PMC to execute the command */
634 err = readx_poll_timeout(tegra_powergate_state, id, status,
635 status == new_state, 10, 100000);
643 * tegra_powergate_set() - set the state of a partition
644 * @pmc: power management controller
646 * @new_state: new state of the partition
648 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
653 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
656 mutex_lock(&pmc->powergates_lock);
658 if (tegra_powergate_state(id) == new_state) {
659 mutex_unlock(&pmc->powergates_lock);
663 err = pmc->soc->powergate_set(pmc, id, new_state);
665 mutex_unlock(&pmc->powergates_lock);
670 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
675 mutex_lock(&pmc->powergates_lock);
678 * On Tegra124 and later, the clamps for the GPU are controlled by a
679 * separate register (with different semantics).
681 if (id == TEGRA_POWERGATE_3D) {
682 if (pmc->soc->has_gpu_clamps) {
683 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
689 * Tegra 2 has a bug where PCIE and VDE clamping masks are
690 * swapped relatively to the partition ids
692 if (id == TEGRA_POWERGATE_VDEC)
693 mask = (1 << TEGRA_POWERGATE_PCIE);
694 else if (id == TEGRA_POWERGATE_PCIE)
695 mask = (1 << TEGRA_POWERGATE_VDEC);
699 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
702 mutex_unlock(&pmc->powergates_lock);
707 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
709 unsigned long safe_rate = 100 * 1000 * 1000;
713 for (i = 0; i < pg->num_clks; i++) {
714 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
716 if (!pg->clk_rates[i]) {
721 if (pg->clk_rates[i] <= safe_rate)
725 * We don't know whether voltage state is okay for the
726 * current clock rate, hence it's better to temporally
727 * switch clock to a safe rate which is suitable for
728 * all voltages, before enabling the clock.
730 err = clk_set_rate(pg->clks[i], safe_rate);
739 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
744 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
749 for (i = 0; i < pg->num_clks; i++) {
750 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
758 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
762 for (i = 0; i < pg->num_clks; i++)
763 clk_disable_unprepare(pg->clks[i]);
766 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
771 for (i = 0; i < pg->num_clks; i++) {
772 err = clk_prepare_enable(pg->clks[i]);
781 clk_disable_unprepare(pg->clks[i]);
786 static int tegra_powergate_power_up(struct tegra_powergate *pg,
791 err = reset_control_assert(pg->reset);
795 usleep_range(10, 20);
797 err = tegra_powergate_set(pg->pmc, pg->id, true);
801 usleep_range(10, 20);
803 err = tegra_powergate_prepare_clocks(pg);
807 err = tegra_powergate_enable_clocks(pg);
811 usleep_range(10, 20);
813 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
817 usleep_range(10, 20);
819 err = reset_control_deassert(pg->reset);
823 usleep_range(10, 20);
825 if (pg->pmc->soc->needs_mbist_war)
826 err = tegra210_clk_handle_mbist_war(pg->id);
831 tegra_powergate_disable_clocks(pg);
833 err = tegra_powergate_unprepare_clocks(pg);
840 tegra_powergate_disable_clocks(pg);
841 usleep_range(10, 20);
844 tegra_powergate_unprepare_clocks(pg);
847 tegra_powergate_set(pg->pmc, pg->id, false);
852 static int tegra_powergate_power_down(struct tegra_powergate *pg)
856 err = tegra_powergate_prepare_clocks(pg);
860 err = tegra_powergate_enable_clocks(pg);
864 usleep_range(10, 20);
866 err = reset_control_assert(pg->reset);
870 usleep_range(10, 20);
872 tegra_powergate_disable_clocks(pg);
874 usleep_range(10, 20);
876 err = tegra_powergate_set(pg->pmc, pg->id, false);
880 err = tegra_powergate_unprepare_clocks(pg);
887 tegra_powergate_enable_clocks(pg);
888 usleep_range(10, 20);
889 reset_control_deassert(pg->reset);
890 usleep_range(10, 20);
893 tegra_powergate_disable_clocks(pg);
896 tegra_powergate_unprepare_clocks(pg);
901 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
903 struct tegra_powergate *pg = to_powergate(domain);
904 struct device *dev = pg->pmc->dev;
907 err = tegra_powergate_power_up(pg, true);
909 dev_err(dev, "failed to turn on PM domain %s: %d\n",
910 pg->genpd.name, err);
914 reset_control_release(pg->reset);
920 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
922 struct tegra_powergate *pg = to_powergate(domain);
923 struct device *dev = pg->pmc->dev;
926 err = reset_control_acquire(pg->reset);
928 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
929 pg->genpd.name, err);
933 err = tegra_powergate_power_down(pg);
935 dev_err(dev, "failed to turn off PM domain %s: %d\n",
936 pg->genpd.name, err);
937 reset_control_release(pg->reset);
944 * tegra_powergate_power_on() - power on partition
947 int tegra_powergate_power_on(unsigned int id)
949 if (!tegra_powergate_is_available(pmc, id))
952 return tegra_powergate_set(pmc, id, true);
954 EXPORT_SYMBOL(tegra_powergate_power_on);
957 * tegra_powergate_power_off() - power off partition
960 int tegra_powergate_power_off(unsigned int id)
962 if (!tegra_powergate_is_available(pmc, id))
965 return tegra_powergate_set(pmc, id, false);
967 EXPORT_SYMBOL(tegra_powergate_power_off);
970 * tegra_powergate_is_powered() - check if partition is powered
971 * @pmc: power management controller
974 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
976 if (!tegra_powergate_is_valid(pmc, id))
979 return tegra_powergate_state(id);
983 * tegra_powergate_remove_clamping() - remove power clamps for partition
986 int tegra_powergate_remove_clamping(unsigned int id)
988 if (!tegra_powergate_is_available(pmc, id))
991 return __tegra_powergate_remove_clamping(pmc, id);
993 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
996 * tegra_powergate_sequence_power_up() - power up partition
998 * @clk: clock for partition
999 * @rst: reset for partition
1001 * Must be called with clk disabled, and returns with clk enabled.
1003 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
1004 struct reset_control *rst)
1006 struct tegra_powergate *pg;
1009 if (!tegra_powergate_is_available(pmc, id))
1012 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1016 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
1017 if (!pg->clk_rates) {
1028 err = tegra_powergate_power_up(pg, false);
1030 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
1033 kfree(pg->clk_rates);
1038 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1041 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1042 * @pmc: power management controller
1043 * @cpuid: CPU partition ID
1045 * Returns the partition ID corresponding to the CPU partition ID or a
1046 * negative error code on failure.
1048 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1051 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1052 return pmc->soc->cpu_powergates[cpuid];
1058 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1059 * @cpuid: CPU partition ID
1061 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1065 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1069 return tegra_powergate_is_powered(pmc, id);
1073 * tegra_pmc_cpu_power_on() - power on CPU partition
1074 * @cpuid: CPU partition ID
1076 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1080 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1084 return tegra_powergate_set(pmc, id, true);
1088 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1089 * @cpuid: CPU partition ID
1091 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1095 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1099 return tegra_powergate_remove_clamping(id);
1102 static void tegra_pmc_program_reboot_reason(const char *cmd)
1106 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1107 value &= ~PMC_SCRATCH0_MODE_MASK;
1110 if (strcmp(cmd, "recovery") == 0)
1111 value |= PMC_SCRATCH0_MODE_RECOVERY;
1113 if (strcmp(cmd, "bootloader") == 0)
1114 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1116 if (strcmp(cmd, "forced-recovery") == 0)
1117 value |= PMC_SCRATCH0_MODE_RCM;
1120 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1123 static int tegra_pmc_reboot_notify(struct notifier_block *this,
1124 unsigned long action, void *data)
1126 if (action == SYS_RESTART)
1127 tegra_pmc_program_reboot_reason(data);
1132 static struct notifier_block tegra_pmc_reboot_notifier = {
1133 .notifier_call = tegra_pmc_reboot_notify,
1136 static void tegra_pmc_restart(void)
1140 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1141 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1142 value |= PMC_CNTRL_MAIN_RST;
1143 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1146 static int tegra_pmc_restart_handler(struct sys_off_data *data)
1148 tegra_pmc_restart();
1153 static int tegra_pmc_power_off_handler(struct sys_off_data *data)
1156 * Reboot Nexus 7 into special bootloader mode if USB cable is
1157 * connected in order to display battery status and power off.
1159 if (of_machine_is_compatible("asus,grouper") &&
1160 power_supply_is_system_supplied()) {
1161 const u32 go_to_charger_mode = 0xa5a55a5a;
1163 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
1164 tegra_pmc_restart();
1170 static int powergate_show(struct seq_file *s, void *data)
1175 seq_printf(s, " powergate powered\n");
1176 seq_printf(s, "------------------\n");
1178 for (i = 0; i < pmc->soc->num_powergates; i++) {
1179 status = tegra_powergate_is_powered(pmc, i);
1183 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1184 status ? "yes" : "no");
1190 DEFINE_SHOW_ATTRIBUTE(powergate);
1192 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1193 struct device_node *np)
1196 unsigned int i, count;
1199 count = of_clk_get_parent_count(np);
1203 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1207 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1208 if (!pg->clk_rates) {
1213 for (i = 0; i < count; i++) {
1214 pg->clks[i] = of_clk_get(np, i);
1215 if (IS_ERR(pg->clks[i])) {
1216 err = PTR_ERR(pg->clks[i]);
1221 pg->num_clks = count;
1227 clk_put(pg->clks[i]);
1229 kfree(pg->clk_rates);
1235 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1236 struct device_node *np, bool off)
1238 struct device *dev = pg->pmc->dev;
1241 pg->reset = of_reset_control_array_get_exclusive_released(np);
1242 if (IS_ERR(pg->reset)) {
1243 err = PTR_ERR(pg->reset);
1244 dev_err(dev, "failed to get device resets: %d\n", err);
1248 err = reset_control_acquire(pg->reset);
1250 pr_err("failed to acquire resets: %d\n", err);
1255 err = reset_control_assert(pg->reset);
1257 err = reset_control_deassert(pg->reset);
1261 reset_control_release(pg->reset);
1266 reset_control_release(pg->reset);
1267 reset_control_put(pg->reset);
1273 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1275 struct device *dev = pmc->dev;
1276 struct tegra_powergate *pg;
1280 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1284 id = tegra_powergate_lookup(pmc, np->name);
1286 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1292 * Clear the bit for this powergate so it cannot be managed
1293 * directly via the legacy APIs for controlling powergates.
1295 clear_bit(id, pmc->powergates_available);
1298 pg->genpd.name = np->name;
1299 pg->genpd.power_off = tegra_genpd_power_off;
1300 pg->genpd.power_on = tegra_genpd_power_on;
1303 off = !tegra_powergate_is_powered(pmc, pg->id);
1305 err = tegra_powergate_of_get_clks(pg, np);
1307 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1311 err = tegra_powergate_of_get_resets(pg, np, off);
1313 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1317 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1319 WARN_ON(tegra_powergate_power_up(pg, true));
1324 err = pm_genpd_init(&pg->genpd, NULL, off);
1326 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1331 err = of_genpd_add_provider_simple(np, &pg->genpd);
1333 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1338 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1343 pm_genpd_remove(&pg->genpd);
1346 reset_control_put(pg->reset);
1349 while (pg->num_clks--)
1350 clk_put(pg->clks[pg->num_clks]);
1355 set_bit(id, pmc->powergates_available);
1363 bool tegra_pmc_core_domain_state_synced(void)
1365 return pmc->core_domain_state_synced;
1369 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1372 struct dev_pm_opp *opp;
1375 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1377 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1379 return PTR_ERR(opp);
1382 mutex_lock(&pmc->powergates_lock);
1383 err = dev_pm_opp_set_opp(pmc->dev, opp);
1384 mutex_unlock(&pmc->powergates_lock);
1386 dev_pm_opp_put(opp);
1389 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1397 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1399 struct generic_pm_domain *genpd;
1400 const char *rname[] = { "core", NULL};
1403 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1407 genpd->name = "core";
1408 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1410 err = devm_pm_opp_set_regulators(pmc->dev, rname);
1412 return dev_err_probe(pmc->dev, err,
1413 "failed to set core OPP regulator\n");
1415 err = pm_genpd_init(genpd, NULL, false);
1417 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1421 err = of_genpd_add_provider_simple(np, genpd);
1423 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1427 pmc->core_domain_registered = true;
1432 pm_genpd_remove(genpd);
1437 static int tegra_powergate_init(struct tegra_pmc *pmc,
1438 struct device_node *parent)
1440 struct of_phandle_args child_args, parent_args;
1441 struct device_node *np, *child;
1445 * Core power domain is the parent of powergate domains, hence it
1446 * should be registered first.
1448 np = of_get_child_by_name(parent, "core-domain");
1450 err = tegra_pmc_core_pd_add(pmc, np);
1456 np = of_get_child_by_name(parent, "powergates");
1460 for_each_child_of_node(np, child) {
1461 err = tegra_powergate_add(pmc, child);
1467 if (of_parse_phandle_with_args(child, "power-domains",
1468 "#power-domain-cells",
1472 child_args.np = child;
1473 child_args.args_count = 0;
1475 err = of_genpd_add_subdomain(&parent_args, &child_args);
1476 of_node_put(parent_args.np);
1488 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1490 struct tegra_powergate *pg = to_powergate(genpd);
1492 reset_control_put(pg->reset);
1494 while (pg->num_clks--)
1495 clk_put(pg->clks[pg->num_clks]);
1499 set_bit(pg->id, pmc->powergates_available);
1504 static void tegra_powergate_remove_all(struct device_node *parent)
1506 struct generic_pm_domain *genpd;
1507 struct device_node *np, *child;
1509 np = of_get_child_by_name(parent, "powergates");
1513 for_each_child_of_node(np, child) {
1514 of_genpd_del_provider(child);
1516 genpd = of_genpd_remove_last(child);
1520 tegra_powergate_remove(genpd);
1525 np = of_get_child_by_name(parent, "core-domain");
1527 of_genpd_del_provider(np);
1528 of_genpd_remove_last(np);
1532 static const struct tegra_io_pad_soc *
1533 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1537 for (i = 0; i < pmc->soc->num_io_pads; i++)
1538 if (pmc->soc->io_pads[i].id == id)
1539 return &pmc->soc->io_pads[i];
1544 static int tegra_io_pad_prepare(struct tegra_pmc *pmc,
1545 const struct tegra_io_pad_soc *pad,
1546 unsigned long *request,
1547 unsigned long *status,
1550 unsigned long rate, value;
1552 if (pad->dpd == UINT_MAX)
1555 *request = pad->request;
1556 *status = pad->status;
1557 *mask = BIT(pad->dpd);
1562 dev_err(pmc->dev, "failed to get clock rate\n");
1566 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1568 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1569 value = DIV_ROUND_UP(1000000000, rate);
1570 value = DIV_ROUND_UP(200, value);
1571 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1577 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1578 u32 mask, u32 val, unsigned long timeout)
1582 timeout = jiffies + msecs_to_jiffies(timeout);
1584 while (time_after(timeout, jiffies)) {
1585 value = tegra_pmc_readl(pmc, offset);
1586 if ((value & mask) == val)
1589 usleep_range(250, 1000);
1595 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1598 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1602 * tegra_io_pad_power_enable() - enable power to I/O pad
1603 * @id: Tegra I/O pad ID for which to enable power
1605 * Returns: 0 on success or a negative error code on failure.
1607 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1609 const struct tegra_io_pad_soc *pad;
1610 unsigned long request, status;
1614 pad = tegra_io_pad_find(pmc, id);
1616 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1620 mutex_lock(&pmc->powergates_lock);
1622 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1624 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1628 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1630 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1632 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1636 tegra_io_pad_unprepare(pmc);
1639 mutex_unlock(&pmc->powergates_lock);
1642 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1645 * tegra_io_pad_power_disable() - disable power to I/O pad
1646 * @id: Tegra I/O pad ID for which to disable power
1648 * Returns: 0 on success or a negative error code on failure.
1650 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1652 const struct tegra_io_pad_soc *pad;
1653 unsigned long request, status;
1657 pad = tegra_io_pad_find(pmc, id);
1659 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1663 mutex_lock(&pmc->powergates_lock);
1665 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1667 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1671 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1673 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1675 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1679 tegra_io_pad_unprepare(pmc);
1682 mutex_unlock(&pmc->powergates_lock);
1685 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1687 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1689 const struct tegra_io_pad_soc *pad;
1690 unsigned long status;
1693 pad = tegra_io_pad_find(pmc, id);
1695 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1699 if (pad->dpd == UINT_MAX)
1702 status = pad->status;
1703 mask = BIT(pad->dpd);
1705 value = tegra_pmc_readl(pmc, status);
1707 return !(value & mask);
1710 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1713 const struct tegra_io_pad_soc *pad;
1716 pad = tegra_io_pad_find(pmc, id);
1720 if (pad->voltage == UINT_MAX)
1723 mutex_lock(&pmc->powergates_lock);
1725 if (pmc->soc->has_impl_33v_pwr) {
1726 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1728 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1729 value &= ~BIT(pad->voltage);
1731 value |= BIT(pad->voltage);
1733 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1735 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1736 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1737 value |= BIT(pad->voltage);
1738 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1740 /* update I/O voltage */
1741 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1743 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1744 value &= ~BIT(pad->voltage);
1746 value |= BIT(pad->voltage);
1748 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1751 mutex_unlock(&pmc->powergates_lock);
1753 usleep_range(100, 250);
1758 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1760 const struct tegra_io_pad_soc *pad;
1763 pad = tegra_io_pad_find(pmc, id);
1767 if (pad->voltage == UINT_MAX)
1770 if (pmc->soc->has_impl_33v_pwr)
1771 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1773 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1775 if ((value & BIT(pad->voltage)) == 0)
1776 return TEGRA_IO_PAD_VOLTAGE_1V8;
1778 return TEGRA_IO_PAD_VOLTAGE_3V3;
1781 #ifdef CONFIG_PM_SLEEP
1782 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1784 return pmc->suspend_mode;
1787 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1789 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1792 pmc->suspend_mode = mode;
1795 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1797 unsigned long long rate = 0;
1802 case TEGRA_SUSPEND_LP1:
1806 case TEGRA_SUSPEND_LP2:
1814 if (WARN_ON_ONCE(rate == 0))
1817 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1818 do_div(ticks, USEC_PER_SEC);
1819 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1821 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1822 do_div(ticks, USEC_PER_SEC);
1823 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1825 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1826 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1827 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1828 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1832 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1834 u32 value, values[2];
1836 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1837 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1841 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1845 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1849 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1853 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1858 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1860 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1861 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1863 pmc->cpu_good_time = value;
1865 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1866 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1868 pmc->cpu_off_time = value;
1870 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1871 values, ARRAY_SIZE(values)))
1872 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1874 pmc->core_osc_time = values[0];
1875 pmc->core_pmu_time = values[1];
1877 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1878 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1880 pmc->core_off_time = value;
1882 pmc->corereq_high = of_property_read_bool(np,
1883 "nvidia,core-power-req-active-high");
1885 pmc->sysclkreq_high = of_property_read_bool(np,
1886 "nvidia,sys-clock-req-active-high");
1888 pmc->combined_req = of_property_read_bool(np,
1889 "nvidia,combined-power-req");
1891 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1892 "nvidia,cpu-pwr-good-en");
1894 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1895 ARRAY_SIZE(values)))
1896 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1897 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1899 pmc->lp0_vec_phys = values[0];
1900 pmc->lp0_vec_size = values[1];
1905 static int tegra_pmc_init(struct tegra_pmc *pmc)
1907 if (pmc->soc->max_wake_events > 0) {
1908 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1909 if (!pmc->wake_type_level_map)
1912 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1913 if (!pmc->wake_type_dual_edge_map)
1916 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1917 if (!pmc->wake_sw_status_map)
1920 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1921 if (!pmc->wake_cntrl_level_map)
1926 pmc->soc->init(pmc);
1931 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1933 static const char disabled[] = "emergency thermal reset disabled";
1934 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1935 struct device *dev = pmc->dev;
1936 struct device_node *np;
1937 u32 value, checksum;
1939 if (!pmc->soc->has_tsense_reset)
1942 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1944 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1948 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1949 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1953 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1954 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1958 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1959 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1963 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1964 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1968 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1971 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1972 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1973 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1975 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1976 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1977 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1979 value = PMC_SCRATCH55_RESET_TEGRA;
1980 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1981 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1982 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1985 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1986 * contain the checksum and are currently zero, so they are not added.
1988 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1989 + ((value >> 24) & 0xff);
1991 checksum = 0x100 - checksum;
1993 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1995 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1997 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1998 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1999 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2001 dev_info(pmc->dev, "emergency thermal reset enabled\n");
2007 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
2009 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2011 return pmc->soc->num_io_pads;
2014 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
2017 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
2019 return pmc->soc->io_pads[group].name;
2022 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
2024 const unsigned int **pins,
2025 unsigned int *num_pins)
2027 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2029 *pins = &pmc->soc->io_pads[group].id;
2035 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
2036 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
2037 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
2038 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
2039 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
2040 .dt_free_map = pinconf_generic_dt_free_map,
2043 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2044 unsigned int pin, unsigned long *config)
2046 enum pin_config_param param = pinconf_to_config_param(*config);
2047 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2048 const struct tegra_io_pad_soc *pad;
2052 pad = tegra_io_pad_find(pmc, pin);
2057 case PIN_CONFIG_POWER_SOURCE:
2058 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2065 case PIN_CONFIG_MODE_LOW_POWER:
2066 ret = tegra_io_pad_is_powered(pmc, pad->id);
2077 *config = pinconf_to_config_packed(param, arg);
2082 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2083 unsigned int pin, unsigned long *configs,
2084 unsigned int num_configs)
2086 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2087 const struct tegra_io_pad_soc *pad;
2088 enum pin_config_param param;
2093 pad = tegra_io_pad_find(pmc, pin);
2097 for (i = 0; i < num_configs; ++i) {
2098 param = pinconf_to_config_param(configs[i]);
2099 arg = pinconf_to_config_argument(configs[i]);
2102 case PIN_CONFIG_MODE_LOW_POWER:
2104 err = tegra_io_pad_power_disable(pad->id);
2106 err = tegra_io_pad_power_enable(pad->id);
2110 case PIN_CONFIG_POWER_SOURCE:
2111 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2112 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2114 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2126 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2127 .pin_config_get = tegra_io_pad_pinconf_get,
2128 .pin_config_set = tegra_io_pad_pinconf_set,
2132 static struct pinctrl_desc tegra_pmc_pctl_desc = {
2133 .pctlops = &tegra_io_pad_pinctrl_ops,
2134 .confops = &tegra_io_pad_pinconf_ops,
2137 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2141 if (!pmc->soc->num_pin_descs)
2144 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2145 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2146 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2148 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2150 if (IS_ERR(pmc->pctl_dev)) {
2151 err = PTR_ERR(pmc->pctl_dev);
2152 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2160 static ssize_t reset_reason_show(struct device *dev,
2161 struct device_attribute *attr, char *buf)
2165 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2166 value &= pmc->soc->regs->rst_source_mask;
2167 value >>= pmc->soc->regs->rst_source_shift;
2169 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2170 return sprintf(buf, "%s\n", "UNKNOWN");
2172 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2175 static DEVICE_ATTR_RO(reset_reason);
2177 static ssize_t reset_level_show(struct device *dev,
2178 struct device_attribute *attr, char *buf)
2182 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2183 value &= pmc->soc->regs->rst_level_mask;
2184 value >>= pmc->soc->regs->rst_level_shift;
2186 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2187 return sprintf(buf, "%s\n", "UNKNOWN");
2189 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2192 static DEVICE_ATTR_RO(reset_level);
2194 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2196 struct device *dev = pmc->dev;
2199 if (pmc->soc->reset_sources) {
2200 err = device_create_file(dev, &dev_attr_reset_reason);
2203 "failed to create attr \"reset_reason\": %d\n",
2207 if (pmc->soc->reset_levels) {
2208 err = device_create_file(dev, &dev_attr_reset_level);
2211 "failed to create attr \"reset_level\": %d\n",
2216 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2217 struct irq_fwspec *fwspec,
2218 unsigned long *hwirq,
2221 if (WARN_ON(fwspec->param_count < 2))
2224 *hwirq = fwspec->param[0];
2225 *type = fwspec->param[1];
2230 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2231 unsigned int num_irqs, void *data)
2233 struct tegra_pmc *pmc = domain->host_data;
2234 const struct tegra_pmc_soc *soc = pmc->soc;
2235 struct irq_fwspec *fwspec = data;
2239 if (WARN_ON(num_irqs > 1))
2242 for (i = 0; i < soc->num_wake_events; i++) {
2243 const struct tegra_wake_event *event = &soc->wake_events[i];
2245 /* IRQ and simple wake events */
2246 if (fwspec->param_count == 2) {
2247 struct irq_fwspec spec;
2249 if (event->id != fwspec->param[0])
2252 err = irq_domain_set_hwirq_and_chip(domain, virq,
2258 /* simple hierarchies stop at the PMC level */
2259 if (event->irq == 0) {
2260 err = irq_domain_disconnect_hierarchy(domain->parent, virq);
2264 spec.fwnode = &pmc->dev->of_node->fwnode;
2265 spec.param_count = 3;
2266 spec.param[0] = GIC_SPI;
2267 spec.param[1] = event->irq;
2268 spec.param[2] = fwspec->param[1];
2270 err = irq_domain_alloc_irqs_parent(domain, virq,
2276 /* GPIO wake events */
2277 if (fwspec->param_count == 3) {
2278 if (event->gpio.instance != fwspec->param[0] ||
2279 event->gpio.pin != fwspec->param[1])
2282 err = irq_domain_set_hwirq_and_chip(domain, virq,
2286 /* GPIO hierarchies stop at the PMC level */
2287 if (!err && domain->parent)
2288 err = irq_domain_disconnect_hierarchy(domain->parent,
2294 /* If there is no wake-up event, there is no PMC mapping */
2295 if (i == soc->num_wake_events)
2296 err = irq_domain_disconnect_hierarchy(domain, virq);
2301 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2302 .translate = tegra_pmc_irq_translate,
2303 .alloc = tegra_pmc_irq_alloc,
2306 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2308 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2309 unsigned int offset, bit;
2312 offset = data->hwirq / 32;
2313 bit = data->hwirq % 32;
2315 /* clear wake status */
2316 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2317 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2319 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2320 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2322 /* enable PMC wake */
2323 if (data->hwirq >= 32)
2324 offset = PMC_WAKE2_MASK;
2326 offset = PMC_WAKE_MASK;
2328 value = tegra_pmc_readl(pmc, offset);
2335 tegra_pmc_writel(pmc, value, offset);
2340 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2342 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2343 unsigned int offset, bit;
2346 offset = data->hwirq / 32;
2347 bit = data->hwirq % 32;
2349 if (data->hwirq >= 32)
2350 offset = PMC_WAKE2_LEVEL;
2352 offset = PMC_WAKE_LEVEL;
2354 value = tegra_pmc_readl(pmc, offset);
2357 case IRQ_TYPE_EDGE_RISING:
2358 case IRQ_TYPE_LEVEL_HIGH:
2362 case IRQ_TYPE_EDGE_FALLING:
2363 case IRQ_TYPE_LEVEL_LOW:
2367 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2375 tegra_pmc_writel(pmc, value, offset);
2380 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc)
2384 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */
2385 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2386 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN;
2387 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2388 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value);
2391 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2393 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2394 unsigned int offset, bit;
2397 offset = data->hwirq / 32;
2398 bit = data->hwirq % 32;
2400 /* clear wake status */
2401 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2403 /* route wake to tier 2 */
2404 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2407 value &= ~(1 << bit);
2411 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2413 /* enable wakeup event */
2414 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2419 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2421 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2424 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2427 case IRQ_TYPE_EDGE_RISING:
2428 case IRQ_TYPE_LEVEL_HIGH:
2429 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2430 set_bit(data->hwirq, pmc->wake_type_level_map);
2431 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2434 case IRQ_TYPE_EDGE_FALLING:
2435 case IRQ_TYPE_LEVEL_LOW:
2436 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2437 clear_bit(data->hwirq, pmc->wake_type_level_map);
2438 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2441 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2442 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2443 clear_bit(data->hwirq, pmc->wake_type_level_map);
2444 set_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2451 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2456 static void tegra_irq_mask_parent(struct irq_data *data)
2458 if (data->parent_data)
2459 irq_chip_mask_parent(data);
2462 static void tegra_irq_unmask_parent(struct irq_data *data)
2464 if (data->parent_data)
2465 irq_chip_unmask_parent(data);
2468 static void tegra_irq_eoi_parent(struct irq_data *data)
2470 if (data->parent_data)
2471 irq_chip_eoi_parent(data);
2474 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2475 const struct cpumask *dest,
2478 if (data->parent_data)
2479 return irq_chip_set_affinity_parent(data, dest, force);
2484 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2486 struct irq_domain *parent = NULL;
2487 struct device_node *np;
2489 np = of_irq_find_parent(pmc->dev->of_node);
2491 parent = irq_find_host(np);
2498 pmc->irq.name = dev_name(pmc->dev);
2499 pmc->irq.irq_mask = tegra_irq_mask_parent;
2500 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2501 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2502 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2503 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2504 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2506 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2507 &tegra_pmc_irq_domain_ops, pmc);
2509 dev_err(pmc->dev, "failed to allocate domain\n");
2516 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2517 unsigned long action, void *ptr)
2519 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2520 struct clk_notifier_data *data = ptr;
2523 case PRE_RATE_CHANGE:
2524 mutex_lock(&pmc->powergates_lock);
2527 case POST_RATE_CHANGE:
2528 pmc->rate = data->new_rate;
2531 case ABORT_RATE_CHANGE:
2532 mutex_unlock(&pmc->powergates_lock);
2537 return notifier_from_errno(-EINVAL);
2543 static void pmc_clk_fence_udelay(u32 offset)
2545 tegra_pmc_readl(pmc, offset);
2546 /* pmc clk propagation delay 2 us */
2550 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2552 struct pmc_clk *clk = to_pmc_clk(hw);
2555 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2556 val &= PMC_CLK_OUT_MUX_MASK;
2561 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2563 struct pmc_clk *clk = to_pmc_clk(hw);
2566 val = tegra_pmc_readl(pmc, clk->offs);
2567 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2568 val |= index << clk->mux_shift;
2569 tegra_pmc_writel(pmc, val, clk->offs);
2570 pmc_clk_fence_udelay(clk->offs);
2575 static int pmc_clk_is_enabled(struct clk_hw *hw)
2577 struct pmc_clk *clk = to_pmc_clk(hw);
2580 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2585 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2589 val = tegra_pmc_readl(pmc, offs);
2590 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2591 tegra_pmc_writel(pmc, val, offs);
2592 pmc_clk_fence_udelay(offs);
2595 static int pmc_clk_enable(struct clk_hw *hw)
2597 struct pmc_clk *clk = to_pmc_clk(hw);
2599 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2604 static void pmc_clk_disable(struct clk_hw *hw)
2606 struct pmc_clk *clk = to_pmc_clk(hw);
2608 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2611 static const struct clk_ops pmc_clk_ops = {
2612 .get_parent = pmc_clk_mux_get_parent,
2613 .set_parent = pmc_clk_mux_set_parent,
2614 .determine_rate = __clk_mux_determine_rate,
2615 .is_enabled = pmc_clk_is_enabled,
2616 .enable = pmc_clk_enable,
2617 .disable = pmc_clk_disable,
2621 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2622 const struct pmc_clk_init_data *data,
2623 unsigned long offset)
2625 struct clk_init_data init;
2626 struct pmc_clk *pmc_clk;
2628 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2630 return ERR_PTR(-ENOMEM);
2632 init.name = data->name;
2633 init.ops = &pmc_clk_ops;
2634 init.parent_names = data->parents;
2635 init.num_parents = data->num_parents;
2636 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2637 CLK_SET_PARENT_GATE;
2639 pmc_clk->hw.init = &init;
2640 pmc_clk->offs = offset;
2641 pmc_clk->mux_shift = data->mux_shift;
2642 pmc_clk->force_en_shift = data->force_en_shift;
2644 return clk_register(NULL, &pmc_clk->hw);
2647 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2649 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2651 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2654 static int pmc_clk_gate_enable(struct clk_hw *hw)
2656 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2658 pmc_clk_set_state(gate->offs, gate->shift, 1);
2663 static void pmc_clk_gate_disable(struct clk_hw *hw)
2665 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2667 pmc_clk_set_state(gate->offs, gate->shift, 0);
2670 static const struct clk_ops pmc_clk_gate_ops = {
2671 .is_enabled = pmc_clk_gate_is_enabled,
2672 .enable = pmc_clk_gate_enable,
2673 .disable = pmc_clk_gate_disable,
2677 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2678 const char *parent_name, unsigned long offset,
2681 struct clk_init_data init;
2682 struct pmc_clk_gate *gate;
2684 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2686 return ERR_PTR(-ENOMEM);
2689 init.ops = &pmc_clk_gate_ops;
2690 init.parent_names = &parent_name;
2691 init.num_parents = 1;
2694 gate->hw.init = &init;
2695 gate->offs = offset;
2696 gate->shift = shift;
2698 return clk_register(NULL, &gate->hw);
2701 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2702 struct device_node *np)
2705 struct clk_onecell_data *clk_data;
2706 unsigned int num_clks;
2709 num_clks = pmc->soc->num_pmc_clks;
2710 if (pmc->soc->has_blink_output)
2716 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2720 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2721 sizeof(*clk_data->clks), GFP_KERNEL);
2722 if (!clk_data->clks)
2725 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2727 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2728 clk_data->clks[i] = ERR_PTR(-ENOENT);
2730 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2731 const struct pmc_clk_init_data *data;
2733 data = pmc->soc->pmc_clks_data + i;
2735 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2737 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2738 data->name, PTR_ERR_OR_ZERO(clk));
2742 err = clk_register_clkdev(clk, data->name, NULL);
2745 "unable to register %s clock lookup: %d\n",
2750 clk_data->clks[data->clk_id] = clk;
2753 if (pmc->soc->has_blink_output) {
2754 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2755 clk = tegra_pmc_clk_gate_register(pmc,
2756 "pmc_blink_override",
2759 PMC_DPD_PADS_ORIDE_BLINK);
2762 "unable to register pmc_blink_override: %d\n",
2763 PTR_ERR_OR_ZERO(clk));
2767 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2768 "pmc_blink_override",
2770 PMC_CNTRL_BLINK_EN);
2773 "unable to register pmc_blink: %d\n",
2774 PTR_ERR_OR_ZERO(clk));
2778 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2781 "unable to register pmc_blink lookup: %d\n",
2786 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2789 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2791 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2795 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2796 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2797 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2798 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2799 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2800 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2801 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2802 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2803 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2806 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2807 .yes_ranges = pmc_usb_sleepwalk_ranges,
2808 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2811 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2813 struct tegra_pmc *pmc = context;
2815 *value = tegra_pmc_readl(pmc, offset);
2819 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2821 struct tegra_pmc *pmc = context;
2823 tegra_pmc_writel(pmc, value, offset);
2827 static const struct regmap_config usb_sleepwalk_regmap_config = {
2828 .name = "usb_sleepwalk",
2833 .rd_table = &pmc_usb_sleepwalk_table,
2834 .wr_table = &pmc_usb_sleepwalk_table,
2835 .reg_read = tegra_pmc_regmap_readl,
2836 .reg_write = tegra_pmc_regmap_writel,
2839 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2841 struct regmap *regmap;
2844 if (pmc->soc->has_usb_sleepwalk) {
2845 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2846 if (IS_ERR(regmap)) {
2847 err = PTR_ERR(regmap);
2848 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2856 static void tegra_pmc_reset_suspend_mode(void *data)
2858 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2861 static int tegra_pmc_probe(struct platform_device *pdev)
2864 struct resource *res;
2868 * Early initialisation should have configured an initial
2869 * register mapping and setup the soc data pointer. If these
2870 * are not valid then something went badly wrong!
2872 if (WARN_ON(!pmc->base || !pmc->soc))
2875 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2879 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2884 /* take over the memory region from the early initialization */
2885 base = devm_platform_ioremap_resource(pdev, 0);
2887 return PTR_ERR(base);
2889 if (pmc->soc->has_single_mmio_aperture) {
2892 pmc->scratch = base;
2894 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2896 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2897 if (IS_ERR(pmc->wake))
2898 return PTR_ERR(pmc->wake);
2900 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2902 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2903 if (IS_ERR(pmc->aotag))
2904 return PTR_ERR(pmc->aotag);
2906 /* "scratch" is an optional aperture */
2907 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2910 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2911 if (IS_ERR(pmc->scratch))
2912 return PTR_ERR(pmc->scratch);
2914 pmc->scratch = NULL;
2918 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");
2919 if (IS_ERR(pmc->clk))
2920 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),
2921 "failed to get pclk\n");
2924 * PMC should be last resort for restarting since it soft-resets
2925 * CPU without resetting everything else.
2928 err = devm_register_reboot_notifier(&pdev->dev,
2929 &tegra_pmc_reboot_notifier);
2932 "unable to register reboot notifier, %d\n",
2938 err = devm_register_sys_off_handler(&pdev->dev,
2939 SYS_OFF_MODE_RESTART,
2941 tegra_pmc_restart_handler, NULL);
2943 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2949 * PMC should be primary power-off method if it soft-resets CPU,
2950 * asking bootloader to shutdown hardware.
2952 err = devm_register_sys_off_handler(&pdev->dev,
2953 SYS_OFF_MODE_POWER_OFF,
2954 SYS_OFF_PRIO_FIRMWARE,
2955 tegra_pmc_power_off_handler, NULL);
2957 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2963 * PCLK clock rate can't be retrieved using CLK API because it
2964 * causes lockup if CPU enters LP2 idle state from some other
2965 * CLK notifier, hence we're caching the rate's value locally.
2968 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2969 err = devm_clk_notifier_register(&pdev->dev, pmc->clk,
2973 "failed to register clk notifier\n");
2977 pmc->rate = clk_get_rate(pmc->clk);
2980 pmc->dev = &pdev->dev;
2982 err = tegra_pmc_init(pmc);
2984 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err);
2988 tegra_pmc_init_tsense_reset(pmc);
2990 tegra_pmc_reset_sysfs_init(pmc);
2992 err = tegra_pmc_pinctrl_init(pmc);
2996 err = tegra_pmc_regmap_init(pmc);
3000 err = tegra_powergate_init(pmc, pdev->dev.of_node);
3002 goto cleanup_powergates;
3004 err = tegra_pmc_irq_init(pmc);
3006 goto cleanup_powergates;
3008 mutex_lock(&pmc->powergates_lock);
3011 mutex_unlock(&pmc->powergates_lock);
3013 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
3014 platform_set_drvdata(pdev, pmc);
3015 tegra_pm_init_suspend();
3017 /* Some wakes require specific filter configuration */
3018 if (pmc->soc->set_wake_filters)
3019 pmc->soc->set_wake_filters(pmc);
3021 debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops);
3026 tegra_powergate_remove_all(pdev->dev.of_node);
3028 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
3029 device_remove_file(&pdev->dev, &dev_attr_reset_level);
3035 * Ensures that sufficient time is passed for a register write to
3036 * serialize into the 32KHz domain.
3038 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)
3040 writel(value, pmc->wake + offset);
3044 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)
3046 unsigned int offset = WAKE_AOWAKE_CNTRL(wake);
3049 value = readl(pmc->wake + offset);
3051 value |= WAKE_AOWAKE_CNTRL_LEVEL;
3053 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
3055 writel(value, pmc->wake + offset);
3058 static void wke_write_wake_levels(struct tegra_pmc *pmc)
3062 for (i = 0; i < pmc->soc->max_wake_events; i++)
3063 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));
3066 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)
3068 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);
3071 static void wke_read_sw_wake_status(struct tegra_pmc *pmc)
3073 unsigned long status;
3074 unsigned int wake, i;
3076 for (i = 0; i < pmc->soc->max_wake_events; i++)
3077 wke_write_wake_level(pmc, i, 0);
3079 wke_clear_sw_wake_status(pmc);
3081 wke_32kwritel(pmc, 1, WAKE_LATCH_SW);
3084 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to
3085 * obtain the current status of the input wake signals, change
3086 * the polarity of the wake level from 0->1 while latching to force
3087 * a positive edge if the sampled signal is '1'.
3089 for (i = 0; i < pmc->soc->max_wake_events; i++)
3090 wke_write_wake_level(pmc, i, 1);
3093 * Wait for the update to be synced into the 32kHz domain,
3094 * and let enough time lapse, so that the wake signals have time to
3099 wke_32kwritel(pmc, 0, WAKE_LATCH_SW);
3101 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3103 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3104 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));
3106 for_each_set_bit(wake, &status, 32)
3107 set_bit(wake + (i * 32), pmc->wake_sw_status_map);
3111 static void wke_clear_wake_status(struct tegra_pmc *pmc)
3113 unsigned long status;
3114 unsigned int i, wake;
3117 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3118 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3119 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3121 for_each_set_bit(wake, &status, 32)
3122 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));
3126 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */
3127 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
3128 unsigned long status)
3132 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status);
3134 for_each_set_bit(wake, &status, 32) {
3135 irq_hw_number_t hwirq = wake + 32 * index;
3136 struct irq_desc *desc;
3139 irq = irq_find_mapping(pmc->domain, hwirq);
3141 desc = irq_to_desc(irq);
3142 if (!desc || !desc->action || !desc->action->name) {
3143 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
3147 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
3148 generic_handle_irq(irq);
3152 static void tegra186_pmc_wake_syscore_resume(void)
3157 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3158 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3159 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3161 tegra186_pmc_process_wake_events(pmc, i, status);
3165 static int tegra186_pmc_wake_syscore_suspend(void)
3167 wke_read_sw_wake_status(pmc);
3169 /* flip the wakeup trigger for dual-edge triggered pads
3170 * which are currently asserting as wakeups
3172 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,
3173 pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3174 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,
3175 pmc->wake_type_level_map, pmc->soc->max_wake_events);
3177 /* Clear PMC Wake Status registers while going to suspend */
3178 wke_clear_wake_status(pmc);
3179 wke_write_wake_levels(pmc);
3184 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3185 static int tegra_pmc_suspend(struct device *dev)
3187 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3189 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
3194 static int tegra_pmc_resume(struct device *dev)
3196 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3198 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
3203 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
3207 static const char * const tegra20_powergates[] = {
3208 [TEGRA_POWERGATE_CPU] = "cpu",
3209 [TEGRA_POWERGATE_3D] = "td",
3210 [TEGRA_POWERGATE_VENC] = "venc",
3211 [TEGRA_POWERGATE_VDEC] = "vdec",
3212 [TEGRA_POWERGATE_PCIE] = "pcie",
3213 [TEGRA_POWERGATE_L2] = "l2",
3214 [TEGRA_POWERGATE_MPE] = "mpe",
3217 static const struct tegra_pmc_regs tegra20_pmc_regs = {
3219 .rst_status = 0x1b4,
3220 .rst_source_shift = 0x0,
3221 .rst_source_mask = 0x7,
3222 .rst_level_shift = 0x0,
3223 .rst_level_mask = 0x0,
3226 static void tegra20_pmc_init(struct tegra_pmc *pmc)
3228 u32 value, osc, pmu, off;
3230 /* Always enable CPU power request */
3231 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3232 value |= PMC_CNTRL_CPU_PWRREQ_OE;
3233 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3235 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3237 if (pmc->sysclkreq_high)
3238 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3240 value |= PMC_CNTRL_SYSCLK_POLARITY;
3242 if (pmc->corereq_high)
3243 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3245 value |= PMC_CNTRL_PWRREQ_POLARITY;
3247 /* configure the output polarity while the request is tristated */
3248 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3250 /* now enable the request */
3251 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3252 value |= PMC_CNTRL_SYSCLK_OE;
3253 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3255 /* program core timings which are applicable only for suspend state */
3256 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3257 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3258 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3259 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3260 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3261 PMC_COREPWRGOOD_TIMER);
3262 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3266 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3267 struct device_node *np,
3272 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3275 value |= PMC_CNTRL_INTR_POLARITY;
3277 value &= ~PMC_CNTRL_INTR_POLARITY;
3279 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3282 static const struct tegra_pmc_soc tegra20_pmc_soc = {
3283 .supports_core_domain = true,
3284 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3285 .powergates = tegra20_powergates,
3286 .num_cpu_powergates = 0,
3287 .cpu_powergates = NULL,
3288 .has_tsense_reset = false,
3289 .has_gpu_clamps = false,
3290 .needs_mbist_war = false,
3291 .has_impl_33v_pwr = false,
3292 .maybe_tz_only = false,
3297 .regs = &tegra20_pmc_regs,
3298 .init = tegra20_pmc_init,
3299 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3300 .powergate_set = tegra20_powergate_set,
3301 .reset_sources = NULL,
3302 .num_reset_sources = 0,
3303 .reset_levels = NULL,
3304 .num_reset_levels = 0,
3305 .pmc_clks_data = NULL,
3307 .has_blink_output = true,
3308 .has_usb_sleepwalk = true,
3309 .has_single_mmio_aperture = true,
3312 static const char * const tegra30_powergates[] = {
3313 [TEGRA_POWERGATE_CPU] = "cpu0",
3314 [TEGRA_POWERGATE_3D] = "td",
3315 [TEGRA_POWERGATE_VENC] = "venc",
3316 [TEGRA_POWERGATE_VDEC] = "vdec",
3317 [TEGRA_POWERGATE_PCIE] = "pcie",
3318 [TEGRA_POWERGATE_L2] = "l2",
3319 [TEGRA_POWERGATE_MPE] = "mpe",
3320 [TEGRA_POWERGATE_HEG] = "heg",
3321 [TEGRA_POWERGATE_SATA] = "sata",
3322 [TEGRA_POWERGATE_CPU1] = "cpu1",
3323 [TEGRA_POWERGATE_CPU2] = "cpu2",
3324 [TEGRA_POWERGATE_CPU3] = "cpu3",
3325 [TEGRA_POWERGATE_CELP] = "celp",
3326 [TEGRA_POWERGATE_3D1] = "td2",
3329 static const u8 tegra30_cpu_powergates[] = {
3330 TEGRA_POWERGATE_CPU,
3331 TEGRA_POWERGATE_CPU1,
3332 TEGRA_POWERGATE_CPU2,
3333 TEGRA_POWERGATE_CPU3,
3336 static const char * const tegra30_reset_sources[] = {
3344 static const struct tegra_pmc_soc tegra30_pmc_soc = {
3345 .supports_core_domain = true,
3346 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3347 .powergates = tegra30_powergates,
3348 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3349 .cpu_powergates = tegra30_cpu_powergates,
3350 .has_tsense_reset = true,
3351 .has_gpu_clamps = false,
3352 .needs_mbist_war = false,
3353 .has_impl_33v_pwr = false,
3354 .maybe_tz_only = false,
3359 .regs = &tegra20_pmc_regs,
3360 .init = tegra20_pmc_init,
3361 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3362 .powergate_set = tegra20_powergate_set,
3363 .reset_sources = tegra30_reset_sources,
3364 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3365 .reset_levels = NULL,
3366 .num_reset_levels = 0,
3367 .pmc_clks_data = tegra_pmc_clks_data,
3368 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3369 .has_blink_output = true,
3370 .has_usb_sleepwalk = true,
3371 .has_single_mmio_aperture = true,
3374 static const char * const tegra114_powergates[] = {
3375 [TEGRA_POWERGATE_CPU] = "crail",
3376 [TEGRA_POWERGATE_3D] = "td",
3377 [TEGRA_POWERGATE_VENC] = "venc",
3378 [TEGRA_POWERGATE_VDEC] = "vdec",
3379 [TEGRA_POWERGATE_MPE] = "mpe",
3380 [TEGRA_POWERGATE_HEG] = "heg",
3381 [TEGRA_POWERGATE_CPU1] = "cpu1",
3382 [TEGRA_POWERGATE_CPU2] = "cpu2",
3383 [TEGRA_POWERGATE_CPU3] = "cpu3",
3384 [TEGRA_POWERGATE_CELP] = "celp",
3385 [TEGRA_POWERGATE_CPU0] = "cpu0",
3386 [TEGRA_POWERGATE_C0NC] = "c0nc",
3387 [TEGRA_POWERGATE_C1NC] = "c1nc",
3388 [TEGRA_POWERGATE_DIS] = "dis",
3389 [TEGRA_POWERGATE_DISB] = "disb",
3390 [TEGRA_POWERGATE_XUSBA] = "xusba",
3391 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3392 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3395 static const u8 tegra114_cpu_powergates[] = {
3396 TEGRA_POWERGATE_CPU0,
3397 TEGRA_POWERGATE_CPU1,
3398 TEGRA_POWERGATE_CPU2,
3399 TEGRA_POWERGATE_CPU3,
3402 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3403 .supports_core_domain = false,
3404 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3405 .powergates = tegra114_powergates,
3406 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3407 .cpu_powergates = tegra114_cpu_powergates,
3408 .has_tsense_reset = true,
3409 .has_gpu_clamps = false,
3410 .needs_mbist_war = false,
3411 .has_impl_33v_pwr = false,
3412 .maybe_tz_only = false,
3417 .regs = &tegra20_pmc_regs,
3418 .init = tegra20_pmc_init,
3419 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3420 .powergate_set = tegra114_powergate_set,
3421 .reset_sources = tegra30_reset_sources,
3422 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3423 .reset_levels = NULL,
3424 .num_reset_levels = 0,
3425 .pmc_clks_data = tegra_pmc_clks_data,
3426 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3427 .has_blink_output = true,
3428 .has_usb_sleepwalk = true,
3429 .has_single_mmio_aperture = true,
3432 static const char * const tegra124_powergates[] = {
3433 [TEGRA_POWERGATE_CPU] = "crail",
3434 [TEGRA_POWERGATE_3D] = "3d",
3435 [TEGRA_POWERGATE_VENC] = "venc",
3436 [TEGRA_POWERGATE_PCIE] = "pcie",
3437 [TEGRA_POWERGATE_VDEC] = "vdec",
3438 [TEGRA_POWERGATE_MPE] = "mpe",
3439 [TEGRA_POWERGATE_HEG] = "heg",
3440 [TEGRA_POWERGATE_SATA] = "sata",
3441 [TEGRA_POWERGATE_CPU1] = "cpu1",
3442 [TEGRA_POWERGATE_CPU2] = "cpu2",
3443 [TEGRA_POWERGATE_CPU3] = "cpu3",
3444 [TEGRA_POWERGATE_CELP] = "celp",
3445 [TEGRA_POWERGATE_CPU0] = "cpu0",
3446 [TEGRA_POWERGATE_C0NC] = "c0nc",
3447 [TEGRA_POWERGATE_C1NC] = "c1nc",
3448 [TEGRA_POWERGATE_SOR] = "sor",
3449 [TEGRA_POWERGATE_DIS] = "dis",
3450 [TEGRA_POWERGATE_DISB] = "disb",
3451 [TEGRA_POWERGATE_XUSBA] = "xusba",
3452 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3453 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3454 [TEGRA_POWERGATE_VIC] = "vic",
3455 [TEGRA_POWERGATE_IRAM] = "iram",
3458 static const u8 tegra124_cpu_powergates[] = {
3459 TEGRA_POWERGATE_CPU0,
3460 TEGRA_POWERGATE_CPU1,
3461 TEGRA_POWERGATE_CPU2,
3462 TEGRA_POWERGATE_CPU3,
3465 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \
3466 ((struct tegra_io_pad_soc) { \
3469 .request = (_request), \
3470 .status = (_status), \
3471 .voltage = (_voltage), \
3475 #define TEGRA_IO_PIN_DESC(_id, _name) \
3476 ((struct pinctrl_pin_desc) { \
3481 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3482 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"),
3483 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"),
3484 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"),
3485 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"),
3486 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3487 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3488 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3489 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3490 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3491 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3492 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3493 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3494 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3495 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),
3496 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3497 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3498 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"),
3499 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3500 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3501 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3502 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),
3503 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"),
3504 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),
3505 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"),
3506 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"),
3507 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"),
3508 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3509 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3510 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3511 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"),
3514 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3515 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3516 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"),
3517 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3518 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"),
3519 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3520 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3521 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3522 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3523 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3524 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3525 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3527 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3528 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),
3529 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3530 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3531 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"),
3532 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3533 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3534 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3535 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3536 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3537 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3538 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3539 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"),
3540 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3541 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3542 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3543 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3544 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"),
3547 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3548 .supports_core_domain = false,
3549 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3550 .powergates = tegra124_powergates,
3551 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3552 .cpu_powergates = tegra124_cpu_powergates,
3553 .has_tsense_reset = true,
3554 .has_gpu_clamps = true,
3555 .needs_mbist_war = false,
3556 .has_impl_33v_pwr = false,
3557 .maybe_tz_only = false,
3558 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3559 .io_pads = tegra124_io_pads,
3560 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3561 .pin_descs = tegra124_pin_descs,
3562 .regs = &tegra20_pmc_regs,
3563 .init = tegra20_pmc_init,
3564 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3565 .powergate_set = tegra114_powergate_set,
3566 .reset_sources = tegra30_reset_sources,
3567 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3568 .reset_levels = NULL,
3569 .num_reset_levels = 0,
3570 .pmc_clks_data = tegra_pmc_clks_data,
3571 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3572 .has_blink_output = true,
3573 .has_usb_sleepwalk = true,
3574 .has_single_mmio_aperture = true,
3577 static const char * const tegra210_powergates[] = {
3578 [TEGRA_POWERGATE_CPU] = "crail",
3579 [TEGRA_POWERGATE_3D] = "3d",
3580 [TEGRA_POWERGATE_VENC] = "venc",
3581 [TEGRA_POWERGATE_PCIE] = "pcie",
3582 [TEGRA_POWERGATE_MPE] = "mpe",
3583 [TEGRA_POWERGATE_SATA] = "sata",
3584 [TEGRA_POWERGATE_CPU1] = "cpu1",
3585 [TEGRA_POWERGATE_CPU2] = "cpu2",
3586 [TEGRA_POWERGATE_CPU3] = "cpu3",
3587 [TEGRA_POWERGATE_CPU0] = "cpu0",
3588 [TEGRA_POWERGATE_C0NC] = "c0nc",
3589 [TEGRA_POWERGATE_SOR] = "sor",
3590 [TEGRA_POWERGATE_DIS] = "dis",
3591 [TEGRA_POWERGATE_DISB] = "disb",
3592 [TEGRA_POWERGATE_XUSBA] = "xusba",
3593 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3594 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3595 [TEGRA_POWERGATE_VIC] = "vic",
3596 [TEGRA_POWERGATE_IRAM] = "iram",
3597 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3598 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3599 [TEGRA_POWERGATE_AUD] = "aud",
3600 [TEGRA_POWERGATE_DFD] = "dfd",
3601 [TEGRA_POWERGATE_VE2] = "ve2",
3604 static const u8 tegra210_cpu_powergates[] = {
3605 TEGRA_POWERGATE_CPU0,
3606 TEGRA_POWERGATE_CPU1,
3607 TEGRA_POWERGATE_CPU2,
3608 TEGRA_POWERGATE_CPU3,
3611 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3612 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"),
3613 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),
3614 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"),
3615 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),
3616 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),
3617 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"),
3618 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"),
3619 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),
3620 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"),
3621 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"),
3622 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),
3623 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"),
3624 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"),
3625 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),
3626 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),
3627 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),
3628 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),
3629 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"),
3630 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"),
3631 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"),
3632 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),
3633 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),
3634 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),
3635 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),
3636 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),
3637 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),
3638 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),
3639 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),
3640 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"),
3641 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),
3642 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"),
3643 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),
3644 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"),
3645 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),
3646 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),
3647 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),
3648 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"),
3649 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),
3652 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3653 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3654 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3655 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3656 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3657 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3658 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3659 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3660 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3661 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3662 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3663 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),
3664 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"),
3665 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"),
3666 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3667 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"),
3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"),
3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"),
3673 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),
3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3675 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),
3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),
3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),
3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),
3683 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3684 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),
3685 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3686 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3687 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3688 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3689 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"),
3690 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3693 static const char * const tegra210_reset_sources[] = {
3702 static const struct tegra_wake_event tegra210_wake_events[] = {
3703 TEGRA_WAKE_IRQ("rtc", 16, 2),
3704 TEGRA_WAKE_IRQ("pmu", 51, 86),
3707 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3708 .supports_core_domain = false,
3709 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3710 .powergates = tegra210_powergates,
3711 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3712 .cpu_powergates = tegra210_cpu_powergates,
3713 .has_tsense_reset = true,
3714 .has_gpu_clamps = true,
3715 .needs_mbist_war = true,
3716 .has_impl_33v_pwr = false,
3717 .maybe_tz_only = true,
3718 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3719 .io_pads = tegra210_io_pads,
3720 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3721 .pin_descs = tegra210_pin_descs,
3722 .regs = &tegra20_pmc_regs,
3723 .init = tegra20_pmc_init,
3724 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3725 .powergate_set = tegra114_powergate_set,
3726 .irq_set_wake = tegra210_pmc_irq_set_wake,
3727 .irq_set_type = tegra210_pmc_irq_set_type,
3728 .reset_sources = tegra210_reset_sources,
3729 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3730 .reset_levels = NULL,
3731 .num_reset_levels = 0,
3732 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3733 .wake_events = tegra210_wake_events,
3734 .pmc_clks_data = tegra_pmc_clks_data,
3735 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3736 .has_blink_output = true,
3737 .has_usb_sleepwalk = true,
3738 .has_single_mmio_aperture = true,
3741 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3742 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3743 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3744 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"),
3745 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3746 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3747 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3748 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3749 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3750 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"),
3751 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"),
3752 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"),
3753 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),
3754 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3755 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3756 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"),
3757 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3758 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3759 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3760 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3761 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),
3762 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3763 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3764 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),
3765 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"),
3766 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"),
3767 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3768 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3769 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3770 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3771 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3772 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3773 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),
3774 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
3775 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3776 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3777 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
3778 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3779 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3782 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3783 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3784 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3785 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),
3786 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3787 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3788 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3789 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3790 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3791 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),
3792 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),
3793 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),
3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),
3795 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
3796 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),
3798 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),
3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),
3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),
3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),
3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
3813 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
3814 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),
3815 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
3816 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
3817 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
3818 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
3819 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
3820 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
3823 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3826 .rst_source_shift = 0x2,
3827 .rst_source_mask = 0x3c,
3828 .rst_level_shift = 0x0,
3829 .rst_level_mask = 0x3,
3832 static void tegra186_pmc_init(struct tegra_pmc *pmc)
3834 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
3835 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
3837 register_syscore_ops(&pmc->syscore);
3840 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3841 struct device_node *np,
3844 struct resource regs;
3849 index = of_property_match_string(np, "reg-names", "wake");
3851 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3855 of_address_to_resource(np, index, ®s);
3857 wake = ioremap(regs.start, resource_size(®s));
3859 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3863 value = readl(wake + WAKE_AOWAKE_CTRL);
3866 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3868 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3870 writel(value, wake + WAKE_AOWAKE_CTRL);
3875 static const char * const tegra186_reset_sources[] = {
3893 static const char * const tegra186_reset_levels[] = {
3894 "L0", "L1", "L2", "WARM"
3897 static const struct tegra_wake_event tegra186_wake_events[] = {
3898 TEGRA_WAKE_IRQ("pmu", 24, 209),
3899 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3900 TEGRA_WAKE_IRQ("rtc", 73, 10),
3903 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3904 .supports_core_domain = false,
3905 .num_powergates = 0,
3907 .num_cpu_powergates = 0,
3908 .cpu_powergates = NULL,
3909 .has_tsense_reset = false,
3910 .has_gpu_clamps = false,
3911 .needs_mbist_war = false,
3912 .has_impl_33v_pwr = true,
3913 .maybe_tz_only = false,
3914 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3915 .io_pads = tegra186_io_pads,
3916 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3917 .pin_descs = tegra186_pin_descs,
3918 .regs = &tegra186_pmc_regs,
3919 .init = tegra186_pmc_init,
3920 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3921 .set_wake_filters = tegra186_pmc_set_wake_filters,
3922 .irq_set_wake = tegra186_pmc_irq_set_wake,
3923 .irq_set_type = tegra186_pmc_irq_set_type,
3924 .reset_sources = tegra186_reset_sources,
3925 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3926 .reset_levels = tegra186_reset_levels,
3927 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3928 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3929 .wake_events = tegra186_wake_events,
3930 .max_wake_events = 96,
3931 .max_wake_vectors = 3,
3932 .pmc_clks_data = NULL,
3934 .has_blink_output = false,
3935 .has_usb_sleepwalk = false,
3936 .has_single_mmio_aperture = false,
3939 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3940 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),
3941 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),
3942 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),
3943 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),
3944 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),
3945 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),
3946 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),
3947 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"),
3948 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),
3949 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),
3950 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"),
3951 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"),
3952 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),
3953 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),
3954 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),
3955 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),
3956 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),
3957 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),
3958 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),
3959 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),
3960 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),
3961 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"),
3962 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"),
3963 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),
3964 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),
3965 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),
3966 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),
3967 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),
3968 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),
3969 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),
3970 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),
3971 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),
3972 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),
3973 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),
3974 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),
3975 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),
3976 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),
3977 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),
3978 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),
3979 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),
3980 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),
3981 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"),
3982 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"),
3983 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),
3984 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),
3985 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),
3986 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),
3987 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),
3988 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
3991 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3992 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
3993 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
3994 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),
3995 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),
3996 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),
3997 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),
3998 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),
3999 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"),
4000 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),
4001 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),
4002 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"),
4003 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"),
4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),
4005 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),
4006 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),
4007 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),
4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),
4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),
4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),
4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),
4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),
4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"),
4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"),
4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),
4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),
4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),
4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),
4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),
4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),
4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),
4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),
4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),
4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),
4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),
4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),
4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4033 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4034 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4035 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4036 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4037 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4038 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),
4039 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4040 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4043 static const struct tegra_pmc_regs tegra194_pmc_regs = {
4046 .rst_source_shift = 0x2,
4047 .rst_source_mask = 0x7c,
4048 .rst_level_shift = 0x0,
4049 .rst_level_mask = 0x3,
4052 static const char * const tegra194_reset_sources[] = {
4076 static const struct tegra_wake_event tegra194_wake_events[] = {
4077 TEGRA_WAKE_IRQ("pmu", 24, 209),
4078 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
4079 TEGRA_WAKE_IRQ("rtc", 73, 10),
4080 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
4081 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
4082 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
4083 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
4084 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
4085 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
4086 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
4089 static const struct tegra_pmc_soc tegra194_pmc_soc = {
4090 .supports_core_domain = false,
4091 .num_powergates = 0,
4093 .num_cpu_powergates = 0,
4094 .cpu_powergates = NULL,
4095 .has_tsense_reset = false,
4096 .has_gpu_clamps = false,
4097 .needs_mbist_war = false,
4098 .has_impl_33v_pwr = true,
4099 .maybe_tz_only = false,
4100 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
4101 .io_pads = tegra194_io_pads,
4102 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
4103 .pin_descs = tegra194_pin_descs,
4104 .regs = &tegra194_pmc_regs,
4105 .init = tegra186_pmc_init,
4106 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4107 .set_wake_filters = tegra186_pmc_set_wake_filters,
4108 .irq_set_wake = tegra186_pmc_irq_set_wake,
4109 .irq_set_type = tegra186_pmc_irq_set_type,
4110 .reset_sources = tegra194_reset_sources,
4111 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
4112 .reset_levels = tegra186_reset_levels,
4113 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4114 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
4115 .wake_events = tegra194_wake_events,
4116 .max_wake_events = 96,
4117 .max_wake_vectors = 3,
4118 .pmc_clks_data = NULL,
4120 .has_blink_output = false,
4121 .has_usb_sleepwalk = false,
4122 .has_single_mmio_aperture = false,
4125 static const struct tegra_io_pad_soc tegra234_io_pads[] = {
4126 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"),
4127 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"),
4128 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),
4129 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"),
4130 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"),
4131 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"),
4132 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"),
4133 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"),
4134 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"),
4135 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),
4136 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),
4137 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),
4138 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),
4139 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"),
4140 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"),
4143 static const struct pinctrl_pin_desc tegra234_pin_descs[] = {
4144 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),
4145 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),
4146 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),
4147 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),
4148 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),
4149 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),
4150 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),
4151 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),
4152 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),
4153 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),
4154 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),
4155 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),
4156 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),
4157 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),
4158 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),
4161 static const struct tegra_pmc_regs tegra234_pmc_regs = {
4164 .rst_source_shift = 0x2,
4165 .rst_source_mask = 0xfc,
4166 .rst_level_shift = 0x0,
4167 .rst_level_mask = 0x3,
4170 static const char * const tegra234_reset_sources[] = {
4171 "SYS_RESET_N", /* 0x0 */
4195 "CSITE_SW", /* 0x18 */
4203 "FSI_R52C0WDT", /* 0x20 */
4208 "FSI_VMON", /* 0x25 */
4211 static const struct tegra_wake_event tegra234_wake_events[] = {
4212 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)),
4213 TEGRA_WAKE_IRQ("pmu", 24, 209),
4214 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
4215 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)),
4216 TEGRA_WAKE_IRQ("rtc", 73, 10),
4217 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
4220 static const struct tegra_pmc_soc tegra234_pmc_soc = {
4221 .supports_core_domain = false,
4222 .num_powergates = 0,
4224 .num_cpu_powergates = 0,
4225 .cpu_powergates = NULL,
4226 .has_tsense_reset = false,
4227 .has_gpu_clamps = false,
4228 .needs_mbist_war = false,
4229 .has_impl_33v_pwr = true,
4230 .maybe_tz_only = false,
4231 .num_io_pads = ARRAY_SIZE(tegra234_io_pads),
4232 .io_pads = tegra234_io_pads,
4233 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),
4234 .pin_descs = tegra234_pin_descs,
4235 .regs = &tegra234_pmc_regs,
4236 .init = tegra186_pmc_init,
4237 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
4238 .set_wake_filters = tegra186_pmc_set_wake_filters,
4239 .irq_set_wake = tegra186_pmc_irq_set_wake,
4240 .irq_set_type = tegra186_pmc_irq_set_type,
4241 .reset_sources = tegra234_reset_sources,
4242 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
4243 .reset_levels = tegra186_reset_levels,
4244 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
4245 .num_wake_events = ARRAY_SIZE(tegra234_wake_events),
4246 .wake_events = tegra234_wake_events,
4247 .max_wake_events = 96,
4248 .max_wake_vectors = 3,
4249 .pmc_clks_data = NULL,
4251 .has_blink_output = false,
4252 .has_single_mmio_aperture = false,
4255 static const struct of_device_id tegra_pmc_match[] = {
4256 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4257 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4258 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4259 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4260 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4261 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4262 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4263 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4264 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4268 static void tegra_pmc_sync_state(struct device *dev)
4273 * Newer device-trees have power domains, but we need to prepare all
4274 * device drivers with runtime PM and OPP support first, otherwise
4275 * state syncing is unsafe.
4277 if (!pmc->soc->supports_core_domain)
4281 * Older device-trees don't have core PD, and thus, there are
4282 * no dependencies that will block the state syncing. We shouldn't
4283 * mark the domain as synced in this case.
4285 if (!pmc->core_domain_registered)
4288 pmc->core_domain_state_synced = true;
4290 /* this is a no-op if core regulator isn't used */
4291 mutex_lock(&pmc->powergates_lock);
4292 err = dev_pm_opp_sync_regulators(dev);
4293 mutex_unlock(&pmc->powergates_lock);
4296 dev_err(dev, "failed to sync regulators: %d\n", err);
4299 static struct platform_driver tegra_pmc_driver = {
4301 .name = "tegra-pmc",
4302 .suppress_bind_attrs = true,
4303 .of_match_table = tegra_pmc_match,
4304 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
4305 .pm = &tegra_pmc_pm_ops,
4307 .sync_state = tegra_pmc_sync_state,
4309 .probe = tegra_pmc_probe,
4311 builtin_platform_driver(tegra_pmc_driver);
4313 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
4317 saved = readl(pmc->base + pmc->soc->regs->scratch0);
4318 value = saved ^ 0xffffffff;
4320 if (value == 0xffffffff)
4323 /* write pattern and read it back */
4324 writel(value, pmc->base + pmc->soc->regs->scratch0);
4325 value = readl(pmc->base + pmc->soc->regs->scratch0);
4327 /* if we read all-zeroes, access is restricted to TZ only */
4329 pr_info("access to PMC is restricted to TZ\n");
4333 /* restore original value */
4334 writel(saved, pmc->base + pmc->soc->regs->scratch0);
4340 * Early initialization to allow access to registers in the very early boot
4343 static int __init tegra_pmc_early_init(void)
4345 const struct of_device_id *match;
4346 struct device_node *np;
4347 struct resource regs;
4351 mutex_init(&pmc->powergates_lock);
4353 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
4356 * Fall back to legacy initialization for 32-bit ARM only. All
4357 * 64-bit ARM device tree files for Tegra are required to have
4360 * This is for backwards-compatibility with old device trees
4361 * that didn't contain a PMC node. Note that in this case the
4362 * SoC data can't be matched and therefore powergating is
4365 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
4366 pr_warn("DT node not found, powergating disabled\n");
4368 regs.start = 0x7000e400;
4369 regs.end = 0x7000e7ff;
4370 regs.flags = IORESOURCE_MEM;
4372 pr_warn("Using memory region %pR\n", ®s);
4375 * At this point we're not running on Tegra, so play
4376 * nice with multi-platform kernels.
4382 * Extract information from the device tree if we've found a
4385 if (of_address_to_resource(np, 0, ®s) < 0) {
4386 pr_err("failed to get PMC registers\n");
4392 pmc->base = ioremap(regs.start, resource_size(®s));
4394 pr_err("failed to map PMC registers\n");
4399 if (of_device_is_available(np)) {
4400 pmc->soc = match->data;
4402 if (pmc->soc->maybe_tz_only)
4403 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
4405 /* Create a bitmap of the available and valid partitions */
4406 for (i = 0; i < pmc->soc->num_powergates; i++)
4407 if (pmc->soc->powergates[i])
4408 set_bit(i, pmc->powergates_available);
4411 * Invert the interrupt polarity if a PMC device tree node
4412 * exists and contains the nvidia,invert-interrupt property.
4414 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
4416 pmc->soc->setup_irq_polarity(pmc, np, invert);
4423 early_initcall(tegra_pmc_early_init);