1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/device.h>
7 #include <linux/kernel.h>
10 #include <soc/tegra/fuse.h>
14 #define CPU_PROCESS_CORNERS 2
15 #define GPU_PROCESS_CORNERS 2
16 #define SOC_PROCESS_CORNERS 2
18 #define FUSE_CPU_SPEEDO_0 0x14
19 #define FUSE_CPU_SPEEDO_1 0x2c
20 #define FUSE_CPU_SPEEDO_2 0x30
21 #define FUSE_SOC_SPEEDO_0 0x34
22 #define FUSE_SOC_SPEEDO_1 0x38
23 #define FUSE_SOC_SPEEDO_2 0x3c
24 #define FUSE_CPU_IDDQ 0x18
25 #define FUSE_SOC_IDDQ 0x40
26 #define FUSE_GPU_IDDQ 0x128
27 #define FUSE_FT_REV 0x28
32 THRESHOLD_INDEX_COUNT,
35 static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
40 static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
45 static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
50 static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
53 int sku = sku_info->sku_id;
55 /* Assign to default */
56 sku_info->cpu_speedo_id = 0;
57 sku_info->soc_speedo_id = 0;
58 sku_info->gpu_speedo_id = 0;
59 *threshold = THRESHOLD_INDEX_0;
62 case 0x00: /* Eng sku */
65 /* Using the default */
68 sku_info->cpu_speedo_id = 2;
74 sku_info->cpu_speedo_id = 2;
75 sku_info->soc_speedo_id = 0;
76 sku_info->gpu_speedo_id = 1;
77 *threshold = THRESHOLD_INDEX_0;
82 sku_info->cpu_speedo_id = 1;
83 sku_info->soc_speedo_id = 1;
84 sku_info->gpu_speedo_id = 1;
85 *threshold = THRESHOLD_INDEX_1;
90 sku_info->cpu_speedo_id = 4;
91 sku_info->soc_speedo_id = 2;
92 sku_info->gpu_speedo_id = 3;
93 *threshold = THRESHOLD_INDEX_1;
96 pr_err("Tegra Unknown SKU %d\n", sku);
97 /* Using the default for the error case */
102 void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
104 int i, threshold, cpu_speedo_0_value, soc_speedo_0_value;
105 int cpu_iddq_value, gpu_iddq_value, soc_iddq_value;
107 BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
108 THRESHOLD_INDEX_COUNT);
109 BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
110 THRESHOLD_INDEX_COUNT);
111 BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
112 THRESHOLD_INDEX_COUNT);
114 cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
116 /* GPU Speedo is stored in CPU_SPEEDO_2 */
117 sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
119 soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
121 cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
122 soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ);
123 gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ);
125 sku_info->cpu_speedo_value = cpu_speedo_0_value;
127 if (sku_info->cpu_speedo_value == 0) {
128 pr_warn("Tegra Warning: Speedo value not fused.\n");
133 rev_sku_to_speedo_ids(sku_info, &threshold);
135 sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
137 for (i = 0; i < GPU_PROCESS_CORNERS; i++)
138 if (sku_info->gpu_speedo_value <
139 gpu_process_speedos[threshold][i])
141 sku_info->gpu_process_id = i;
143 for (i = 0; i < CPU_PROCESS_CORNERS; i++)
144 if (sku_info->cpu_speedo_value <
145 cpu_process_speedos[threshold][i])
147 sku_info->cpu_process_id = i;
149 for (i = 0; i < SOC_PROCESS_CORNERS; i++)
150 if (soc_speedo_0_value <
151 soc_process_speedos[threshold][i])
153 sku_info->soc_process_id = i;
155 pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
156 sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);