1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
6 #define dev_fmt(fmt) "tegra-soc: " fmt
9 #include <linux/device.h>
10 #include <linux/export.h>
12 #include <linux/pm_opp.h>
13 #include <linux/pm_runtime.h>
15 #include <soc/tegra/common.h>
16 #include <soc/tegra/fuse.h>
18 static const struct of_device_id tegra_machine_match[] = {
19 { .compatible = "nvidia,tegra20", },
20 { .compatible = "nvidia,tegra30", },
21 { .compatible = "nvidia,tegra114", },
22 { .compatible = "nvidia,tegra124", },
23 { .compatible = "nvidia,tegra132", },
24 { .compatible = "nvidia,tegra210", },
28 bool soc_is_tegra(void)
30 const struct of_device_id *match;
31 struct device_node *root;
33 root = of_find_node_by_path("/");
37 match = of_match_node(tegra_machine_match, root);
43 static int tegra_core_dev_init_opp_state(struct device *dev)
50 clk = devm_clk_get(dev, NULL);
52 dev_err(dev, "failed to get clk: %pe\n", clk);
56 rate = clk_get_rate(clk);
58 dev_err(dev, "failed to get clk rate\n");
63 * Runtime PM of the device must be enabled in order to set up
64 * GENPD's performance properly because GENPD core checks whether
65 * device is suspended and this check doesn't work while RPM is
66 * disabled. This makes sure the OPP vote below gets cached in
67 * GENPD for the device. Instead, the vote is done the next time
68 * the device gets runtime resumed.
70 rpm_enabled = pm_runtime_enabled(dev);
72 pm_runtime_enable(dev);
74 /* should never happen in practice */
75 if (!pm_runtime_enabled(dev)) {
76 dev_WARN(dev, "failed to enable runtime PM\n");
77 pm_runtime_disable(dev);
81 /* first dummy rate-setting initializes voltage vote */
82 err = dev_pm_opp_set_rate(dev, rate);
85 pm_runtime_disable(dev);
88 dev_err(dev, "failed to initialize OPP clock: %d\n", err);
96 * devm_tegra_core_dev_init_opp_table() - initialize OPP table
97 * @dev: device for which OPP table is initialized
98 * @params: pointer to the OPP table configuration
100 * This function will initialize OPP table and sync OPP state of a Tegra SoC
103 * Return: 0 on success or errorno.
105 int devm_tegra_core_dev_init_opp_table(struct device *dev,
106 struct tegra_core_opp_params *params)
111 err = devm_pm_opp_set_clkname(dev, NULL);
113 dev_err(dev, "failed to set OPP clk: %d\n", err);
117 /* Tegra114+ doesn't support OPP yet */
118 if (!of_machine_is_compatible("nvidia,tegra20") &&
119 !of_machine_is_compatible("nvidia,tegra30"))
122 if (of_machine_is_compatible("nvidia,tegra20"))
123 hw_version = BIT(tegra_sku_info.soc_process_id);
125 hw_version = BIT(tegra_sku_info.soc_speedo_id);
127 err = devm_pm_opp_set_supported_hw(dev, &hw_version, 1);
129 dev_err(dev, "failed to set OPP supported HW: %d\n", err);
134 * Older device-trees have an empty OPP table, we will get
135 * -ENODEV from devm_pm_opp_of_add_table() in this case.
137 err = devm_pm_opp_of_add_table(dev);
140 dev_err(dev, "failed to add OPP table: %d\n", err);
145 if (params->init_state) {
146 err = tegra_core_dev_init_opp_state(dev);
153 EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table);