1 // SPDX-License-Identifier: GPL-2.0
3 * SiFive L2 cache controller Driver
5 * Copyright (C) 2018-2019 SiFive, Inc.
8 #include <linux/debugfs.h>
9 #include <linux/interrupt.h>
10 #include <linux/of_irq.h>
11 #include <linux/of_address.h>
12 #include <linux/device.h>
13 #include <asm/cacheinfo.h>
14 #include <soc/sifive/sifive_l2_cache.h>
16 #define SIFIVE_L2_DIRECCFIX_LOW 0x100
17 #define SIFIVE_L2_DIRECCFIX_HIGH 0x104
18 #define SIFIVE_L2_DIRECCFIX_COUNT 0x108
20 #define SIFIVE_L2_DIRECCFAIL_LOW 0x120
21 #define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
22 #define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
24 #define SIFIVE_L2_DATECCFIX_LOW 0x140
25 #define SIFIVE_L2_DATECCFIX_HIGH 0x144
26 #define SIFIVE_L2_DATECCFIX_COUNT 0x148
28 #define SIFIVE_L2_DATECCFAIL_LOW 0x160
29 #define SIFIVE_L2_DATECCFAIL_HIGH 0x164
30 #define SIFIVE_L2_DATECCFAIL_COUNT 0x168
32 #define SIFIVE_L2_CONFIG 0x00
33 #define SIFIVE_L2_WAYENABLE 0x08
34 #define SIFIVE_L2_ECCINJECTERR 0x40
36 #define SIFIVE_L2_MAX_ECCINTR 4
38 static void __iomem *l2_base;
39 static int g_irq[SIFIVE_L2_MAX_ECCINTR];
40 static struct riscv_cacheinfo_ops l2_cache_ops;
49 #ifdef CONFIG_DEBUG_FS
50 static struct dentry *sifive_test;
52 static ssize_t l2_write(struct file *file, const char __user *data,
53 size_t count, loff_t *ppos)
57 if (kstrtouint_from_user(data, count, 0, &val))
59 if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
60 writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
66 static const struct file_operations l2_fops = {
72 static void setup_sifive_debug(void)
74 sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
76 debugfs_create_file("sifive_debug_inject_error", 0200,
77 sifive_test, NULL, &l2_fops);
81 static void l2_config_read(void)
85 regval = readl(l2_base + SIFIVE_L2_CONFIG);
87 pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
88 val = (regval & 0xFF00) >> 8;
89 pr_info("L2CACHE: No. of ways per bank: %d\n", val);
90 val = (regval & 0xFF0000) >> 16;
91 pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
92 val = (regval & 0xFF000000) >> 24;
93 pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
95 regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
96 pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
99 static const struct of_device_id sifive_l2_ids[] = {
100 { .compatible = "sifive,fu540-c000-ccache" },
101 { .compatible = "sifive,fu740-c000-ccache" },
102 { /* end of table */ },
105 static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
107 int register_sifive_l2_error_notifier(struct notifier_block *nb)
109 return atomic_notifier_chain_register(&l2_err_chain, nb);
111 EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
113 int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
115 return atomic_notifier_chain_unregister(&l2_err_chain, nb);
117 EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
119 static int l2_largest_wayenabled(void)
121 return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
124 static ssize_t number_of_ways_enabled_show(struct device *dev,
125 struct device_attribute *attr,
128 return sprintf(buf, "%u\n", l2_largest_wayenabled());
131 static DEVICE_ATTR_RO(number_of_ways_enabled);
133 static struct attribute *priv_attrs[] = {
134 &dev_attr_number_of_ways_enabled.attr,
138 static const struct attribute_group priv_attr_group = {
142 static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
144 /* We want to use private group for L2 cache only */
145 if (this_leaf->level == 2)
146 return &priv_attr_group;
151 static irqreturn_t l2_int_handler(int irq, void *device)
153 unsigned int add_h, add_l;
155 if (irq == g_irq[DIR_CORR]) {
156 add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
157 add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
158 pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
159 /* Reading this register clears the DirError interrupt sig */
160 readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
161 atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
164 if (irq == g_irq[DIR_UNCORR]) {
165 add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
166 add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
167 /* Reading this register clears the DirFail interrupt sig */
168 readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
169 atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
171 panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
173 if (irq == g_irq[DATA_CORR]) {
174 add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
175 add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
176 pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
177 /* Reading this register clears the DataError interrupt sig */
178 readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
179 atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
182 if (irq == g_irq[DATA_UNCORR]) {
183 add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
184 add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
185 pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
186 /* Reading this register clears the DataFail interrupt sig */
187 readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
188 atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
195 static int __init sifive_l2_init(void)
197 struct device_node *np;
201 np = of_find_matching_node(NULL, sifive_l2_ids);
205 if (of_address_to_resource(np, 0, &res))
208 l2_base = ioremap(res.start, resource_size(&res));
212 intr_num = of_property_count_u32_elems(np, "interrupts");
214 pr_err("L2CACHE: no interrupts property\n");
218 for (i = 0; i < intr_num; i++) {
219 g_irq[i] = irq_of_parse_and_map(np, i);
220 rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
222 pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
229 l2_cache_ops.get_priv_group = l2_get_priv_group;
230 riscv_set_cacheinfo_ops(&l2_cache_ops);
232 #ifdef CONFIG_DEBUG_FS
233 setup_sifive_debug();
237 device_initcall(sifive_l2_init);