2 * Rockchip Generic power domain support.
4 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/iopoll.h>
13 #include <linux/err.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_platform.h>
19 #include <linux/clk.h>
20 #include <linux/regmap.h>
21 #include <linux/mfd/syscon.h>
22 #include <dt-bindings/power/px30-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3128-power.h>
25 #include <dt-bindings/power/rk3228-power.h>
26 #include <dt-bindings/power/rk3288-power.h>
27 #include <dt-bindings/power/rk3328-power.h>
28 #include <dt-bindings/power/rk3366-power.h>
29 #include <dt-bindings/power/rk3368-power.h>
30 #include <dt-bindings/power/rk3399-power.h>
32 struct rockchip_domain_info {
43 struct rockchip_pmu_info {
50 u32 core_pwrcnt_offset;
51 u32 gpu_pwrcnt_offset;
53 unsigned int core_power_transition_time;
54 unsigned int gpu_power_transition_time;
57 const struct rockchip_domain_info *domain_info;
60 #define MAX_QOS_REGS_NUM 5
61 #define QOS_PRIORITY 0x08
63 #define QOS_BANDWIDTH 0x10
64 #define QOS_SATURATION 0x14
65 #define QOS_EXTCONTROL 0x18
67 struct rockchip_pm_domain {
68 struct generic_pm_domain genpd;
69 const struct rockchip_domain_info *info;
70 struct rockchip_pmu *pmu;
72 struct regmap **qos_regmap;
73 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
75 struct clk_bulk_data *clks;
80 struct regmap *regmap;
81 const struct rockchip_pmu_info *info;
82 struct mutex mutex; /* mutex lock for pmu */
83 struct genpd_onecell_data genpd_data;
84 struct generic_pm_domain *domains[];
87 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
89 #define DOMAIN(pwr, status, req, idle, ack, wakeup) \
91 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
92 .status_mask = (status >= 0) ? BIT(status) : 0, \
93 .req_mask = (req >= 0) ? BIT(req) : 0, \
94 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
95 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
96 .active_wakeup = wakeup, \
99 #define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
101 .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0, \
102 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
103 .status_mask = (status >= 0) ? BIT(status) : 0, \
104 .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \
105 .req_mask = (req >= 0) ? BIT(req) : 0, \
106 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
107 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
108 .active_wakeup = wakeup, \
111 #define DOMAIN_RK3036(req, ack, idle, wakeup) \
113 .req_mask = (req >= 0) ? BIT(req) : 0, \
114 .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \
115 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
116 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
117 .active_wakeup = wakeup, \
120 #define DOMAIN_PX30(pwr, status, req, wakeup) \
121 DOMAIN_M(pwr, status, req, (req) + 16, req, wakeup)
123 #define DOMAIN_RK3288(pwr, status, req, wakeup) \
124 DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
126 #define DOMAIN_RK3328(pwr, status, req, wakeup) \
127 DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
129 #define DOMAIN_RK3368(pwr, status, req, wakeup) \
130 DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
132 #define DOMAIN_RK3399(pwr, status, req, wakeup) \
133 DOMAIN(pwr, status, req, req, req, wakeup)
135 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
137 struct rockchip_pmu *pmu = pd->pmu;
138 const struct rockchip_domain_info *pd_info = pd->info;
141 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
142 return (val & pd_info->idle_mask) == pd_info->idle_mask;
145 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
149 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
153 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
156 const struct rockchip_domain_info *pd_info = pd->info;
157 struct generic_pm_domain *genpd = &pd->genpd;
158 struct rockchip_pmu *pmu = pd->pmu;
159 unsigned int target_ack;
164 if (pd_info->req_mask == 0)
166 else if (pd_info->req_w_mask)
167 regmap_write(pmu->regmap, pmu->info->req_offset,
168 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
169 pd_info->req_w_mask);
171 regmap_update_bits(pmu->regmap, pmu->info->req_offset,
172 pd_info->req_mask, idle ? -1U : 0);
176 /* Wait util idle_ack = 1 */
177 target_ack = idle ? pd_info->ack_mask : 0;
178 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
179 (val & pd_info->ack_mask) == target_ack,
183 "failed to get ack on domain '%s', val=0x%x\n",
188 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
189 is_idle, is_idle == idle, 0, 10000);
192 "failed to set idle on domain '%s', val=%d\n",
193 genpd->name, is_idle);
200 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
204 for (i = 0; i < pd->num_qos; i++) {
205 regmap_read(pd->qos_regmap[i],
207 &pd->qos_save_regs[0][i]);
208 regmap_read(pd->qos_regmap[i],
210 &pd->qos_save_regs[1][i]);
211 regmap_read(pd->qos_regmap[i],
213 &pd->qos_save_regs[2][i]);
214 regmap_read(pd->qos_regmap[i],
216 &pd->qos_save_regs[3][i]);
217 regmap_read(pd->qos_regmap[i],
219 &pd->qos_save_regs[4][i]);
224 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
228 for (i = 0; i < pd->num_qos; i++) {
229 regmap_write(pd->qos_regmap[i],
231 pd->qos_save_regs[0][i]);
232 regmap_write(pd->qos_regmap[i],
234 pd->qos_save_regs[1][i]);
235 regmap_write(pd->qos_regmap[i],
237 pd->qos_save_regs[2][i]);
238 regmap_write(pd->qos_regmap[i],
240 pd->qos_save_regs[3][i]);
241 regmap_write(pd->qos_regmap[i],
243 pd->qos_save_regs[4][i]);
249 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
251 struct rockchip_pmu *pmu = pd->pmu;
254 /* check idle status for idle-only domains */
255 if (pd->info->status_mask == 0)
256 return !rockchip_pmu_domain_is_idle(pd);
258 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
260 /* 1'b0: power on, 1'b1: power off */
261 return !(val & pd->info->status_mask);
264 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
267 struct rockchip_pmu *pmu = pd->pmu;
268 struct generic_pm_domain *genpd = &pd->genpd;
271 if (pd->info->pwr_mask == 0)
273 else if (pd->info->pwr_w_mask)
274 regmap_write(pmu->regmap, pmu->info->pwr_offset,
275 on ? pd->info->pwr_w_mask :
276 (pd->info->pwr_mask | pd->info->pwr_w_mask));
278 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
279 pd->info->pwr_mask, on ? 0 : -1U);
283 if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
284 is_on == on, 0, 10000)) {
286 "failed to set domain '%s', val=%d\n",
292 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
294 struct rockchip_pmu *pmu = pd->pmu;
297 mutex_lock(&pmu->mutex);
299 if (rockchip_pmu_domain_is_on(pd) != power_on) {
300 ret = clk_bulk_enable(pd->num_clks, pd->clks);
302 dev_err(pmu->dev, "failed to enable clocks\n");
303 mutex_unlock(&pmu->mutex);
308 rockchip_pmu_save_qos(pd);
310 /* if powering down, idle request to NIU first */
311 rockchip_pmu_set_idle_request(pd, true);
314 rockchip_do_pmu_set_power_domain(pd, power_on);
317 /* if powering up, leave idle mode */
318 rockchip_pmu_set_idle_request(pd, false);
320 rockchip_pmu_restore_qos(pd);
323 clk_bulk_disable(pd->num_clks, pd->clks);
326 mutex_unlock(&pmu->mutex);
330 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
332 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
334 return rockchip_pd_power(pd, true);
337 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
339 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
341 return rockchip_pd_power(pd, false);
344 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
351 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
353 error = pm_clk_create(dev);
355 dev_err(dev, "pm_clk_create failed %d\n", error);
360 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
361 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
362 error = pm_clk_add_clk(dev, clk);
364 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
374 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
377 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
382 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
383 struct device_node *node)
385 const struct rockchip_domain_info *pd_info;
386 struct rockchip_pm_domain *pd;
387 struct device_node *qos_node;
392 error = of_property_read_u32(node, "reg", &id);
395 "%s: failed to retrieve domain id (reg): %d\n",
400 if (id >= pmu->info->num_domains) {
401 dev_err(pmu->dev, "%s: invalid domain id %d\n",
406 pd_info = &pmu->info->domain_info[id];
408 dev_err(pmu->dev, "%s: undefined domain id %d\n",
413 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
420 pd->num_clks = of_clk_get_parent_count(node);
421 if (pd->num_clks > 0) {
422 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
423 sizeof(*pd->clks), GFP_KERNEL);
427 dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
428 node->name, pd->num_clks);
432 for (i = 0; i < pd->num_clks; i++) {
433 pd->clks[i].clk = of_clk_get(node, i);
434 if (IS_ERR(pd->clks[i].clk)) {
435 error = PTR_ERR(pd->clks[i].clk);
437 "%s: failed to get clk at index %d: %d\n",
438 node->name, i, error);
443 error = clk_bulk_prepare(pd->num_clks, pd->clks);
447 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
450 if (pd->num_qos > 0) {
451 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
452 sizeof(*pd->qos_regmap),
454 if (!pd->qos_regmap) {
456 goto err_unprepare_clocks;
459 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
460 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
464 if (!pd->qos_save_regs[j]) {
466 goto err_unprepare_clocks;
470 for (j = 0; j < pd->num_qos; j++) {
471 qos_node = of_parse_phandle(node, "pm_qos", j);
474 goto err_unprepare_clocks;
476 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
477 if (IS_ERR(pd->qos_regmap[j])) {
479 of_node_put(qos_node);
480 goto err_unprepare_clocks;
482 of_node_put(qos_node);
486 error = rockchip_pd_power(pd, true);
489 "failed to power on domain '%s': %d\n",
491 goto err_unprepare_clocks;
494 pd->genpd.name = node->name;
495 pd->genpd.power_off = rockchip_pd_power_off;
496 pd->genpd.power_on = rockchip_pd_power_on;
497 pd->genpd.attach_dev = rockchip_pd_attach_dev;
498 pd->genpd.detach_dev = rockchip_pd_detach_dev;
499 pd->genpd.flags = GENPD_FLAG_PM_CLK;
500 if (pd_info->active_wakeup)
501 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
502 pm_genpd_init(&pd->genpd, NULL, false);
504 pmu->genpd_data.domains[id] = &pd->genpd;
507 err_unprepare_clocks:
508 clk_bulk_unprepare(pd->num_clks, pd->clks);
510 clk_bulk_put(pd->num_clks, pd->clks);
514 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
519 * We're in the error cleanup already, so we only complain,
520 * but won't emit another error on top of the original one.
522 ret = pm_genpd_remove(&pd->genpd);
524 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
525 pd->genpd.name, ret);
527 clk_bulk_unprepare(pd->num_clks, pd->clks);
528 clk_bulk_put(pd->num_clks, pd->clks);
530 /* protect the zeroing of pm->num_clks */
531 mutex_lock(&pd->pmu->mutex);
533 mutex_unlock(&pd->pmu->mutex);
535 /* devm will free our memory */
538 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
540 struct generic_pm_domain *genpd;
541 struct rockchip_pm_domain *pd;
544 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
545 genpd = pmu->genpd_data.domains[i];
547 pd = to_rockchip_pd(genpd);
548 rockchip_pm_remove_one_domain(pd);
552 /* devm will free our memory */
555 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
556 u32 domain_reg_offset,
559 /* First configure domain power down transition count ... */
560 regmap_write(pmu->regmap, domain_reg_offset, count);
561 /* ... and then power up count. */
562 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
565 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
566 struct device_node *parent)
568 struct device_node *np;
569 struct generic_pm_domain *child_domain, *parent_domain;
572 for_each_child_of_node(parent, np) {
575 error = of_property_read_u32(parent, "reg", &idx);
578 "%s: failed to retrieve domain id (reg): %d\n",
579 parent->name, error);
582 parent_domain = pmu->genpd_data.domains[idx];
584 error = rockchip_pm_add_one_domain(pmu, np);
586 dev_err(pmu->dev, "failed to handle node %s: %d\n",
591 error = of_property_read_u32(np, "reg", &idx);
594 "%s: failed to retrieve domain id (reg): %d\n",
598 child_domain = pmu->genpd_data.domains[idx];
600 error = pm_genpd_add_subdomain(parent_domain, child_domain);
602 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
603 parent_domain->name, child_domain->name, error);
606 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
607 parent_domain->name, child_domain->name);
610 rockchip_pm_add_subdomain(pmu, np);
620 static int rockchip_pm_domain_probe(struct platform_device *pdev)
622 struct device *dev = &pdev->dev;
623 struct device_node *np = dev->of_node;
624 struct device_node *node;
625 struct device *parent;
626 struct rockchip_pmu *pmu;
627 const struct of_device_id *match;
628 const struct rockchip_pmu_info *pmu_info;
632 dev_err(dev, "device tree node not found\n");
636 match = of_match_device(dev->driver->of_match_table, dev);
637 if (!match || !match->data) {
638 dev_err(dev, "missing pmu data\n");
642 pmu_info = match->data;
644 pmu = devm_kzalloc(dev,
645 struct_size(pmu, domains, pmu_info->num_domains),
650 pmu->dev = &pdev->dev;
651 mutex_init(&pmu->mutex);
653 pmu->info = pmu_info;
655 pmu->genpd_data.domains = pmu->domains;
656 pmu->genpd_data.num_domains = pmu_info->num_domains;
658 parent = dev->parent;
660 dev_err(dev, "no parent for syscon devices\n");
664 pmu->regmap = syscon_node_to_regmap(parent->of_node);
665 if (IS_ERR(pmu->regmap)) {
666 dev_err(dev, "no regmap available\n");
667 return PTR_ERR(pmu->regmap);
671 * Configure power up and down transition delays for CORE
674 if (pmu_info->core_power_transition_time)
675 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
676 pmu_info->core_power_transition_time);
677 if (pmu_info->gpu_pwrcnt_offset)
678 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
679 pmu_info->gpu_power_transition_time);
683 for_each_available_child_of_node(np, node) {
684 error = rockchip_pm_add_one_domain(pmu, node);
686 dev_err(dev, "failed to handle node %s: %d\n",
692 error = rockchip_pm_add_subdomain(pmu, node);
694 dev_err(dev, "failed to handle subdomain node %s: %d\n",
702 dev_dbg(dev, "no power domains defined\n");
706 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
708 dev_err(dev, "failed to add provider: %d\n", error);
715 rockchip_pm_domain_cleanup(pmu);
719 static const struct rockchip_domain_info px30_pm_domains[] = {
720 [PX30_PD_USB] = DOMAIN_PX30(5, 5, 10, false),
721 [PX30_PD_SDCARD] = DOMAIN_PX30(8, 8, 9, false),
722 [PX30_PD_GMAC] = DOMAIN_PX30(10, 10, 6, false),
723 [PX30_PD_MMC_NAND] = DOMAIN_PX30(11, 11, 5, false),
724 [PX30_PD_VPU] = DOMAIN_PX30(12, 12, 14, false),
725 [PX30_PD_VO] = DOMAIN_PX30(13, 13, 7, false),
726 [PX30_PD_VI] = DOMAIN_PX30(14, 14, 8, false),
727 [PX30_PD_GPU] = DOMAIN_PX30(15, 15, 2, false),
730 static const struct rockchip_domain_info rk3036_pm_domains[] = {
731 [RK3036_PD_MSCH] = DOMAIN_RK3036(14, 23, 30, true),
732 [RK3036_PD_CORE] = DOMAIN_RK3036(13, 17, 24, false),
733 [RK3036_PD_PERI] = DOMAIN_RK3036(12, 18, 25, false),
734 [RK3036_PD_VIO] = DOMAIN_RK3036(11, 19, 26, false),
735 [RK3036_PD_VPU] = DOMAIN_RK3036(10, 20, 27, false),
736 [RK3036_PD_GPU] = DOMAIN_RK3036(9, 21, 28, false),
737 [RK3036_PD_SYS] = DOMAIN_RK3036(8, 22, 29, false),
740 static const struct rockchip_domain_info rk3128_pm_domains[] = {
741 [RK3128_PD_CORE] = DOMAIN_RK3288(0, 0, 4, false),
742 [RK3128_PD_MSCH] = DOMAIN_RK3288(-1, -1, 6, true),
743 [RK3128_PD_VIO] = DOMAIN_RK3288(3, 3, 2, false),
744 [RK3128_PD_VIDEO] = DOMAIN_RK3288(2, 2, 1, false),
745 [RK3128_PD_GPU] = DOMAIN_RK3288(1, 1, 3, false),
748 static const struct rockchip_domain_info rk3228_pm_domains[] = {
749 [RK3228_PD_CORE] = DOMAIN_RK3036(0, 0, 16, true),
750 [RK3228_PD_MSCH] = DOMAIN_RK3036(1, 1, 17, true),
751 [RK3228_PD_BUS] = DOMAIN_RK3036(2, 2, 18, true),
752 [RK3228_PD_SYS] = DOMAIN_RK3036(3, 3, 19, true),
753 [RK3228_PD_VIO] = DOMAIN_RK3036(4, 4, 20, false),
754 [RK3228_PD_VOP] = DOMAIN_RK3036(5, 5, 21, false),
755 [RK3228_PD_VPU] = DOMAIN_RK3036(6, 6, 22, false),
756 [RK3228_PD_RKVDEC] = DOMAIN_RK3036(7, 7, 23, false),
757 [RK3228_PD_GPU] = DOMAIN_RK3036(8, 8, 24, false),
758 [RK3228_PD_PERI] = DOMAIN_RK3036(9, 9, 25, true),
759 [RK3228_PD_GMAC] = DOMAIN_RK3036(10, 10, 26, false),
762 static const struct rockchip_domain_info rk3288_pm_domains[] = {
763 [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4, false),
764 [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9, false),
765 [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3, false),
766 [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2, false),
769 static const struct rockchip_domain_info rk3328_pm_domains[] = {
770 [RK3328_PD_CORE] = DOMAIN_RK3328(-1, 0, 0, false),
771 [RK3328_PD_GPU] = DOMAIN_RK3328(-1, 1, 1, false),
772 [RK3328_PD_BUS] = DOMAIN_RK3328(-1, 2, 2, true),
773 [RK3328_PD_MSCH] = DOMAIN_RK3328(-1, 3, 3, true),
774 [RK3328_PD_PERI] = DOMAIN_RK3328(-1, 4, 4, true),
775 [RK3328_PD_VIDEO] = DOMAIN_RK3328(-1, 5, 5, false),
776 [RK3328_PD_HEVC] = DOMAIN_RK3328(-1, 6, 6, false),
777 [RK3328_PD_VIO] = DOMAIN_RK3328(-1, 8, 8, false),
778 [RK3328_PD_VPU] = DOMAIN_RK3328(-1, 9, 9, false),
781 static const struct rockchip_domain_info rk3366_pm_domains[] = {
782 [RK3366_PD_PERI] = DOMAIN_RK3368(10, 10, 6, true),
783 [RK3366_PD_VIO] = DOMAIN_RK3368(14, 14, 8, false),
784 [RK3366_PD_VIDEO] = DOMAIN_RK3368(13, 13, 7, false),
785 [RK3366_PD_RKVDEC] = DOMAIN_RK3368(11, 11, 7, false),
786 [RK3366_PD_WIFIBT] = DOMAIN_RK3368(8, 8, 9, false),
787 [RK3366_PD_VPU] = DOMAIN_RK3368(12, 12, 7, false),
788 [RK3366_PD_GPU] = DOMAIN_RK3368(15, 15, 2, false),
791 static const struct rockchip_domain_info rk3368_pm_domains[] = {
792 [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6, true),
793 [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8, false),
794 [RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7, false),
795 [RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2, false),
796 [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2, false),
799 static const struct rockchip_domain_info rk3399_pm_domains[] = {
800 [RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1, false),
801 [RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1, false),
802 [RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1, true),
803 [RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15, true),
804 [RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16, true),
805 [RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1, true),
806 [RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2, true),
807 [RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14, true),
808 [RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17, false),
809 [RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0, false),
810 [RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3, false),
811 [RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4, false),
812 [RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5, false),
813 [RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6, false),
814 [RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1, false),
815 [RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7, false),
816 [RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8, false),
817 [RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9, false),
818 [RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10, false),
819 [RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11, false),
820 [RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23, true),
821 [RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24, true),
822 [RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12, true),
823 [RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22, false),
824 [RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27, true),
825 [RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28, true),
826 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29, true),
829 static const struct rockchip_pmu_info px30_pmu = {
831 .status_offset = 0x20,
836 .num_domains = ARRAY_SIZE(px30_pm_domains),
837 .domain_info = px30_pm_domains,
840 static const struct rockchip_pmu_info rk3036_pmu = {
842 .idle_offset = 0x14c,
845 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
846 .domain_info = rk3036_pm_domains,
849 static const struct rockchip_pmu_info rk3128_pmu = {
851 .status_offset = 0x08,
856 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
857 .domain_info = rk3128_pm_domains,
860 static const struct rockchip_pmu_info rk3228_pmu = {
862 .idle_offset = 0x488,
865 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
866 .domain_info = rk3228_pm_domains,
869 static const struct rockchip_pmu_info rk3288_pmu = {
871 .status_offset = 0x0c,
876 .core_pwrcnt_offset = 0x34,
877 .gpu_pwrcnt_offset = 0x3c,
879 .core_power_transition_time = 24, /* 1us */
880 .gpu_power_transition_time = 24, /* 1us */
882 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
883 .domain_info = rk3288_pm_domains,
886 static const struct rockchip_pmu_info rk3328_pmu = {
888 .idle_offset = 0x484,
891 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
892 .domain_info = rk3328_pm_domains,
895 static const struct rockchip_pmu_info rk3366_pmu = {
897 .status_offset = 0x10,
902 .core_pwrcnt_offset = 0x48,
903 .gpu_pwrcnt_offset = 0x50,
905 .core_power_transition_time = 24,
906 .gpu_power_transition_time = 24,
908 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
909 .domain_info = rk3366_pm_domains,
912 static const struct rockchip_pmu_info rk3368_pmu = {
914 .status_offset = 0x10,
919 .core_pwrcnt_offset = 0x48,
920 .gpu_pwrcnt_offset = 0x50,
922 .core_power_transition_time = 24,
923 .gpu_power_transition_time = 24,
925 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
926 .domain_info = rk3368_pm_domains,
929 static const struct rockchip_pmu_info rk3399_pmu = {
931 .status_offset = 0x18,
936 /* ARM Trusted Firmware manages power transition times */
938 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
939 .domain_info = rk3399_pm_domains,
942 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
944 .compatible = "rockchip,px30-power-controller",
945 .data = (void *)&px30_pmu,
948 .compatible = "rockchip,rk3036-power-controller",
949 .data = (void *)&rk3036_pmu,
952 .compatible = "rockchip,rk3128-power-controller",
953 .data = (void *)&rk3128_pmu,
956 .compatible = "rockchip,rk3228-power-controller",
957 .data = (void *)&rk3228_pmu,
960 .compatible = "rockchip,rk3288-power-controller",
961 .data = (void *)&rk3288_pmu,
964 .compatible = "rockchip,rk3328-power-controller",
965 .data = (void *)&rk3328_pmu,
968 .compatible = "rockchip,rk3366-power-controller",
969 .data = (void *)&rk3366_pmu,
972 .compatible = "rockchip,rk3368-power-controller",
973 .data = (void *)&rk3368_pmu,
976 .compatible = "rockchip,rk3399-power-controller",
977 .data = (void *)&rk3399_pmu,
982 static struct platform_driver rockchip_pm_domain_driver = {
983 .probe = rockchip_pm_domain_probe,
985 .name = "rockchip-pm-domain",
986 .of_match_table = rockchip_pm_domain_dt_match,
988 * We can't forcibly eject devices form power domain,
989 * so we can't really remove power domains once they
992 .suppress_bind_attrs = true,
996 static int __init rockchip_pm_domain_drv_register(void)
998 return platform_driver_register(&rockchip_pm_domain_driver);
1000 postcore_initcall(rockchip_pm_domain_drv_register);