1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 #include <linux/acpi.h>
6 #include <linux/slab.h>
7 #include <linux/dma-mapping.h>
9 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <linux/pinctrl/consumer.h>
13 #include <linux/platform_device.h>
14 #include <linux/qcom-geni-se.h>
19 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
20 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
21 * controller. QUP Wrapper is designed to support various serial bus protocols
22 * like UART, SPI, I2C, I3C, etc.
26 * DOC: Hardware description
28 * GENI based QUP is a highly-flexible and programmable module for supporting
29 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
30 * QUP module can provide upto 8 serial interfaces, using its internal
31 * serial engines. The actual configuration is determined by the target
32 * platform configuration. The protocol supported by each interface is
33 * determined by the firmware loaded to the serial engine. Each SE consists
34 * of a DMA Engine and GENI sub modules which enable serial engines to
35 * support FIFO and DMA modes of operation.
38 * +-----------------------------------------+
40 * | +----------------------------+ |
41 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
42 * | | ... | | Interface
43 * <---Clock Perf.----+ +----+-----------------------+ | |
44 * State Interface | | Serial Engine 1 | | |
47 * <--------AHB-------> | | | |
51 * <------SE IRQ------+ +----------------------------+ |
53 * +-----------------------------------------+
55 * Figure 1: GENI based QUP Wrapper
57 * The GENI submodules include primary and secondary sequencers which are
58 * used to drive TX & RX operations. On serial interfaces that operate using
59 * master-slave model, primary sequencer drives both TX & RX operations. On
60 * serial interfaces that operate using peer-to-peer model, primary sequencer
61 * drives TX operation and secondary sequencer drives RX operation.
65 * DOC: Software description
67 * GENI SE Wrapper driver is structured into 2 parts:
69 * geni_wrapper represents QUP Wrapper controller. This part of the driver
70 * manages QUP Wrapper information such as hardware version, clock
71 * performance table that is common to all the internal serial engines.
73 * geni_se represents serial engine. This part of the driver manages serial
74 * engine information such as clocks, containing QUP Wrapper, etc. This part
75 * of driver also supports operations (eg. initialize the concerned serial
76 * engine, select between FIFO and DMA mode of operation etc.) that are
77 * common to all the serial engines and are independent of serial interfaces.
80 #define MAX_CLK_PERF_LEVEL 32
81 #define NUM_AHB_CLKS 2
84 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
85 * @dev: Device pointer of the QUP wrapper core
86 * @base: Base address of this instance of QUP wrapper core
87 * @ahb_clks: Handle to the primary & secondary AHB clocks
92 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
95 #define QUP_HW_VER_REG 0x4
97 /* Common SE registers */
98 #define GENI_INIT_CFG_REVISION 0x0
99 #define GENI_S_INIT_CFG_REVISION 0x4
100 #define GENI_OUTPUT_CTRL 0x24
101 #define GENI_CGC_CTRL 0x28
102 #define GENI_CLK_CTRL_RO 0x60
103 #define GENI_IF_DISABLE_RO 0x64
104 #define GENI_FW_S_REVISION_RO 0x6c
105 #define SE_GENI_BYTE_GRAN 0x254
106 #define SE_GENI_TX_PACKING_CFG0 0x260
107 #define SE_GENI_TX_PACKING_CFG1 0x264
108 #define SE_GENI_RX_PACKING_CFG0 0x284
109 #define SE_GENI_RX_PACKING_CFG1 0x288
110 #define SE_GENI_M_GP_LENGTH 0x910
111 #define SE_GENI_S_GP_LENGTH 0x914
112 #define SE_DMA_TX_PTR_L 0xc30
113 #define SE_DMA_TX_PTR_H 0xc34
114 #define SE_DMA_TX_ATTR 0xc38
115 #define SE_DMA_TX_LEN 0xc3c
116 #define SE_DMA_TX_IRQ_EN 0xc48
117 #define SE_DMA_TX_IRQ_EN_SET 0xc4c
118 #define SE_DMA_TX_IRQ_EN_CLR 0xc50
119 #define SE_DMA_TX_LEN_IN 0xc54
120 #define SE_DMA_TX_MAX_BURST 0xc5c
121 #define SE_DMA_RX_PTR_L 0xd30
122 #define SE_DMA_RX_PTR_H 0xd34
123 #define SE_DMA_RX_ATTR 0xd38
124 #define SE_DMA_RX_LEN 0xd3c
125 #define SE_DMA_RX_IRQ_EN 0xd48
126 #define SE_DMA_RX_IRQ_EN_SET 0xd4c
127 #define SE_DMA_RX_IRQ_EN_CLR 0xd50
128 #define SE_DMA_RX_LEN_IN 0xd54
129 #define SE_DMA_RX_MAX_BURST 0xd5c
130 #define SE_DMA_RX_FLUSH 0xd60
131 #define SE_GSI_EVENT_EN 0xe18
132 #define SE_IRQ_EN 0xe1c
133 #define SE_DMA_GENERAL_CFG 0xe30
135 /* GENI_OUTPUT_CTRL fields */
136 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
138 /* GENI_CGC_CTRL fields */
139 #define CFG_AHB_CLK_CGC_ON BIT(0)
140 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
141 #define DATA_AHB_CLK_CGC_ON BIT(2)
142 #define SCLK_CGC_ON BIT(3)
143 #define TX_CLK_CGC_ON BIT(4)
144 #define RX_CLK_CGC_ON BIT(5)
145 #define EXT_CLK_CGC_ON BIT(6)
146 #define PROG_RAM_HCLK_OFF BIT(8)
147 #define PROG_RAM_SCLK_OFF BIT(9)
148 #define DEFAULT_CGC_EN GENMASK(6, 0)
150 /* SE_GSI_EVENT_EN fields */
151 #define DMA_RX_EVENT_EN BIT(0)
152 #define DMA_TX_EVENT_EN BIT(1)
153 #define GENI_M_EVENT_EN BIT(2)
154 #define GENI_S_EVENT_EN BIT(3)
156 /* SE_IRQ_EN fields */
157 #define DMA_RX_IRQ_EN BIT(0)
158 #define DMA_TX_IRQ_EN BIT(1)
159 #define GENI_M_IRQ_EN BIT(2)
160 #define GENI_S_IRQ_EN BIT(3)
162 /* SE_DMA_GENERAL_CFG */
163 #define DMA_RX_CLK_CGC_ON BIT(0)
164 #define DMA_TX_CLK_CGC_ON BIT(1)
165 #define DMA_AHB_SLV_CFG_ON BIT(2)
166 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
167 #define DUMMY_RX_NON_BUFFERABLE BIT(4)
168 #define RX_DMA_ZERO_PADDING_EN BIT(5)
169 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
170 #define RX_DMA_IRQ_DELAY_SHFT 6
173 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
174 * @se: Pointer to the corresponding serial engine.
176 * Return: Hardware Version of the wrapper.
178 u32 geni_se_get_qup_hw_version(struct geni_se *se)
180 struct geni_wrapper *wrapper = se->wrapper;
182 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
184 EXPORT_SYMBOL(geni_se_get_qup_hw_version);
186 static void geni_se_io_set_mode(void __iomem *base)
190 val = readl_relaxed(base + SE_IRQ_EN);
191 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
192 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
193 writel_relaxed(val, base + SE_IRQ_EN);
195 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
196 val &= ~GENI_DMA_MODE_EN;
197 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
199 writel_relaxed(0, base + SE_GSI_EVENT_EN);
202 static void geni_se_io_init(void __iomem *base)
206 val = readl_relaxed(base + GENI_CGC_CTRL);
207 val |= DEFAULT_CGC_EN;
208 writel_relaxed(val, base + GENI_CGC_CTRL);
210 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
211 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
212 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
213 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
215 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
216 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
219 static void geni_se_irq_clear(struct geni_se *se)
221 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
222 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
223 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
224 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
225 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
226 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
230 * geni_se_init() - Initialize the GENI serial engine
231 * @se: Pointer to the concerned serial engine.
232 * @rx_wm: Receive watermark, in units of FIFO words.
233 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
235 * This function is used to initialize the GENI serial engine, configure
236 * receive watermark and ready-for-receive watermarks.
238 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
242 geni_se_irq_clear(se);
243 geni_se_io_init(se->base);
244 geni_se_io_set_mode(se->base);
246 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
247 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
249 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
250 val |= M_COMMON_GENI_M_IRQ_EN;
251 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
253 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
254 val |= S_COMMON_GENI_S_IRQ_EN;
255 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
257 EXPORT_SYMBOL(geni_se_init);
259 static void geni_se_select_fifo_mode(struct geni_se *se)
261 u32 proto = geni_se_read_proto(se);
264 geni_se_irq_clear(se);
266 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
267 if (proto != GENI_SE_UART) {
268 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
269 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
271 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
273 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
274 if (proto != GENI_SE_UART)
275 val |= S_CMD_DONE_EN;
276 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
278 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
279 val &= ~GENI_DMA_MODE_EN;
280 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
283 static void geni_se_select_dma_mode(struct geni_se *se)
285 u32 proto = geni_se_read_proto(se);
288 geni_se_irq_clear(se);
290 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
291 if (proto != GENI_SE_UART) {
292 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
293 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
295 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
297 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
298 if (proto != GENI_SE_UART)
299 val &= ~S_CMD_DONE_EN;
300 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
302 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
303 val |= GENI_DMA_MODE_EN;
304 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
308 * geni_se_select_mode() - Select the serial engine transfer mode
309 * @se: Pointer to the concerned serial engine.
310 * @mode: Transfer mode to be selected.
312 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
314 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
318 geni_se_select_fifo_mode(se);
321 geni_se_select_dma_mode(se);
323 case GENI_SE_INVALID:
328 EXPORT_SYMBOL(geni_se_select_mode);
333 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
334 * of up to 4 operations, each operation represented by 4 configuration vectors
335 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
336 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
337 * Refer to below examples for detailed bit-field description.
339 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
341 * +-----------+-------+-------+-------+-------+
342 * | | vec_0 | vec_1 | vec_2 | vec_3 |
343 * +-----------+-------+-------+-------+-------+
344 * | start | 0x6 | 0xe | 0x16 | 0x1e |
345 * | direction | 1 | 1 | 1 | 1 |
346 * | length | 6 | 6 | 6 | 6 |
347 * | stop | 0 | 0 | 0 | 1 |
348 * +-----------+-------+-------+-------+-------+
350 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
352 * +-----------+-------+-------+-------+-------+
353 * | | vec_0 | vec_1 | vec_2 | vec_3 |
354 * +-----------+-------+-------+-------+-------+
355 * | start | 0x0 | 0x8 | 0x10 | 0x18 |
356 * | direction | 0 | 0 | 0 | 0 |
357 * | length | 7 | 6 | 7 | 6 |
358 * | stop | 0 | 0 | 0 | 1 |
359 * +-----------+-------+-------+-------+-------+
361 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
363 * +-----------+-------+-------+-------+-------+
364 * | | vec_0 | vec_1 | vec_2 | vec_3 |
365 * +-----------+-------+-------+-------+-------+
366 * | start | 0x16 | 0xe | 0x6 | 0x0 |
367 * | direction | 1 | 1 | 1 | 1 |
368 * | length | 7 | 7 | 6 | 0 |
369 * | stop | 0 | 0 | 1 | 0 |
370 * +-----------+-------+-------+-------+-------+
374 #define NUM_PACKING_VECTORS 4
375 #define PACKING_START_SHIFT 5
376 #define PACKING_DIR_SHIFT 4
377 #define PACKING_LEN_SHIFT 1
378 #define PACKING_STOP_BIT BIT(0)
379 #define PACKING_VECTOR_SHIFT 10
381 * geni_se_config_packing() - Packing configuration of the serial engine
382 * @se: Pointer to the concerned serial engine
383 * @bpw: Bits of data per transfer word.
384 * @pack_words: Number of words per fifo element.
385 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
386 * @tx_cfg: Flag to configure the TX Packing.
387 * @rx_cfg: Flag to configure the RX Packing.
389 * This function is used to configure the packing rules for the current
392 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
393 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
395 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
398 int idx_start = msb_to_lsb ? bpw - 1 : 0;
400 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
401 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
402 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
405 if (iter <= 0 || iter > NUM_PACKING_VECTORS)
408 for (i = 0; i < iter; i++) {
409 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
410 cfg[i] = idx << PACKING_START_SHIFT;
411 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
412 cfg[i] |= len << PACKING_LEN_SHIFT;
414 if (temp_bpw <= BITS_PER_BYTE) {
415 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
418 idx = idx + idx_delta;
419 temp_bpw = temp_bpw - BITS_PER_BYTE;
422 cfg[iter - 1] |= PACKING_STOP_BIT;
423 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
424 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
427 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
428 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
431 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
432 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
436 * Number of protocol words in each FIFO entry
437 * 0 - 4x8, four words in each entry, max word size of 8 bits
438 * 1 - 2x16, two words in each entry, max word size of 16 bits
439 * 2 - 1x32, one word in each entry, max word size of 32 bits
442 if (pack_words || bpw == 32)
443 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
445 EXPORT_SYMBOL(geni_se_config_packing);
447 static void geni_se_clks_off(struct geni_se *se)
449 struct geni_wrapper *wrapper = se->wrapper;
451 clk_disable_unprepare(se->clk);
452 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
457 * geni_se_resources_off() - Turn off resources associated with the serial
459 * @se: Pointer to the concerned serial engine.
461 * Return: 0 on success, standard Linux error codes on failure/error.
463 int geni_se_resources_off(struct geni_se *se)
467 if (has_acpi_companion(se->dev))
470 ret = pinctrl_pm_select_sleep_state(se->dev);
474 geni_se_clks_off(se);
477 EXPORT_SYMBOL(geni_se_resources_off);
479 static int geni_se_clks_on(struct geni_se *se)
482 struct geni_wrapper *wrapper = se->wrapper;
484 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
489 ret = clk_prepare_enable(se->clk);
491 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
497 * geni_se_resources_on() - Turn on resources associated with the serial
499 * @se: Pointer to the concerned serial engine.
501 * Return: 0 on success, standard Linux error codes on failure/error.
503 int geni_se_resources_on(struct geni_se *se)
507 if (has_acpi_companion(se->dev))
510 ret = geni_se_clks_on(se);
514 ret = pinctrl_pm_select_default_state(se->dev);
516 geni_se_clks_off(se);
520 EXPORT_SYMBOL(geni_se_resources_on);
523 * geni_se_clk_tbl_get() - Get the clock table to program DFS
524 * @se: Pointer to the concerned serial engine.
525 * @tbl: Table in which the output is returned.
527 * This function is called by the protocol drivers to determine the different
528 * clock frequencies supported by serial engine core clock. The protocol
529 * drivers use the output to determine the clock frequency index to be
530 * programmed into DFS.
532 * Return: number of valid performance levels in the table on success,
533 * standard Linux error codes on failure.
535 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
540 if (se->clk_perf_tbl) {
541 *tbl = se->clk_perf_tbl;
542 return se->num_clk_levels;
545 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
546 sizeof(*se->clk_perf_tbl),
548 if (!se->clk_perf_tbl)
551 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
552 freq = clk_round_rate(se->clk, freq + 1);
553 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
555 se->clk_perf_tbl[i] = freq;
557 se->num_clk_levels = i;
558 *tbl = se->clk_perf_tbl;
559 return se->num_clk_levels;
561 EXPORT_SYMBOL(geni_se_clk_tbl_get);
564 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
565 * @se: Pointer to the concerned serial engine.
566 * @req_freq: Requested clock frequency.
567 * @index: Index of the resultant frequency in the table.
568 * @res_freq: Resultant frequency of the source clock.
569 * @exact: Flag to indicate exact multiple requirement of the requested
572 * This function is called by the protocol drivers to determine the best match
573 * of the requested frequency as provided by the serial engine clock in order
574 * to meet the performance requirements.
576 * If we return success:
577 * - if @exact is true then @res_freq / <an_integer> == @req_freq
578 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
580 * Return: 0 on success, standard Linux error codes on failure.
582 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
583 unsigned int *index, unsigned long *res_freq,
589 unsigned long best_delta;
590 unsigned long new_delta;
591 unsigned int divider;
593 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
594 if (num_clk_levels < 0)
595 return num_clk_levels;
597 if (num_clk_levels == 0)
600 best_delta = ULONG_MAX;
601 for (i = 0; i < num_clk_levels; i++) {
602 divider = DIV_ROUND_UP(tbl[i], req_freq);
603 new_delta = req_freq - tbl[i] / divider;
604 if (new_delta < best_delta) {
605 /* We have a new best! */
609 /* If the new best is exact then we're done */
613 /* Record how close we got */
614 best_delta = new_delta;
623 EXPORT_SYMBOL(geni_se_clk_freq_match);
625 #define GENI_SE_DMA_DONE_EN BIT(0)
626 #define GENI_SE_DMA_EOT_EN BIT(1)
627 #define GENI_SE_DMA_AHB_ERR_EN BIT(2)
628 #define GENI_SE_DMA_EOT_BUF BIT(0)
630 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
631 * @se: Pointer to the concerned serial engine.
632 * @buf: Pointer to the TX buffer.
633 * @len: Length of the TX buffer.
634 * @iova: Pointer to store the mapped DMA address.
636 * This function is used to prepare the buffers for DMA TX.
638 * Return: 0 on success, standard Linux error codes on failure.
640 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
643 struct geni_wrapper *wrapper = se->wrapper;
649 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
650 if (dma_mapping_error(wrapper->dev, *iova))
653 val = GENI_SE_DMA_DONE_EN;
654 val |= GENI_SE_DMA_EOT_EN;
655 val |= GENI_SE_DMA_AHB_ERR_EN;
656 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
657 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
658 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
659 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
660 writel(len, se->base + SE_DMA_TX_LEN);
663 EXPORT_SYMBOL(geni_se_tx_dma_prep);
666 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
667 * @se: Pointer to the concerned serial engine.
668 * @buf: Pointer to the RX buffer.
669 * @len: Length of the RX buffer.
670 * @iova: Pointer to store the mapped DMA address.
672 * This function is used to prepare the buffers for DMA RX.
674 * Return: 0 on success, standard Linux error codes on failure.
676 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
679 struct geni_wrapper *wrapper = se->wrapper;
685 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
686 if (dma_mapping_error(wrapper->dev, *iova))
689 val = GENI_SE_DMA_DONE_EN;
690 val |= GENI_SE_DMA_EOT_EN;
691 val |= GENI_SE_DMA_AHB_ERR_EN;
692 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
693 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
694 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
695 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
696 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
697 writel(len, se->base + SE_DMA_RX_LEN);
700 EXPORT_SYMBOL(geni_se_rx_dma_prep);
703 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
704 * @se: Pointer to the concerned serial engine.
705 * @iova: DMA address of the TX buffer.
706 * @len: Length of the TX buffer.
708 * This function is used to unprepare the DMA buffers after DMA TX.
710 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
712 struct geni_wrapper *wrapper = se->wrapper;
714 if (iova && !dma_mapping_error(wrapper->dev, iova))
715 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
717 EXPORT_SYMBOL(geni_se_tx_dma_unprep);
720 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
721 * @se: Pointer to the concerned serial engine.
722 * @iova: DMA address of the RX buffer.
723 * @len: Length of the RX buffer.
725 * This function is used to unprepare the DMA buffers after DMA RX.
727 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
729 struct geni_wrapper *wrapper = se->wrapper;
731 if (iova && !dma_mapping_error(wrapper->dev, iova))
732 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
734 EXPORT_SYMBOL(geni_se_rx_dma_unprep);
736 static int geni_se_probe(struct platform_device *pdev)
738 struct device *dev = &pdev->dev;
739 struct resource *res;
740 struct geni_wrapper *wrapper;
743 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
748 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
749 wrapper->base = devm_ioremap_resource(dev, res);
750 if (IS_ERR(wrapper->base))
751 return PTR_ERR(wrapper->base);
753 if (!has_acpi_companion(&pdev->dev)) {
754 wrapper->ahb_clks[0].id = "m-ahb";
755 wrapper->ahb_clks[1].id = "s-ahb";
756 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
758 dev_err(dev, "Err getting AHB clks %d\n", ret);
763 dev_set_drvdata(dev, wrapper);
764 dev_dbg(dev, "GENI SE Driver probed\n");
765 return devm_of_platform_populate(dev);
768 static const struct of_device_id geni_se_dt_match[] = {
769 { .compatible = "qcom,geni-se-qup", },
772 MODULE_DEVICE_TABLE(of, geni_se_dt_match);
774 static struct platform_driver geni_se_driver = {
776 .name = "geni_se_qup",
777 .of_match_table = geni_se_dt_match,
779 .probe = geni_se_probe,
781 module_platform_driver(geni_se_driver);
783 MODULE_DESCRIPTION("GENI Serial Engine Driver");
784 MODULE_LICENSE("GPL v2");