drivers/soc/mediatek/mtk-scpsys.c

   1 /*
   2  * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #include <linux/clk.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/soc/mediatek/infracfg.h>
  23
  24 #include <dt-bindings/power/mt2701-power.h>
  25 #include <dt-bindings/power/mt2712-power.h>
  26 #include <dt-bindings/power/mt6797-power.h>
  27 #include <dt-bindings/power/mt7622-power.h>
  28 #include <dt-bindings/power/mt7623a-power.h>
  29 #include <dt-bindings/power/mt8173-power.h>
  30
  31 #define MTK_POLL_DELAY_US   10
  32 #define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
  33
  34 #define MTK_SCPD_ACTIVE_WAKEUP          BIT(0)
  35 #define MTK_SCPD_FWAIT_SRAM             BIT(1)
  36 #define MTK_SCPD_CAPS(_scpd, _x)        ((_scpd)->data->caps & (_x))
  37
  38 #define SPM_VDE_PWR_CON                 0x0210
  39 #define SPM_MFG_PWR_CON                 0x0214
  40 #define SPM_VEN_PWR_CON                 0x0230
  41 #define SPM_ISP_PWR_CON                 0x0238
  42 #define SPM_DIS_PWR_CON                 0x023c
  43 #define SPM_CONN_PWR_CON                0x0280
  44 #define SPM_VEN2_PWR_CON                0x0298
  45 #define SPM_AUDIO_PWR_CON               0x029c  /* MT8173, MT2712 */
  46 #define SPM_BDP_PWR_CON                 0x029c  /* MT2701 */
  47 #define SPM_ETH_PWR_CON                 0x02a0
  48 #define SPM_HIF_PWR_CON                 0x02a4
  49 #define SPM_IFR_MSC_PWR_CON             0x02a8
  50 #define SPM_MFG_2D_PWR_CON              0x02c0
  51 #define SPM_MFG_ASYNC_PWR_CON           0x02c4
  52 #define SPM_USB_PWR_CON                 0x02cc
  53 #define SPM_USB2_PWR_CON                0x02d4  /* MT2712 */
  54 #define SPM_ETHSYS_PWR_CON              0x02e0  /* MT7622 */
  55 #define SPM_HIF0_PWR_CON                0x02e4  /* MT7622 */
  56 #define SPM_HIF1_PWR_CON                0x02e8  /* MT7622 */
  57 #define SPM_WB_PWR_CON                  0x02ec  /* MT7622 */
  58
  59 #define SPM_PWR_STATUS                  0x060c
  60 #define SPM_PWR_STATUS_2ND              0x0610
  61
  62 #define PWR_RST_B_BIT                   BIT(0)
  63 #define PWR_ISO_BIT                     BIT(1)
  64 #define PWR_ON_BIT                      BIT(2)
  65 #define PWR_ON_2ND_BIT                  BIT(3)
  66 #define PWR_CLK_DIS_BIT                 BIT(4)
  67
  68 #define PWR_STATUS_CONN                 BIT(1)
  69 #define PWR_STATUS_DISP                 BIT(3)
  70 #define PWR_STATUS_MFG                  BIT(4)
  71 #define PWR_STATUS_ISP                  BIT(5)
  72 #define PWR_STATUS_VDEC                 BIT(7)
  73 #define PWR_STATUS_BDP                  BIT(14)
  74 #define PWR_STATUS_ETH                  BIT(15)
  75 #define PWR_STATUS_HIF                  BIT(16)
  76 #define PWR_STATUS_IFR_MSC              BIT(17)
  77 #define PWR_STATUS_USB2                 BIT(19) /* MT2712 */
  78 #define PWR_STATUS_VENC_LT              BIT(20)
  79 #define PWR_STATUS_VENC                 BIT(21)
  80 #define PWR_STATUS_MFG_2D               BIT(22) /* MT8173 */
  81 #define PWR_STATUS_MFG_ASYNC            BIT(23) /* MT8173 */
  82 #define PWR_STATUS_AUDIO                BIT(24) /* MT8173, MT2712 */
  83 #define PWR_STATUS_USB                  BIT(25) /* MT8173, MT2712 */
  84 #define PWR_STATUS_ETHSYS               BIT(24) /* MT7622 */
  85 #define PWR_STATUS_HIF0                 BIT(25) /* MT7622 */
  86 #define PWR_STATUS_HIF1                 BIT(26) /* MT7622 */
  87 #define PWR_STATUS_WB                   BIT(27) /* MT7622 */
  88
  89 enum clk_id {
  90         CLK_NONE,
  91         CLK_MM,
  92         CLK_MFG,
  93         CLK_VENC,
  94         CLK_VENC_LT,
  95         CLK_ETHIF,
  96         CLK_VDEC,
  97         CLK_HIFSEL,
  98         CLK_JPGDEC,
  99         CLK_AUDIO,
 100         CLK_MAX,
 101 };
 102
 103 static const char * const clk_names[] = {
 104         NULL,
 105         "mm",
 106         "mfg",
 107         "venc",
 108         "venc_lt",
 109         "ethif",
 110         "vdec",
 111         "hif_sel",
 112         "jpgdec",
 113         "audio",
 114         NULL,
 115 };
 116
 117 #define MAX_CLKS        3
 118
 119 struct scp_domain_data {
 120         const char *name;
 121         u32 sta_mask;
 122         int ctl_offs;
 123         u32 sram_pdn_bits;
 124         u32 sram_pdn_ack_bits;
 125         u32 bus_prot_mask;
 126         enum clk_id clk_id[MAX_CLKS];
 127         u8 caps;
 128 };
 129
 130 struct scp;
 131
 132 struct scp_domain {
 133         struct generic_pm_domain genpd;
 134         struct scp *scp;
 135         struct clk *clk[MAX_CLKS];
 136         const struct scp_domain_data *data;
 137         struct regulator *supply;
 138 };
 139
 140 struct scp_ctrl_reg {
 141         int pwr_sta_offs;
 142         int pwr_sta2nd_offs;
 143 };
 144
 145 struct scp {
 146         struct scp_domain *domains;
 147         struct genpd_onecell_data pd_data;
 148         struct device *dev;
 149         void __iomem *base;
 150         struct regmap *infracfg;
 151         struct scp_ctrl_reg ctrl_reg;
 152         bool bus_prot_reg_update;
 153 };
 154
 155 struct scp_subdomain {
 156         int origin;
 157         int subdomain;
 158 };
 159
 160 struct scp_soc_data {
 161         const struct scp_domain_data *domains;
 162         int num_domains;
 163         const struct scp_subdomain *subdomains;
 164         int num_subdomains;
 165         const struct scp_ctrl_reg regs;
 166         bool bus_prot_reg_update;
 167 };
 168
 169 static int scpsys_domain_is_on(struct scp_domain *scpd)
 170 {
 171         struct scp *scp = scpd->scp;
 172
 173         u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) &
 174                                                 scpd->data->sta_mask;
 175         u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) &
 176                                                 scpd->data->sta_mask;
 177
 178         /*
 179          * A domain is on when both status bits are set. If only one is set
 180          * return an error. This happens while powering up a domain
 181          */
 182
 183         if (status && status2)
 184                 return true;
 185         if (!status && !status2)
 186                 return false;
 187
 188         return -EINVAL;
 189 }
 190
 191 static int scpsys_power_on(struct generic_pm_domain *genpd)
 192 {
 193         struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
 194         struct scp *scp = scpd->scp;
 195         void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
 196         u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
 197         u32 val;
 198         int ret, tmp;
 199         int i;
 200
 201         if (scpd->supply) {
 202                 ret = regulator_enable(scpd->supply);
 203                 if (ret)
 204                         return ret;
 205         }
 206
 207         for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
 208                 ret = clk_prepare_enable(scpd->clk[i]);
 209                 if (ret) {
 210                         for (--i; i >= 0; i--)
 211                                 clk_disable_unprepare(scpd->clk[i]);
 212
 213                         goto err_clk;
 214                 }
 215         }
 216
 217         val = readl(ctl_addr);
 218         val |= PWR_ON_BIT;
 219         writel(val, ctl_addr);
 220         val |= PWR_ON_2ND_BIT;
 221         writel(val, ctl_addr);
 222
 223         /* wait until PWR_ACK = 1 */
 224         ret = readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp > 0,
 225                                  MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
 226         if (ret < 0)
 227                 goto err_pwr_ack;
 228
 229         val &= ~PWR_CLK_DIS_BIT;
 230         writel(val, ctl_addr);
 231
 232         val &= ~PWR_ISO_BIT;
 233         writel(val, ctl_addr);
 234
 235         val |= PWR_RST_B_BIT;
 236         writel(val, ctl_addr);
 237
 238         val &= ~scpd->data->sram_pdn_bits;
 239         writel(val, ctl_addr);
 240
 241         /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
 242         if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
 243                 /*
 244                  * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
 245                  * MT7622_POWER_DOMAIN_WB and thus just a trivial setup is
 246                  * applied here.
 247                  */
 248                 usleep_range(12000, 12100);
 249
 250         } else {
 251                 ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
 252                                          MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
 253                 if (ret < 0)
 254                         goto err_pwr_ack;
 255         }
 256
 257         if (scpd->data->bus_prot_mask) {
 258                 ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
 259                                 scpd->data->bus_prot_mask,
 260                                 scp->bus_prot_reg_update);
 261                 if (ret)
 262                         goto err_pwr_ack;
 263         }
 264
 265         return 0;
 266
 267 err_pwr_ack:
 268         for (i = MAX_CLKS - 1; i >= 0; i--) {
 269                 if (scpd->clk[i])
 270                         clk_disable_unprepare(scpd->clk[i]);
 271         }
 272 err_clk:
 273         if (scpd->supply)
 274                 regulator_disable(scpd->supply);
 275
 276         dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
 277
 278         return ret;
 279 }
 280
 281 static int scpsys_power_off(struct generic_pm_domain *genpd)
 282 {
 283         struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
 284         struct scp *scp = scpd->scp;
 285         void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
 286         u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
 287         u32 val;
 288         int ret, tmp;
 289         int i;
 290
 291         if (scpd->data->bus_prot_mask) {
 292                 ret = mtk_infracfg_set_bus_protection(scp->infracfg,
 293                                 scpd->data->bus_prot_mask,
 294                                 scp->bus_prot_reg_update);
 295                 if (ret)
 296                         goto out;
 297         }
 298
 299         val = readl(ctl_addr);
 300         val |= scpd->data->sram_pdn_bits;
 301         writel(val, ctl_addr);
 302
 303         /* wait until SRAM_PDN_ACK all 1 */
 304         ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
 305                                  MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
 306         if (ret < 0)
 307                 goto out;
 308
 309         val |= PWR_ISO_BIT;
 310         writel(val, ctl_addr);
 311
 312         val &= ~PWR_RST_B_BIT;
 313         writel(val, ctl_addr);
 314
 315         val |= PWR_CLK_DIS_BIT;
 316         writel(val, ctl_addr);
 317
 318         val &= ~PWR_ON_BIT;
 319         writel(val, ctl_addr);
 320
 321         val &= ~PWR_ON_2ND_BIT;
 322         writel(val, ctl_addr);
 323
 324         /* wait until PWR_ACK = 0 */
 325         ret = readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp == 0,
 326                                  MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
 327         if (ret < 0)
 328                 goto out;
 329
 330         for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
 331                 clk_disable_unprepare(scpd->clk[i]);
 332
 333         if (scpd->supply)
 334                 regulator_disable(scpd->supply);
 335
 336         return 0;
 337
 338 out:
 339         dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
 340
 341         return ret;
 342 }
 343
 344 static void init_clks(struct platform_device *pdev, struct clk **clk)
 345 {
 346         int i;
 347
 348         for (i = CLK_NONE + 1; i < CLK_MAX; i++)
 349                 clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
 350 }
 351
 352 static struct scp *init_scp(struct platform_device *pdev,
 353                         const struct scp_domain_data *scp_domain_data, int num,
 354                         const struct scp_ctrl_reg *scp_ctrl_reg,
 355                         bool bus_prot_reg_update)
 356 {
 357         struct genpd_onecell_data *pd_data;
 358         struct resource *res;
 359         int i, j;
 360         struct scp *scp;
 361         struct clk *clk[CLK_MAX];
 362
 363         scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
 364         if (!scp)
 365                 return ERR_PTR(-ENOMEM);
 366
 367         scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
 368         scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
 369
 370         scp->bus_prot_reg_update = bus_prot_reg_update;
 371
 372         scp->dev = &pdev->dev;
 373
 374         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 375         scp->base = devm_ioremap_resource(&pdev->dev, res);
 376         if (IS_ERR(scp->base))
 377                 return ERR_CAST(scp->base);
 378
 379         scp->domains = devm_kcalloc(&pdev->dev,
 380                                 num, sizeof(*scp->domains), GFP_KERNEL);
 381         if (!scp->domains)
 382                 return ERR_PTR(-ENOMEM);
 383
 384         pd_data = &scp->pd_data;
 385
 386         pd_data->domains = devm_kcalloc(&pdev->dev,
 387                         num, sizeof(*pd_data->domains), GFP_KERNEL);
 388         if (!pd_data->domains)
 389                 return ERR_PTR(-ENOMEM);
 390
 391         scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 392                         "infracfg");
 393         if (IS_ERR(scp->infracfg)) {
 394                 dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
 395                                 PTR_ERR(scp->infracfg));
 396                 return ERR_CAST(scp->infracfg);
 397         }
 398
 399         for (i = 0; i < num; i++) {
 400                 struct scp_domain *scpd = &scp->domains[i];
 401                 const struct scp_domain_data *data = &scp_domain_data[i];
 402
 403                 scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
 404                 if (IS_ERR(scpd->supply)) {
 405                         if (PTR_ERR(scpd->supply) == -ENODEV)
 406                                 scpd->supply = NULL;
 407                         else
 408                                 return ERR_CAST(scpd->supply);
 409                 }
 410         }
 411
 412         pd_data->num_domains = num;
 413
 414         init_clks(pdev, clk);
 415
 416         for (i = 0; i < num; i++) {
 417                 struct scp_domain *scpd = &scp->domains[i];
 418                 struct generic_pm_domain *genpd = &scpd->genpd;
 419                 const struct scp_domain_data *data = &scp_domain_data[i];
 420
 421                 pd_data->domains[i] = genpd;
 422                 scpd->scp = scp;
 423
 424                 scpd->data = data;
 425
 426                 for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
 427                         struct clk *c = clk[data->clk_id[j]];
 428
 429                         if (IS_ERR(c)) {
 430                                 dev_err(&pdev->dev, "%s: clk unavailable\n",
 431                                         data->name);
 432                                 return ERR_CAST(c);
 433                         }
 434
 435                         scpd->clk[j] = c;
 436                 }
 437
 438                 genpd->name = data->name;
 439                 genpd->power_off = scpsys_power_off;
 440                 genpd->power_on = scpsys_power_on;
 441                 if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP))
 442                         genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP;
 443         }
 444
 445         return scp;
 446 }
 447
 448 static void mtk_register_power_domains(struct platform_device *pdev,
 449                                 struct scp *scp, int num)
 450 {
 451         struct genpd_onecell_data *pd_data;
 452         int i, ret;
 453
 454         for (i = 0; i < num; i++) {
 455                 struct scp_domain *scpd = &scp->domains[i];
 456                 struct generic_pm_domain *genpd = &scpd->genpd;
 457                 bool on;
 458
 459                 /*
 460                  * Initially turn on all domains to make the domains usable
 461                  * with !CONFIG_PM and to get the hardware in sync with the
 462                  * software.  The unused domains will be switched off during
 463                  * late_init time.
 464                  */
 465                 on = !WARN_ON(genpd->power_on(genpd) < 0);
 466
 467                 pm_genpd_init(genpd, NULL, !on);
 468         }
 469
 470         /*
 471          * We are not allowed to fail here since there is no way to unregister
 472          * a power domain. Once registered above we have to keep the domains
 473          * valid.
 474          */
 475
 476         pd_data = &scp->pd_data;
 477
 478         ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
 479         if (ret)
 480                 dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
 481 }
 482
 483 /*
 484  * MT2701 power domain support
 485  */
 486
 487 static const struct scp_domain_data scp_domain_data_mt2701[] = {
 488         [MT2701_POWER_DOMAIN_CONN] = {
 489                 .name = "conn",
 490                 .sta_mask = PWR_STATUS_CONN,
 491                 .ctl_offs = SPM_CONN_PWR_CON,
 492                 .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
 493                                  MT2701_TOP_AXI_PROT_EN_CONN_S,
 494                 .clk_id = {CLK_NONE},
 495                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 496         },
 497         [MT2701_POWER_DOMAIN_DISP] = {
 498                 .name = "disp",
 499                 .sta_mask = PWR_STATUS_DISP,
 500                 .ctl_offs = SPM_DIS_PWR_CON,
 501                 .sram_pdn_bits = GENMASK(11, 8),
 502                 .clk_id = {CLK_MM},
 503                 .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
 504                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 505         },
 506         [MT2701_POWER_DOMAIN_MFG] = {
 507                 .name = "mfg",
 508                 .sta_mask = PWR_STATUS_MFG,
 509                 .ctl_offs = SPM_MFG_PWR_CON,
 510                 .sram_pdn_bits = GENMASK(11, 8),
 511                 .sram_pdn_ack_bits = GENMASK(12, 12),
 512                 .clk_id = {CLK_MFG},
 513                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 514         },
 515         [MT2701_POWER_DOMAIN_VDEC] = {
 516                 .name = "vdec",
 517                 .sta_mask = PWR_STATUS_VDEC,
 518                 .ctl_offs = SPM_VDE_PWR_CON,
 519                 .sram_pdn_bits = GENMASK(11, 8),
 520                 .sram_pdn_ack_bits = GENMASK(12, 12),
 521                 .clk_id = {CLK_MM},
 522                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 523         },
 524         [MT2701_POWER_DOMAIN_ISP] = {
 525                 .name = "isp",
 526                 .sta_mask = PWR_STATUS_ISP,
 527                 .ctl_offs = SPM_ISP_PWR_CON,
 528                 .sram_pdn_bits = GENMASK(11, 8),
 529                 .sram_pdn_ack_bits = GENMASK(13, 12),
 530                 .clk_id = {CLK_MM},
 531                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 532         },
 533         [MT2701_POWER_DOMAIN_BDP] = {
 534                 .name = "bdp",
 535                 .sta_mask = PWR_STATUS_BDP,
 536                 .ctl_offs = SPM_BDP_PWR_CON,
 537                 .sram_pdn_bits = GENMASK(11, 8),
 538                 .clk_id = {CLK_NONE},
 539                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 540         },
 541         [MT2701_POWER_DOMAIN_ETH] = {
 542                 .name = "eth",
 543                 .sta_mask = PWR_STATUS_ETH,
 544                 .ctl_offs = SPM_ETH_PWR_CON,
 545                 .sram_pdn_bits = GENMASK(11, 8),
 546                 .sram_pdn_ack_bits = GENMASK(15, 12),
 547                 .clk_id = {CLK_ETHIF},
 548                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 549         },
 550         [MT2701_POWER_DOMAIN_HIF] = {
 551                 .name = "hif",
 552                 .sta_mask = PWR_STATUS_HIF,
 553                 .ctl_offs = SPM_HIF_PWR_CON,
 554                 .sram_pdn_bits = GENMASK(11, 8),
 555                 .sram_pdn_ack_bits = GENMASK(15, 12),
 556                 .clk_id = {CLK_ETHIF},
 557                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 558         },
 559         [MT2701_POWER_DOMAIN_IFR_MSC] = {
 560                 .name = "ifr_msc",
 561                 .sta_mask = PWR_STATUS_IFR_MSC,
 562                 .ctl_offs = SPM_IFR_MSC_PWR_CON,
 563                 .clk_id = {CLK_NONE},
 564                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 565         },
 566 };
 567
 568 /*
 569  * MT2712 power domain support
 570  */
 571 static const struct scp_domain_data scp_domain_data_mt2712[] = {
 572         [MT2712_POWER_DOMAIN_MM] = {
 573                 .name = "mm",
 574                 .sta_mask = PWR_STATUS_DISP,
 575                 .ctl_offs = SPM_DIS_PWR_CON,
 576                 .sram_pdn_bits = GENMASK(8, 8),
 577                 .sram_pdn_ack_bits = GENMASK(12, 12),
 578                 .clk_id = {CLK_MM},
 579                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 580         },
 581         [MT2712_POWER_DOMAIN_VDEC] = {
 582                 .name = "vdec",
 583                 .sta_mask = PWR_STATUS_VDEC,
 584                 .ctl_offs = SPM_VDE_PWR_CON,
 585                 .sram_pdn_bits = GENMASK(8, 8),
 586                 .sram_pdn_ack_bits = GENMASK(12, 12),
 587                 .clk_id = {CLK_MM, CLK_VDEC},
 588                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 589         },
 590         [MT2712_POWER_DOMAIN_VENC] = {
 591                 .name = "venc",
 592                 .sta_mask = PWR_STATUS_VENC,
 593                 .ctl_offs = SPM_VEN_PWR_CON,
 594                 .sram_pdn_bits = GENMASK(11, 8),
 595                 .sram_pdn_ack_bits = GENMASK(15, 12),
 596                 .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
 597                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 598         },
 599         [MT2712_POWER_DOMAIN_ISP] = {
 600                 .name = "isp",
 601                 .sta_mask = PWR_STATUS_ISP,
 602                 .ctl_offs = SPM_ISP_PWR_CON,
 603                 .sram_pdn_bits = GENMASK(11, 8),
 604                 .sram_pdn_ack_bits = GENMASK(13, 12),
 605                 .clk_id = {CLK_MM},
 606                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 607         },
 608         [MT2712_POWER_DOMAIN_AUDIO] = {
 609                 .name = "audio",
 610                 .sta_mask = PWR_STATUS_AUDIO,
 611                 .ctl_offs = SPM_AUDIO_PWR_CON,
 612                 .sram_pdn_bits = GENMASK(11, 8),
 613                 .sram_pdn_ack_bits = GENMASK(15, 12),
 614                 .clk_id = {CLK_AUDIO},
 615                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 616         },
 617         [MT2712_POWER_DOMAIN_USB] = {
 618                 .name = "usb",
 619                 .sta_mask = PWR_STATUS_USB,
 620                 .ctl_offs = SPM_USB_PWR_CON,
 621                 .sram_pdn_bits = GENMASK(10, 8),
 622                 .sram_pdn_ack_bits = GENMASK(14, 12),
 623                 .clk_id = {CLK_NONE},
 624                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 625         },
 626         [MT2712_POWER_DOMAIN_USB2] = {
 627                 .name = "usb2",
 628                 .sta_mask = PWR_STATUS_USB2,
 629                 .ctl_offs = SPM_USB2_PWR_CON,
 630                 .sram_pdn_bits = GENMASK(10, 8),
 631                 .sram_pdn_ack_bits = GENMASK(14, 12),
 632                 .clk_id = {CLK_NONE},
 633                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 634         },
 635         [MT2712_POWER_DOMAIN_MFG] = {
 636                 .name = "mfg",
 637                 .sta_mask = PWR_STATUS_MFG,
 638                 .ctl_offs = SPM_MFG_PWR_CON,
 639                 .sram_pdn_bits = GENMASK(8, 8),
 640                 .sram_pdn_ack_bits = GENMASK(16, 16),
 641                 .clk_id = {CLK_MFG},
 642                 .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
 643                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 644         },
 645         [MT2712_POWER_DOMAIN_MFG_SC1] = {
 646                 .name = "mfg_sc1",
 647                 .sta_mask = BIT(22),
 648                 .ctl_offs = 0x02c0,
 649                 .sram_pdn_bits = GENMASK(8, 8),
 650                 .sram_pdn_ack_bits = GENMASK(16, 16),
 651                 .clk_id = {CLK_NONE},
 652                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 653         },
 654         [MT2712_POWER_DOMAIN_MFG_SC2] = {
 655                 .name = "mfg_sc2",
 656                 .sta_mask = BIT(23),
 657                 .ctl_offs = 0x02c4,
 658                 .sram_pdn_bits = GENMASK(8, 8),
 659                 .sram_pdn_ack_bits = GENMASK(16, 16),
 660                 .clk_id = {CLK_NONE},
 661                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 662         },
 663         [MT2712_POWER_DOMAIN_MFG_SC3] = {
 664                 .name = "mfg_sc3",
 665                 .sta_mask = BIT(30),
 666                 .ctl_offs = 0x01f8,
 667                 .sram_pdn_bits = GENMASK(8, 8),
 668                 .sram_pdn_ack_bits = GENMASK(16, 16),
 669                 .clk_id = {CLK_NONE},
 670                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 671         },
 672 };
 673
 674 static const struct scp_subdomain scp_subdomain_mt2712[] = {
 675         {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VDEC},
 676         {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VENC},
 677         {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_ISP},
 678         {MT2712_POWER_DOMAIN_MFG, MT2712_POWER_DOMAIN_MFG_SC1},
 679         {MT2712_POWER_DOMAIN_MFG_SC1, MT2712_POWER_DOMAIN_MFG_SC2},
 680         {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
 681 };
 682
 683 /*
 684  * MT6797 power domain support
 685  */
 686
 687 static const struct scp_domain_data scp_domain_data_mt6797[] = {
 688         [MT6797_POWER_DOMAIN_VDEC] = {
 689                 .name = "vdec",
 690                 .sta_mask = BIT(7),
 691                 .ctl_offs = 0x300,
 692                 .sram_pdn_bits = GENMASK(8, 8),
 693                 .sram_pdn_ack_bits = GENMASK(12, 12),
 694                 .clk_id = {CLK_VDEC},
 695         },
 696         [MT6797_POWER_DOMAIN_VENC] = {
 697                 .name = "venc",
 698                 .sta_mask = BIT(21),
 699                 .ctl_offs = 0x304,
 700                 .sram_pdn_bits = GENMASK(11, 8),
 701                 .sram_pdn_ack_bits = GENMASK(15, 12),
 702                 .clk_id = {CLK_NONE},
 703         },
 704         [MT6797_POWER_DOMAIN_ISP] = {
 705                 .name = "isp",
 706                 .sta_mask = BIT(5),
 707                 .ctl_offs = 0x308,
 708                 .sram_pdn_bits = GENMASK(9, 8),
 709                 .sram_pdn_ack_bits = GENMASK(13, 12),
 710                 .clk_id = {CLK_NONE},
 711         },
 712         [MT6797_POWER_DOMAIN_MM] = {
 713                 .name = "mm",
 714                 .sta_mask = BIT(3),
 715                 .ctl_offs = 0x30C,
 716                 .sram_pdn_bits = GENMASK(8, 8),
 717                 .sram_pdn_ack_bits = GENMASK(12, 12),
 718                 .clk_id = {CLK_MM},
 719                 .bus_prot_mask = (BIT(1) | BIT(2)),
 720         },
 721         [MT6797_POWER_DOMAIN_AUDIO] = {
 722                 .name = "audio",
 723                 .sta_mask = BIT(24),
 724                 .ctl_offs = 0x314,
 725                 .sram_pdn_bits = GENMASK(11, 8),
 726                 .sram_pdn_ack_bits = GENMASK(15, 12),
 727                 .clk_id = {CLK_NONE},
 728         },
 729         [MT6797_POWER_DOMAIN_MFG_ASYNC] = {
 730                 .name = "mfg_async",
 731                 .sta_mask = BIT(13),
 732                 .ctl_offs = 0x334,
 733                 .sram_pdn_bits = 0,
 734                 .sram_pdn_ack_bits = 0,
 735                 .clk_id = {CLK_MFG},
 736         },
 737         [MT6797_POWER_DOMAIN_MJC] = {
 738                 .name = "mjc",
 739                 .sta_mask = BIT(20),
 740                 .ctl_offs = 0x310,
 741                 .sram_pdn_bits = GENMASK(8, 8),
 742                 .sram_pdn_ack_bits = GENMASK(12, 12),
 743                 .clk_id = {CLK_NONE},
 744         },
 745 };
 746
 747 #define SPM_PWR_STATUS_MT6797           0x0180
 748 #define SPM_PWR_STATUS_2ND_MT6797       0x0184
 749
 750 static const struct scp_subdomain scp_subdomain_mt6797[] = {
 751         {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VDEC},
 752         {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_ISP},
 753         {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VENC},
 754         {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_MJC},
 755 };
 756
 757 /*
 758  * MT7622 power domain support
 759  */
 760
 761 static const struct scp_domain_data scp_domain_data_mt7622[] = {
 762         [MT7622_POWER_DOMAIN_ETHSYS] = {
 763                 .name = "ethsys",
 764                 .sta_mask = PWR_STATUS_ETHSYS,
 765                 .ctl_offs = SPM_ETHSYS_PWR_CON,
 766                 .sram_pdn_bits = GENMASK(11, 8),
 767                 .sram_pdn_ack_bits = GENMASK(15, 12),
 768                 .clk_id = {CLK_NONE},
 769                 .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
 770                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 771         },
 772         [MT7622_POWER_DOMAIN_HIF0] = {
 773                 .name = "hif0",
 774                 .sta_mask = PWR_STATUS_HIF0,
 775                 .ctl_offs = SPM_HIF0_PWR_CON,
 776                 .sram_pdn_bits = GENMASK(11, 8),
 777                 .sram_pdn_ack_bits = GENMASK(15, 12),
 778                 .clk_id = {CLK_HIFSEL},
 779                 .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
 780                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 781         },
 782         [MT7622_POWER_DOMAIN_HIF1] = {
 783                 .name = "hif1",
 784                 .sta_mask = PWR_STATUS_HIF1,
 785                 .ctl_offs = SPM_HIF1_PWR_CON,
 786                 .sram_pdn_bits = GENMASK(11, 8),
 787                 .sram_pdn_ack_bits = GENMASK(15, 12),
 788                 .clk_id = {CLK_HIFSEL},
 789                 .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
 790                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 791         },
 792         [MT7622_POWER_DOMAIN_WB] = {
 793                 .name = "wb",
 794                 .sta_mask = PWR_STATUS_WB,
 795                 .ctl_offs = SPM_WB_PWR_CON,
 796                 .sram_pdn_bits = 0,
 797                 .sram_pdn_ack_bits = 0,
 798                 .clk_id = {CLK_NONE},
 799                 .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
 800                 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
 801         },
 802 };
 803
 804 /*
 805  * MT7623A power domain support
 806  */
 807
 808 static const struct scp_domain_data scp_domain_data_mt7623a[] = {
 809         [MT7623A_POWER_DOMAIN_CONN] = {
 810                 .name = "conn",
 811                 .sta_mask = PWR_STATUS_CONN,
 812                 .ctl_offs = SPM_CONN_PWR_CON,
 813                 .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
 814                                  MT2701_TOP_AXI_PROT_EN_CONN_S,
 815                 .clk_id = {CLK_NONE},
 816                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 817         },
 818         [MT7623A_POWER_DOMAIN_ETH] = {
 819                 .name = "eth",
 820                 .sta_mask = PWR_STATUS_ETH,
 821                 .ctl_offs = SPM_ETH_PWR_CON,
 822                 .sram_pdn_bits = GENMASK(11, 8),
 823                 .sram_pdn_ack_bits = GENMASK(15, 12),
 824                 .clk_id = {CLK_ETHIF},
 825                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 826         },
 827         [MT7623A_POWER_DOMAIN_HIF] = {
 828                 .name = "hif",
 829                 .sta_mask = PWR_STATUS_HIF,
 830                 .ctl_offs = SPM_HIF_PWR_CON,
 831                 .sram_pdn_bits = GENMASK(11, 8),
 832                 .sram_pdn_ack_bits = GENMASK(15, 12),
 833                 .clk_id = {CLK_ETHIF},
 834                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 835         },
 836         [MT7623A_POWER_DOMAIN_IFR_MSC] = {
 837                 .name = "ifr_msc",
 838                 .sta_mask = PWR_STATUS_IFR_MSC,
 839                 .ctl_offs = SPM_IFR_MSC_PWR_CON,
 840                 .clk_id = {CLK_NONE},
 841                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 842         },
 843 };
 844
 845 /*
 846  * MT8173 power domain support
 847  */
 848
 849 static const struct scp_domain_data scp_domain_data_mt8173[] = {
 850         [MT8173_POWER_DOMAIN_VDEC] = {
 851                 .name = "vdec",
 852                 .sta_mask = PWR_STATUS_VDEC,
 853                 .ctl_offs = SPM_VDE_PWR_CON,
 854                 .sram_pdn_bits = GENMASK(11, 8),
 855                 .sram_pdn_ack_bits = GENMASK(12, 12),
 856                 .clk_id = {CLK_MM},
 857         },
 858         [MT8173_POWER_DOMAIN_VENC] = {
 859                 .name = "venc",
 860                 .sta_mask = PWR_STATUS_VENC,
 861                 .ctl_offs = SPM_VEN_PWR_CON,
 862                 .sram_pdn_bits = GENMASK(11, 8),
 863                 .sram_pdn_ack_bits = GENMASK(15, 12),
 864                 .clk_id = {CLK_MM, CLK_VENC},
 865         },
 866         [MT8173_POWER_DOMAIN_ISP] = {
 867                 .name = "isp",
 868                 .sta_mask = PWR_STATUS_ISP,
 869                 .ctl_offs = SPM_ISP_PWR_CON,
 870                 .sram_pdn_bits = GENMASK(11, 8),
 871                 .sram_pdn_ack_bits = GENMASK(13, 12),
 872                 .clk_id = {CLK_MM},
 873         },
 874         [MT8173_POWER_DOMAIN_MM] = {
 875                 .name = "mm",
 876                 .sta_mask = PWR_STATUS_DISP,
 877                 .ctl_offs = SPM_DIS_PWR_CON,
 878                 .sram_pdn_bits = GENMASK(11, 8),
 879                 .sram_pdn_ack_bits = GENMASK(12, 12),
 880                 .clk_id = {CLK_MM},
 881                 .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
 882                         MT8173_TOP_AXI_PROT_EN_MM_M1,
 883         },
 884         [MT8173_POWER_DOMAIN_VENC_LT] = {
 885                 .name = "venc_lt",
 886                 .sta_mask = PWR_STATUS_VENC_LT,
 887                 .ctl_offs = SPM_VEN2_PWR_CON,
 888                 .sram_pdn_bits = GENMASK(11, 8),
 889                 .sram_pdn_ack_bits = GENMASK(15, 12),
 890                 .clk_id = {CLK_MM, CLK_VENC_LT},
 891         },
 892         [MT8173_POWER_DOMAIN_AUDIO] = {
 893                 .name = "audio",
 894                 .sta_mask = PWR_STATUS_AUDIO,
 895                 .ctl_offs = SPM_AUDIO_PWR_CON,
 896                 .sram_pdn_bits = GENMASK(11, 8),
 897                 .sram_pdn_ack_bits = GENMASK(15, 12),
 898                 .clk_id = {CLK_NONE},
 899         },
 900         [MT8173_POWER_DOMAIN_USB] = {
 901                 .name = "usb",
 902                 .sta_mask = PWR_STATUS_USB,
 903                 .ctl_offs = SPM_USB_PWR_CON,
 904                 .sram_pdn_bits = GENMASK(11, 8),
 905                 .sram_pdn_ack_bits = GENMASK(15, 12),
 906                 .clk_id = {CLK_NONE},
 907                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
 908         },
 909         [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
 910                 .name = "mfg_async",
 911                 .sta_mask = PWR_STATUS_MFG_ASYNC,
 912                 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
 913                 .sram_pdn_bits = GENMASK(11, 8),
 914                 .sram_pdn_ack_bits = 0,
 915                 .clk_id = {CLK_MFG},
 916         },
 917         [MT8173_POWER_DOMAIN_MFG_2D] = {
 918                 .name = "mfg_2d",
 919                 .sta_mask = PWR_STATUS_MFG_2D,
 920                 .ctl_offs = SPM_MFG_2D_PWR_CON,
 921                 .sram_pdn_bits = GENMASK(11, 8),
 922                 .sram_pdn_ack_bits = GENMASK(13, 12),
 923                 .clk_id = {CLK_NONE},
 924         },
 925         [MT8173_POWER_DOMAIN_MFG] = {
 926                 .name = "mfg",
 927                 .sta_mask = PWR_STATUS_MFG,
 928                 .ctl_offs = SPM_MFG_PWR_CON,
 929                 .sram_pdn_bits = GENMASK(13, 8),
 930                 .sram_pdn_ack_bits = GENMASK(21, 16),
 931                 .clk_id = {CLK_NONE},
 932                 .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
 933                         MT8173_TOP_AXI_PROT_EN_MFG_M0 |
 934                         MT8173_TOP_AXI_PROT_EN_MFG_M1 |
 935                         MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
 936         },
 937 };
 938
 939 static const struct scp_subdomain scp_subdomain_mt8173[] = {
 940         {MT8173_POWER_DOMAIN_MFG_ASYNC, MT8173_POWER_DOMAIN_MFG_2D},
 941         {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
 942 };
 943
 944 static const struct scp_soc_data mt2701_data = {
 945         .domains = scp_domain_data_mt2701,
 946         .num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
 947         .regs = {
 948                 .pwr_sta_offs = SPM_PWR_STATUS,
 949                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
 950         },
 951         .bus_prot_reg_update = true,
 952 };
 953
 954 static const struct scp_soc_data mt2712_data = {
 955         .domains = scp_domain_data_mt2712,
 956         .num_domains = ARRAY_SIZE(scp_domain_data_mt2712),
 957         .subdomains = scp_subdomain_mt2712,
 958         .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
 959         .regs = {
 960                 .pwr_sta_offs = SPM_PWR_STATUS,
 961                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
 962         },
 963         .bus_prot_reg_update = false,
 964 };
 965
 966 static const struct scp_soc_data mt6797_data = {
 967         .domains = scp_domain_data_mt6797,
 968         .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
 969         .subdomains = scp_subdomain_mt6797,
 970         .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
 971         .regs = {
 972                 .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
 973                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
 974         },
 975         .bus_prot_reg_update = true,
 976 };
 977
 978 static const struct scp_soc_data mt7622_data = {
 979         .domains = scp_domain_data_mt7622,
 980         .num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
 981         .regs = {
 982                 .pwr_sta_offs = SPM_PWR_STATUS,
 983                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
 984         },
 985         .bus_prot_reg_update = true,
 986 };
 987
 988 static const struct scp_soc_data mt7623a_data = {
 989         .domains = scp_domain_data_mt7623a,
 990         .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
 991         .regs = {
 992                 .pwr_sta_offs = SPM_PWR_STATUS,
 993                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
 994         },
 995         .bus_prot_reg_update = true,
 996 };
 997
 998 static const struct scp_soc_data mt8173_data = {
 999         .domains = scp_domain_data_mt8173,
1000         .num_domains = ARRAY_SIZE(scp_domain_data_mt8173),
1001         .subdomains = scp_subdomain_mt8173,
1002         .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
1003         .regs = {
1004                 .pwr_sta_offs = SPM_PWR_STATUS,
1005                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
1006         },
1007         .bus_prot_reg_update = true,
1008 };
1009
1010 /*
1011  * scpsys driver init
1012  */
1013
1014 static const struct of_device_id of_scpsys_match_tbl[] = {
1015         {
1016                 .compatible = "mediatek,mt2701-scpsys",
1017                 .data = &mt2701_data,
1018         }, {
1019                 .compatible = "mediatek,mt2712-scpsys",
1020                 .data = &mt2712_data,
1021         }, {
1022                 .compatible = "mediatek,mt6797-scpsys",
1023                 .data = &mt6797_data,
1024         }, {
1025                 .compatible = "mediatek,mt7622-scpsys",
1026                 .data = &mt7622_data,
1027         }, {
1028                 .compatible = "mediatek,mt7623a-scpsys",
1029                 .data = &mt7623a_data,
1030         }, {
1031                 .compatible = "mediatek,mt8173-scpsys",
1032                 .data = &mt8173_data,
1033         }, {
1034                 /* sentinel */
1035         }
1036 };
1037
1038 static int scpsys_probe(struct platform_device *pdev)
1039 {
1040         const struct scp_subdomain *sd;
1041         const struct scp_soc_data *soc;
1042         struct scp *scp;
1043         struct genpd_onecell_data *pd_data;
1044         int i, ret;
1045
1046         soc = of_device_get_match_data(&pdev->dev);
1047
1048         scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
1049                         soc->bus_prot_reg_update);
1050         if (IS_ERR(scp))
1051                 return PTR_ERR(scp);
1052
1053         mtk_register_power_domains(pdev, scp, soc->num_domains);
1054
1055         pd_data = &scp->pd_data;
1056
1057         for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) {
1058                 ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
1059                                              pd_data->domains[sd->subdomain]);
1060                 if (ret && IS_ENABLED(CONFIG_PM))
1061                         dev_err(&pdev->dev, "Failed to add subdomain: %d\n",
1062                                 ret);
1063         }
1064
1065         return 0;
1066 }
1067
1068 static struct platform_driver scpsys_drv = {
1069         .probe = scpsys_probe,
1070         .driver = {
1071                 .name = "mtk-scpsys",
1072                 .suppress_bind_attrs = true,
1073                 .owner = THIS_MODULE,
1074                 .of_match_table = of_match_ptr(of_scpsys_match_tbl),
1075         },
1076 };
1077 builtin_platform_driver(scpsys_drv);