1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Flora Fu, MediaTek
7 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/reset.h>
16 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
17 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
18 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
19 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
20 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
21 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38
22 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
23 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
24 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
26 /* macro for wrapper status */
27 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
28 #define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007)
29 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
30 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
31 #define PWRAP_STATE_SYNC_IDLE0 BIT(20)
32 #define PWRAP_STATE_INIT_DONE0 BIT(21)
33 #define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22)
34 #define PWRAP_STATE_INIT_DONE1 BIT(15)
36 /* macro for WACS FSM */
37 #define PWRAP_WACS_FSM_IDLE 0x00
38 #define PWRAP_WACS_FSM_REQ 0x02
39 #define PWRAP_WACS_FSM_WFDLE 0x04
40 #define PWRAP_WACS_FSM_WFVLDCLR 0x06
41 #define PWRAP_WACS_INIT_DONE 0x01
42 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01
43 #define PWRAP_WACS_SYNC_BUSY 0x00
45 /* macro for device wrapper default value */
46 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5
47 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
49 /* macro for manual command */
50 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
51 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
52 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
53 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
54 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
55 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
56 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
57 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
59 /* macro for Watch Dog Timer Source */
60 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
61 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
62 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
63 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
64 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
65 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
66 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
68 /* Group of bits used for shown slave capability */
69 #define PWRAP_SLV_CAP_SPI BIT(0)
70 #define PWRAP_SLV_CAP_DUALIO BIT(1)
71 #define PWRAP_SLV_CAP_SECURITY BIT(2)
72 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
74 /* Group of bits used for shown pwrap capability */
75 #define PWRAP_CAP_BRIDGE BIT(0)
76 #define PWRAP_CAP_RESET BIT(1)
77 #define PWRAP_CAP_DCM BIT(2)
78 #define PWRAP_CAP_INT1_EN BIT(3)
79 #define PWRAP_CAP_WDT_SRC1 BIT(4)
80 #define PWRAP_CAP_ARB BIT(5)
81 #define PWRAP_CAP_ARB_MT8186 BIT(8)
83 /* defines for slave device wrapper registers */
91 PWRAP_DEW_MON_GRP_SEL,
92 PWRAP_DEW_CIPHER_KEY_SEL,
93 PWRAP_DEW_CIPHER_IV_SEL,
95 PWRAP_DEW_CIPHER_MODE,
96 PWRAP_DEW_CIPHER_SWRST,
98 /* MT6323 only regs */
102 /* MT6358 only regs */
106 PWRAP_GPIO_PULLEN0_CLR,
108 PWRAP_RG_SPI_RECORD0,
119 /* MT6359 only regs */
121 PWRAP_DEW_RG_EN_RECORD,
122 PWRAP_DEW_RECORD_CMD0,
123 PWRAP_DEW_RECORD_CMD1,
124 PWRAP_DEW_RECORD_CMD2,
125 PWRAP_DEW_RECORD_CMD3,
126 PWRAP_DEW_RECORD_CMD4,
127 PWRAP_DEW_RECORD_CMD5,
128 PWRAP_DEW_RECORD_WDATA0,
129 PWRAP_DEW_RECORD_WDATA1,
130 PWRAP_DEW_RECORD_WDATA2,
131 PWRAP_DEW_RECORD_WDATA3,
132 PWRAP_DEW_RECORD_WDATA4,
133 PWRAP_DEW_RECORD_WDATA5,
134 PWRAP_DEW_RG_ADDR_TARGET,
135 PWRAP_DEW_RG_ADDR_MASK,
136 PWRAP_DEW_RG_WDATA_TARGET,
137 PWRAP_DEW_RG_WDATA_MASK,
138 PWRAP_DEW_RG_SPI_RECORD_CLR,
139 PWRAP_DEW_RG_CMD_ALERT_CLR,
141 /* MT6397 only regs */
142 PWRAP_DEW_EVENT_OUT_EN,
143 PWRAP_DEW_EVENT_SRC_EN,
145 PWRAP_DEW_EVENT_FLAG,
146 PWRAP_DEW_MON_FLAG_SEL,
147 PWRAP_DEW_EVENT_TEST,
148 PWRAP_DEW_CIPHER_LOAD,
149 PWRAP_DEW_CIPHER_START,
152 static const u32 mt6323_regs[] = {
153 [PWRAP_DEW_BASE] = 0x0000,
154 [PWRAP_DEW_DIO_EN] = 0x018a,
155 [PWRAP_DEW_READ_TEST] = 0x018c,
156 [PWRAP_DEW_WRITE_TEST] = 0x018e,
157 [PWRAP_DEW_CRC_EN] = 0x0192,
158 [PWRAP_DEW_CRC_VAL] = 0x0194,
159 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
160 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
161 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
162 [PWRAP_DEW_CIPHER_EN] = 0x019c,
163 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
164 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
165 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
166 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
169 static const u32 mt6351_regs[] = {
170 [PWRAP_DEW_DIO_EN] = 0x02F2,
171 [PWRAP_DEW_READ_TEST] = 0x02F4,
172 [PWRAP_DEW_WRITE_TEST] = 0x02F6,
173 [PWRAP_DEW_CRC_EN] = 0x02FA,
174 [PWRAP_DEW_CRC_VAL] = 0x02FC,
175 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
176 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
177 [PWRAP_DEW_CIPHER_EN] = 0x0304,
178 [PWRAP_DEW_CIPHER_RDY] = 0x0306,
179 [PWRAP_DEW_CIPHER_MODE] = 0x0308,
180 [PWRAP_DEW_CIPHER_SWRST] = 0x030A,
181 [PWRAP_DEW_RDDMY_NO] = 0x030C,
184 static const u32 mt6357_regs[] = {
185 [PWRAP_DEW_DIO_EN] = 0x040A,
186 [PWRAP_DEW_READ_TEST] = 0x040C,
187 [PWRAP_DEW_WRITE_TEST] = 0x040E,
188 [PWRAP_DEW_CRC_EN] = 0x0412,
189 [PWRAP_DEW_CRC_VAL] = 0x0414,
190 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
191 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,
192 [PWRAP_DEW_CIPHER_EN] = 0x041C,
193 [PWRAP_DEW_CIPHER_RDY] = 0x041E,
194 [PWRAP_DEW_CIPHER_MODE] = 0x0420,
195 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
196 [PWRAP_DEW_RDDMY_NO] = 0x0424,
199 static const u32 mt6358_regs[] = {
200 [PWRAP_SMT_CON1] = 0x0030,
201 [PWRAP_DRV_CON1] = 0x0038,
202 [PWRAP_FILTER_CON0] = 0x0040,
203 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
204 [PWRAP_RG_SPI_CON0] = 0x0408,
205 [PWRAP_RG_SPI_RECORD0] = 0x040a,
206 [PWRAP_DEW_DIO_EN] = 0x040c,
207 [PWRAP_DEW_READ_TEST] = 0x040e,
208 [PWRAP_DEW_WRITE_TEST] = 0x0410,
209 [PWRAP_DEW_CRC_EN] = 0x0414,
210 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
211 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
212 [PWRAP_DEW_CIPHER_EN] = 0x041e,
213 [PWRAP_DEW_CIPHER_RDY] = 0x0420,
214 [PWRAP_DEW_CIPHER_MODE] = 0x0422,
215 [PWRAP_DEW_CIPHER_SWRST] = 0x0424,
216 [PWRAP_RG_SPI_CON2] = 0x0432,
217 [PWRAP_RG_SPI_CON3] = 0x0434,
218 [PWRAP_RG_SPI_CON4] = 0x0436,
219 [PWRAP_RG_SPI_CON5] = 0x0438,
220 [PWRAP_RG_SPI_CON6] = 0x043a,
221 [PWRAP_RG_SPI_CON7] = 0x043c,
222 [PWRAP_RG_SPI_CON8] = 0x043e,
223 [PWRAP_RG_SPI_CON13] = 0x0448,
224 [PWRAP_SPISLV_KEY] = 0x044a,
227 static const u32 mt6359_regs[] = {
228 [PWRAP_DEW_RG_EN_RECORD] = 0x040a,
229 [PWRAP_DEW_DIO_EN] = 0x040c,
230 [PWRAP_DEW_READ_TEST] = 0x040e,
231 [PWRAP_DEW_WRITE_TEST] = 0x0410,
232 [PWRAP_DEW_CRC_SWRST] = 0x0412,
233 [PWRAP_DEW_CRC_EN] = 0x0414,
234 [PWRAP_DEW_CRC_VAL] = 0x0416,
235 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
236 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
237 [PWRAP_DEW_CIPHER_EN] = 0x041c,
238 [PWRAP_DEW_CIPHER_RDY] = 0x041e,
239 [PWRAP_DEW_CIPHER_MODE] = 0x0420,
240 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
241 [PWRAP_DEW_RDDMY_NO] = 0x0424,
242 [PWRAP_DEW_RECORD_CMD0] = 0x0428,
243 [PWRAP_DEW_RECORD_CMD1] = 0x042a,
244 [PWRAP_DEW_RECORD_CMD2] = 0x042c,
245 [PWRAP_DEW_RECORD_CMD3] = 0x042e,
246 [PWRAP_DEW_RECORD_CMD4] = 0x0430,
247 [PWRAP_DEW_RECORD_CMD5] = 0x0432,
248 [PWRAP_DEW_RECORD_WDATA0] = 0x0434,
249 [PWRAP_DEW_RECORD_WDATA1] = 0x0436,
250 [PWRAP_DEW_RECORD_WDATA2] = 0x0438,
251 [PWRAP_DEW_RECORD_WDATA3] = 0x043a,
252 [PWRAP_DEW_RECORD_WDATA4] = 0x043c,
253 [PWRAP_DEW_RECORD_WDATA5] = 0x043e,
254 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
255 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
256 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
257 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
258 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
259 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
260 [PWRAP_SPISLV_KEY] = 0x044a,
263 static const u32 mt6397_regs[] = {
264 [PWRAP_DEW_BASE] = 0xbc00,
265 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
266 [PWRAP_DEW_DIO_EN] = 0xbc02,
267 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
268 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
269 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
270 [PWRAP_DEW_READ_TEST] = 0xbc0a,
271 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
272 [PWRAP_DEW_CRC_EN] = 0xbc0e,
273 [PWRAP_DEW_CRC_VAL] = 0xbc10,
274 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
275 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
276 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
277 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
278 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
279 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
280 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
281 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
282 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
283 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
297 PWRAP_STAUPD_MAN_TRIG,
339 PWRAP_CIPHER_KEY_SEL,
348 PWRAP_SWINF_2_WDATA_31_0,
349 PWRAP_SWINF_2_RDATA_31_0,
351 /* MT2701 only regs */
355 PWRAP_ADC_RDATA_ADDR1,
356 PWRAP_ADC_RDATA_ADDR2,
358 /* MT7622 only regs */
378 PWRAP_ADC_RDATA_ADDR,
381 PWRAP_DVFS_STEP_CTRL0,
382 PWRAP_DVFS_STEP_CTRL1,
383 PWRAP_DVFS_STEP_CTRL2,
386 /* MT8135 only regs */
399 /* MT8173 only regs */
421 /* MT8183 only regs */
422 PWRAP_SI_SAMPLE_CTRL,
430 PWRAP_INIT_DONE_MD32,
435 PWRAP_INT_GPS_AUXADC_CMD_ADDR,
436 PWRAP_INT_GPS_AUXADC_CMD,
437 PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
438 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
442 /* MT8516 only regs */
447 static int mt2701_regs[] = {
448 [PWRAP_MUX_SEL] = 0x0,
449 [PWRAP_WRAP_EN] = 0x4,
450 [PWRAP_DIO_EN] = 0x8,
452 [PWRAP_RDDMY] = 0x18,
453 [PWRAP_SI_CK_CON] = 0x1c,
454 [PWRAP_CSHEXT_WRITE] = 0x20,
455 [PWRAP_CSHEXT_READ] = 0x24,
456 [PWRAP_CSLEXT_START] = 0x28,
457 [PWRAP_CSLEXT_END] = 0x2c,
458 [PWRAP_STAUPD_PRD] = 0x30,
459 [PWRAP_STAUPD_GRPEN] = 0x34,
460 [PWRAP_STAUPD_MAN_TRIG] = 0x38,
461 [PWRAP_STAUPD_STA] = 0x3c,
462 [PWRAP_WRAP_STA] = 0x44,
463 [PWRAP_HARB_INIT] = 0x48,
464 [PWRAP_HARB_HPRIO] = 0x4c,
465 [PWRAP_HIPRIO_ARB_EN] = 0x50,
466 [PWRAP_HARB_STA0] = 0x54,
467 [PWRAP_HARB_STA1] = 0x58,
468 [PWRAP_MAN_EN] = 0x5c,
469 [PWRAP_MAN_CMD] = 0x60,
470 [PWRAP_MAN_RDATA] = 0x64,
471 [PWRAP_MAN_VLDCLR] = 0x68,
472 [PWRAP_WACS0_EN] = 0x6c,
473 [PWRAP_INIT_DONE0] = 0x70,
474 [PWRAP_WACS0_CMD] = 0x74,
475 [PWRAP_WACS0_RDATA] = 0x78,
476 [PWRAP_WACS0_VLDCLR] = 0x7c,
477 [PWRAP_WACS1_EN] = 0x80,
478 [PWRAP_INIT_DONE1] = 0x84,
479 [PWRAP_WACS1_CMD] = 0x88,
480 [PWRAP_WACS1_RDATA] = 0x8c,
481 [PWRAP_WACS1_VLDCLR] = 0x90,
482 [PWRAP_WACS2_EN] = 0x94,
483 [PWRAP_INIT_DONE2] = 0x98,
484 [PWRAP_WACS2_CMD] = 0x9c,
485 [PWRAP_WACS2_RDATA] = 0xa0,
486 [PWRAP_WACS2_VLDCLR] = 0xa4,
487 [PWRAP_INT_EN] = 0xa8,
488 [PWRAP_INT_FLG_RAW] = 0xac,
489 [PWRAP_INT_FLG] = 0xb0,
490 [PWRAP_INT_CLR] = 0xb4,
491 [PWRAP_SIG_ADR] = 0xb8,
492 [PWRAP_SIG_MODE] = 0xbc,
493 [PWRAP_SIG_VALUE] = 0xc0,
494 [PWRAP_SIG_ERRVAL] = 0xc4,
495 [PWRAP_CRC_EN] = 0xc8,
496 [PWRAP_TIMER_EN] = 0xcc,
497 [PWRAP_TIMER_STA] = 0xd0,
498 [PWRAP_WDT_UNIT] = 0xd4,
499 [PWRAP_WDT_SRC_EN] = 0xd8,
500 [PWRAP_WDT_FLG] = 0xdc,
501 [PWRAP_DEBUG_INT_SEL] = 0xe0,
502 [PWRAP_DVFS_ADR0] = 0xe4,
503 [PWRAP_DVFS_WDATA0] = 0xe8,
504 [PWRAP_DVFS_ADR1] = 0xec,
505 [PWRAP_DVFS_WDATA1] = 0xf0,
506 [PWRAP_DVFS_ADR2] = 0xf4,
507 [PWRAP_DVFS_WDATA2] = 0xf8,
508 [PWRAP_DVFS_ADR3] = 0xfc,
509 [PWRAP_DVFS_WDATA3] = 0x100,
510 [PWRAP_DVFS_ADR4] = 0x104,
511 [PWRAP_DVFS_WDATA4] = 0x108,
512 [PWRAP_DVFS_ADR5] = 0x10c,
513 [PWRAP_DVFS_WDATA5] = 0x110,
514 [PWRAP_DVFS_ADR6] = 0x114,
515 [PWRAP_DVFS_WDATA6] = 0x118,
516 [PWRAP_DVFS_ADR7] = 0x11c,
517 [PWRAP_DVFS_WDATA7] = 0x120,
518 [PWRAP_CIPHER_KEY_SEL] = 0x124,
519 [PWRAP_CIPHER_IV_SEL] = 0x128,
520 [PWRAP_CIPHER_EN] = 0x12c,
521 [PWRAP_CIPHER_RDY] = 0x130,
522 [PWRAP_CIPHER_MODE] = 0x134,
523 [PWRAP_CIPHER_SWRST] = 0x138,
524 [PWRAP_DCM_EN] = 0x13c,
525 [PWRAP_DCM_DBC_PRD] = 0x140,
526 [PWRAP_ADC_CMD_ADDR] = 0x144,
527 [PWRAP_PWRAP_ADC_CMD] = 0x148,
528 [PWRAP_ADC_RDY_ADDR] = 0x14c,
529 [PWRAP_ADC_RDATA_ADDR1] = 0x150,
530 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
533 static int mt6765_regs[] = {
534 [PWRAP_MUX_SEL] = 0x0,
535 [PWRAP_WRAP_EN] = 0x4,
536 [PWRAP_DIO_EN] = 0x8,
537 [PWRAP_RDDMY] = 0x20,
538 [PWRAP_CSHEXT_WRITE] = 0x24,
539 [PWRAP_CSHEXT_READ] = 0x28,
540 [PWRAP_CSLEXT_START] = 0x2C,
541 [PWRAP_CSLEXT_END] = 0x30,
542 [PWRAP_STAUPD_PRD] = 0x3C,
543 [PWRAP_HARB_HPRIO] = 0x68,
544 [PWRAP_HIPRIO_ARB_EN] = 0x6C,
545 [PWRAP_MAN_EN] = 0x7C,
546 [PWRAP_MAN_CMD] = 0x80,
547 [PWRAP_WACS0_EN] = 0x8C,
548 [PWRAP_WACS1_EN] = 0x94,
549 [PWRAP_WACS2_EN] = 0x9C,
550 [PWRAP_INIT_DONE2] = 0xA0,
551 [PWRAP_WACS2_CMD] = 0xC20,
552 [PWRAP_WACS2_RDATA] = 0xC24,
553 [PWRAP_WACS2_VLDCLR] = 0xC28,
554 [PWRAP_INT_EN] = 0xB4,
555 [PWRAP_INT_FLG_RAW] = 0xB8,
556 [PWRAP_INT_FLG] = 0xBC,
557 [PWRAP_INT_CLR] = 0xC0,
558 [PWRAP_TIMER_EN] = 0xE8,
559 [PWRAP_WDT_UNIT] = 0xF0,
560 [PWRAP_WDT_SRC_EN] = 0xF4,
561 [PWRAP_DCM_EN] = 0x1DC,
562 [PWRAP_DCM_DBC_PRD] = 0x1E0,
565 static int mt6779_regs[] = {
566 [PWRAP_MUX_SEL] = 0x0,
567 [PWRAP_WRAP_EN] = 0x4,
568 [PWRAP_DIO_EN] = 0x8,
569 [PWRAP_RDDMY] = 0x20,
570 [PWRAP_CSHEXT_WRITE] = 0x24,
571 [PWRAP_CSHEXT_READ] = 0x28,
572 [PWRAP_CSLEXT_WRITE] = 0x2C,
573 [PWRAP_CSLEXT_READ] = 0x30,
574 [PWRAP_EXT_CK_WRITE] = 0x34,
575 [PWRAP_STAUPD_CTRL] = 0x3C,
576 [PWRAP_STAUPD_GRPEN] = 0x40,
577 [PWRAP_EINT_STA0_ADR] = 0x44,
578 [PWRAP_HARB_HPRIO] = 0x68,
579 [PWRAP_HIPRIO_ARB_EN] = 0x6C,
580 [PWRAP_MAN_EN] = 0x7C,
581 [PWRAP_MAN_CMD] = 0x80,
582 [PWRAP_WACS0_EN] = 0x8C,
583 [PWRAP_INIT_DONE0] = 0x90,
584 [PWRAP_WACS1_EN] = 0x94,
585 [PWRAP_WACS2_EN] = 0x9C,
586 [PWRAP_INIT_DONE1] = 0x98,
587 [PWRAP_INIT_DONE2] = 0xA0,
588 [PWRAP_INT_EN] = 0xBC,
589 [PWRAP_INT_FLG_RAW] = 0xC0,
590 [PWRAP_INT_FLG] = 0xC4,
591 [PWRAP_INT_CLR] = 0xC8,
592 [PWRAP_INT1_EN] = 0xCC,
593 [PWRAP_INT1_FLG] = 0xD4,
594 [PWRAP_INT1_CLR] = 0xD8,
595 [PWRAP_TIMER_EN] = 0xF0,
596 [PWRAP_WDT_UNIT] = 0xF8,
597 [PWRAP_WDT_SRC_EN] = 0xFC,
598 [PWRAP_WDT_SRC_EN_1] = 0x100,
599 [PWRAP_WACS2_CMD] = 0xC20,
600 [PWRAP_WACS2_RDATA] = 0xC24,
601 [PWRAP_WACS2_VLDCLR] = 0xC28,
604 static int mt6797_regs[] = {
605 [PWRAP_MUX_SEL] = 0x0,
606 [PWRAP_WRAP_EN] = 0x4,
607 [PWRAP_DIO_EN] = 0x8,
609 [PWRAP_RDDMY] = 0x10,
610 [PWRAP_CSHEXT_WRITE] = 0x18,
611 [PWRAP_CSHEXT_READ] = 0x1C,
612 [PWRAP_CSLEXT_START] = 0x20,
613 [PWRAP_CSLEXT_END] = 0x24,
614 [PWRAP_STAUPD_PRD] = 0x28,
615 [PWRAP_HARB_HPRIO] = 0x50,
616 [PWRAP_HIPRIO_ARB_EN] = 0x54,
617 [PWRAP_MAN_EN] = 0x60,
618 [PWRAP_MAN_CMD] = 0x64,
619 [PWRAP_WACS0_EN] = 0x70,
620 [PWRAP_WACS1_EN] = 0x84,
621 [PWRAP_WACS2_EN] = 0x98,
622 [PWRAP_INIT_DONE2] = 0x9C,
623 [PWRAP_WACS2_CMD] = 0xA0,
624 [PWRAP_WACS2_RDATA] = 0xA4,
625 [PWRAP_WACS2_VLDCLR] = 0xA8,
626 [PWRAP_INT_EN] = 0xC0,
627 [PWRAP_INT_FLG_RAW] = 0xC4,
628 [PWRAP_INT_FLG] = 0xC8,
629 [PWRAP_INT_CLR] = 0xCC,
630 [PWRAP_TIMER_EN] = 0xF4,
631 [PWRAP_WDT_UNIT] = 0xFC,
632 [PWRAP_WDT_SRC_EN] = 0x100,
633 [PWRAP_DCM_EN] = 0x1CC,
634 [PWRAP_DCM_DBC_PRD] = 0x1D4,
637 static int mt6873_regs[] = {
638 [PWRAP_INIT_DONE2] = 0x0,
639 [PWRAP_TIMER_EN] = 0x3E0,
640 [PWRAP_INT_EN] = 0x448,
641 [PWRAP_WACS2_CMD] = 0xC80,
642 [PWRAP_SWINF_2_WDATA_31_0] = 0xC84,
643 [PWRAP_SWINF_2_RDATA_31_0] = 0xC94,
644 [PWRAP_WACS2_VLDCLR] = 0xCA4,
645 [PWRAP_WACS2_RDATA] = 0xCA8,
648 static int mt7622_regs[] = {
649 [PWRAP_MUX_SEL] = 0x0,
650 [PWRAP_WRAP_EN] = 0x4,
651 [PWRAP_DIO_EN] = 0x8,
653 [PWRAP_RDDMY] = 0x10,
654 [PWRAP_SI_CK_CON] = 0x14,
655 [PWRAP_CSHEXT_WRITE] = 0x18,
656 [PWRAP_CSHEXT_READ] = 0x1C,
657 [PWRAP_CSLEXT_START] = 0x20,
658 [PWRAP_CSLEXT_END] = 0x24,
659 [PWRAP_STAUPD_PRD] = 0x28,
660 [PWRAP_STAUPD_GRPEN] = 0x2C,
661 [PWRAP_EINT_STA0_ADR] = 0x30,
662 [PWRAP_EINT_STA1_ADR] = 0x34,
665 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
666 [PWRAP_STAUPD_STA] = 0x44,
667 [PWRAP_WRAP_STA] = 0x48,
668 [PWRAP_HARB_INIT] = 0x4C,
669 [PWRAP_HARB_HPRIO] = 0x50,
670 [PWRAP_HIPRIO_ARB_EN] = 0x54,
671 [PWRAP_HARB_STA0] = 0x58,
672 [PWRAP_HARB_STA1] = 0x5C,
673 [PWRAP_MAN_EN] = 0x60,
674 [PWRAP_MAN_CMD] = 0x64,
675 [PWRAP_MAN_RDATA] = 0x68,
676 [PWRAP_MAN_VLDCLR] = 0x6C,
677 [PWRAP_WACS0_EN] = 0x70,
678 [PWRAP_INIT_DONE0] = 0x74,
679 [PWRAP_WACS0_CMD] = 0x78,
680 [PWRAP_WACS0_RDATA] = 0x7C,
681 [PWRAP_WACS0_VLDCLR] = 0x80,
682 [PWRAP_WACS1_EN] = 0x84,
683 [PWRAP_INIT_DONE1] = 0x88,
684 [PWRAP_WACS1_CMD] = 0x8C,
685 [PWRAP_WACS1_RDATA] = 0x90,
686 [PWRAP_WACS1_VLDCLR] = 0x94,
687 [PWRAP_WACS2_EN] = 0x98,
688 [PWRAP_INIT_DONE2] = 0x9C,
689 [PWRAP_WACS2_CMD] = 0xA0,
690 [PWRAP_WACS2_RDATA] = 0xA4,
691 [PWRAP_WACS2_VLDCLR] = 0xA8,
692 [PWRAP_INT_EN] = 0xAC,
693 [PWRAP_INT_FLG_RAW] = 0xB0,
694 [PWRAP_INT_FLG] = 0xB4,
695 [PWRAP_INT_CLR] = 0xB8,
696 [PWRAP_SIG_ADR] = 0xBC,
697 [PWRAP_SIG_MODE] = 0xC0,
698 [PWRAP_SIG_VALUE] = 0xC4,
699 [PWRAP_SIG_ERRVAL] = 0xC8,
700 [PWRAP_CRC_EN] = 0xCC,
701 [PWRAP_TIMER_EN] = 0xD0,
702 [PWRAP_TIMER_STA] = 0xD4,
703 [PWRAP_WDT_UNIT] = 0xD8,
704 [PWRAP_WDT_SRC_EN] = 0xDC,
705 [PWRAP_WDT_FLG] = 0xE0,
706 [PWRAP_DEBUG_INT_SEL] = 0xE4,
707 [PWRAP_DVFS_ADR0] = 0xE8,
708 [PWRAP_DVFS_WDATA0] = 0xEC,
709 [PWRAP_DVFS_ADR1] = 0xF0,
710 [PWRAP_DVFS_WDATA1] = 0xF4,
711 [PWRAP_DVFS_ADR2] = 0xF8,
712 [PWRAP_DVFS_WDATA2] = 0xFC,
713 [PWRAP_DVFS_ADR3] = 0x100,
714 [PWRAP_DVFS_WDATA3] = 0x104,
715 [PWRAP_DVFS_ADR4] = 0x108,
716 [PWRAP_DVFS_WDATA4] = 0x10C,
717 [PWRAP_DVFS_ADR5] = 0x110,
718 [PWRAP_DVFS_WDATA5] = 0x114,
719 [PWRAP_DVFS_ADR6] = 0x118,
720 [PWRAP_DVFS_WDATA6] = 0x11C,
721 [PWRAP_DVFS_ADR7] = 0x120,
722 [PWRAP_DVFS_WDATA7] = 0x124,
723 [PWRAP_DVFS_ADR8] = 0x128,
724 [PWRAP_DVFS_WDATA8] = 0x12C,
725 [PWRAP_DVFS_ADR9] = 0x130,
726 [PWRAP_DVFS_WDATA9] = 0x134,
727 [PWRAP_DVFS_ADR10] = 0x138,
728 [PWRAP_DVFS_WDATA10] = 0x13C,
729 [PWRAP_DVFS_ADR11] = 0x140,
730 [PWRAP_DVFS_WDATA11] = 0x144,
731 [PWRAP_DVFS_ADR12] = 0x148,
732 [PWRAP_DVFS_WDATA12] = 0x14C,
733 [PWRAP_DVFS_ADR13] = 0x150,
734 [PWRAP_DVFS_WDATA13] = 0x154,
735 [PWRAP_DVFS_ADR14] = 0x158,
736 [PWRAP_DVFS_WDATA14] = 0x15C,
737 [PWRAP_DVFS_ADR15] = 0x160,
738 [PWRAP_DVFS_WDATA15] = 0x164,
739 [PWRAP_SPMINF_STA] = 0x168,
740 [PWRAP_CIPHER_KEY_SEL] = 0x16C,
741 [PWRAP_CIPHER_IV_SEL] = 0x170,
742 [PWRAP_CIPHER_EN] = 0x174,
743 [PWRAP_CIPHER_RDY] = 0x178,
744 [PWRAP_CIPHER_MODE] = 0x17C,
745 [PWRAP_CIPHER_SWRST] = 0x180,
746 [PWRAP_DCM_EN] = 0x184,
747 [PWRAP_DCM_DBC_PRD] = 0x188,
748 [PWRAP_EXT_CK] = 0x18C,
749 [PWRAP_ADC_CMD_ADDR] = 0x190,
750 [PWRAP_PWRAP_ADC_CMD] = 0x194,
751 [PWRAP_ADC_RDATA_ADDR] = 0x198,
752 [PWRAP_GPS_STA] = 0x19C,
753 [PWRAP_SW_RST] = 0x1A0,
754 [PWRAP_DVFS_STEP_CTRL0] = 0x238,
755 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
756 [PWRAP_DVFS_STEP_CTRL2] = 0x240,
757 [PWRAP_SPI2_CTRL] = 0x244,
760 static int mt8135_regs[] = {
761 [PWRAP_MUX_SEL] = 0x0,
762 [PWRAP_WRAP_EN] = 0x4,
763 [PWRAP_DIO_EN] = 0x8,
765 [PWRAP_CSHEXT] = 0x10,
766 [PWRAP_CSHEXT_WRITE] = 0x14,
767 [PWRAP_CSHEXT_READ] = 0x18,
768 [PWRAP_CSLEXT_START] = 0x1c,
769 [PWRAP_CSLEXT_END] = 0x20,
770 [PWRAP_STAUPD_PRD] = 0x24,
771 [PWRAP_STAUPD_GRPEN] = 0x28,
772 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
773 [PWRAP_STAUPD_STA] = 0x30,
774 [PWRAP_EVENT_IN_EN] = 0x34,
775 [PWRAP_EVENT_DST_EN] = 0x38,
776 [PWRAP_WRAP_STA] = 0x3c,
777 [PWRAP_RRARB_INIT] = 0x40,
778 [PWRAP_RRARB_EN] = 0x44,
779 [PWRAP_RRARB_STA0] = 0x48,
780 [PWRAP_RRARB_STA1] = 0x4c,
781 [PWRAP_HARB_INIT] = 0x50,
782 [PWRAP_HARB_HPRIO] = 0x54,
783 [PWRAP_HIPRIO_ARB_EN] = 0x58,
784 [PWRAP_HARB_STA0] = 0x5c,
785 [PWRAP_HARB_STA1] = 0x60,
786 [PWRAP_MAN_EN] = 0x64,
787 [PWRAP_MAN_CMD] = 0x68,
788 [PWRAP_MAN_RDATA] = 0x6c,
789 [PWRAP_MAN_VLDCLR] = 0x70,
790 [PWRAP_WACS0_EN] = 0x74,
791 [PWRAP_INIT_DONE0] = 0x78,
792 [PWRAP_WACS0_CMD] = 0x7c,
793 [PWRAP_WACS0_RDATA] = 0x80,
794 [PWRAP_WACS0_VLDCLR] = 0x84,
795 [PWRAP_WACS1_EN] = 0x88,
796 [PWRAP_INIT_DONE1] = 0x8c,
797 [PWRAP_WACS1_CMD] = 0x90,
798 [PWRAP_WACS1_RDATA] = 0x94,
799 [PWRAP_WACS1_VLDCLR] = 0x98,
800 [PWRAP_WACS2_EN] = 0x9c,
801 [PWRAP_INIT_DONE2] = 0xa0,
802 [PWRAP_WACS2_CMD] = 0xa4,
803 [PWRAP_WACS2_RDATA] = 0xa8,
804 [PWRAP_WACS2_VLDCLR] = 0xac,
805 [PWRAP_INT_EN] = 0xb0,
806 [PWRAP_INT_FLG_RAW] = 0xb4,
807 [PWRAP_INT_FLG] = 0xb8,
808 [PWRAP_INT_CLR] = 0xbc,
809 [PWRAP_SIG_ADR] = 0xc0,
810 [PWRAP_SIG_MODE] = 0xc4,
811 [PWRAP_SIG_VALUE] = 0xc8,
812 [PWRAP_SIG_ERRVAL] = 0xcc,
813 [PWRAP_CRC_EN] = 0xd0,
814 [PWRAP_EVENT_STA] = 0xd4,
815 [PWRAP_EVENT_STACLR] = 0xd8,
816 [PWRAP_TIMER_EN] = 0xdc,
817 [PWRAP_TIMER_STA] = 0xe0,
818 [PWRAP_WDT_UNIT] = 0xe4,
819 [PWRAP_WDT_SRC_EN] = 0xe8,
820 [PWRAP_WDT_FLG] = 0xec,
821 [PWRAP_DEBUG_INT_SEL] = 0xf0,
822 [PWRAP_CIPHER_KEY_SEL] = 0x134,
823 [PWRAP_CIPHER_IV_SEL] = 0x138,
824 [PWRAP_CIPHER_LOAD] = 0x13c,
825 [PWRAP_CIPHER_START] = 0x140,
826 [PWRAP_CIPHER_RDY] = 0x144,
827 [PWRAP_CIPHER_MODE] = 0x148,
828 [PWRAP_CIPHER_SWRST] = 0x14c,
829 [PWRAP_DCM_EN] = 0x15c,
830 [PWRAP_DCM_DBC_PRD] = 0x160,
833 static int mt8173_regs[] = {
834 [PWRAP_MUX_SEL] = 0x0,
835 [PWRAP_WRAP_EN] = 0x4,
836 [PWRAP_DIO_EN] = 0x8,
838 [PWRAP_RDDMY] = 0x10,
839 [PWRAP_SI_CK_CON] = 0x14,
840 [PWRAP_CSHEXT_WRITE] = 0x18,
841 [PWRAP_CSHEXT_READ] = 0x1c,
842 [PWRAP_CSLEXT_START] = 0x20,
843 [PWRAP_CSLEXT_END] = 0x24,
844 [PWRAP_STAUPD_PRD] = 0x28,
845 [PWRAP_STAUPD_GRPEN] = 0x2c,
846 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
847 [PWRAP_STAUPD_STA] = 0x44,
848 [PWRAP_WRAP_STA] = 0x48,
849 [PWRAP_HARB_INIT] = 0x4c,
850 [PWRAP_HARB_HPRIO] = 0x50,
851 [PWRAP_HIPRIO_ARB_EN] = 0x54,
852 [PWRAP_HARB_STA0] = 0x58,
853 [PWRAP_HARB_STA1] = 0x5c,
854 [PWRAP_MAN_EN] = 0x60,
855 [PWRAP_MAN_CMD] = 0x64,
856 [PWRAP_MAN_RDATA] = 0x68,
857 [PWRAP_MAN_VLDCLR] = 0x6c,
858 [PWRAP_WACS0_EN] = 0x70,
859 [PWRAP_INIT_DONE0] = 0x74,
860 [PWRAP_WACS0_CMD] = 0x78,
861 [PWRAP_WACS0_RDATA] = 0x7c,
862 [PWRAP_WACS0_VLDCLR] = 0x80,
863 [PWRAP_WACS1_EN] = 0x84,
864 [PWRAP_INIT_DONE1] = 0x88,
865 [PWRAP_WACS1_CMD] = 0x8c,
866 [PWRAP_WACS1_RDATA] = 0x90,
867 [PWRAP_WACS1_VLDCLR] = 0x94,
868 [PWRAP_WACS2_EN] = 0x98,
869 [PWRAP_INIT_DONE2] = 0x9c,
870 [PWRAP_WACS2_CMD] = 0xa0,
871 [PWRAP_WACS2_RDATA] = 0xa4,
872 [PWRAP_WACS2_VLDCLR] = 0xa8,
873 [PWRAP_INT_EN] = 0xac,
874 [PWRAP_INT_FLG_RAW] = 0xb0,
875 [PWRAP_INT_FLG] = 0xb4,
876 [PWRAP_INT_CLR] = 0xb8,
877 [PWRAP_SIG_ADR] = 0xbc,
878 [PWRAP_SIG_MODE] = 0xc0,
879 [PWRAP_SIG_VALUE] = 0xc4,
880 [PWRAP_SIG_ERRVAL] = 0xc8,
881 [PWRAP_CRC_EN] = 0xcc,
882 [PWRAP_TIMER_EN] = 0xd0,
883 [PWRAP_TIMER_STA] = 0xd4,
884 [PWRAP_WDT_UNIT] = 0xd8,
885 [PWRAP_WDT_SRC_EN] = 0xdc,
886 [PWRAP_WDT_FLG] = 0xe0,
887 [PWRAP_DEBUG_INT_SEL] = 0xe4,
888 [PWRAP_DVFS_ADR0] = 0xe8,
889 [PWRAP_DVFS_WDATA0] = 0xec,
890 [PWRAP_DVFS_ADR1] = 0xf0,
891 [PWRAP_DVFS_WDATA1] = 0xf4,
892 [PWRAP_DVFS_ADR2] = 0xf8,
893 [PWRAP_DVFS_WDATA2] = 0xfc,
894 [PWRAP_DVFS_ADR3] = 0x100,
895 [PWRAP_DVFS_WDATA3] = 0x104,
896 [PWRAP_DVFS_ADR4] = 0x108,
897 [PWRAP_DVFS_WDATA4] = 0x10c,
898 [PWRAP_DVFS_ADR5] = 0x110,
899 [PWRAP_DVFS_WDATA5] = 0x114,
900 [PWRAP_DVFS_ADR6] = 0x118,
901 [PWRAP_DVFS_WDATA6] = 0x11c,
902 [PWRAP_DVFS_ADR7] = 0x120,
903 [PWRAP_DVFS_WDATA7] = 0x124,
904 [PWRAP_SPMINF_STA] = 0x128,
905 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
906 [PWRAP_CIPHER_IV_SEL] = 0x130,
907 [PWRAP_CIPHER_EN] = 0x134,
908 [PWRAP_CIPHER_RDY] = 0x138,
909 [PWRAP_CIPHER_MODE] = 0x13c,
910 [PWRAP_CIPHER_SWRST] = 0x140,
911 [PWRAP_DCM_EN] = 0x144,
912 [PWRAP_DCM_DBC_PRD] = 0x148,
915 static int mt8183_regs[] = {
916 [PWRAP_MUX_SEL] = 0x0,
917 [PWRAP_WRAP_EN] = 0x4,
918 [PWRAP_DIO_EN] = 0x8,
919 [PWRAP_SI_SAMPLE_CTRL] = 0xC,
920 [PWRAP_RDDMY] = 0x14,
921 [PWRAP_CSHEXT_WRITE] = 0x18,
922 [PWRAP_CSHEXT_READ] = 0x1C,
923 [PWRAP_CSLEXT_WRITE] = 0x20,
924 [PWRAP_CSLEXT_READ] = 0x24,
925 [PWRAP_EXT_CK_WRITE] = 0x28,
926 [PWRAP_STAUPD_CTRL] = 0x30,
927 [PWRAP_STAUPD_GRPEN] = 0x34,
928 [PWRAP_EINT_STA0_ADR] = 0x38,
929 [PWRAP_HARB_HPRIO] = 0x5C,
930 [PWRAP_HIPRIO_ARB_EN] = 0x60,
931 [PWRAP_MAN_EN] = 0x70,
932 [PWRAP_MAN_CMD] = 0x74,
933 [PWRAP_WACS0_EN] = 0x80,
934 [PWRAP_INIT_DONE0] = 0x84,
935 [PWRAP_WACS1_EN] = 0x88,
936 [PWRAP_INIT_DONE1] = 0x8C,
937 [PWRAP_WACS2_EN] = 0x90,
938 [PWRAP_INIT_DONE2] = 0x94,
939 [PWRAP_WACS_P2P_EN] = 0xA0,
940 [PWRAP_INIT_DONE_P2P] = 0xA4,
941 [PWRAP_WACS_MD32_EN] = 0xA8,
942 [PWRAP_INIT_DONE_MD32] = 0xAC,
943 [PWRAP_INT_EN] = 0xB0,
944 [PWRAP_INT_FLG] = 0xB8,
945 [PWRAP_INT_CLR] = 0xBC,
946 [PWRAP_INT1_EN] = 0xC0,
947 [PWRAP_INT1_FLG] = 0xC8,
948 [PWRAP_INT1_CLR] = 0xCC,
949 [PWRAP_SIG_ADR] = 0xD0,
950 [PWRAP_CRC_EN] = 0xE0,
951 [PWRAP_TIMER_EN] = 0xE4,
952 [PWRAP_WDT_UNIT] = 0xEC,
953 [PWRAP_WDT_SRC_EN] = 0xF0,
954 [PWRAP_WDT_SRC_EN_1] = 0xF4,
955 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
956 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
957 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
958 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
959 [PWRAP_GPSINF_0_STA] = 0x1EC,
960 [PWRAP_GPSINF_1_STA] = 0x1F0,
961 [PWRAP_WACS2_CMD] = 0xC20,
962 [PWRAP_WACS2_RDATA] = 0xC24,
963 [PWRAP_WACS2_VLDCLR] = 0xC28,
966 static int mt8195_regs[] = {
967 [PWRAP_INIT_DONE2] = 0x0,
968 [PWRAP_STAUPD_CTRL] = 0x4C,
969 [PWRAP_TIMER_EN] = 0x3E4,
970 [PWRAP_INT_EN] = 0x420,
971 [PWRAP_INT_FLG] = 0x428,
972 [PWRAP_INT_CLR] = 0x42C,
973 [PWRAP_INT1_EN] = 0x450,
974 [PWRAP_INT1_FLG] = 0x458,
975 [PWRAP_INT1_CLR] = 0x45C,
976 [PWRAP_WACS2_CMD] = 0x880,
977 [PWRAP_SWINF_2_WDATA_31_0] = 0x884,
978 [PWRAP_SWINF_2_RDATA_31_0] = 0x894,
979 [PWRAP_WACS2_VLDCLR] = 0x8A4,
980 [PWRAP_WACS2_RDATA] = 0x8A8,
983 static int mt8516_regs[] = {
984 [PWRAP_MUX_SEL] = 0x0,
985 [PWRAP_WRAP_EN] = 0x4,
986 [PWRAP_DIO_EN] = 0x8,
988 [PWRAP_RDDMY] = 0x10,
989 [PWRAP_SI_CK_CON] = 0x14,
990 [PWRAP_CSHEXT_WRITE] = 0x18,
991 [PWRAP_CSHEXT_READ] = 0x1c,
992 [PWRAP_CSLEXT_START] = 0x20,
993 [PWRAP_CSLEXT_END] = 0x24,
994 [PWRAP_STAUPD_PRD] = 0x28,
995 [PWRAP_STAUPD_GRPEN] = 0x2c,
996 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
997 [PWRAP_STAUPD_STA] = 0x44,
998 [PWRAP_WRAP_STA] = 0x48,
999 [PWRAP_HARB_INIT] = 0x4c,
1000 [PWRAP_HARB_HPRIO] = 0x50,
1001 [PWRAP_HIPRIO_ARB_EN] = 0x54,
1002 [PWRAP_HARB_STA0] = 0x58,
1003 [PWRAP_HARB_STA1] = 0x5c,
1004 [PWRAP_MAN_EN] = 0x60,
1005 [PWRAP_MAN_CMD] = 0x64,
1006 [PWRAP_MAN_RDATA] = 0x68,
1007 [PWRAP_MAN_VLDCLR] = 0x6c,
1008 [PWRAP_WACS0_EN] = 0x70,
1009 [PWRAP_INIT_DONE0] = 0x74,
1010 [PWRAP_WACS0_CMD] = 0x78,
1011 [PWRAP_WACS0_RDATA] = 0x7c,
1012 [PWRAP_WACS0_VLDCLR] = 0x80,
1013 [PWRAP_WACS1_EN] = 0x84,
1014 [PWRAP_INIT_DONE1] = 0x88,
1015 [PWRAP_WACS1_CMD] = 0x8c,
1016 [PWRAP_WACS1_RDATA] = 0x90,
1017 [PWRAP_WACS1_VLDCLR] = 0x94,
1018 [PWRAP_WACS2_EN] = 0x98,
1019 [PWRAP_INIT_DONE2] = 0x9c,
1020 [PWRAP_WACS2_CMD] = 0xa0,
1021 [PWRAP_WACS2_RDATA] = 0xa4,
1022 [PWRAP_WACS2_VLDCLR] = 0xa8,
1023 [PWRAP_INT_EN] = 0xac,
1024 [PWRAP_INT_FLG_RAW] = 0xb0,
1025 [PWRAP_INT_FLG] = 0xb4,
1026 [PWRAP_INT_CLR] = 0xb8,
1027 [PWRAP_SIG_ADR] = 0xbc,
1028 [PWRAP_SIG_MODE] = 0xc0,
1029 [PWRAP_SIG_VALUE] = 0xc4,
1030 [PWRAP_SIG_ERRVAL] = 0xc8,
1031 [PWRAP_CRC_EN] = 0xcc,
1032 [PWRAP_TIMER_EN] = 0xd0,
1033 [PWRAP_TIMER_STA] = 0xd4,
1034 [PWRAP_WDT_UNIT] = 0xd8,
1035 [PWRAP_WDT_SRC_EN] = 0xdc,
1036 [PWRAP_WDT_FLG] = 0xe0,
1037 [PWRAP_DEBUG_INT_SEL] = 0xe4,
1038 [PWRAP_DVFS_ADR0] = 0xe8,
1039 [PWRAP_DVFS_WDATA0] = 0xec,
1040 [PWRAP_DVFS_ADR1] = 0xf0,
1041 [PWRAP_DVFS_WDATA1] = 0xf4,
1042 [PWRAP_DVFS_ADR2] = 0xf8,
1043 [PWRAP_DVFS_WDATA2] = 0xfc,
1044 [PWRAP_DVFS_ADR3] = 0x100,
1045 [PWRAP_DVFS_WDATA3] = 0x104,
1046 [PWRAP_DVFS_ADR4] = 0x108,
1047 [PWRAP_DVFS_WDATA4] = 0x10c,
1048 [PWRAP_DVFS_ADR5] = 0x110,
1049 [PWRAP_DVFS_WDATA5] = 0x114,
1050 [PWRAP_DVFS_ADR6] = 0x118,
1051 [PWRAP_DVFS_WDATA6] = 0x11c,
1052 [PWRAP_DVFS_ADR7] = 0x120,
1053 [PWRAP_DVFS_WDATA7] = 0x124,
1054 [PWRAP_SPMINF_STA] = 0x128,
1055 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
1056 [PWRAP_CIPHER_IV_SEL] = 0x130,
1057 [PWRAP_CIPHER_EN] = 0x134,
1058 [PWRAP_CIPHER_RDY] = 0x138,
1059 [PWRAP_CIPHER_MODE] = 0x13c,
1060 [PWRAP_CIPHER_SWRST] = 0x140,
1061 [PWRAP_DCM_EN] = 0x144,
1062 [PWRAP_DCM_DBC_PRD] = 0x148,
1063 [PWRAP_SW_RST] = 0x168,
1064 [PWRAP_OP_TYPE] = 0x16c,
1065 [PWRAP_MSB_FIRST] = 0x170,
1068 static int mt8186_regs[] = {
1069 [PWRAP_MUX_SEL] = 0x0,
1070 [PWRAP_WRAP_EN] = 0x4,
1071 [PWRAP_DIO_EN] = 0x8,
1072 [PWRAP_RDDMY] = 0x20,
1073 [PWRAP_CSHEXT_WRITE] = 0x24,
1074 [PWRAP_CSHEXT_READ] = 0x28,
1075 [PWRAP_CSLEXT_WRITE] = 0x2C,
1076 [PWRAP_CSLEXT_READ] = 0x30,
1077 [PWRAP_EXT_CK_WRITE] = 0x34,
1078 [PWRAP_STAUPD_CTRL] = 0x3C,
1079 [PWRAP_STAUPD_GRPEN] = 0x40,
1080 [PWRAP_EINT_STA0_ADR] = 0x44,
1081 [PWRAP_EINT_STA1_ADR] = 0x48,
1082 [PWRAP_INT_CLR] = 0xC8,
1083 [PWRAP_INT_FLG] = 0xC4,
1084 [PWRAP_MAN_EN] = 0x7C,
1085 [PWRAP_MAN_CMD] = 0x80,
1086 [PWRAP_WACS0_EN] = 0x8C,
1087 [PWRAP_WACS1_EN] = 0x94,
1088 [PWRAP_WACS2_EN] = 0x9C,
1089 [PWRAP_INIT_DONE0] = 0x90,
1090 [PWRAP_INIT_DONE1] = 0x98,
1091 [PWRAP_INIT_DONE2] = 0xA0,
1092 [PWRAP_INT_EN] = 0xBC,
1093 [PWRAP_INT1_EN] = 0xCC,
1094 [PWRAP_INT1_FLG] = 0xD4,
1095 [PWRAP_INT1_CLR] = 0xD8,
1096 [PWRAP_TIMER_EN] = 0xF0,
1097 [PWRAP_WDT_UNIT] = 0xF8,
1098 [PWRAP_WDT_SRC_EN] = 0xFC,
1099 [PWRAP_WDT_SRC_EN_1] = 0x100,
1100 [PWRAP_WDT_FLG] = 0x104,
1101 [PWRAP_SPMINF_STA] = 0x1B4,
1102 [PWRAP_DCM_EN] = 0x1EC,
1103 [PWRAP_DCM_DBC_PRD] = 0x1F0,
1104 [PWRAP_GPSINF_0_STA] = 0x204,
1105 [PWRAP_GPSINF_1_STA] = 0x208,
1106 [PWRAP_WACS0_CMD] = 0xC00,
1107 [PWRAP_WACS0_RDATA] = 0xC04,
1108 [PWRAP_WACS0_VLDCLR] = 0xC08,
1109 [PWRAP_WACS1_CMD] = 0xC10,
1110 [PWRAP_WACS1_RDATA] = 0xC14,
1111 [PWRAP_WACS1_VLDCLR] = 0xC18,
1112 [PWRAP_WACS2_CMD] = 0xC20,
1113 [PWRAP_WACS2_RDATA] = 0xC24,
1114 [PWRAP_WACS2_VLDCLR] = 0xC28,
1142 struct pmic_wrapper;
1143 struct pwrap_slv_type {
1144 const u32 *dew_regs;
1145 enum pmic_type type;
1146 const struct regmap_config *regmap;
1147 /* Flags indicating the capability for the target slave */
1150 * pwrap operations are highly associated with the PMIC types,
1151 * so the pointers added increases flexibility allowing determination
1152 * which type is used by the detection through device tree.
1154 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1155 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1158 struct pmic_wrapper {
1161 struct regmap *regmap;
1162 const struct pmic_wrapper_type *master;
1163 const struct pwrap_slv_type *slave;
1164 struct clk *clk_spi;
1165 struct clk *clk_wrap;
1166 struct reset_control *rstc;
1168 struct reset_control *rstc_bridge;
1169 void __iomem *bridge_base;
1172 struct pmic_wrapper_type {
1174 enum pwrap_type type;
1180 /* Flags indicating the capability for the target pwrap */
1182 int (*init_reg_clock)(struct pmic_wrapper *wrp);
1183 int (*init_soc_specific)(struct pmic_wrapper *wrp);
1186 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1188 return readl(wrp->base + wrp->master->regs[reg]);
1191 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1193 writel(val, wrp->base + wrp->master->regs[reg]);
1196 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)
1200 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1201 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1202 return PWRAP_GET_WACS_ARB_FSM(val);
1204 return PWRAP_GET_WACS_FSM(val);
1207 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1209 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;
1212 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1214 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;
1218 * Timeout issue sometimes caused by the last read command
1219 * failed because pmic wrap could not got the FSM_VLDCLR
1220 * in time after finishing WACS2_CMD. It made state machine
1221 * still on FSM_VLDCLR and timeout next time.
1222 * Check the status of FSM and clear the vldclr to recovery the
1225 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1227 if (pwrap_is_fsm_vldclr(wrp))
1228 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1231 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1233 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1236 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1238 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1240 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
1241 (val & PWRAP_STATE_SYNC_IDLE0);
1244 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
1245 bool (*fp)(struct pmic_wrapper *))
1247 unsigned long timeout;
1249 timeout = jiffies + usecs_to_jiffies(10000);
1252 if (time_after(jiffies, timeout))
1253 return fp(wrp) ? 0 : -ETIMEDOUT;
1259 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1264 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1266 pwrap_leave_fsm_vldclr(wrp);
1270 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1273 val = (adr >> 1) << 16;
1274 pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
1276 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1280 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1281 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
1283 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1284 *rdata = PWRAP_GET_WACS_RDATA(val);
1286 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1291 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1296 for (msb = 0; msb < 2; msb++) {
1297 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1299 pwrap_leave_fsm_vldclr(wrp);
1303 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1306 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
1310 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1311 PWRAP_WACS2_RDATA)) << (16 * msb));
1313 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1319 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1321 return wrp->slave->pwrap_read(wrp, adr, rdata);
1324 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1328 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1330 pwrap_leave_fsm_vldclr(wrp);
1334 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
1335 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
1336 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
1338 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
1345 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1347 int ret, msb, rdata;
1349 for (msb = 0; msb < 2; msb++) {
1350 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
1352 pwrap_leave_fsm_vldclr(wrp);
1356 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1357 ((wdata >> (msb * 16)) & 0xffff),
1361 * The pwrap_read operation is the requirement of hardware used
1362 * for the synchronization between two successive 16-bit
1363 * pwrap_writel operations composing one 32-bit bus writing.
1364 * Otherwise, we'll find the result fails on the lower 16-bit
1368 pwrap_read(wrp, adr, &rdata);
1374 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1376 return wrp->slave->pwrap_write(wrp, adr, wdata);
1379 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1381 return pwrap_read(context, adr, rdata);
1384 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1386 return pwrap_write(context, adr, wdata);
1389 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1393 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1394 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1395 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1396 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1397 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1399 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1401 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1403 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1406 for (i = 0; i < 4; i++)
1407 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1410 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
1412 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1416 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1417 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1423 * pwrap_init_sidly - configure serial input delay
1425 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1426 * delay. Do a read test with all possible values and chose the best delay.
1428 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1433 signed char dly[16] = {
1434 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1437 for (i = 0; i < 4; i++) {
1438 pwrap_writel(wrp, i, PWRAP_SIDLY);
1439 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1441 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1442 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1447 if (dly[pass] < 0) {
1448 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1453 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1458 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1463 /* Enable dual IO mode */
1464 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1466 /* Check IDLE & INIT_DONE in advance */
1467 ret = pwrap_wait_for_state(wrp,
1468 pwrap_is_fsm_idle_and_sync_idle);
1470 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1474 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1478 wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1479 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1481 "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1482 PWRAP_DEW_READ_TEST_VAL, rdata);
1490 * pwrap_init_chip_select_ext is used to configure CS extension time for each
1491 * phase during data transactions on the pwrap bus.
1493 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1494 u8 hext_read, u8 lext_start,
1498 * After finishing a write and read transaction, extends CS high time
1499 * to be at least xT of BUS CLK as hext_write and hext_read specifies
1502 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1503 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1506 * Extends CS low time after CSL and before CSH command to be at
1507 * least xT of BUS CLK as lext_start and lext_end specifies
1510 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1511 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1514 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1516 switch (wrp->master->type) {
1518 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1521 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1522 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1531 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1533 switch (wrp->slave->type) {
1535 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1536 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1540 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1541 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1543 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1552 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1554 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1557 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1562 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1570 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1575 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1576 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1577 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1578 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1580 switch (wrp->master->type) {
1582 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1583 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1592 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1595 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1603 /* Config cipher mode @PMIC */
1604 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1605 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1606 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1607 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1609 switch (wrp->slave->type) {
1611 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1613 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1619 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1626 /* wait for cipher data ready@AP */
1627 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1629 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1633 /* wait for cipher data ready@PMIC */
1634 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1637 "timeout waiting for cipher data ready@PMIC\n");
1641 /* wait for cipher mode idle */
1642 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1643 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1645 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1649 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1652 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1653 PWRAP_DEW_WRITE_TEST_VAL) ||
1654 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1656 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1657 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1664 static int pwrap_init_security(struct pmic_wrapper *wrp)
1668 /* Enable encryption */
1669 ret = pwrap_init_cipher(wrp);
1673 /* Signature checking - using CRC */
1674 if (pwrap_write(wrp,
1675 wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1678 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1679 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1680 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1683 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1688 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1690 /* enable pwrap events and pwrap bridge in AP side */
1691 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1692 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1693 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1694 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1695 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1696 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1697 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1698 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1699 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1701 /* enable PMIC event out and sources */
1702 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1704 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1706 dev_err(wrp->dev, "enable dewrap fail\n");
1713 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1715 /* PMIC_DEWRAP enables */
1716 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1718 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1720 dev_err(wrp->dev, "enable dewrap fail\n");
1727 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1729 /* GPS_INTF initialization */
1730 switch (wrp->slave->type) {
1732 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1733 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1734 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1735 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1736 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1745 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1747 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1748 /* enable 2wire SPI master */
1749 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1754 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1756 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1758 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1759 pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1760 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1761 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1763 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1764 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1765 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1766 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1771 static int pwrap_init(struct pmic_wrapper *wrp)
1776 reset_control_reset(wrp->rstc);
1777 if (wrp->rstc_bridge)
1778 reset_control_reset(wrp->rstc_bridge);
1780 if (wrp->master->type == PWRAP_MT8173) {
1782 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1783 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1786 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1787 /* Reset SPI slave */
1788 ret = pwrap_reset_spislave(wrp);
1793 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1795 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1797 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1799 ret = wrp->master->init_reg_clock(wrp);
1803 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1804 /* Setup serial input delay */
1805 ret = pwrap_init_sidly(wrp);
1810 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1811 /* Enable dual I/O mode */
1812 ret = pwrap_init_dual_io(wrp);
1817 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1818 /* Enable security on bus */
1819 ret = pwrap_init_security(wrp);
1824 if (wrp->master->type == PWRAP_MT8135)
1825 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1827 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1828 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1829 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1830 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1831 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1833 if (wrp->master->init_soc_specific) {
1834 ret = wrp->master->init_soc_specific(wrp);
1839 /* Setup the init done registers */
1840 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1841 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1842 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1844 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1845 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1846 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1852 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1855 struct pmic_wrapper *wrp = dev_id;
1857 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1858 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1859 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1861 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1862 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1863 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1864 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1870 static const struct regmap_config pwrap_regmap_config16 = {
1874 .reg_read = pwrap_regmap_read,
1875 .reg_write = pwrap_regmap_write,
1876 .max_register = 0xffff,
1879 static const struct regmap_config pwrap_regmap_config32 = {
1883 .reg_read = pwrap_regmap_read,
1884 .reg_write = pwrap_regmap_write,
1885 .max_register = 0xffff,
1888 static const struct pwrap_slv_type pmic_mt6323 = {
1889 .dew_regs = mt6323_regs,
1890 .type = PMIC_MT6323,
1891 .regmap = &pwrap_regmap_config16,
1892 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1893 PWRAP_SLV_CAP_SECURITY,
1894 .pwrap_read = pwrap_read16,
1895 .pwrap_write = pwrap_write16,
1898 static const struct pwrap_slv_type pmic_mt6351 = {
1899 .dew_regs = mt6351_regs,
1900 .type = PMIC_MT6351,
1901 .regmap = &pwrap_regmap_config16,
1903 .pwrap_read = pwrap_read16,
1904 .pwrap_write = pwrap_write16,
1907 static const struct pwrap_slv_type pmic_mt6357 = {
1908 .dew_regs = mt6357_regs,
1909 .type = PMIC_MT6357,
1910 .regmap = &pwrap_regmap_config16,
1912 .pwrap_read = pwrap_read16,
1913 .pwrap_write = pwrap_write16,
1916 static const struct pwrap_slv_type pmic_mt6358 = {
1917 .dew_regs = mt6358_regs,
1918 .type = PMIC_MT6358,
1919 .regmap = &pwrap_regmap_config16,
1920 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1921 .pwrap_read = pwrap_read16,
1922 .pwrap_write = pwrap_write16,
1925 static const struct pwrap_slv_type pmic_mt6359 = {
1926 .dew_regs = mt6359_regs,
1927 .type = PMIC_MT6359,
1928 .regmap = &pwrap_regmap_config16,
1929 .caps = PWRAP_SLV_CAP_DUALIO,
1930 .pwrap_read = pwrap_read16,
1931 .pwrap_write = pwrap_write16,
1934 static const struct pwrap_slv_type pmic_mt6380 = {
1936 .type = PMIC_MT6380,
1937 .regmap = &pwrap_regmap_config32,
1939 .pwrap_read = pwrap_read32,
1940 .pwrap_write = pwrap_write32,
1943 static const struct pwrap_slv_type pmic_mt6397 = {
1944 .dew_regs = mt6397_regs,
1945 .type = PMIC_MT6397,
1946 .regmap = &pwrap_regmap_config16,
1947 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1948 PWRAP_SLV_CAP_SECURITY,
1949 .pwrap_read = pwrap_read16,
1950 .pwrap_write = pwrap_write16,
1953 static const struct of_device_id of_slave_match_tbl[] = {
1955 .compatible = "mediatek,mt6323",
1956 .data = &pmic_mt6323,
1958 .compatible = "mediatek,mt6351",
1959 .data = &pmic_mt6351,
1961 .compatible = "mediatek,mt6357",
1962 .data = &pmic_mt6357,
1964 .compatible = "mediatek,mt6358",
1965 .data = &pmic_mt6358,
1967 .compatible = "mediatek,mt6359",
1968 .data = &pmic_mt6359,
1970 /* The MT6380 PMIC only implements a regulator, so we bind it
1971 * directly instead of using a MFD.
1973 .compatible = "mediatek,mt6380-regulator",
1974 .data = &pmic_mt6380,
1976 .compatible = "mediatek,mt6397",
1977 .data = &pmic_mt6397,
1982 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1984 static const struct pmic_wrapper_type pwrap_mt2701 = {
1985 .regs = mt2701_regs,
1986 .type = PWRAP_MT2701,
1988 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1990 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1991 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1992 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1993 .init_reg_clock = pwrap_mt2701_init_reg_clock,
1994 .init_soc_specific = pwrap_mt2701_init_soc_specific,
1997 static const struct pmic_wrapper_type pwrap_mt6765 = {
1998 .regs = mt6765_regs,
1999 .type = PWRAP_MT6765,
2000 .arb_en_all = 0x3fd35,
2001 .int_en_all = 0xffffffff,
2002 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2003 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2004 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2005 .init_reg_clock = pwrap_common_init_reg_clock,
2006 .init_soc_specific = NULL,
2009 static const struct pmic_wrapper_type pwrap_mt6779 = {
2010 .regs = mt6779_regs,
2011 .type = PWRAP_MT6779,
2012 .arb_en_all = 0xfbb7f,
2013 .int_en_all = 0xfffffffe,
2015 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2016 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2018 .init_reg_clock = pwrap_common_init_reg_clock,
2019 .init_soc_specific = NULL,
2022 static const struct pmic_wrapper_type pwrap_mt6797 = {
2023 .regs = mt6797_regs,
2024 .type = PWRAP_MT6797,
2025 .arb_en_all = 0x01fff,
2026 .int_en_all = 0xffffffc6,
2028 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2029 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2030 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2031 .init_reg_clock = pwrap_common_init_reg_clock,
2032 .init_soc_specific = NULL,
2035 static const struct pmic_wrapper_type pwrap_mt6873 = {
2036 .regs = mt6873_regs,
2037 .type = PWRAP_MT6873,
2038 .arb_en_all = 0x777f,
2039 .int_en_all = BIT(4) | BIT(5),
2041 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2042 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2043 .caps = PWRAP_CAP_ARB,
2044 .init_reg_clock = pwrap_common_init_reg_clock,
2045 .init_soc_specific = NULL,
2048 static const struct pmic_wrapper_type pwrap_mt7622 = {
2049 .regs = mt7622_regs,
2050 .type = PWRAP_MT7622,
2052 .int_en_all = ~(u32)BIT(31),
2054 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2055 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2056 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2057 .init_reg_clock = pwrap_common_init_reg_clock,
2058 .init_soc_specific = pwrap_mt7622_init_soc_specific,
2061 static const struct pmic_wrapper_type pwrap_mt8135 = {
2062 .regs = mt8135_regs,
2063 .type = PWRAP_MT8135,
2064 .arb_en_all = 0x1ff,
2065 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2067 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2068 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2069 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2070 .init_reg_clock = pwrap_common_init_reg_clock,
2071 .init_soc_specific = pwrap_mt8135_init_soc_specific,
2074 static const struct pmic_wrapper_type pwrap_mt8173 = {
2075 .regs = mt8173_regs,
2076 .type = PWRAP_MT8173,
2078 .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2080 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2081 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
2082 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2083 .init_reg_clock = pwrap_common_init_reg_clock,
2084 .init_soc_specific = pwrap_mt8173_init_soc_specific,
2087 static const struct pmic_wrapper_type pwrap_mt8183 = {
2088 .regs = mt8183_regs,
2089 .type = PWRAP_MT8183,
2090 .arb_en_all = 0x3fa75,
2091 .int_en_all = 0xffffffff,
2092 .int1_en_all = 0xeef7ffff,
2093 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2094 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2095 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
2096 .init_reg_clock = pwrap_common_init_reg_clock,
2097 .init_soc_specific = pwrap_mt8183_init_soc_specific,
2100 static struct pmic_wrapper_type pwrap_mt8195 = {
2101 .regs = mt8195_regs,
2102 .type = PWRAP_MT8195,
2103 .arb_en_all = 0x777f, /* NEED CONFIRM */
2104 .int_en_all = 0x180000, /* NEED CONFIRM */
2106 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2107 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2108 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,
2109 .init_reg_clock = pwrap_common_init_reg_clock,
2110 .init_soc_specific = NULL,
2113 static struct pmic_wrapper_type pwrap_mt8516 = {
2114 .regs = mt8516_regs,
2115 .type = PWRAP_MT8516,
2117 .int_en_all = ~(u32)(BIT(31) | BIT(2)),
2118 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2119 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2120 .caps = PWRAP_CAP_DCM,
2121 .init_reg_clock = pwrap_mt2701_init_reg_clock,
2122 .init_soc_specific = NULL,
2125 static struct pmic_wrapper_type pwrap_mt8186 = {
2126 .regs = mt8186_regs,
2127 .type = PWRAP_MT8186,
2128 .arb_en_all = 0xfb27f,
2129 .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */
2130 .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */
2131 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2132 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2133 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186,
2134 .init_reg_clock = pwrap_common_init_reg_clock,
2135 .init_soc_specific = NULL,
2138 static const struct of_device_id of_pwrap_match_tbl[] = {
2140 .compatible = "mediatek,mt2701-pwrap",
2141 .data = &pwrap_mt2701,
2143 .compatible = "mediatek,mt6765-pwrap",
2144 .data = &pwrap_mt6765,
2146 .compatible = "mediatek,mt6779-pwrap",
2147 .data = &pwrap_mt6779,
2149 .compatible = "mediatek,mt6797-pwrap",
2150 .data = &pwrap_mt6797,
2152 .compatible = "mediatek,mt6873-pwrap",
2153 .data = &pwrap_mt6873,
2155 .compatible = "mediatek,mt7622-pwrap",
2156 .data = &pwrap_mt7622,
2158 .compatible = "mediatek,mt8135-pwrap",
2159 .data = &pwrap_mt8135,
2161 .compatible = "mediatek,mt8173-pwrap",
2162 .data = &pwrap_mt8173,
2164 .compatible = "mediatek,mt8183-pwrap",
2165 .data = &pwrap_mt8183,
2167 .compatible = "mediatek,mt8186-pwrap",
2168 .data = &pwrap_mt8186,
2170 .compatible = "mediatek,mt8195-pwrap",
2171 .data = &pwrap_mt8195,
2173 .compatible = "mediatek,mt8516-pwrap",
2174 .data = &pwrap_mt8516,
2179 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
2181 static int pwrap_probe(struct platform_device *pdev)
2185 struct pmic_wrapper *wrp;
2186 struct device_node *np = pdev->dev.of_node;
2187 const struct of_device_id *of_slave_id = NULL;
2188 struct resource *res;
2191 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
2194 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
2198 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2202 platform_set_drvdata(pdev, wrp);
2204 wrp->master = of_device_get_match_data(&pdev->dev);
2205 wrp->slave = of_slave_id->data;
2206 wrp->dev = &pdev->dev;
2208 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
2209 wrp->base = devm_ioremap_resource(wrp->dev, res);
2210 if (IS_ERR(wrp->base))
2211 return PTR_ERR(wrp->base);
2213 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2214 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2215 if (IS_ERR(wrp->rstc)) {
2216 ret = PTR_ERR(wrp->rstc);
2217 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2222 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2223 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2225 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
2226 if (IS_ERR(wrp->bridge_base))
2227 return PTR_ERR(wrp->bridge_base);
2229 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2231 if (IS_ERR(wrp->rstc_bridge)) {
2232 ret = PTR_ERR(wrp->rstc_bridge);
2234 "cannot get pwrap-bridge reset: %d\n", ret);
2239 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2240 if (IS_ERR(wrp->clk_spi)) {
2241 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2242 PTR_ERR(wrp->clk_spi));
2243 return PTR_ERR(wrp->clk_spi);
2246 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2247 if (IS_ERR(wrp->clk_wrap)) {
2248 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2249 PTR_ERR(wrp->clk_wrap));
2250 return PTR_ERR(wrp->clk_wrap);
2253 ret = clk_prepare_enable(wrp->clk_spi);
2257 ret = clk_prepare_enable(wrp->clk_wrap);
2261 /* Enable internal dynamic clock */
2262 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2263 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2264 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2268 * The PMIC could already be initialized by the bootloader.
2269 * Skip initialization here in this case.
2271 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2272 ret = pwrap_init(wrp);
2274 dev_dbg(wrp->dev, "init failed with %d\n", ret);
2279 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2280 mask_done = PWRAP_STATE_INIT_DONE1;
2281 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))
2282 mask_done = PWRAP_STATE_INIT_DONE0_MT8186;
2284 mask_done = PWRAP_STATE_INIT_DONE0;
2286 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {
2287 dev_dbg(wrp->dev, "initialization isn't finished\n");
2292 /* Initialize watchdog, may not be done by the bootloader */
2293 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2294 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2297 * Since STAUPD was not used on mt8173 platform,
2298 * so STAUPD of WDT_SRC which should be turned off
2300 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2301 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2302 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2304 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2305 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
2307 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2309 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2311 * We add INT1 interrupt to handle starvation and request exception
2312 * If we support it, we should enable it here.
2314 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2315 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2317 irq = platform_get_irq(pdev, 0);
2318 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2320 "mt-pmic-pwrap", wrp);
2324 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
2325 if (IS_ERR(wrp->regmap)) {
2326 ret = PTR_ERR(wrp->regmap);
2330 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2332 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2340 clk_disable_unprepare(wrp->clk_wrap);
2342 clk_disable_unprepare(wrp->clk_spi);
2347 static struct platform_driver pwrap_drv = {
2349 .name = "mt-pmic-pwrap",
2350 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
2352 .probe = pwrap_probe,
2355 module_platform_driver(pwrap_drv);
2357 MODULE_AUTHOR("Flora Fu, MediaTek");
2358 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
2359 MODULE_LICENSE("GPL v2");