1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H
4 #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H
6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
7 #define MTK_SCPD_FWAIT_SRAM BIT(1)
8 #define MTK_SCPD_SRAM_ISO BIT(2)
9 #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
10 #define MTK_SCPD_DOMAIN_SUPPLY BIT(4)
11 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
13 #define SPM_VDE_PWR_CON 0x0210
14 #define SPM_MFG_PWR_CON 0x0214
15 #define SPM_VEN_PWR_CON 0x0230
16 #define SPM_ISP_PWR_CON 0x0238
17 #define SPM_DIS_PWR_CON 0x023c
18 #define SPM_CONN_PWR_CON 0x0280
19 #define SPM_VEN2_PWR_CON 0x0298
20 #define SPM_AUDIO_PWR_CON 0x029c
21 #define SPM_MFG_2D_PWR_CON 0x02c0
22 #define SPM_MFG_ASYNC_PWR_CON 0x02c4
23 #define SPM_USB_PWR_CON 0x02cc
25 #define SPM_PWR_STATUS 0x060c
26 #define SPM_PWR_STATUS_2ND 0x0610
28 #define PWR_STATUS_CONN BIT(1)
29 #define PWR_STATUS_DISP BIT(3)
30 #define PWR_STATUS_MFG BIT(4)
31 #define PWR_STATUS_ISP BIT(5)
32 #define PWR_STATUS_VDEC BIT(7)
33 #define PWR_STATUS_VENC_LT BIT(20)
34 #define PWR_STATUS_VENC BIT(21)
35 #define PWR_STATUS_MFG_2D BIT(22)
36 #define PWR_STATUS_MFG_ASYNC BIT(23)
37 #define PWR_STATUS_AUDIO BIT(24)
38 #define PWR_STATUS_USB BIT(25)
40 #define SPM_MAX_BUS_PROT_DATA 6
42 #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
43 .bus_prot_mask = (_mask), \
44 .bus_prot_set = _set, \
45 .bus_prot_clr = _clr, \
46 .bus_prot_sta = _sta, \
47 .bus_prot_reg_update = _update, \
48 .ignore_clr_ack = _ignore, \
51 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \
52 _BUS_PROT(_mask, _set, _clr, _sta, false, false)
54 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \
55 _BUS_PROT(_mask, _set, _clr, _sta, false, true)
57 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \
58 _BUS_PROT(_mask, _set, _clr, _sta, true, false)
60 #define BUS_PROT_UPDATE_TOPAXI(_mask) \
61 BUS_PROT_UPDATE(_mask, \
62 INFRA_TOPAXI_PROTECTEN, \
63 INFRA_TOPAXI_PROTECTEN, \
64 INFRA_TOPAXI_PROTECTSTA1)
66 struct scpsys_bus_prot_data {
71 bool bus_prot_reg_update;
76 * struct scpsys_domain_data - scp domain data for power on/off flow
77 * @name: The name of the power domain.
78 * @sta_mask: The mask for power on/off status bit.
79 * @ctl_offs: The offset for main power control register.
80 * @sram_pdn_bits: The mask for sram power control bits.
81 * @sram_pdn_ack_bits: The mask for sram power control acked bits.
82 * @caps: The flag for active wake-up action.
83 * @bp_infracfg: bus protection for infracfg subsystem
84 * @bp_smi: bus protection for smi subsystem
86 struct scpsys_domain_data {
91 u32 sram_pdn_ack_bits;
93 const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
94 const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA];
99 struct scpsys_soc_data {
100 const struct scpsys_domain_data *domains_data;
104 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */