1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
4 #define __SOC_MEDIATEK_MT8186_MMSYS_H
6 #define MT8186_MMSYS_OVL_CON 0xF04
7 #define MT8186_MMSYS_OVL0_CON_MASK 0x3
8 #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
9 #define MT8186_OVL0_GO_BLEND BIT(0)
10 #define MT8186_OVL0_GO_BG BIT(1)
11 #define MT8186_OVL0_2L_GO_BLEND BIT(2)
12 #define MT8186_OVL0_2L_GO_BG BIT(3)
13 #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
14 #define MT8186_RDMA0_SOUT_SEL_MASK 0xF
15 #define MT8186_RDMA0_SOUT_TO_DSI0 (0)
16 #define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
17 #define MT8186_RDMA0_SOUT_TO_DPI0 (2)
18 #define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
19 #define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
20 #define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
21 #define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
22 #define MT8186_DISP_OVL0_MOUT_EN 0xF18
23 #define MT8186_OVL0_MOUT_EN_MASK 0xF
24 #define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
25 #define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
26 #define MT8186_DISP_DITHER0_MOUT_EN 0xF20
27 #define MT8186_DITHER0_MOUT_EN_MASK 0xF
28 #define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
29 #define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
30 #define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
31 #define MT8186_DISP_RDMA0_SEL_IN 0xF28
32 #define MT8186_RDMA0_SEL_IN_MASK 0xF
33 #define MT8186_RDMA0_FROM_OVL0 0
34 #define MT8186_RDMA0_FROM_OVL0_2L 2
35 #define MT8186_DISP_DSI0_SEL_IN 0xF30
36 #define MT8186_DSI0_SEL_IN_MASK 0xF
37 #define MT8186_DSI0_FROM_RDMA0 0
38 #define MT8186_DSI0_FROM_DITHER0 1
39 #define MT8186_DSI0_FROM_RDMA1 2
40 #define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
41 #define MT8186_RDMA1_MOUT_EN_MASK 0xF
42 #define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
43 #define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
44 #define MT8186_DISP_RDMA1_SEL_IN 0xF40
45 #define MT8186_RDMA1_SEL_IN_MASK 0xF
46 #define MT8186_RDMA1_FROM_OVL0 0
47 #define MT8186_RDMA1_FROM_OVL0_2L 2
48 #define MT8186_RDMA1_FROM_DITHER0 3
49 #define MT8186_DISP_DPI0_SEL_IN 0xF44
50 #define MT8186_DPI0_SEL_IN_MASK 0xF
51 #define MT8186_DPI0_FROM_RDMA1 0
52 #define MT8186_DPI0_FROM_DITHER0 1
53 #define MT8186_DPI0_FROM_RDMA0 2
55 #define MT8186_MMSYS_SW0_RST_B 0x160
57 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
59 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
60 MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
61 MT8186_OVL0_MOUT_TO_RDMA0
64 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
65 MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
66 MT8186_RDMA0_FROM_OVL0
69 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
70 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
74 DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
75 MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
76 MT8186_RDMA0_SOUT_TO_COLOR0
79 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
80 MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
81 MT8186_DITHER0_MOUT_TO_DSI0,
84 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
85 MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
86 MT8186_DSI0_FROM_DITHER0
89 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
90 MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
91 MT8186_OVL0_2L_MOUT_TO_RDMA1
94 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
95 MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
96 MT8186_RDMA1_FROM_OVL0_2L
99 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
100 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
101 MT8186_OVL0_2L_GO_BLEND
104 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
105 MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
106 MT8186_RDMA1_MOUT_TO_DPI0_SEL
109 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
110 MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
111 MT8186_DPI0_FROM_RDMA1
115 #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */