drivers/soc/imx/gpcv2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 Impinj, Inc
   4  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   5  *
   6  * Based on the code of analogus driver:
   7  *
   8  * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/reset.h>
  19 #include <linux/sizes.h>
  20 #include <dt-bindings/power/imx7-power.h>
  21 #include <dt-bindings/power/imx8mq-power.h>
  22 #include <dt-bindings/power/imx8mm-power.h>
  23 #include <dt-bindings/power/imx8mn-power.h>
  24 #include <dt-bindings/power/imx8mp-power.h>
  25
  26 #define GPC_LPCR_A_CORE_BSC                     0x000
  27
  28 #define GPC_PGC_CPU_MAPPING             0x0ec
  29 #define IMX8MP_GPC_PGC_CPU_MAPPING      0x1cc
  30
  31 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN         BIT(6)
  32 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN         BIT(5)
  33 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN         BIT(4)
  34 #define IMX7_PCIE_PHY_A_CORE_DOMAIN             BIT(3)
  35 #define IMX7_MIPI_PHY_A_CORE_DOMAIN             BIT(2)
  36
  37 #define IMX8M_PCIE2_A53_DOMAIN                  BIT(15)
  38 #define IMX8M_MIPI_CSI2_A53_DOMAIN              BIT(14)
  39 #define IMX8M_MIPI_CSI1_A53_DOMAIN              BIT(13)
  40 #define IMX8M_DISP_A53_DOMAIN                   BIT(12)
  41 #define IMX8M_HDMI_A53_DOMAIN                   BIT(11)
  42 #define IMX8M_VPU_A53_DOMAIN                    BIT(10)
  43 #define IMX8M_GPU_A53_DOMAIN                    BIT(9)
  44 #define IMX8M_DDR2_A53_DOMAIN                   BIT(8)
  45 #define IMX8M_DDR1_A53_DOMAIN                   BIT(7)
  46 #define IMX8M_OTG2_A53_DOMAIN                   BIT(5)
  47 #define IMX8M_OTG1_A53_DOMAIN                   BIT(4)
  48 #define IMX8M_PCIE1_A53_DOMAIN                  BIT(3)
  49 #define IMX8M_MIPI_A53_DOMAIN                   BIT(2)
  50
  51 #define IMX8MM_VPUH1_A53_DOMAIN                 BIT(15)
  52 #define IMX8MM_VPUG2_A53_DOMAIN                 BIT(14)
  53 #define IMX8MM_VPUG1_A53_DOMAIN                 BIT(13)
  54 #define IMX8MM_DISPMIX_A53_DOMAIN               BIT(12)
  55 #define IMX8MM_VPUMIX_A53_DOMAIN                BIT(10)
  56 #define IMX8MM_GPUMIX_A53_DOMAIN                BIT(9)
  57 #define IMX8MM_GPU_A53_DOMAIN                   (BIT(8) | BIT(11))
  58 #define IMX8MM_DDR1_A53_DOMAIN                  BIT(7)
  59 #define IMX8MM_OTG2_A53_DOMAIN                  BIT(5)
  60 #define IMX8MM_OTG1_A53_DOMAIN                  BIT(4)
  61 #define IMX8MM_PCIE_A53_DOMAIN                  BIT(3)
  62 #define IMX8MM_MIPI_A53_DOMAIN                  BIT(2)
  63
  64 #define IMX8MN_DISPMIX_A53_DOMAIN               BIT(12)
  65 #define IMX8MN_GPUMIX_A53_DOMAIN                BIT(9)
  66 #define IMX8MN_DDR1_A53_DOMAIN          BIT(7)
  67 #define IMX8MN_OTG1_A53_DOMAIN          BIT(4)
  68 #define IMX8MN_MIPI_A53_DOMAIN          BIT(2)
  69
  70 #define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN  BIT(20)
  71 #define IMX8MP_HSIOMIX_A53_DOMAIN               BIT(19)
  72 #define IMX8MP_MIPI_PHY2_A53_DOMAIN             BIT(18)
  73 #define IMX8MP_HDMI_PHY_A53_DOMAIN              BIT(17)
  74 #define IMX8MP_HDMIMIX_A53_DOMAIN               BIT(16)
  75 #define IMX8MP_VPU_VC8000E_A53_DOMAIN           BIT(15)
  76 #define IMX8MP_VPU_G2_A53_DOMAIN                BIT(14)
  77 #define IMX8MP_VPU_G1_A53_DOMAIN                BIT(13)
  78 #define IMX8MP_MEDIAMIX_A53_DOMAIN              BIT(12)
  79 #define IMX8MP_GPU3D_A53_DOMAIN                 BIT(11)
  80 #define IMX8MP_VPUMIX_A53_DOMAIN                BIT(10)
  81 #define IMX8MP_GPUMIX_A53_DOMAIN                BIT(9)
  82 #define IMX8MP_GPU2D_A53_DOMAIN                 BIT(8)
  83 #define IMX8MP_AUDIOMIX_A53_DOMAIN              BIT(7)
  84 #define IMX8MP_MLMIX_A53_DOMAIN                 BIT(6)
  85 #define IMX8MP_USB2_PHY_A53_DOMAIN              BIT(5)
  86 #define IMX8MP_USB1_PHY_A53_DOMAIN              BIT(4)
  87 #define IMX8MP_PCIE_PHY_A53_DOMAIN              BIT(3)
  88 #define IMX8MP_MIPI_PHY1_A53_DOMAIN             BIT(2)
  89
  90 #define IMX8MP_GPC_PU_PGC_SW_PUP_REQ    0x0d8
  91 #define IMX8MP_GPC_PU_PGC_SW_PDN_REQ    0x0e4
  92
  93 #define GPC_PU_PGC_SW_PUP_REQ           0x0f8
  94 #define GPC_PU_PGC_SW_PDN_REQ           0x104
  95
  96 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ            BIT(4)
  97 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ            BIT(3)
  98 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ            BIT(2)
  99 #define IMX7_PCIE_PHY_SW_Pxx_REQ                BIT(1)
 100 #define IMX7_MIPI_PHY_SW_Pxx_REQ                BIT(0)
 101
 102 #define IMX8M_PCIE2_SW_Pxx_REQ                  BIT(13)
 103 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ              BIT(12)
 104 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ              BIT(11)
 105 #define IMX8M_DISP_SW_Pxx_REQ                   BIT(10)
 106 #define IMX8M_HDMI_SW_Pxx_REQ                   BIT(9)
 107 #define IMX8M_VPU_SW_Pxx_REQ                    BIT(8)
 108 #define IMX8M_GPU_SW_Pxx_REQ                    BIT(7)
 109 #define IMX8M_DDR2_SW_Pxx_REQ                   BIT(6)
 110 #define IMX8M_DDR1_SW_Pxx_REQ                   BIT(5)
 111 #define IMX8M_OTG2_SW_Pxx_REQ                   BIT(3)
 112 #define IMX8M_OTG1_SW_Pxx_REQ                   BIT(2)
 113 #define IMX8M_PCIE1_SW_Pxx_REQ                  BIT(1)
 114 #define IMX8M_MIPI_SW_Pxx_REQ                   BIT(0)
 115
 116 #define IMX8MM_VPUH1_SW_Pxx_REQ                 BIT(13)
 117 #define IMX8MM_VPUG2_SW_Pxx_REQ                 BIT(12)
 118 #define IMX8MM_VPUG1_SW_Pxx_REQ                 BIT(11)
 119 #define IMX8MM_DISPMIX_SW_Pxx_REQ               BIT(10)
 120 #define IMX8MM_VPUMIX_SW_Pxx_REQ                BIT(8)
 121 #define IMX8MM_GPUMIX_SW_Pxx_REQ                BIT(7)
 122 #define IMX8MM_GPU_SW_Pxx_REQ                   (BIT(6) | BIT(9))
 123 #define IMX8MM_DDR1_SW_Pxx_REQ                  BIT(5)
 124 #define IMX8MM_OTG2_SW_Pxx_REQ                  BIT(3)
 125 #define IMX8MM_OTG1_SW_Pxx_REQ                  BIT(2)
 126 #define IMX8MM_PCIE_SW_Pxx_REQ                  BIT(1)
 127 #define IMX8MM_MIPI_SW_Pxx_REQ                  BIT(0)
 128
 129 #define IMX8MN_DISPMIX_SW_Pxx_REQ               BIT(10)
 130 #define IMX8MN_GPUMIX_SW_Pxx_REQ                BIT(7)
 131 #define IMX8MN_DDR1_SW_Pxx_REQ          BIT(5)
 132 #define IMX8MN_OTG1_SW_Pxx_REQ          BIT(2)
 133 #define IMX8MN_MIPI_SW_Pxx_REQ          BIT(0)
 134
 135 #define IMX8MP_DDRMIX_Pxx_REQ                   BIT(19)
 136 #define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ            BIT(18)
 137 #define IMX8MP_HSIOMIX_Pxx_REQ                  BIT(17)
 138 #define IMX8MP_MIPI_PHY2_Pxx_REQ                BIT(16)
 139 #define IMX8MP_HDMI_PHY_Pxx_REQ                 BIT(15)
 140 #define IMX8MP_HDMIMIX_Pxx_REQ                  BIT(14)
 141 #define IMX8MP_VPU_VC8K_Pxx_REQ                 BIT(13)
 142 #define IMX8MP_VPU_G2_Pxx_REQ                   BIT(12)
 143 #define IMX8MP_VPU_G1_Pxx_REQ                   BIT(11)
 144 #define IMX8MP_MEDIMIX_Pxx_REQ                  BIT(10)
 145 #define IMX8MP_GPU_3D_Pxx_REQ                   BIT(9)
 146 #define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ      BIT(8)
 147 #define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ          BIT(7)
 148 #define IMX8MP_GPU_2D_Pxx_REQ                   BIT(6)
 149 #define IMX8MP_AUDIOMIX_Pxx_REQ                 BIT(5)
 150 #define IMX8MP_MLMIX_Pxx_REQ                    BIT(4)
 151 #define IMX8MP_USB2_PHY_Pxx_REQ                 BIT(3)
 152 #define IMX8MP_USB1_PHY_Pxx_REQ                 BIT(2)
 153 #define IMX8MP_PCIE_PHY_SW_Pxx_REQ              BIT(1)
 154 #define IMX8MP_MIPI_PHY1_SW_Pxx_REQ             BIT(0)
 155
 156 #define GPC_M4_PU_PDN_FLG               0x1bc
 157
 158 #define IMX8MP_GPC_PU_PWRHSK            0x190
 159 #define GPC_PU_PWRHSK                   0x1fc
 160
 161 #define IMX8M_GPU_HSK_PWRDNACKN                 BIT(26)
 162 #define IMX8M_VPU_HSK_PWRDNACKN                 BIT(25)
 163 #define IMX8M_DISP_HSK_PWRDNACKN                BIT(24)
 164 #define IMX8M_GPU_HSK_PWRDNREQN                 BIT(6)
 165 #define IMX8M_VPU_HSK_PWRDNREQN                 BIT(5)
 166 #define IMX8M_DISP_HSK_PWRDNREQN                BIT(4)
 167
 168 #define IMX8MM_GPUMIX_HSK_PWRDNACKN             BIT(29)
 169 #define IMX8MM_GPU_HSK_PWRDNACKN                (BIT(27) | BIT(28))
 170 #define IMX8MM_VPUMIX_HSK_PWRDNACKN             BIT(26)
 171 #define IMX8MM_DISPMIX_HSK_PWRDNACKN            BIT(25)
 172 #define IMX8MM_HSIO_HSK_PWRDNACKN               (BIT(23) | BIT(24))
 173 #define IMX8MM_GPUMIX_HSK_PWRDNREQN             BIT(11)
 174 #define IMX8MM_GPU_HSK_PWRDNREQN                (BIT(9) | BIT(10))
 175 #define IMX8MM_VPUMIX_HSK_PWRDNREQN             BIT(8)
 176 #define IMX8MM_DISPMIX_HSK_PWRDNREQN            BIT(7)
 177 #define IMX8MM_HSIO_HSK_PWRDNREQN               (BIT(5) | BIT(6))
 178
 179 #define IMX8MN_GPUMIX_HSK_PWRDNACKN             (BIT(29) | BIT(27))
 180 #define IMX8MN_DISPMIX_HSK_PWRDNACKN            BIT(25)
 181 #define IMX8MN_HSIO_HSK_PWRDNACKN               BIT(23)
 182 #define IMX8MN_GPUMIX_HSK_PWRDNREQN             (BIT(11) | BIT(9))
 183 #define IMX8MN_DISPMIX_HSK_PWRDNREQN            BIT(7)
 184 #define IMX8MN_HSIO_HSK_PWRDNREQN               BIT(5)
 185
 186 #define IMX8MP_MEDIAMIX_PWRDNACKN               BIT(30)
 187 #define IMX8MP_HDMIMIX_PWRDNACKN                BIT(29)
 188 #define IMX8MP_HSIOMIX_PWRDNACKN                BIT(28)
 189 #define IMX8MP_VPUMIX_PWRDNACKN                 BIT(26)
 190 #define IMX8MP_GPUMIX_PWRDNACKN                 BIT(25)
 191 #define IMX8MP_MLMIX_PWRDNACKN                  (BIT(23) | BIT(24))
 192 #define IMX8MP_AUDIOMIX_PWRDNACKN               (BIT(20) | BIT(31))
 193 #define IMX8MP_MEDIAMIX_PWRDNREQN               BIT(14)
 194 #define IMX8MP_HDMIMIX_PWRDNREQN                BIT(13)
 195 #define IMX8MP_HSIOMIX_PWRDNREQN                BIT(12)
 196 #define IMX8MP_VPUMIX_PWRDNREQN                 BIT(10)
 197 #define IMX8MP_GPUMIX_PWRDNREQN                 BIT(9)
 198 #define IMX8MP_MLMIX_PWRDNREQN                  (BIT(7) | BIT(8))
 199 #define IMX8MP_AUDIOMIX_PWRDNREQN               (BIT(4) | BIT(15))
 200
 201 /*
 202  * The PGC offset values in Reference Manual
 203  * (Rev. 1, 01/2018 and the older ones) GPC chapter's
 204  * GPC_PGC memory map are incorrect, below offset
 205  * values are from design RTL.
 206  */
 207 #define IMX7_PGC_MIPI                   16
 208 #define IMX7_PGC_PCIE                   17
 209 #define IMX7_PGC_USB_HSIC               20
 210
 211 #define IMX8M_PGC_MIPI                  16
 212 #define IMX8M_PGC_PCIE1                 17
 213 #define IMX8M_PGC_OTG1                  18
 214 #define IMX8M_PGC_OTG2                  19
 215 #define IMX8M_PGC_DDR1                  21
 216 #define IMX8M_PGC_GPU                   23
 217 #define IMX8M_PGC_VPU                   24
 218 #define IMX8M_PGC_DISP                  26
 219 #define IMX8M_PGC_MIPI_CSI1             27
 220 #define IMX8M_PGC_MIPI_CSI2             28
 221 #define IMX8M_PGC_PCIE2                 29
 222
 223 #define IMX8MM_PGC_MIPI                 16
 224 #define IMX8MM_PGC_PCIE                 17
 225 #define IMX8MM_PGC_OTG1                 18
 226 #define IMX8MM_PGC_OTG2                 19
 227 #define IMX8MM_PGC_DDR1                 21
 228 #define IMX8MM_PGC_GPU2D                22
 229 #define IMX8MM_PGC_GPUMIX               23
 230 #define IMX8MM_PGC_VPUMIX               24
 231 #define IMX8MM_PGC_GPU3D                25
 232 #define IMX8MM_PGC_DISPMIX              26
 233 #define IMX8MM_PGC_VPUG1                27
 234 #define IMX8MM_PGC_VPUG2                28
 235 #define IMX8MM_PGC_VPUH1                29
 236
 237 #define IMX8MN_PGC_MIPI         16
 238 #define IMX8MN_PGC_OTG1         18
 239 #define IMX8MN_PGC_DDR1         21
 240 #define IMX8MN_PGC_GPUMIX               23
 241 #define IMX8MN_PGC_DISPMIX              26
 242
 243 #define IMX8MP_PGC_NOC                  9
 244 #define IMX8MP_PGC_MIPI1                12
 245 #define IMX8MP_PGC_PCIE                 13
 246 #define IMX8MP_PGC_USB1                 14
 247 #define IMX8MP_PGC_USB2                 15
 248 #define IMX8MP_PGC_MLMIX                16
 249 #define IMX8MP_PGC_AUDIOMIX             17
 250 #define IMX8MP_PGC_GPU2D                18
 251 #define IMX8MP_PGC_GPUMIX               19
 252 #define IMX8MP_PGC_VPUMIX               20
 253 #define IMX8MP_PGC_GPU3D                21
 254 #define IMX8MP_PGC_MEDIAMIX             22
 255 #define IMX8MP_PGC_VPU_G1               23
 256 #define IMX8MP_PGC_VPU_G2               24
 257 #define IMX8MP_PGC_VPU_VC8000E          25
 258 #define IMX8MP_PGC_HDMIMIX              26
 259 #define IMX8MP_PGC_HDMI                 27
 260 #define IMX8MP_PGC_MIPI2                28
 261 #define IMX8MP_PGC_HSIOMIX              29
 262 #define IMX8MP_PGC_MEDIA_ISP_DWP        30
 263 #define IMX8MP_PGC_DDRMIX               31
 264
 265 #define GPC_PGC_CTRL(n)                 (0x800 + (n) * 0x40)
 266 #define GPC_PGC_SR(n)                   (GPC_PGC_CTRL(n) + 0xc)
 267
 268 #define GPC_PGC_CTRL_PCR                BIT(0)
 269
 270 struct imx_pgc_regs {
 271         u16 map;
 272         u16 pup;
 273         u16 pdn;
 274         u16 hsk;
 275 };
 276
 277 struct imx_pgc_domain {
 278         struct generic_pm_domain genpd;
 279         struct regmap *regmap;
 280         const struct imx_pgc_regs *regs;
 281         struct regulator *regulator;
 282         struct reset_control *reset;
 283         struct clk_bulk_data *clks;
 284         int num_clks;
 285
 286         unsigned long pgc;
 287
 288         const struct {
 289                 u32 pxx;
 290                 u32 map;
 291                 u32 hskreq;
 292                 u32 hskack;
 293         } bits;
 294
 295         const int voltage;
 296         const bool keep_clocks;
 297         struct device *dev;
 298
 299         unsigned int pgc_sw_pup_reg;
 300         unsigned int pgc_sw_pdn_reg;
 301 };
 302
 303 struct imx_pgc_domain_data {
 304         const struct imx_pgc_domain *domains;
 305         size_t domains_num;
 306         const struct regmap_access_table *reg_access_table;
 307         const struct imx_pgc_regs *pgc_regs;
 308 };
 309
 310 static inline struct imx_pgc_domain *
 311 to_imx_pgc_domain(struct generic_pm_domain *genpd)
 312 {
 313         return container_of(genpd, struct imx_pgc_domain, genpd);
 314 }
 315
 316 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 317 {
 318         struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
 319         u32 reg_val, pgc;
 320         int ret;
 321
 322         ret = pm_runtime_get_sync(domain->dev);
 323         if (ret < 0) {
 324                 pm_runtime_put_noidle(domain->dev);
 325                 return ret;
 326         }
 327
 328         if (!IS_ERR(domain->regulator)) {
 329                 ret = regulator_enable(domain->regulator);
 330                 if (ret) {
 331                         dev_err(domain->dev, "failed to enable regulator\n");
 332                         goto out_put_pm;
 333                 }
 334         }
 335
 336         /* Enable reset clocks for all devices in the domain */
 337         ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 338         if (ret) {
 339                 dev_err(domain->dev, "failed to enable reset clocks\n");
 340                 goto out_regulator_disable;
 341         }
 342
 343         reset_control_assert(domain->reset);
 344
 345         if (domain->bits.pxx) {
 346                 /* request the domain to power up */
 347                 regmap_update_bits(domain->regmap, domain->regs->pup,
 348                                    domain->bits.pxx, domain->bits.pxx);
 349                 /*
 350                  * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 351                  * for PUP_REQ/PDN_REQ bit to be cleared
 352                  */
 353                 ret = regmap_read_poll_timeout(domain->regmap,
 354                                                domain->regs->pup, reg_val,
 355                                                !(reg_val & domain->bits.pxx),
 356                                                0, USEC_PER_MSEC);
 357                 if (ret) {
 358                         dev_err(domain->dev, "failed to command PGC\n");
 359                         goto out_clk_disable;
 360                 }
 361
 362                 /* disable power control */
 363                 for_each_set_bit(pgc, &domain->pgc, 32) {
 364                         regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc),
 365                                           GPC_PGC_CTRL_PCR);
 366                 }
 367         }
 368
 369         /* delay for reset to propagate */
 370         udelay(5);
 371
 372         reset_control_deassert(domain->reset);
 373
 374         /* request the ADB400 to power up */
 375         if (domain->bits.hskreq) {
 376                 regmap_update_bits(domain->regmap, domain->regs->hsk,
 377                                    domain->bits.hskreq, domain->bits.hskreq);
 378
 379                 /*
 380                  * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
 381                  *                                (reg_val & domain->bits.hskack), 0,
 382                  *                                USEC_PER_MSEC);
 383                  * Technically we need the commented code to wait handshake. But that needs
 384                  * the BLK-CTL module BUS clk-en bit being set.
 385                  *
 386                  * There is a separate BLK-CTL module and we will have such a driver for it,
 387                  * that driver will set the BUS clk-en bit and handshake will be triggered
 388                  * automatically there. Just add a delay and suppose the handshake finish
 389                  * after that.
 390                  */
 391         }
 392
 393         /* Disable reset clocks for all devices in the domain */
 394         if (!domain->keep_clocks)
 395                 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 396
 397         return 0;
 398
 399 out_clk_disable:
 400         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 401 out_regulator_disable:
 402         if (!IS_ERR(domain->regulator))
 403                 regulator_disable(domain->regulator);
 404 out_put_pm:
 405         pm_runtime_put(domain->dev);
 406
 407         return ret;
 408 }
 409
 410 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
 411 {
 412         struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
 413         u32 reg_val, pgc;
 414         int ret;
 415
 416         /* Enable reset clocks for all devices in the domain */
 417         if (!domain->keep_clocks) {
 418                 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 419                 if (ret) {
 420                         dev_err(domain->dev, "failed to enable reset clocks\n");
 421                         return ret;
 422                 }
 423         }
 424
 425         /* request the ADB400 to power down */
 426         if (domain->bits.hskreq) {
 427                 regmap_clear_bits(domain->regmap, domain->regs->hsk,
 428                                   domain->bits.hskreq);
 429
 430                 ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
 431                                                reg_val,
 432                                                !(reg_val & domain->bits.hskack),
 433                                                0, USEC_PER_MSEC);
 434                 if (ret) {
 435                         dev_err(domain->dev, "failed to power down ADB400\n");
 436                         goto out_clk_disable;
 437                 }
 438         }
 439
 440         if (domain->bits.pxx) {
 441                 /* enable power control */
 442                 for_each_set_bit(pgc, &domain->pgc, 32) {
 443                         regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc),
 444                                            GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
 445                 }
 446
 447                 /* request the domain to power down */
 448                 regmap_update_bits(domain->regmap, domain->regs->pdn,
 449                                    domain->bits.pxx, domain->bits.pxx);
 450                 /*
 451                  * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
 452                  * for PUP_REQ/PDN_REQ bit to be cleared
 453                  */
 454                 ret = regmap_read_poll_timeout(domain->regmap,
 455                                                domain->regs->pdn, reg_val,
 456                                                !(reg_val & domain->bits.pxx),
 457                                                0, USEC_PER_MSEC);
 458                 if (ret) {
 459                         dev_err(domain->dev, "failed to command PGC\n");
 460                         goto out_clk_disable;
 461                 }
 462         }
 463
 464         /* Disable reset clocks for all devices in the domain */
 465         clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 466
 467         if (!IS_ERR(domain->regulator)) {
 468                 ret = regulator_disable(domain->regulator);
 469                 if (ret) {
 470                         dev_err(domain->dev, "failed to disable regulator\n");
 471                         return ret;
 472                 }
 473         }
 474
 475         pm_runtime_put_sync_suspend(domain->dev);
 476
 477         return 0;
 478
 479 out_clk_disable:
 480         if (!domain->keep_clocks)
 481                 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
 482
 483         return ret;
 484 }
 485
 486 static const struct imx_pgc_domain imx7_pgc_domains[] = {
 487         [IMX7_POWER_DOMAIN_MIPI_PHY] = {
 488                 .genpd = {
 489                         .name      = "mipi-phy",
 490                 },
 491                 .bits  = {
 492                         .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
 493                         .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
 494                 },
 495                 .voltage   = 1000000,
 496                 .pgc       = BIT(IMX7_PGC_MIPI),
 497         },
 498
 499         [IMX7_POWER_DOMAIN_PCIE_PHY] = {
 500                 .genpd = {
 501                         .name      = "pcie-phy",
 502                 },
 503                 .bits  = {
 504                         .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
 505                         .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
 506                 },
 507                 .voltage   = 1000000,
 508                 .pgc       = BIT(IMX7_PGC_PCIE),
 509         },
 510
 511         [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
 512                 .genpd = {
 513                         .name      = "usb-hsic-phy",
 514                 },
 515                 .bits  = {
 516                         .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
 517                         .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
 518                 },
 519                 .voltage   = 1200000,
 520                 .pgc       = BIT(IMX7_PGC_USB_HSIC),
 521         },
 522 };
 523
 524 static const struct regmap_range imx7_yes_ranges[] = {
 525                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 526                                  GPC_M4_PU_PDN_FLG),
 527                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
 528                                  GPC_PGC_SR(IMX7_PGC_MIPI)),
 529                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
 530                                  GPC_PGC_SR(IMX7_PGC_PCIE)),
 531                 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
 532                                  GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
 533 };
 534
 535 static const struct regmap_access_table imx7_access_table = {
 536         .yes_ranges     = imx7_yes_ranges,
 537         .n_yes_ranges   = ARRAY_SIZE(imx7_yes_ranges),
 538 };
 539
 540 static const struct imx_pgc_regs imx7_pgc_regs = {
 541         .map = GPC_PGC_CPU_MAPPING,
 542         .pup = GPC_PU_PGC_SW_PUP_REQ,
 543         .pdn = GPC_PU_PGC_SW_PDN_REQ,
 544         .hsk = GPC_PU_PWRHSK,
 545 };
 546
 547 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
 548         .domains = imx7_pgc_domains,
 549         .domains_num = ARRAY_SIZE(imx7_pgc_domains),
 550         .reg_access_table = &imx7_access_table,
 551         .pgc_regs = &imx7_pgc_regs,
 552 };
 553
 554 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
 555         [IMX8M_POWER_DOMAIN_MIPI] = {
 556                 .genpd = {
 557                         .name      = "mipi",
 558                 },
 559                 .bits  = {
 560                         .pxx = IMX8M_MIPI_SW_Pxx_REQ,
 561                         .map = IMX8M_MIPI_A53_DOMAIN,
 562                 },
 563                 .pgc       = BIT(IMX8M_PGC_MIPI),
 564         },
 565
 566         [IMX8M_POWER_DOMAIN_PCIE1] = {
 567                 .genpd = {
 568                         .name = "pcie1",
 569                 },
 570                 .bits  = {
 571                         .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
 572                         .map = IMX8M_PCIE1_A53_DOMAIN,
 573                 },
 574                 .pgc   = BIT(IMX8M_PGC_PCIE1),
 575         },
 576
 577         [IMX8M_POWER_DOMAIN_USB_OTG1] = {
 578                 .genpd = {
 579                         .name = "usb-otg1",
 580                 },
 581                 .bits  = {
 582                         .pxx = IMX8M_OTG1_SW_Pxx_REQ,
 583                         .map = IMX8M_OTG1_A53_DOMAIN,
 584                 },
 585                 .pgc   = BIT(IMX8M_PGC_OTG1),
 586         },
 587
 588         [IMX8M_POWER_DOMAIN_USB_OTG2] = {
 589                 .genpd = {
 590                         .name = "usb-otg2",
 591                 },
 592                 .bits  = {
 593                         .pxx = IMX8M_OTG2_SW_Pxx_REQ,
 594                         .map = IMX8M_OTG2_A53_DOMAIN,
 595                 },
 596                 .pgc   = BIT(IMX8M_PGC_OTG2),
 597         },
 598
 599         [IMX8M_POWER_DOMAIN_DDR1] = {
 600                 .genpd = {
 601                         .name = "ddr1",
 602                 },
 603                 .bits  = {
 604                         .pxx = IMX8M_DDR1_SW_Pxx_REQ,
 605                         .map = IMX8M_DDR2_A53_DOMAIN,
 606                 },
 607                 .pgc   = BIT(IMX8M_PGC_DDR1),
 608         },
 609
 610         [IMX8M_POWER_DOMAIN_GPU] = {
 611                 .genpd = {
 612                         .name = "gpu",
 613                 },
 614                 .bits  = {
 615                         .pxx = IMX8M_GPU_SW_Pxx_REQ,
 616                         .map = IMX8M_GPU_A53_DOMAIN,
 617                         .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
 618                         .hskack = IMX8M_GPU_HSK_PWRDNACKN,
 619                 },
 620                 .pgc   = BIT(IMX8M_PGC_GPU),
 621         },
 622
 623         [IMX8M_POWER_DOMAIN_VPU] = {
 624                 .genpd = {
 625                         .name = "vpu",
 626                 },
 627                 .bits  = {
 628                         .pxx = IMX8M_VPU_SW_Pxx_REQ,
 629                         .map = IMX8M_VPU_A53_DOMAIN,
 630                         .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
 631                         .hskack = IMX8M_VPU_HSK_PWRDNACKN,
 632                 },
 633                 .pgc   = BIT(IMX8M_PGC_VPU),
 634                 .keep_clocks = true,
 635         },
 636
 637         [IMX8M_POWER_DOMAIN_DISP] = {
 638                 .genpd = {
 639                         .name = "disp",
 640                 },
 641                 .bits  = {
 642                         .pxx = IMX8M_DISP_SW_Pxx_REQ,
 643                         .map = IMX8M_DISP_A53_DOMAIN,
 644                         .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
 645                         .hskack = IMX8M_DISP_HSK_PWRDNACKN,
 646                 },
 647                 .pgc   = BIT(IMX8M_PGC_DISP),
 648         },
 649
 650         [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
 651                 .genpd = {
 652                         .name = "mipi-csi1",
 653                 },
 654                 .bits  = {
 655                         .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
 656                         .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
 657                 },
 658                 .pgc   = BIT(IMX8M_PGC_MIPI_CSI1),
 659         },
 660
 661         [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
 662                 .genpd = {
 663                         .name = "mipi-csi2",
 664                 },
 665                 .bits  = {
 666                         .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
 667                         .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
 668                 },
 669                 .pgc   = BIT(IMX8M_PGC_MIPI_CSI2),
 670         },
 671
 672         [IMX8M_POWER_DOMAIN_PCIE2] = {
 673                 .genpd = {
 674                         .name = "pcie2",
 675                 },
 676                 .bits  = {
 677                         .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
 678                         .map = IMX8M_PCIE2_A53_DOMAIN,
 679                 },
 680                 .pgc   = BIT(IMX8M_PGC_PCIE2),
 681         },
 682 };
 683
 684 static const struct regmap_range imx8m_yes_ranges[] = {
 685                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 686                                  GPC_PU_PWRHSK),
 687                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
 688                                  GPC_PGC_SR(IMX8M_PGC_MIPI)),
 689                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
 690                                  GPC_PGC_SR(IMX8M_PGC_PCIE1)),
 691                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
 692                                  GPC_PGC_SR(IMX8M_PGC_OTG1)),
 693                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
 694                                  GPC_PGC_SR(IMX8M_PGC_OTG2)),
 695                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
 696                                  GPC_PGC_SR(IMX8M_PGC_DDR1)),
 697                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
 698                                  GPC_PGC_SR(IMX8M_PGC_GPU)),
 699                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
 700                                  GPC_PGC_SR(IMX8M_PGC_VPU)),
 701                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
 702                                  GPC_PGC_SR(IMX8M_PGC_DISP)),
 703                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
 704                                  GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
 705                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
 706                                  GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
 707                 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
 708                                  GPC_PGC_SR(IMX8M_PGC_PCIE2)),
 709 };
 710
 711 static const struct regmap_access_table imx8m_access_table = {
 712         .yes_ranges     = imx8m_yes_ranges,
 713         .n_yes_ranges   = ARRAY_SIZE(imx8m_yes_ranges),
 714 };
 715
 716 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
 717         .domains = imx8m_pgc_domains,
 718         .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
 719         .reg_access_table = &imx8m_access_table,
 720         .pgc_regs = &imx7_pgc_regs,
 721 };
 722
 723 static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
 724         [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
 725                 .genpd = {
 726                         .name = "hsiomix",
 727                 },
 728                 .bits  = {
 729                         .pxx = 0, /* no power sequence control */
 730                         .map = 0, /* no power sequence control */
 731                         .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
 732                         .hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
 733                 },
 734                 .keep_clocks = true,
 735         },
 736
 737         [IMX8MM_POWER_DOMAIN_PCIE] = {
 738                 .genpd = {
 739                         .name = "pcie",
 740                 },
 741                 .bits  = {
 742                         .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
 743                         .map = IMX8MM_PCIE_A53_DOMAIN,
 744                 },
 745                 .pgc   = BIT(IMX8MM_PGC_PCIE),
 746         },
 747
 748         [IMX8MM_POWER_DOMAIN_OTG1] = {
 749                 .genpd = {
 750                         .name = "usb-otg1",
 751                 },
 752                 .bits  = {
 753                         .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
 754                         .map = IMX8MM_OTG1_A53_DOMAIN,
 755                 },
 756                 .pgc   = BIT(IMX8MM_PGC_OTG1),
 757         },
 758
 759         [IMX8MM_POWER_DOMAIN_OTG2] = {
 760                 .genpd = {
 761                         .name = "usb-otg2",
 762                 },
 763                 .bits  = {
 764                         .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
 765                         .map = IMX8MM_OTG2_A53_DOMAIN,
 766                 },
 767                 .pgc   = BIT(IMX8MM_PGC_OTG2),
 768         },
 769
 770         [IMX8MM_POWER_DOMAIN_GPUMIX] = {
 771                 .genpd = {
 772                         .name = "gpumix",
 773                 },
 774                 .bits  = {
 775                         .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
 776                         .map = IMX8MM_GPUMIX_A53_DOMAIN,
 777                         .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
 778                         .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
 779                 },
 780                 .pgc   = BIT(IMX8MM_PGC_GPUMIX),
 781                 .keep_clocks = true,
 782         },
 783
 784         [IMX8MM_POWER_DOMAIN_GPU] = {
 785                 .genpd = {
 786                         .name = "gpu",
 787                 },
 788                 .bits  = {
 789                         .pxx = IMX8MM_GPU_SW_Pxx_REQ,
 790                         .map = IMX8MM_GPU_A53_DOMAIN,
 791                         .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
 792                         .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
 793                 },
 794                 .pgc   = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D),
 795         },
 796
 797         [IMX8MM_POWER_DOMAIN_VPUMIX] = {
 798                 .genpd = {
 799                         .name = "vpumix",
 800                 },
 801                 .bits  = {
 802                         .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ,
 803                         .map = IMX8MM_VPUMIX_A53_DOMAIN,
 804                         .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
 805                         .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
 806                 },
 807                 .pgc   = BIT(IMX8MM_PGC_VPUMIX),
 808                 .keep_clocks = true,
 809         },
 810
 811         [IMX8MM_POWER_DOMAIN_VPUG1] = {
 812                 .genpd = {
 813                         .name = "vpu-g1",
 814                 },
 815                 .bits  = {
 816                         .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
 817                         .map = IMX8MM_VPUG1_A53_DOMAIN,
 818                 },
 819                 .pgc   = BIT(IMX8MM_PGC_VPUG1),
 820         },
 821
 822         [IMX8MM_POWER_DOMAIN_VPUG2] = {
 823                 .genpd = {
 824                         .name = "vpu-g2",
 825                 },
 826                 .bits  = {
 827                         .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
 828                         .map = IMX8MM_VPUG2_A53_DOMAIN,
 829                 },
 830                 .pgc   = BIT(IMX8MM_PGC_VPUG2),
 831         },
 832
 833         [IMX8MM_POWER_DOMAIN_VPUH1] = {
 834                 .genpd = {
 835                         .name = "vpu-h1",
 836                 },
 837                 .bits  = {
 838                         .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
 839                         .map = IMX8MM_VPUH1_A53_DOMAIN,
 840                 },
 841                 .pgc   = BIT(IMX8MM_PGC_VPUH1),
 842                 .keep_clocks = true,
 843         },
 844
 845         [IMX8MM_POWER_DOMAIN_DISPMIX] = {
 846                 .genpd = {
 847                         .name = "dispmix",
 848                 },
 849                 .bits  = {
 850                         .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ,
 851                         .map = IMX8MM_DISPMIX_A53_DOMAIN,
 852                         .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
 853                         .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
 854                 },
 855                 .pgc   = BIT(IMX8MM_PGC_DISPMIX),
 856                 .keep_clocks = true,
 857         },
 858
 859         [IMX8MM_POWER_DOMAIN_MIPI] = {
 860                 .genpd = {
 861                         .name = "mipi",
 862                 },
 863                 .bits  = {
 864                         .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
 865                         .map = IMX8MM_MIPI_A53_DOMAIN,
 866                 },
 867                 .pgc   = BIT(IMX8MM_PGC_MIPI),
 868         },
 869 };
 870
 871 static const struct regmap_range imx8mm_yes_ranges[] = {
 872                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
 873                                  GPC_PU_PWRHSK),
 874                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
 875                                  GPC_PGC_SR(IMX8MM_PGC_MIPI)),
 876                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
 877                                  GPC_PGC_SR(IMX8MM_PGC_PCIE)),
 878                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
 879                                  GPC_PGC_SR(IMX8MM_PGC_OTG1)),
 880                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
 881                                  GPC_PGC_SR(IMX8MM_PGC_OTG2)),
 882                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
 883                                  GPC_PGC_SR(IMX8MM_PGC_DDR1)),
 884                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
 885                                  GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
 886                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
 887                                  GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
 888                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
 889                                  GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
 890                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
 891                                  GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
 892                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
 893                                  GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
 894                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
 895                                  GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
 896                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
 897                                  GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
 898                 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
 899                                  GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
 900 };
 901
 902 static const struct regmap_access_table imx8mm_access_table = {
 903         .yes_ranges     = imx8mm_yes_ranges,
 904         .n_yes_ranges   = ARRAY_SIZE(imx8mm_yes_ranges),
 905 };
 906
 907 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
 908         .domains = imx8mm_pgc_domains,
 909         .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
 910         .reg_access_table = &imx8mm_access_table,
 911         .pgc_regs = &imx7_pgc_regs,
 912 };
 913
 914 static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
 915         [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
 916                 .genpd = {
 917                         .name = "mipi-phy1",
 918                 },
 919                 .bits = {
 920                         .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
 921                         .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
 922                 },
 923                 .pgc = BIT(IMX8MP_PGC_MIPI1),
 924         },
 925
 926         [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
 927                 .genpd = {
 928                         .name = "pcie-phy1",
 929                 },
 930                 .bits = {
 931                         .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
 932                         .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
 933                 },
 934                 .pgc = BIT(IMX8MP_PGC_PCIE),
 935         },
 936
 937         [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
 938                 .genpd = {
 939                         .name = "usb-otg1",
 940                 },
 941                 .bits = {
 942                         .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
 943                         .map = IMX8MP_USB1_PHY_A53_DOMAIN,
 944                 },
 945                 .pgc = BIT(IMX8MP_PGC_USB1),
 946         },
 947
 948         [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
 949                 .genpd = {
 950                         .name = "usb-otg2",
 951                 },
 952                 .bits = {
 953                         .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
 954                         .map = IMX8MP_USB2_PHY_A53_DOMAIN,
 955                 },
 956                 .pgc = BIT(IMX8MP_PGC_USB2),
 957         },
 958
 959         [IMX8MP_POWER_DOMAIN_MLMIX] = {
 960                 .genpd = {
 961                         .name = "mlmix",
 962                 },
 963                 .bits = {
 964                         .pxx = IMX8MP_MLMIX_Pxx_REQ,
 965                         .map = IMX8MP_MLMIX_A53_DOMAIN,
 966                         .hskreq = IMX8MP_MLMIX_PWRDNREQN,
 967                         .hskack = IMX8MP_MLMIX_PWRDNACKN,
 968                 },
 969                 .pgc = BIT(IMX8MP_PGC_MLMIX),
 970                 .keep_clocks = true,
 971         },
 972
 973         [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
 974                 .genpd = {
 975                         .name = "audiomix",
 976                 },
 977                 .bits = {
 978                         .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
 979                         .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
 980                         .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
 981                         .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
 982                 },
 983                 .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
 984                 .keep_clocks = true,
 985         },
 986
 987         [IMX8MP_POWER_DOMAIN_GPU2D] = {
 988                 .genpd = {
 989                         .name = "gpu2d",
 990                 },
 991                 .bits = {
 992                         .pxx = IMX8MP_GPU_2D_Pxx_REQ,
 993                         .map = IMX8MP_GPU2D_A53_DOMAIN,
 994                 },
 995                 .pgc = BIT(IMX8MP_PGC_GPU2D),
 996         },
 997
 998         [IMX8MP_POWER_DOMAIN_GPUMIX] = {
 999                 .genpd = {
1000                         .name = "gpumix",
1001                 },
1002                 .bits = {
1003                         .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
1004                         .map = IMX8MP_GPUMIX_A53_DOMAIN,
1005                         .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
1006                         .hskack = IMX8MP_GPUMIX_PWRDNACKN,
1007                 },
1008                 .pgc = BIT(IMX8MP_PGC_GPUMIX),
1009                 .keep_clocks = true,
1010         },
1011
1012         [IMX8MP_POWER_DOMAIN_VPUMIX] = {
1013                 .genpd = {
1014                         .name = "vpumix",
1015                 },
1016                 .bits = {
1017                         .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
1018                         .map = IMX8MP_VPUMIX_A53_DOMAIN,
1019                         .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
1020                         .hskack = IMX8MP_VPUMIX_PWRDNACKN,
1021                 },
1022                 .pgc = BIT(IMX8MP_PGC_VPUMIX),
1023                 .keep_clocks = true,
1024         },
1025
1026         [IMX8MP_POWER_DOMAIN_GPU3D] = {
1027                 .genpd = {
1028                         .name = "gpu3d",
1029                 },
1030                 .bits = {
1031                         .pxx = IMX8MP_GPU_3D_Pxx_REQ,
1032                         .map = IMX8MP_GPU3D_A53_DOMAIN,
1033                 },
1034                 .pgc = BIT(IMX8MP_PGC_GPU3D),
1035         },
1036
1037         [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
1038                 .genpd = {
1039                         .name = "mediamix",
1040                 },
1041                 .bits = {
1042                         .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
1043                         .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
1044                         .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
1045                         .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
1046                 },
1047                 .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
1048                 .keep_clocks = true,
1049         },
1050
1051         [IMX8MP_POWER_DOMAIN_VPU_G1] = {
1052                 .genpd = {
1053                         .name = "vpu-g1",
1054                 },
1055                 .bits = {
1056                         .pxx = IMX8MP_VPU_G1_Pxx_REQ,
1057                         .map = IMX8MP_VPU_G1_A53_DOMAIN,
1058                 },
1059                 .pgc = BIT(IMX8MP_PGC_VPU_G1),
1060         },
1061
1062         [IMX8MP_POWER_DOMAIN_VPU_G2] = {
1063                 .genpd = {
1064                         .name = "vpu-g2",
1065                 },
1066                 .bits = {
1067                         .pxx = IMX8MP_VPU_G2_Pxx_REQ,
1068                         .map = IMX8MP_VPU_G2_A53_DOMAIN
1069                 },
1070                 .pgc = BIT(IMX8MP_PGC_VPU_G2),
1071         },
1072
1073         [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
1074                 .genpd = {
1075                         .name = "vpu-h1",
1076                 },
1077                 .bits = {
1078                         .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
1079                         .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
1080                 },
1081                 .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
1082         },
1083
1084         [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
1085                 .genpd = {
1086                         .name = "hdmimix",
1087                 },
1088                 .bits = {
1089                         .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
1090                         .map = IMX8MP_HDMIMIX_A53_DOMAIN,
1091                         .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
1092                         .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
1093                 },
1094                 .pgc = BIT(IMX8MP_PGC_HDMIMIX),
1095                 .keep_clocks = true,
1096         },
1097
1098         [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
1099                 .genpd = {
1100                         .name = "hdmi-phy",
1101                 },
1102                 .bits = {
1103                         .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
1104                         .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
1105                 },
1106                 .pgc = BIT(IMX8MP_PGC_HDMI),
1107         },
1108
1109         [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
1110                 .genpd = {
1111                         .name = "mipi-phy2",
1112                 },
1113                 .bits = {
1114                         .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
1115                         .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
1116                 },
1117                 .pgc = BIT(IMX8MP_PGC_MIPI2),
1118         },
1119
1120         [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
1121                 .genpd = {
1122                         .name = "hsiomix",
1123                 },
1124                 .bits = {
1125                         .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
1126                         .map = IMX8MP_HSIOMIX_A53_DOMAIN,
1127                         .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
1128                         .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
1129                 },
1130                 .pgc = BIT(IMX8MP_PGC_HSIOMIX),
1131                 .keep_clocks = true,
1132         },
1133
1134         [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
1135                 .genpd = {
1136                         .name = "mediamix-isp-dwp",
1137                 },
1138                 .bits = {
1139                         .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
1140                         .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
1141                 },
1142                 .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
1143         },
1144 };
1145
1146 static const struct regmap_range imx8mp_yes_ranges[] = {
1147                 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
1148                                  IMX8MP_GPC_PGC_CPU_MAPPING),
1149                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
1150                                  GPC_PGC_SR(IMX8MP_PGC_NOC)),
1151                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
1152                                  GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
1153                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
1154                                  GPC_PGC_SR(IMX8MP_PGC_PCIE)),
1155                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
1156                                  GPC_PGC_SR(IMX8MP_PGC_USB1)),
1157                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
1158                                  GPC_PGC_SR(IMX8MP_PGC_USB2)),
1159                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
1160                                  GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
1161                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
1162                                  GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
1163                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
1164                                  GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
1165                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
1166                                  GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
1167                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
1168                                  GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
1169                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
1170                                  GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
1171                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
1172                                  GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
1173                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
1174                                  GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
1175                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
1176                                  GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
1177                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
1178                                  GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
1179                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
1180                                  GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
1181                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
1182                                  GPC_PGC_SR(IMX8MP_PGC_HDMI)),
1183                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
1184                                  GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
1185                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
1186                                  GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
1187                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
1188                                  GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
1189                 regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
1190                                  GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
1191 };
1192
1193 static const struct regmap_access_table imx8mp_access_table = {
1194         .yes_ranges     = imx8mp_yes_ranges,
1195         .n_yes_ranges   = ARRAY_SIZE(imx8mp_yes_ranges),
1196 };
1197
1198 static const struct imx_pgc_regs imx8mp_pgc_regs = {
1199         .map = IMX8MP_GPC_PGC_CPU_MAPPING,
1200         .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
1201         .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
1202         .hsk = IMX8MP_GPC_PU_PWRHSK,
1203 };
1204 static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
1205         .domains = imx8mp_pgc_domains,
1206         .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
1207         .reg_access_table = &imx8mp_access_table,
1208         .pgc_regs = &imx8mp_pgc_regs,
1209 };
1210
1211 static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
1212         [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
1213                 .genpd = {
1214                         .name = "hsiomix",
1215                 },
1216                 .bits  = {
1217                         .pxx = 0, /* no power sequence control */
1218                         .map = 0, /* no power sequence control */
1219                         .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
1220                         .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
1221                 },
1222                 .keep_clocks = true,
1223         },
1224
1225         [IMX8MN_POWER_DOMAIN_OTG1] = {
1226                 .genpd = {
1227                         .name = "usb-otg1",
1228                 },
1229                 .bits  = {
1230                         .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
1231                         .map = IMX8MN_OTG1_A53_DOMAIN,
1232                 },
1233                 .pgc   = BIT(IMX8MN_PGC_OTG1),
1234         },
1235
1236         [IMX8MN_POWER_DOMAIN_GPUMIX] = {
1237                 .genpd = {
1238                         .name = "gpumix",
1239                 },
1240                 .bits  = {
1241                         .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
1242                         .map = IMX8MN_GPUMIX_A53_DOMAIN,
1243                         .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
1244                         .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
1245                 },
1246                 .pgc   = BIT(IMX8MN_PGC_GPUMIX),
1247                 .keep_clocks = true,
1248         },
1249
1250         [IMX8MN_POWER_DOMAIN_DISPMIX] = {
1251                 .genpd = {
1252                         .name = "dispmix",
1253                 },
1254                         .bits  = {
1255                         .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
1256                         .map = IMX8MN_DISPMIX_A53_DOMAIN,
1257                         .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
1258                         .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
1259                 },
1260                 .pgc   = BIT(IMX8MN_PGC_DISPMIX),
1261                 .keep_clocks = true,
1262         },
1263
1264         [IMX8MN_POWER_DOMAIN_MIPI] = {
1265                 .genpd = {
1266                         .name = "mipi",
1267                 },
1268                         .bits  = {
1269                         .pxx = IMX8MN_MIPI_SW_Pxx_REQ,
1270                         .map = IMX8MN_MIPI_A53_DOMAIN,
1271                 },
1272                 .pgc   = BIT(IMX8MN_PGC_MIPI),
1273         },
1274 };
1275
1276 static const struct regmap_range imx8mn_yes_ranges[] = {
1277         regmap_reg_range(GPC_LPCR_A_CORE_BSC,
1278                          GPC_PU_PWRHSK),
1279         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
1280                          GPC_PGC_SR(IMX8MN_PGC_MIPI)),
1281         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
1282                          GPC_PGC_SR(IMX8MN_PGC_OTG1)),
1283         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
1284                          GPC_PGC_SR(IMX8MN_PGC_DDR1)),
1285         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
1286                          GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
1287         regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
1288                          GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
1289 };
1290
1291 static const struct regmap_access_table imx8mn_access_table = {
1292         .yes_ranges     = imx8mn_yes_ranges,
1293         .n_yes_ranges   = ARRAY_SIZE(imx8mn_yes_ranges),
1294 };
1295
1296 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
1297         .domains = imx8mn_pgc_domains,
1298         .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
1299         .reg_access_table = &imx8mn_access_table,
1300         .pgc_regs = &imx7_pgc_regs,
1301 };
1302
1303 static int imx_pgc_domain_probe(struct platform_device *pdev)
1304 {
1305         struct imx_pgc_domain *domain = pdev->dev.platform_data;
1306         int ret;
1307
1308         domain->dev = &pdev->dev;
1309
1310         domain->regulator = devm_regulator_get_optional(domain->dev, "power");
1311         if (IS_ERR(domain->regulator)) {
1312                 if (PTR_ERR(domain->regulator) != -ENODEV)
1313                         return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
1314                                              "Failed to get domain's regulator\n");
1315         } else if (domain->voltage) {
1316                 regulator_set_voltage(domain->regulator,
1317                                       domain->voltage, domain->voltage);
1318         }
1319
1320         domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
1321         if (domain->num_clks < 0)
1322                 return dev_err_probe(domain->dev, domain->num_clks,
1323                                      "Failed to get domain's clocks\n");
1324
1325         domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
1326         if (IS_ERR(domain->reset))
1327                 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
1328                                      "Failed to get domain's resets\n");
1329
1330         pm_runtime_enable(domain->dev);
1331
1332         if (domain->bits.map)
1333                 regmap_update_bits(domain->regmap, domain->regs->map,
1334                                    domain->bits.map, domain->bits.map);
1335
1336         ret = pm_genpd_init(&domain->genpd, NULL, true);
1337         if (ret) {
1338                 dev_err(domain->dev, "Failed to init power domain\n");
1339                 goto out_domain_unmap;
1340         }
1341
1342         if (IS_ENABLED(CONFIG_LOCKDEP) &&
1343             of_property_read_bool(domain->dev->of_node, "power-domains"))
1344                 lockdep_set_subclass(&domain->genpd.mlock, 1);
1345
1346         ret = of_genpd_add_provider_simple(domain->dev->of_node,
1347                                            &domain->genpd);
1348         if (ret) {
1349                 dev_err(domain->dev, "Failed to add genpd provider\n");
1350                 goto out_genpd_remove;
1351         }
1352
1353         return 0;
1354
1355 out_genpd_remove:
1356         pm_genpd_remove(&domain->genpd);
1357 out_domain_unmap:
1358         if (domain->bits.map)
1359                 regmap_update_bits(domain->regmap, domain->regs->map,
1360                                    domain->bits.map, 0);
1361         pm_runtime_disable(domain->dev);
1362
1363         return ret;
1364 }
1365
1366 static int imx_pgc_domain_remove(struct platform_device *pdev)
1367 {
1368         struct imx_pgc_domain *domain = pdev->dev.platform_data;
1369
1370         of_genpd_del_provider(domain->dev->of_node);
1371         pm_genpd_remove(&domain->genpd);
1372
1373         if (domain->bits.map)
1374                 regmap_update_bits(domain->regmap, domain->regs->map,
1375                                    domain->bits.map, 0);
1376
1377         pm_runtime_disable(domain->dev);
1378
1379         return 0;
1380 }
1381
1382 #ifdef CONFIG_PM_SLEEP
1383 static int imx_pgc_domain_suspend(struct device *dev)
1384 {
1385         int ret;
1386
1387         /*
1388          * This may look strange, but is done so the generic PM_SLEEP code
1389          * can power down our domain and more importantly power it up again
1390          * after resume, without tripping over our usage of runtime PM to
1391          * power up/down the nested domains.
1392          */
1393         ret = pm_runtime_get_sync(dev);
1394         if (ret < 0) {
1395                 pm_runtime_put_noidle(dev);
1396                 return ret;
1397         }
1398
1399         return 0;
1400 }
1401
1402 static int imx_pgc_domain_resume(struct device *dev)
1403 {
1404         return pm_runtime_put(dev);
1405 }
1406 #endif
1407
1408 static const struct dev_pm_ops imx_pgc_domain_pm_ops = {
1409         SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume)
1410 };
1411
1412 static const struct platform_device_id imx_pgc_domain_id[] = {
1413         { "imx-pgc-domain", },
1414         { },
1415 };
1416
1417 static struct platform_driver imx_pgc_domain_driver = {
1418         .driver = {
1419                 .name = "imx-pgc",
1420                 .pm = &imx_pgc_domain_pm_ops,
1421         },
1422         .probe    = imx_pgc_domain_probe,
1423         .remove   = imx_pgc_domain_remove,
1424         .id_table = imx_pgc_domain_id,
1425 };
1426 builtin_platform_driver(imx_pgc_domain_driver)
1427
1428 static int imx_gpcv2_probe(struct platform_device *pdev)
1429 {
1430         const struct imx_pgc_domain_data *domain_data =
1431                         of_device_get_match_data(&pdev->dev);
1432
1433         struct regmap_config regmap_config = {
1434                 .reg_bits       = 32,
1435                 .val_bits       = 32,
1436                 .reg_stride     = 4,
1437                 .rd_table       = domain_data->reg_access_table,
1438                 .wr_table       = domain_data->reg_access_table,
1439                 .max_register   = SZ_4K,
1440         };
1441         struct device *dev = &pdev->dev;
1442         struct device_node *pgc_np, *np;
1443         struct regmap *regmap;
1444         void __iomem *base;
1445         int ret;
1446
1447         pgc_np = of_get_child_by_name(dev->of_node, "pgc");
1448         if (!pgc_np) {
1449                 dev_err(dev, "No power domains specified in DT\n");
1450                 return -EINVAL;
1451         }
1452
1453         base = devm_platform_ioremap_resource(pdev, 0);
1454         if (IS_ERR(base))
1455                 return PTR_ERR(base);
1456
1457         regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
1458         if (IS_ERR(regmap)) {
1459                 ret = PTR_ERR(regmap);
1460                 dev_err(dev, "failed to init regmap (%d)\n", ret);
1461                 return ret;
1462         }
1463
1464         for_each_child_of_node(pgc_np, np) {
1465                 struct platform_device *pd_pdev;
1466                 struct imx_pgc_domain *domain;
1467                 u32 domain_index;
1468
1469                 if (!of_device_is_available(np))
1470                         continue;
1471
1472                 ret = of_property_read_u32(np, "reg", &domain_index);
1473                 if (ret) {
1474                         dev_err(dev, "Failed to read 'reg' property\n");
1475                         of_node_put(np);
1476                         return ret;
1477                 }
1478
1479                 if (domain_index >= domain_data->domains_num) {
1480                         dev_warn(dev,
1481                                  "Domain index %d is out of bounds\n",
1482                                  domain_index);
1483                         continue;
1484                 }
1485
1486                 pd_pdev = platform_device_alloc("imx-pgc-domain",
1487                                                 domain_index);
1488                 if (!pd_pdev) {
1489                         dev_err(dev, "Failed to allocate platform device\n");
1490                         of_node_put(np);
1491                         return -ENOMEM;
1492                 }
1493
1494                 ret = platform_device_add_data(pd_pdev,
1495                                                &domain_data->domains[domain_index],
1496                                                sizeof(domain_data->domains[domain_index]));
1497                 if (ret) {
1498                         platform_device_put(pd_pdev);
1499                         of_node_put(np);
1500                         return ret;
1501                 }
1502
1503                 domain = pd_pdev->dev.platform_data;
1504                 domain->regmap = regmap;
1505                 domain->regs = domain_data->pgc_regs;
1506
1507                 domain->genpd.power_on  = imx_pgc_power_up;
1508                 domain->genpd.power_off = imx_pgc_power_down;
1509
1510                 pd_pdev->dev.parent = dev;
1511                 pd_pdev->dev.of_node = np;
1512
1513                 ret = platform_device_add(pd_pdev);
1514                 if (ret) {
1515                         platform_device_put(pd_pdev);
1516                         of_node_put(np);
1517                         return ret;
1518                 }
1519         }
1520
1521         return 0;
1522 }
1523
1524 static const struct of_device_id imx_gpcv2_dt_ids[] = {
1525         { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1526         { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1527         { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1528         { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
1529         { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1530         { }
1531 };
1532
1533 static struct platform_driver imx_gpc_driver = {
1534         .driver = {
1535                 .name = "imx-gpcv2",
1536                 .of_match_table = imx_gpcv2_dt_ids,
1537         },
1538         .probe = imx_gpcv2_probe,
1539 };
1540 builtin_platform_driver(imx_gpc_driver)