1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
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15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
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31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <soc/fsl/qman.h>
36 #include <linux/iommu.h>
38 #if defined(CONFIG_FSL_PAMU)
39 #include <asm/fsl_pamu_stash.h>
42 struct qm_mcr_querywq {
45 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
50 static inline u16 qm_mcr_querywq_get_chan(const struct qm_mcr_querywq *wq)
52 return wq->channel_wq >> 3;
55 struct __qm_mcr_querycongestion {
59 /* "Query Congestion Group State" */
60 struct qm_mcr_querycongestion {
64 /* Access this struct using qman_cgrs_get() */
65 struct __qm_mcr_querycongestion state;
69 struct qm_mcr_querycgr {
73 struct __qm_mc_cgr cgr; /* CGR fields */
75 u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */
76 u32 i_bcnt_lo; /* low 32-bits of 40-bit */
78 u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */
79 u32 a_bcnt_lo; /* low 32-bits of 40-bit */
83 static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q)
85 return ((u64)q->i_bcnt_hi << 32) | (u64)q->i_bcnt_lo;
87 static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)
89 return ((u64)q->a_bcnt_hi << 32) | (u64)q->a_bcnt_lo;
92 /* "Query FQ Non-Programmable Fields" */
93 struct qm_mcc_queryfq_np {
96 u32 fqid; /* 24-bit */
100 struct qm_mcr_queryfq_np {
104 u8 state; /* QM_MCR_NP_STATE_*** */
105 u32 fqd_link; /* 24-bit, _res2[24-31] */
106 u16 odp_seq; /* 14-bit, _res3[14-15] */
107 u16 orp_nesn; /* 14-bit, _res4[14-15] */
108 u16 orp_ea_hseq; /* 15-bit, _res5[15] */
109 u16 orp_ea_tseq; /* 15-bit, _res6[15] */
110 u32 orp_ea_hptr; /* 24-bit, _res7[24-31] */
111 u32 orp_ea_tptr; /* 24-bit, _res8[24-31] */
112 u32 pfdr_hptr; /* 24-bit, _res9[24-31] */
113 u32 pfdr_tptr; /* 24-bit, _res10[24-31] */
115 u8 is; /* 1-bit, _res12[1-7] */
118 u32 frm_cnt; /* 24-bit, _res13[24-31] */
120 u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */
121 u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */
123 u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */
124 u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */
125 u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */
128 #define QM_MCR_NP_STATE_FE 0x10
129 #define QM_MCR_NP_STATE_R 0x08
130 #define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */
131 #define QM_MCR_NP_STATE_OOS 0x00
132 #define QM_MCR_NP_STATE_RETIRED 0x01
133 #define QM_MCR_NP_STATE_TEN_SCHED 0x02
134 #define QM_MCR_NP_STATE_TRU_SCHED 0x03
135 #define QM_MCR_NP_STATE_PARKED 0x04
136 #define QM_MCR_NP_STATE_ACTIVE 0x05
137 #define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */
138 #define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
139 #define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
140 #define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
141 #define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
143 enum qm_mcr_queryfq_np_masks {
144 qm_mcr_fqd_link_mask = BIT(24)-1,
145 qm_mcr_odp_seq_mask = BIT(14)-1,
146 qm_mcr_orp_nesn_mask = BIT(14)-1,
147 qm_mcr_orp_ea_hseq_mask = BIT(15)-1,
148 qm_mcr_orp_ea_tseq_mask = BIT(15)-1,
149 qm_mcr_orp_ea_hptr_mask = BIT(24)-1,
150 qm_mcr_orp_ea_tptr_mask = BIT(24)-1,
151 qm_mcr_pfdr_hptr_mask = BIT(24)-1,
152 qm_mcr_pfdr_tptr_mask = BIT(24)-1,
153 qm_mcr_is_mask = BIT(1)-1,
154 qm_mcr_frm_cnt_mask = BIT(24)-1,
156 #define qm_mcr_np_get(np, field) \
157 ((np)->field & (qm_mcr_##field##_mask))
159 /* Congestion Groups */
162 * This wrapper represents a bit-array for the state of the 256 QMan congestion
163 * groups. Is also used as a *mask* for congestion groups, eg. so we ignore
164 * those that don't concern us. We harness the structure and accessor details
165 * already used in the management command to query congestion groups.
167 #define CGR_BITS_PER_WORD 5
168 #define CGR_WORD(x) ((x) >> CGR_BITS_PER_WORD)
169 #define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f))
170 #define CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3)
173 struct __qm_mcr_querycongestion q;
176 static inline void qman_cgrs_init(struct qman_cgrs *c)
178 memset(c, 0, sizeof(*c));
181 static inline void qman_cgrs_fill(struct qman_cgrs *c)
183 memset(c, 0xff, sizeof(*c));
186 static inline int qman_cgrs_get(struct qman_cgrs *c, u8 cgr)
188 return c->q.state[CGR_WORD(cgr)] & CGR_BIT(cgr);
191 static inline void qman_cgrs_cp(struct qman_cgrs *dest,
192 const struct qman_cgrs *src)
197 static inline void qman_cgrs_and(struct qman_cgrs *dest,
198 const struct qman_cgrs *a, const struct qman_cgrs *b)
201 u32 *_d = dest->q.state;
202 const u32 *_a = a->q.state;
203 const u32 *_b = b->q.state;
205 for (ret = 0; ret < 8; ret++)
206 *_d++ = *_a++ & *_b++;
209 static inline void qman_cgrs_xor(struct qman_cgrs *dest,
210 const struct qman_cgrs *a, const struct qman_cgrs *b)
213 u32 *_d = dest->q.state;
214 const u32 *_a = a->q.state;
215 const u32 *_b = b->q.state;
217 for (ret = 0; ret < 8; ret++)
218 *_d++ = *_a++ ^ *_b++;
221 void qman_init_cgr_all(void);
223 struct qm_portal_config {
225 * Corenet portal addresses;
226 * [0]==cache-enabled, [1]==cache-inhibited.
228 void __iomem *addr_virt[2];
230 struct iommu_domain *iommu_domain;
231 /* Allow these to be joined in lists */
232 struct list_head list;
233 /* User-visible portal configuration settings */
234 /* portal is affined to this cpu */
236 /* portal interrupt line */
239 * the portal's dedicated channel id, used initialising
240 * frame queues to target this portal when scheduled
244 * mask of pool channels this portal has dequeue access to
245 * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask)
250 /* Revision info (for errata and feature handling) */
251 #define QMAN_REV11 0x0101
252 #define QMAN_REV12 0x0102
253 #define QMAN_REV20 0x0200
254 #define QMAN_REV30 0x0300
255 #define QMAN_REV31 0x0301
256 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
258 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
259 extern struct gen_pool *qm_fqalloc; /* FQID allocator */
260 extern struct gen_pool *qm_qpalloc; /* pool-channel allocator */
261 extern struct gen_pool *qm_cgralloc; /* CGR ID allocator */
262 u32 qm_get_pools_sdqcr(void);
264 int qman_wq_alloc(void);
265 void qman_liodn_fixup(u16 channel);
266 void qman_set_sdest(u16 channel, unsigned int cpu_idx);
268 struct qman_portal *qman_create_affine_portal(
269 const struct qm_portal_config *config,
270 const struct qman_cgrs *cgrs);
271 const struct qm_portal_config *qman_destroy_affine_portal(void);
274 * qman_query_fq - Queries FQD fields (via h/w query command)
275 * @fq: the frame queue object to be queried
276 * @fqd: storage for the queried FQD fields
278 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
281 * For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
282 * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
283 * FQID(n) to fill in the frame queue ID.
285 #define QM_VDQCR_PRECEDENCE_VDQCR 0x0
286 #define QM_VDQCR_PRECEDENCE_SDQCR 0x80000000
287 #define QM_VDQCR_EXACT 0x40000000
288 #define QM_VDQCR_NUMFRAMES_MASK 0x3f000000
289 #define QM_VDQCR_NUMFRAMES_SET(n) (((n) & 0x3f) << 24)
290 #define QM_VDQCR_NUMFRAMES_GET(n) (((n) >> 24) & 0x3f)
291 #define QM_VDQCR_NUMFRAMES_TILLEMPTY QM_VDQCR_NUMFRAMES_SET(0)
293 #define QMAN_VOLATILE_FLAG_WAIT 0x00000001 /* wait if VDQCR is in use */
294 #define QMAN_VOLATILE_FLAG_WAIT_INT 0x00000002 /* if wait, interruptible? */
295 #define QMAN_VOLATILE_FLAG_FINISH 0x00000004 /* wait till VDQCR completes */
298 * qman_volatile_dequeue - Issue a volatile dequeue command
299 * @fq: the frame queue object to dequeue from
300 * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
301 * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
303 * Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
304 * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
305 * the VDQCR is already in use, otherwise returns non-zero for failure. If
306 * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
307 * the VDQCR command has finished executing (ie. once the callback for the last
308 * DQRR entry resulting from the VDQCR command has been called). If not using
309 * the FINISH flag, completion can be determined either by detecting the
310 * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
311 * in the "stat" parameter passed to the FQ's dequeue callback, or by waiting
312 * for the QMAN_FQ_STATE_VDQCR bit to disappear.
314 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
316 int qman_alloc_fq_table(u32 num_fqids);
318 /* QMan s/w corenet portal, low-level i/face */
321 * For qm_dqrr_sdqcr_set(); Choose one SOURCE. Choose one COUNT. Choose one
322 * dequeue TYPE. Choose TOKEN (8-bit).
323 * If SOURCE == CHANNELS,
324 * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n).
325 * You can choose DEDICATED_PRECEDENCE if the portal channel should have
327 * If SOURCE == SPECIFICWQ,
328 * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
329 * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
330 * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
333 #define QM_SDQCR_SOURCE_CHANNELS 0x0
334 #define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
335 #define QM_SDQCR_COUNT_EXACT1 0x0
336 #define QM_SDQCR_COUNT_UPTO3 0x20000000
337 #define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
338 #define QM_SDQCR_TYPE_MASK 0x03000000
339 #define QM_SDQCR_TYPE_NULL 0x0
340 #define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
341 #define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
342 #define QM_SDQCR_TYPE_ACTIVE 0x03000000
343 #define QM_SDQCR_TOKEN_MASK 0x00ff0000
344 #define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
345 #define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
346 #define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
347 #define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
348 #define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
349 #define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
350 #define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
352 /* For qm_dqrr_vdqcr_set(): use FQID(n) to fill in the frame queue ID */
353 #define QM_VDQCR_FQID_MASK 0x00ffffff
354 #define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
357 * Used by all portal interrupt registers except 'inhibit'
358 * Channels with frame availability
360 #define QM_PIRQ_DQAVAIL 0x0000ffff
362 /* The DQAVAIL interrupt fields break down into these bits; */
363 #define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */
364 #define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */
365 #define QM_DQAVAIL_MASK 0xffff
366 /* This mask contains all the "irqsource" bits visible to API users */
367 #define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
369 extern struct qman_portal *affine_portals[NR_CPUS];
370 const struct qm_portal_config *qman_get_qm_portal_config(
371 struct qman_portal *portal);