1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
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15 * GNU General Public License ("GPL") as published by the Free Software
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31 #include "qman_priv.h"
33 #define DQRR_MAXFILL 15
34 #define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
35 #define IRQNAME "QMan portal %d"
36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
37 #define QMAN_POLL_LIMIT 32
38 #define QMAN_PIRQ_DQRR_ITHRESH 12
39 #define QMAN_PIRQ_MR_ITHRESH 4
40 #define QMAN_PIRQ_IPERIOD 100
42 /* Portal register assists */
44 /* Cache-inhibited register offsets */
45 #define QM_REG_EQCR_PI_CINH 0x0000
46 #define QM_REG_EQCR_CI_CINH 0x0004
47 #define QM_REG_EQCR_ITR 0x0008
48 #define QM_REG_DQRR_PI_CINH 0x0040
49 #define QM_REG_DQRR_CI_CINH 0x0044
50 #define QM_REG_DQRR_ITR 0x0048
51 #define QM_REG_DQRR_DCAP 0x0050
52 #define QM_REG_DQRR_SDQCR 0x0054
53 #define QM_REG_DQRR_VDQCR 0x0058
54 #define QM_REG_DQRR_PDQCR 0x005c
55 #define QM_REG_MR_PI_CINH 0x0080
56 #define QM_REG_MR_CI_CINH 0x0084
57 #define QM_REG_MR_ITR 0x0088
58 #define QM_REG_CFG 0x0100
59 #define QM_REG_ISR 0x0e00
60 #define QM_REG_IER 0x0e04
61 #define QM_REG_ISDR 0x0e08
62 #define QM_REG_IIR 0x0e0c
63 #define QM_REG_ITPR 0x0e14
65 /* Cache-enabled register offsets */
66 #define QM_CL_EQCR 0x0000
67 #define QM_CL_DQRR 0x1000
68 #define QM_CL_MR 0x2000
69 #define QM_CL_EQCR_PI_CENA 0x3000
70 #define QM_CL_EQCR_CI_CENA 0x3100
71 #define QM_CL_DQRR_PI_CENA 0x3200
72 #define QM_CL_DQRR_CI_CENA 0x3300
73 #define QM_CL_MR_PI_CENA 0x3400
74 #define QM_CL_MR_CI_CENA 0x3500
75 #define QM_CL_CR 0x3800
76 #define QM_CL_RR0 0x3900
77 #define QM_CL_RR1 0x3940
80 * BTW, the drivers (and h/w programming model) already obtain the required
81 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
82 * or other order-preserving primitives simply degrade performance. Hence the
83 * use of the __raw_*() interfaces, which simply ensure that the compiler treats
84 * the portal registers as volatile
87 /* Cache-enabled ring access */
88 #define qm_cl(base, idx) ((void *)base + ((idx) << 6))
93 * pmode == production mode
94 * cmode == consumption mode,
95 * dmode == h/w dequeue mode.
96 * Enum values use 3 letter codes. First letter matches the portal mode,
97 * remaining two letters indicate;
98 * ci == cache-inhibited portal register
99 * ce == cache-enabled portal register
100 * vb == in-band valid-bit (cache-enabled)
101 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
102 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
104 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
105 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
106 qm_eqcr_pce = 1, /* PI index, cache-enabled */
107 qm_eqcr_pvb = 2 /* valid-bit */
109 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
110 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
111 qm_dqrr_dpull = 1 /* PDQCR */
113 enum qm_dqrr_pmode { /* s/w-only */
114 qm_dqrr_pci, /* reads DQRR_PI_CINH */
115 qm_dqrr_pce, /* reads DQRR_PI_CENA */
116 qm_dqrr_pvb /* reads valid-bit */
118 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
119 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
120 qm_dqrr_cce = 1, /* CI index, cache-enabled */
121 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
123 enum qm_mr_pmode { /* s/w-only */
124 qm_mr_pci, /* reads MR_PI_CINH */
125 qm_mr_pce, /* reads MR_PI_CENA */
126 qm_mr_pvb /* reads valid-bit */
128 enum qm_mr_cmode { /* matches QCSP_CFG::MM */
129 qm_mr_cci = 0, /* CI index, cache-inhibited */
130 qm_mr_cce = 1 /* CI index, cache-enabled */
133 /* --- Portal structures --- */
135 #define QM_EQCR_SIZE 8
136 #define QM_DQRR_SIZE 16
139 /* "Enqueue Command" */
140 struct qm_eqcr_entry {
141 u8 _ncw_verb; /* writes to this are non-coherent */
144 u32 orp; /* 24-bit */
145 u32 fqid; /* 24-bit */
149 } __packed __aligned(8);
150 #define QM_EQCR_VERB_VBIT 0x80
151 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
152 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01
153 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
154 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
155 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
158 struct qm_eqcr_entry *ring, *cursor;
159 u8 ci, available, ithresh, vbit;
160 #ifdef CONFIG_FSL_DPAA_CHECKING
162 enum qm_eqcr_pmode pmode;
167 const struct qm_dqrr_entry *ring, *cursor;
168 u8 pi, ci, fill, ithresh, vbit;
169 #ifdef CONFIG_FSL_DPAA_CHECKING
170 enum qm_dqrr_dmode dmode;
171 enum qm_dqrr_pmode pmode;
172 enum qm_dqrr_cmode cmode;
177 union qm_mr_entry *ring, *cursor;
178 u8 pi, ci, fill, ithresh, vbit;
179 #ifdef CONFIG_FSL_DPAA_CHECKING
180 enum qm_mr_pmode pmode;
181 enum qm_mr_cmode cmode;
185 /* MC (Management Command) command */
187 struct qm_mcc_queryfq {
190 u32 fqid; /* 24-bit */
193 /* "Alter FQ State Commands " */
194 struct qm_mcc_alterfq {
197 u32 fqid; /* 24-bit */
199 u8 count; /* number of consecutive FQID */
201 u32 context_b; /* frame queue context b */
206 struct qm_mcc_querycgr {
213 struct qm_mcc_querywq {
216 /* select channel if verb != QUERYWQ_DEDICATED */
217 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
221 #define QM_MCC_VERB_VBIT 0x80
222 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
223 #define QM_MCC_VERB_INITFQ_PARKED 0x40
224 #define QM_MCC_VERB_INITFQ_SCHED 0x41
225 #define QM_MCC_VERB_QUERYFQ 0x44
226 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
227 #define QM_MCC_VERB_QUERYWQ 0x46
228 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
229 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
230 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
231 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
232 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
233 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
234 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
235 #define QM_MCC_VERB_INITCGR 0x50
236 #define QM_MCC_VERB_MODIFYCGR 0x51
237 #define QM_MCC_VERB_CGRTESTWRITE 0x52
238 #define QM_MCC_VERB_QUERYCGR 0x58
239 #define QM_MCC_VERB_QUERYCONGESTION 0x59
240 union qm_mc_command {
242 u8 _ncw_verb; /* writes to this are non-coherent */
245 struct qm_mcc_initfq initfq;
246 struct qm_mcc_queryfq queryfq;
247 struct qm_mcc_alterfq alterfq;
248 struct qm_mcc_initcgr initcgr;
249 struct qm_mcc_querycgr querycgr;
250 struct qm_mcc_querywq querywq;
251 struct qm_mcc_queryfq_np queryfq_np;
254 /* MC (Management Command) result */
256 struct qm_mcr_queryfq {
260 struct qm_fqd fqd; /* the FQD fields are here */
264 /* "Alter FQ State Commands" */
265 struct qm_mcr_alterfq {
268 u8 fqs; /* Frame Queue Status */
271 #define QM_MCR_VERB_RRID 0x80
272 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
273 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
274 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
275 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
276 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
277 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
278 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
279 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
280 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
281 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
282 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
283 #define QM_MCR_RESULT_NULL 0x00
284 #define QM_MCR_RESULT_OK 0xf0
285 #define QM_MCR_RESULT_ERR_FQID 0xf1
286 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2
287 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
288 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
289 #define QM_MCR_RESULT_PENDING 0xf8
290 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
291 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
292 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
293 #define QM_MCR_TIMEOUT 10000 /* us */
300 struct qm_mcr_queryfq queryfq;
301 struct qm_mcr_alterfq alterfq;
302 struct qm_mcr_querycgr querycgr;
303 struct qm_mcr_querycongestion querycongestion;
304 struct qm_mcr_querywq querywq;
305 struct qm_mcr_queryfq_np queryfq_np;
309 union qm_mc_command *cr;
310 union qm_mc_result *rr;
312 #ifdef CONFIG_FSL_DPAA_CHECKING
314 /* Can be _mc_start()ed */
316 /* Can be _mc_commit()ed or _mc_abort()ed */
318 /* Can only be _mc_retry()ed */
325 void __iomem *ce; /* cache-enabled */
326 void __iomem *ci; /* cache-inhibited */
331 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
332 * and including 'mc' fits within a cacheline (yay!). The 'config' part
333 * is setup-only, so isn't a cause for a concern. In other words, don't
334 * rearrange this structure on a whim, there be dragons ...
341 } ____cacheline_aligned;
343 /* Cache-inhibited register access. */
344 static inline u32 qm_in(struct qm_portal *p, u32 offset)
346 return __raw_readl(p->addr.ci + offset);
349 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
351 __raw_writel(val, p->addr.ci + offset);
354 /* Cache Enabled Portal Access */
355 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
357 dpaa_invalidate(p->addr.ce + offset);
360 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
362 dpaa_touch_ro(p->addr.ce + offset);
365 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
367 return __raw_readl(p->addr.ce + offset);
370 /* --- EQCR API --- */
372 #define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
373 #define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
375 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
376 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
378 uintptr_t addr = (uintptr_t)p;
382 return (struct qm_eqcr_entry *)addr;
385 /* Bit-wise logic to convert a ring pointer to a ring index */
386 static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
388 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
391 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */
392 static inline void eqcr_inc(struct qm_eqcr *eqcr)
394 /* increment to the next EQCR pointer and handle overflow and 'vbit' */
395 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
397 eqcr->cursor = eqcr_carryclear(partial);
398 if (partial != eqcr->cursor)
399 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
402 static inline int qm_eqcr_init(struct qm_portal *portal,
403 enum qm_eqcr_pmode pmode,
404 unsigned int eq_stash_thresh,
407 struct qm_eqcr *eqcr = &portal->eqcr;
411 eqcr->ring = portal->addr.ce + QM_CL_EQCR;
412 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
413 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
414 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
415 eqcr->cursor = eqcr->ring + pi;
416 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
417 QM_EQCR_VERB_VBIT : 0;
418 eqcr->available = QM_EQCR_SIZE - 1 -
419 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
420 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
421 #ifdef CONFIG_FSL_DPAA_CHECKING
425 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
426 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
427 (eq_stash_prio << 26) | /* QCSP_CFG: EP */
428 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
429 qm_out(portal, QM_REG_CFG, cfg);
433 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
435 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
438 static inline void qm_eqcr_finish(struct qm_portal *portal)
440 struct qm_eqcr *eqcr = &portal->eqcr;
441 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
442 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
444 DPAA_ASSERT(!eqcr->busy);
445 if (pi != eqcr_ptr2idx(eqcr->cursor))
446 pr_crit("losing uncommited EQCR entries\n");
448 pr_crit("missing existing EQCR completions\n");
449 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
450 pr_crit("EQCR destroyed unquiesced\n");
453 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
456 struct qm_eqcr *eqcr = &portal->eqcr;
458 DPAA_ASSERT(!eqcr->busy);
459 if (!eqcr->available)
462 #ifdef CONFIG_FSL_DPAA_CHECKING
465 dpaa_zero(eqcr->cursor);
469 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
472 struct qm_eqcr *eqcr = &portal->eqcr;
475 DPAA_ASSERT(!eqcr->busy);
476 if (!eqcr->available) {
478 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
480 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
481 eqcr->available += diff;
485 #ifdef CONFIG_FSL_DPAA_CHECKING
488 dpaa_zero(eqcr->cursor);
492 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
494 DPAA_ASSERT(eqcr->busy);
495 DPAA_ASSERT(eqcr->cursor->orp == (eqcr->cursor->orp & 0x00ffffff));
496 DPAA_ASSERT(eqcr->cursor->fqid == (eqcr->cursor->fqid & 0x00ffffff));
497 DPAA_ASSERT(eqcr->available >= 1);
500 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
502 struct qm_eqcr *eqcr = &portal->eqcr;
503 struct qm_eqcr_entry *eqcursor;
505 eqcr_commit_checks(eqcr);
506 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
508 eqcursor = eqcr->cursor;
509 eqcursor->_ncw_verb = myverb | eqcr->vbit;
510 dpaa_flush(eqcursor);
513 #ifdef CONFIG_FSL_DPAA_CHECKING
518 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
520 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
523 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
525 struct qm_eqcr *eqcr = &portal->eqcr;
526 u8 diff, old_ci = eqcr->ci;
528 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
529 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
530 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
531 eqcr->available += diff;
535 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
537 struct qm_eqcr *eqcr = &portal->eqcr;
539 eqcr->ithresh = ithresh;
540 qm_out(portal, QM_REG_EQCR_ITR, ithresh);
543 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
545 struct qm_eqcr *eqcr = &portal->eqcr;
547 return eqcr->available;
550 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
552 struct qm_eqcr *eqcr = &portal->eqcr;
554 return QM_EQCR_SIZE - 1 - eqcr->available;
557 /* --- DQRR API --- */
559 #define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
560 #define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
562 static const struct qm_dqrr_entry *dqrr_carryclear(
563 const struct qm_dqrr_entry *p)
565 uintptr_t addr = (uintptr_t)p;
569 return (const struct qm_dqrr_entry *)addr;
572 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
574 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
577 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
579 return dqrr_carryclear(e + 1);
582 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
584 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
585 ((mf & (QM_DQRR_SIZE - 1)) << 20));
588 static inline int qm_dqrr_init(struct qm_portal *portal,
589 const struct qm_portal_config *config,
590 enum qm_dqrr_dmode dmode,
591 enum qm_dqrr_pmode pmode,
592 enum qm_dqrr_cmode cmode, u8 max_fill)
594 struct qm_dqrr *dqrr = &portal->dqrr;
597 /* Make sure the DQRR will be idle when we enable */
598 qm_out(portal, QM_REG_DQRR_SDQCR, 0);
599 qm_out(portal, QM_REG_DQRR_VDQCR, 0);
600 qm_out(portal, QM_REG_DQRR_PDQCR, 0);
601 dqrr->ring = portal->addr.ce + QM_CL_DQRR;
602 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
603 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
604 dqrr->cursor = dqrr->ring + dqrr->ci;
605 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
606 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
607 QM_DQRR_VERB_VBIT : 0;
608 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
609 #ifdef CONFIG_FSL_DPAA_CHECKING
614 /* Invalidate every ring entry before beginning */
615 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
616 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
617 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
618 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
619 ((dmode & 1) << 18) | /* DP */
620 ((cmode & 3) << 16) | /* DCM */
622 (0 ? 0x40 : 0) | /* Ignore RP */
623 (0 ? 0x10 : 0); /* Ignore SP */
624 qm_out(portal, QM_REG_CFG, cfg);
625 qm_dqrr_set_maxfill(portal, max_fill);
629 static inline void qm_dqrr_finish(struct qm_portal *portal)
631 #ifdef CONFIG_FSL_DPAA_CHECKING
632 struct qm_dqrr *dqrr = &portal->dqrr;
634 if (dqrr->cmode != qm_dqrr_cdc &&
635 dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
636 pr_crit("Ignoring completed DQRR entries\n");
640 static inline const struct qm_dqrr_entry *qm_dqrr_current(
641 struct qm_portal *portal)
643 struct qm_dqrr *dqrr = &portal->dqrr;
650 static inline u8 qm_dqrr_next(struct qm_portal *portal)
652 struct qm_dqrr *dqrr = &portal->dqrr;
654 DPAA_ASSERT(dqrr->fill);
655 dqrr->cursor = dqrr_inc(dqrr->cursor);
659 static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
661 struct qm_dqrr *dqrr = &portal->dqrr;
662 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
664 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
665 #ifndef CONFIG_FSL_PAMU
667 * If PAMU is not available we need to invalidate the cache.
668 * When PAMU is available the cache is updated by stash
670 dpaa_invalidate_touch_ro(res);
673 * when accessing 'verb', use __raw_readb() to ensure that compiler
674 * inlining doesn't try to optimise out "excess reads".
676 if ((__raw_readb(&res->verb) & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
677 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
679 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
684 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
685 const struct qm_dqrr_entry *dq,
688 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
689 int idx = dqrr_ptr2idx(dq);
691 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
692 DPAA_ASSERT((dqrr->ring + idx) == dq);
693 DPAA_ASSERT(idx < QM_DQRR_SIZE);
694 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
695 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
696 idx); /* DQRR_DCAP::DCAP_CI */
699 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
701 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
703 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
704 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
705 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
708 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
710 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
713 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
715 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
718 static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
720 qm_out(portal, QM_REG_DQRR_ITR, ithresh);
725 #define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
726 #define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
728 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
730 uintptr_t addr = (uintptr_t)p;
734 return (union qm_mr_entry *)addr;
737 static inline int mr_ptr2idx(const union qm_mr_entry *e)
739 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
742 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
744 return mr_carryclear(e + 1);
747 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
748 enum qm_mr_cmode cmode)
750 struct qm_mr *mr = &portal->mr;
753 mr->ring = portal->addr.ce + QM_CL_MR;
754 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
755 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
756 mr->cursor = mr->ring + mr->ci;
757 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
758 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
759 ? QM_MR_VERB_VBIT : 0;
760 mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
761 #ifdef CONFIG_FSL_DPAA_CHECKING
765 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
766 ((cmode & 1) << 8); /* QCSP_CFG:MM */
767 qm_out(portal, QM_REG_CFG, cfg);
771 static inline void qm_mr_finish(struct qm_portal *portal)
773 struct qm_mr *mr = &portal->mr;
775 if (mr->ci != mr_ptr2idx(mr->cursor))
776 pr_crit("Ignoring completed MR entries\n");
779 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
781 struct qm_mr *mr = &portal->mr;
788 static inline int qm_mr_next(struct qm_portal *portal)
790 struct qm_mr *mr = &portal->mr;
792 DPAA_ASSERT(mr->fill);
793 mr->cursor = mr_inc(mr->cursor);
797 static inline void qm_mr_pvb_update(struct qm_portal *portal)
799 struct qm_mr *mr = &portal->mr;
800 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
802 DPAA_ASSERT(mr->pmode == qm_mr_pvb);
804 * when accessing 'verb', use __raw_readb() to ensure that compiler
805 * inlining doesn't try to optimise out "excess reads".
807 if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) {
808 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
810 mr->vbit ^= QM_MR_VERB_VBIT;
814 dpaa_invalidate_touch_ro(res);
817 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
819 struct qm_mr *mr = &portal->mr;
821 DPAA_ASSERT(mr->cmode == qm_mr_cci);
822 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
823 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
826 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
828 struct qm_mr *mr = &portal->mr;
830 DPAA_ASSERT(mr->cmode == qm_mr_cci);
831 mr->ci = mr_ptr2idx(mr->cursor);
832 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
835 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
837 qm_out(portal, QM_REG_MR_ITR, ithresh);
840 /* --- Management command API --- */
842 static inline int qm_mc_init(struct qm_portal *portal)
844 struct qm_mc *mc = &portal->mc;
846 mc->cr = portal->addr.ce + QM_CL_CR;
847 mc->rr = portal->addr.ce + QM_CL_RR0;
848 mc->rridx = (__raw_readb(&mc->cr->_ncw_verb) & QM_MCC_VERB_VBIT)
850 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
851 #ifdef CONFIG_FSL_DPAA_CHECKING
852 mc->state = qman_mc_idle;
857 static inline void qm_mc_finish(struct qm_portal *portal)
859 #ifdef CONFIG_FSL_DPAA_CHECKING
860 struct qm_mc *mc = &portal->mc;
862 DPAA_ASSERT(mc->state == qman_mc_idle);
863 if (mc->state != qman_mc_idle)
864 pr_crit("Losing incomplete MC command\n");
868 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
870 struct qm_mc *mc = &portal->mc;
872 DPAA_ASSERT(mc->state == qman_mc_idle);
873 #ifdef CONFIG_FSL_DPAA_CHECKING
874 mc->state = qman_mc_user;
880 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
882 struct qm_mc *mc = &portal->mc;
883 union qm_mc_result *rr = mc->rr + mc->rridx;
885 DPAA_ASSERT(mc->state == qman_mc_user);
887 mc->cr->_ncw_verb = myverb | mc->vbit;
889 dpaa_invalidate_touch_ro(rr);
890 #ifdef CONFIG_FSL_DPAA_CHECKING
891 mc->state = qman_mc_hw;
895 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
897 struct qm_mc *mc = &portal->mc;
898 union qm_mc_result *rr = mc->rr + mc->rridx;
900 DPAA_ASSERT(mc->state == qman_mc_hw);
902 * The inactive response register's verb byte always returns zero until
903 * its command is submitted and completed. This includes the valid-bit,
904 * in case you were wondering...
906 if (!__raw_readb(&rr->verb)) {
907 dpaa_invalidate_touch_ro(rr);
911 mc->vbit ^= QM_MCC_VERB_VBIT;
912 #ifdef CONFIG_FSL_DPAA_CHECKING
913 mc->state = qman_mc_idle;
918 static inline int qm_mc_result_timeout(struct qm_portal *portal,
919 union qm_mc_result **mcr)
921 int timeout = QM_MCR_TIMEOUT;
924 *mcr = qm_mc_result(portal);
933 static inline void fq_set(struct qman_fq *fq, u32 mask)
935 set_bits(mask, &fq->flags);
938 static inline void fq_clear(struct qman_fq *fq, u32 mask)
940 clear_bits(mask, &fq->flags);
943 static inline int fq_isset(struct qman_fq *fq, u32 mask)
945 return fq->flags & mask;
948 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
950 return !(fq->flags & mask);
955 /* PORTAL_BITS_*** - dynamic, strictly internal */
957 /* interrupt sources processed by portal_isr(), configurable */
958 unsigned long irq_sources;
959 u32 use_eqcr_ci_stashing;
960 /* only 1 volatile dequeue at a time */
961 struct qman_fq *vdqcr_owned;
963 /* probing time config params for cpu-affine portals */
964 const struct qm_portal_config *config;
965 /* needed for providing a non-NULL device to dma_map_***() */
966 struct platform_device *pdev;
967 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
968 struct qman_cgrs *cgrs;
969 /* linked-list of CSCN handlers. */
970 struct list_head cgr_cbs;
973 struct work_struct congestion_work;
974 struct work_struct mr_work;
975 char irqname[MAX_IRQNAME];
978 static cpumask_t affine_mask;
979 static DEFINE_SPINLOCK(affine_mask_lock);
980 static u16 affine_channels[NR_CPUS];
981 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
982 struct qman_portal *affine_portals[NR_CPUS];
984 static inline struct qman_portal *get_affine_portal(void)
986 return &get_cpu_var(qman_affine_portal);
989 static inline void put_affine_portal(void)
991 put_cpu_var(qman_affine_portal);
994 static struct workqueue_struct *qm_portal_wq;
996 int qman_wq_alloc(void)
998 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
1005 * This is what everything can wait on, even if it migrates to a different cpu
1006 * to the one whose affine portal it is waiting on.
1008 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
1010 static struct qman_fq **fq_table;
1011 static u32 num_fqids;
1013 int qman_alloc_fq_table(u32 _num_fqids)
1015 num_fqids = _num_fqids;
1017 fq_table = vzalloc(num_fqids * 2 * sizeof(struct qman_fq *));
1021 pr_debug("Allocated fq lookup table at %p, entry count %u\n",
1022 fq_table, num_fqids * 2);
1026 static struct qman_fq *idx_to_fq(u32 idx)
1030 #ifdef CONFIG_FSL_DPAA_CHECKING
1031 if (WARN_ON(idx >= num_fqids * 2))
1035 DPAA_ASSERT(!fq || idx == fq->idx);
1041 * Only returns full-service fq objects, not enqueue-only
1042 * references (QMAN_FQ_FLAG_NO_MODIFY).
1044 static struct qman_fq *fqid_to_fq(u32 fqid)
1046 return idx_to_fq(fqid * 2);
1049 static struct qman_fq *tag_to_fq(u32 tag)
1051 #if BITS_PER_LONG == 64
1052 return idx_to_fq(tag);
1054 return (struct qman_fq *)tag;
1058 static u32 fq_to_tag(struct qman_fq *fq)
1060 #if BITS_PER_LONG == 64
1067 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1068 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1069 unsigned int poll_limit);
1070 static void qm_congestion_task(struct work_struct *work);
1071 static void qm_mr_process_task(struct work_struct *work);
1073 static irqreturn_t portal_isr(int irq, void *ptr)
1075 struct qman_portal *p = ptr;
1076 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1082 /* DQRR-handling if it's interrupt-driven */
1083 if (is & QM_PIRQ_DQRI) {
1084 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1085 clear = QM_DQAVAIL_MASK | QM_PIRQ_DQRI;
1087 /* Handling of anything else that's interrupt-driven */
1088 clear |= __poll_portal_slow(p, is) & QM_PIRQ_SLOW;
1089 qm_out(&p->p, QM_REG_ISR, clear);
1093 static int drain_mr_fqrni(struct qm_portal *p)
1095 const union qm_mr_entry *msg;
1097 msg = qm_mr_current(p);
1100 * if MR was full and h/w had other FQRNI entries to produce, we
1101 * need to allow it time to produce those entries once the
1102 * existing entries are consumed. A worst-case situation
1103 * (fully-loaded system) means h/w sequencers may have to do 3-4
1104 * other things before servicing the portal's MR pump, each of
1105 * which (if slow) may take ~50 qman cycles (which is ~200
1106 * processor cycles). So rounding up and then multiplying this
1107 * worst-case estimate by a factor of 10, just to be
1108 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1109 * one entry at a time, so h/w has an opportunity to produce new
1110 * entries well before the ring has been fully consumed, so
1111 * we're being *really* paranoid here.
1113 u64 now, then = jiffies;
1117 } while ((then + 10000) > now);
1118 msg = qm_mr_current(p);
1122 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1123 /* We aren't draining anything but FQRNIs */
1124 pr_err("Found verb 0x%x in MR\n", msg->verb);
1128 qm_mr_cci_consume(p, 1);
1132 static int qman_create_portal(struct qman_portal *portal,
1133 const struct qm_portal_config *c,
1134 const struct qman_cgrs *cgrs)
1136 struct qm_portal *p;
1143 #ifdef CONFIG_FSL_PAMU
1144 /* PAMU is required for stashing */
1145 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1147 portal->use_eqcr_ci_stashing = 0;
1150 * prep the low-level portal struct with the mapped addresses from the
1151 * config, everything that follows depends on it and "config" is more
1154 p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
1155 p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
1157 * If CI-stashing is used, the current defaults use a threshold of 3,
1158 * and stash with high-than-DQRR priority.
1160 if (qm_eqcr_init(p, qm_eqcr_pvb,
1161 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1162 dev_err(c->dev, "EQCR initialisation failed\n");
1165 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1166 qm_dqrr_cdc, DQRR_MAXFILL)) {
1167 dev_err(c->dev, "DQRR initialisation failed\n");
1170 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1171 dev_err(c->dev, "MR initialisation failed\n");
1174 if (qm_mc_init(p)) {
1175 dev_err(c->dev, "MC initialisation failed\n");
1178 /* static interrupt-gating controls */
1179 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1180 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1181 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1182 portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
1185 /* initial snapshot is no-depletion */
1186 qman_cgrs_init(&portal->cgrs[1]);
1188 portal->cgrs[0] = *cgrs;
1190 /* if the given mask is NULL, assume all CGRs can be seen */
1191 qman_cgrs_fill(&portal->cgrs[0]);
1192 INIT_LIST_HEAD(&portal->cgr_cbs);
1193 spin_lock_init(&portal->cgr_lock);
1194 INIT_WORK(&portal->congestion_work, qm_congestion_task);
1195 INIT_WORK(&portal->mr_work, qm_mr_process_task);
1197 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1198 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1199 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
1200 sprintf(buf, "qportal-%d", c->channel);
1201 portal->pdev = platform_device_alloc(buf, -1);
1204 if (dma_set_mask(&portal->pdev->dev, DMA_BIT_MASK(40)))
1206 ret = platform_device_add(portal->pdev);
1210 qm_out(p, QM_REG_ISDR, isdr);
1211 portal->irq_sources = 0;
1212 qm_out(p, QM_REG_IER, 0);
1213 qm_out(p, QM_REG_ISR, 0xffffffff);
1214 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1215 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1216 dev_err(c->dev, "request_irq() failed\n");
1219 if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
1220 irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
1221 dev_err(c->dev, "irq_set_affinity() failed\n");
1225 /* Need EQCR to be empty before continuing */
1226 isdr &= ~QM_PIRQ_EQCI;
1227 qm_out(p, QM_REG_ISDR, isdr);
1228 ret = qm_eqcr_get_fill(p);
1230 dev_err(c->dev, "EQCR unclean\n");
1231 goto fail_eqcr_empty;
1233 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1234 qm_out(p, QM_REG_ISDR, isdr);
1235 if (qm_dqrr_current(p)) {
1236 dev_err(c->dev, "DQRR unclean\n");
1237 qm_dqrr_cdc_consume_n(p, 0xffff);
1239 if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1240 /* special handling, drain just in case it's a few FQRNIs */
1241 const union qm_mr_entry *e = qm_mr_current(p);
1243 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x\n, addr 0x%x",
1244 e->verb, e->ern.rc, e->ern.fd.addr_lo);
1245 goto fail_dqrr_mr_empty;
1249 qm_out(p, QM_REG_ISDR, 0);
1250 qm_out(p, QM_REG_IIR, 0);
1251 /* Write a sane SDQCR */
1252 qm_dqrr_sdqcr_set(p, portal->sdqcr);
1258 free_irq(c->irq, portal);
1260 platform_device_del(portal->pdev);
1262 platform_device_put(portal->pdev);
1264 kfree(portal->cgrs);
1277 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1278 const struct qman_cgrs *cgrs)
1280 struct qman_portal *portal;
1283 portal = &per_cpu(qman_affine_portal, c->cpu);
1284 err = qman_create_portal(portal, c, cgrs);
1288 spin_lock(&affine_mask_lock);
1289 cpumask_set_cpu(c->cpu, &affine_mask);
1290 affine_channels[c->cpu] = c->channel;
1291 affine_portals[c->cpu] = portal;
1292 spin_unlock(&affine_mask_lock);
1297 static void qman_destroy_portal(struct qman_portal *qm)
1299 const struct qm_portal_config *pcfg;
1301 /* Stop dequeues on the portal */
1302 qm_dqrr_sdqcr_set(&qm->p, 0);
1305 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1306 * something related to QM_PIRQ_EQCI, this may need fixing.
1307 * Also, due to the prefetching model used for CI updates in the enqueue
1308 * path, this update will only invalidate the CI cacheline *after*
1309 * working on it, so we need to call this twice to ensure a full update
1310 * irrespective of where the enqueue processing was at when the teardown
1313 qm_eqcr_cce_update(&qm->p);
1314 qm_eqcr_cce_update(&qm->p);
1317 free_irq(pcfg->irq, qm);
1320 qm_mc_finish(&qm->p);
1321 qm_mr_finish(&qm->p);
1322 qm_dqrr_finish(&qm->p);
1323 qm_eqcr_finish(&qm->p);
1325 platform_device_del(qm->pdev);
1326 platform_device_put(qm->pdev);
1331 const struct qm_portal_config *qman_destroy_affine_portal(void)
1333 struct qman_portal *qm = get_affine_portal();
1334 const struct qm_portal_config *pcfg;
1340 qman_destroy_portal(qm);
1342 spin_lock(&affine_mask_lock);
1343 cpumask_clear_cpu(cpu, &affine_mask);
1344 spin_unlock(&affine_mask_lock);
1345 put_affine_portal();
1349 /* Inline helper to reduce nesting in __poll_portal_slow() */
1350 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1351 const union qm_mr_entry *msg, u8 verb)
1354 case QM_MR_VERB_FQRL:
1355 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1356 fq_clear(fq, QMAN_FQ_STATE_ORL);
1358 case QM_MR_VERB_FQRN:
1359 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1360 fq->state == qman_fq_state_sched);
1361 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1362 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1363 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1364 fq_set(fq, QMAN_FQ_STATE_NE);
1365 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1366 fq_set(fq, QMAN_FQ_STATE_ORL);
1367 fq->state = qman_fq_state_retired;
1369 case QM_MR_VERB_FQPN:
1370 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1371 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1372 fq->state = qman_fq_state_parked;
1376 static void qm_congestion_task(struct work_struct *work)
1378 struct qman_portal *p = container_of(work, struct qman_portal,
1380 struct qman_cgrs rr, c;
1381 union qm_mc_result *mcr;
1382 struct qman_cgr *cgr;
1384 spin_lock(&p->cgr_lock);
1386 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1387 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1388 spin_unlock(&p->cgr_lock);
1389 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1392 /* mask out the ones I'm not interested in */
1393 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1395 /* check previous snapshot for delta, enter/exit congestion */
1396 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1397 /* update snapshot */
1398 qman_cgrs_cp(&p->cgrs[1], &rr);
1399 /* Invoke callback */
1400 list_for_each_entry(cgr, &p->cgr_cbs, node)
1401 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1402 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1403 spin_unlock(&p->cgr_lock);
1406 static void qm_mr_process_task(struct work_struct *work)
1408 struct qman_portal *p = container_of(work, struct qman_portal,
1410 const union qm_mr_entry *msg;
1417 qm_mr_pvb_update(&p->p);
1418 msg = qm_mr_current(&p->p);
1422 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1423 /* The message is a software ERN iff the 0x20 bit is clear */
1426 case QM_MR_VERB_FQRNI:
1427 /* nada, we drop FQRNIs on the floor */
1429 case QM_MR_VERB_FQRN:
1430 case QM_MR_VERB_FQRL:
1431 /* Lookup in the retirement table */
1432 fq = fqid_to_fq(msg->fq.fqid);
1435 fq_state_change(p, fq, msg, verb);
1437 fq->cb.fqs(p, fq, msg);
1439 case QM_MR_VERB_FQPN:
1441 fq = tag_to_fq(msg->fq.contextB);
1442 fq_state_change(p, fq, msg, verb);
1444 fq->cb.fqs(p, fq, msg);
1446 case QM_MR_VERB_DC_ERN:
1448 pr_crit_once("Leaking DCP ERNs!\n");
1451 pr_crit("Invalid MR verb 0x%02x\n", verb);
1454 /* Its a software ERN */
1455 fq = tag_to_fq(msg->ern.tag);
1456 fq->cb.ern(p, fq, msg);
1462 qm_mr_cci_consume(&p->p, num);
1466 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1468 if (is & QM_PIRQ_CSCI) {
1469 queue_work_on(smp_processor_id(), qm_portal_wq,
1470 &p->congestion_work);
1473 if (is & QM_PIRQ_EQRI) {
1474 qm_eqcr_cce_update(&p->p);
1475 qm_eqcr_set_ithresh(&p->p, 0);
1476 wake_up(&affine_queue);
1479 if (is & QM_PIRQ_MRI) {
1480 queue_work_on(smp_processor_id(), qm_portal_wq,
1488 * remove some slowish-path stuff from the "fast path" and make sure it isn't
1491 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1493 p->vdqcr_owned = NULL;
1494 fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1495 wake_up(&affine_queue);
1499 * The only states that would conflict with other things if they ran at the
1500 * same time on the same cpu are:
1502 * (i) setting/clearing vdqcr_owned, and
1503 * (ii) clearing the NE (Not Empty) flag.
1505 * Both are safe. Because;
1507 * (i) this clearing can only occur after qman_volatile_dequeue() has set the
1508 * vdqcr_owned field (which it does before setting VDQCR), and
1509 * qman_volatile_dequeue() blocks interrupts and preemption while this is
1510 * done so that we can't interfere.
1511 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1512 * with (i) that API prevents us from interfering until it's safe.
1514 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1515 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1516 * advantage comes from this function not having to "lock" anything at all.
1518 * Note also that the callbacks are invoked at points which are safe against the
1519 * above potential conflicts, but that this function itself is not re-entrant
1520 * (this is because the function tracks one end of each FIFO in the portal and
1521 * we do *not* want to lock that). So the consequence is that it is safe for
1522 * user callbacks to call into any QMan API.
1524 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1525 unsigned int poll_limit)
1527 const struct qm_dqrr_entry *dq;
1529 enum qman_cb_dqrr_result res;
1530 unsigned int limit = 0;
1533 qm_dqrr_pvb_update(&p->p);
1534 dq = qm_dqrr_current(&p->p);
1538 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1540 * VDQCR: don't trust contextB as the FQ may have
1541 * been configured for h/w consumption and we're
1542 * draining it post-retirement.
1544 fq = p->vdqcr_owned;
1546 * We only set QMAN_FQ_STATE_NE when retiring, so we
1547 * only need to check for clearing it when doing
1548 * volatile dequeues. It's one less thing to check
1549 * in the critical path (SDQCR).
1551 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1552 fq_clear(fq, QMAN_FQ_STATE_NE);
1554 * This is duplicated from the SDQCR code, but we
1555 * have stuff to do before *and* after this callback,
1556 * and we don't want multiple if()s in the critical
1559 res = fq->cb.dqrr(p, fq, dq);
1560 if (res == qman_cb_dqrr_stop)
1562 /* Check for VDQCR completion */
1563 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1566 /* SDQCR: contextB points to the FQ */
1567 fq = tag_to_fq(dq->contextB);
1568 /* Now let the callback do its stuff */
1569 res = fq->cb.dqrr(p, fq, dq);
1571 * The callback can request that we exit without
1572 * consuming this entry nor advancing;
1574 if (res == qman_cb_dqrr_stop)
1577 /* Interpret 'dq' from a driver perspective. */
1579 * Parking isn't possible unless HELDACTIVE was set. NB,
1580 * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1581 * check for HELDACTIVE to cover both.
1583 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1584 (res != qman_cb_dqrr_park));
1585 /* just means "skip it, I'll consume it myself later on" */
1586 if (res != qman_cb_dqrr_defer)
1587 qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1588 res == qman_cb_dqrr_park);
1590 qm_dqrr_next(&p->p);
1592 * Entry processed and consumed, increment our counter. The
1593 * callback can request that we exit after consuming the
1594 * entry, and we also exit if we reach our processing limit,
1595 * so loop back only if neither of these conditions is met.
1597 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1602 void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1604 unsigned long irqflags;
1606 local_irq_save(irqflags);
1607 set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources);
1608 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1609 local_irq_restore(irqflags);
1611 EXPORT_SYMBOL(qman_p_irqsource_add);
1613 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1615 unsigned long irqflags;
1619 * Our interrupt handler only processes+clears status register bits that
1620 * are in p->irq_sources. As we're trimming that mask, if one of them
1621 * were to assert in the status register just before we remove it from
1622 * the enable register, there would be an interrupt-storm when we
1623 * release the IRQ lock. So we wait for the enable register update to
1624 * take effect in h/w (by reading it back) and then clear all other bits
1625 * in the status register. Ie. we clear them from ISR once it's certain
1626 * IER won't allow them to reassert.
1628 local_irq_save(irqflags);
1629 bits &= QM_PIRQ_VISIBLE;
1630 clear_bits(bits, &p->irq_sources);
1631 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1632 ier = qm_in(&p->p, QM_REG_IER);
1634 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1635 * data-dependency, ie. to protect against re-ordering.
1637 qm_out(&p->p, QM_REG_ISR, ~ier);
1638 local_irq_restore(irqflags);
1640 EXPORT_SYMBOL(qman_p_irqsource_remove);
1642 const cpumask_t *qman_affine_cpus(void)
1644 return &affine_mask;
1646 EXPORT_SYMBOL(qman_affine_cpus);
1648 u16 qman_affine_channel(int cpu)
1651 struct qman_portal *portal = get_affine_portal();
1653 cpu = portal->config->cpu;
1654 put_affine_portal();
1656 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1657 return affine_channels[cpu];
1659 EXPORT_SYMBOL(qman_affine_channel);
1661 struct qman_portal *qman_get_affine_portal(int cpu)
1663 return affine_portals[cpu];
1665 EXPORT_SYMBOL(qman_get_affine_portal);
1667 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1669 return __poll_portal_fast(p, limit);
1671 EXPORT_SYMBOL(qman_p_poll_dqrr);
1673 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1675 unsigned long irqflags;
1677 local_irq_save(irqflags);
1678 pools &= p->config->pools;
1680 qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1681 local_irq_restore(irqflags);
1683 EXPORT_SYMBOL(qman_p_static_dequeue_add);
1685 /* Frame queue API */
1687 static const char *mcr_result_str(u8 result)
1690 case QM_MCR_RESULT_NULL:
1691 return "QM_MCR_RESULT_NULL";
1692 case QM_MCR_RESULT_OK:
1693 return "QM_MCR_RESULT_OK";
1694 case QM_MCR_RESULT_ERR_FQID:
1695 return "QM_MCR_RESULT_ERR_FQID";
1696 case QM_MCR_RESULT_ERR_FQSTATE:
1697 return "QM_MCR_RESULT_ERR_FQSTATE";
1698 case QM_MCR_RESULT_ERR_NOTEMPTY:
1699 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1700 case QM_MCR_RESULT_PENDING:
1701 return "QM_MCR_RESULT_PENDING";
1702 case QM_MCR_RESULT_ERR_BADCOMMAND:
1703 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1705 return "<unknown MCR result>";
1708 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1710 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1711 int ret = qman_alloc_fqid(&fqid);
1718 fq->state = qman_fq_state_oos;
1719 fq->cgr_groupid = 0;
1721 /* A context_b of 0 is allegedly special, so don't use that fqid */
1722 if (fqid == 0 || fqid >= num_fqids) {
1723 WARN(1, "bad fqid %d\n", fqid);
1728 if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1731 WARN_ON(fq_table[fq->idx]);
1732 fq_table[fq->idx] = fq;
1736 EXPORT_SYMBOL(qman_create_fq);
1738 void qman_destroy_fq(struct qman_fq *fq)
1741 * We don't need to lock the FQ as it is a pre-condition that the FQ be
1742 * quiesced. Instead, run some checks.
1744 switch (fq->state) {
1745 case qman_fq_state_parked:
1746 case qman_fq_state_oos:
1747 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1748 qman_release_fqid(fq->fqid);
1750 DPAA_ASSERT(fq_table[fq->idx]);
1751 fq_table[fq->idx] = NULL;
1756 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1758 EXPORT_SYMBOL(qman_destroy_fq);
1760 u32 qman_fq_fqid(struct qman_fq *fq)
1764 EXPORT_SYMBOL(qman_fq_fqid);
1766 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1768 union qm_mc_command *mcc;
1769 union qm_mc_result *mcr;
1770 struct qman_portal *p;
1774 myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1775 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1777 if (fq->state != qman_fq_state_oos &&
1778 fq->state != qman_fq_state_parked)
1780 #ifdef CONFIG_FSL_DPAA_CHECKING
1781 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1784 if (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) {
1785 /* And can't be set at the same time as TDTHRESH */
1786 if (opts->we_mask & QM_INITFQ_WE_TDTHRESH)
1789 /* Issue an INITFQ_[PARKED|SCHED] management command */
1790 p = get_affine_portal();
1791 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1792 (fq->state != qman_fq_state_oos &&
1793 fq->state != qman_fq_state_parked)) {
1797 mcc = qm_mc_start(&p->p);
1799 mcc->initfq = *opts;
1800 mcc->initfq.fqid = fq->fqid;
1801 mcc->initfq.count = 0;
1803 * If the FQ does *not* have the TO_DCPORTAL flag, contextB is set as a
1804 * demux pointer. Otherwise, the caller-provided value is allowed to
1805 * stand, don't overwrite it.
1807 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1810 mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB;
1811 mcc->initfq.fqd.context_b = fq_to_tag(fq);
1813 * and the physical address - NB, if the user wasn't trying to
1814 * set CONTEXTA, clear the stashing settings.
1816 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) {
1817 mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA;
1818 memset(&mcc->initfq.fqd.context_a, 0,
1819 sizeof(mcc->initfq.fqd.context_a));
1821 phys_fq = dma_map_single(&p->pdev->dev, fq, sizeof(*fq),
1823 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1826 if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1829 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) {
1830 mcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ;
1833 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1835 qm_mc_commit(&p->p, myverb);
1836 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1837 dev_err(p->config->dev, "MCR timeout\n");
1842 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1844 if (res != QM_MCR_RESULT_OK) {
1849 if (opts->we_mask & QM_INITFQ_WE_FQCTRL) {
1850 if (opts->fqd.fq_ctrl & QM_FQCTRL_CGE)
1851 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1853 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1855 if (opts->we_mask & QM_INITFQ_WE_CGID)
1856 fq->cgr_groupid = opts->fqd.cgid;
1858 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1859 qman_fq_state_sched : qman_fq_state_parked;
1862 put_affine_portal();
1865 EXPORT_SYMBOL(qman_init_fq);
1867 int qman_schedule_fq(struct qman_fq *fq)
1869 union qm_mc_command *mcc;
1870 union qm_mc_result *mcr;
1871 struct qman_portal *p;
1874 if (fq->state != qman_fq_state_parked)
1876 #ifdef CONFIG_FSL_DPAA_CHECKING
1877 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1880 /* Issue a ALTERFQ_SCHED management command */
1881 p = get_affine_portal();
1882 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1883 fq->state != qman_fq_state_parked) {
1887 mcc = qm_mc_start(&p->p);
1888 mcc->alterfq.fqid = fq->fqid;
1889 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1890 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1891 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1896 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1897 if (mcr->result != QM_MCR_RESULT_OK) {
1901 fq->state = qman_fq_state_sched;
1903 put_affine_portal();
1906 EXPORT_SYMBOL(qman_schedule_fq);
1908 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1910 union qm_mc_command *mcc;
1911 union qm_mc_result *mcr;
1912 struct qman_portal *p;
1916 if (fq->state != qman_fq_state_parked &&
1917 fq->state != qman_fq_state_sched)
1919 #ifdef CONFIG_FSL_DPAA_CHECKING
1920 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1923 p = get_affine_portal();
1924 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1925 fq->state == qman_fq_state_retired ||
1926 fq->state == qman_fq_state_oos) {
1930 mcc = qm_mc_start(&p->p);
1931 mcc->alterfq.fqid = fq->fqid;
1932 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1933 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1934 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1939 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1942 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1943 * and defer the flags until FQRNI or FQRN (respectively) show up. But
1944 * "Friendly" is to process OK immediately, and not set CHANGING. We do
1945 * friendly, otherwise the caller doesn't necessarily have a fully
1946 * "retired" FQ on return even if the retirement was immediate. However
1947 * this does mean some code duplication between here and
1948 * fq_state_change().
1950 if (res == QM_MCR_RESULT_OK) {
1952 /* Process 'fq' right away, we'll ignore FQRNI */
1953 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1954 fq_set(fq, QMAN_FQ_STATE_NE);
1955 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1956 fq_set(fq, QMAN_FQ_STATE_ORL);
1959 fq->state = qman_fq_state_retired;
1962 * Another issue with supporting "immediate" retirement
1963 * is that we're forced to drop FQRNIs, because by the
1964 * time they're seen it may already be "too late" (the
1965 * fq may have been OOS'd and free()'d already). But if
1966 * the upper layer wants a callback whether it's
1967 * immediate or not, we have to fake a "MR" entry to
1968 * look like an FQRNI...
1970 union qm_mr_entry msg;
1972 msg.verb = QM_MR_VERB_FQRNI;
1973 msg.fq.fqs = mcr->alterfq.fqs;
1974 msg.fq.fqid = fq->fqid;
1975 msg.fq.contextB = fq_to_tag(fq);
1976 fq->cb.fqs(p, fq, &msg);
1978 } else if (res == QM_MCR_RESULT_PENDING) {
1980 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1985 put_affine_portal();
1988 EXPORT_SYMBOL(qman_retire_fq);
1990 int qman_oos_fq(struct qman_fq *fq)
1992 union qm_mc_command *mcc;
1993 union qm_mc_result *mcr;
1994 struct qman_portal *p;
1997 if (fq->state != qman_fq_state_retired)
1999 #ifdef CONFIG_FSL_DPAA_CHECKING
2000 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
2003 p = get_affine_portal();
2004 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
2005 fq->state != qman_fq_state_retired) {
2009 mcc = qm_mc_start(&p->p);
2010 mcc->alterfq.fqid = fq->fqid;
2011 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2012 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2016 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
2017 if (mcr->result != QM_MCR_RESULT_OK) {
2021 fq->state = qman_fq_state_oos;
2023 put_affine_portal();
2026 EXPORT_SYMBOL(qman_oos_fq);
2028 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
2030 union qm_mc_command *mcc;
2031 union qm_mc_result *mcr;
2032 struct qman_portal *p = get_affine_portal();
2035 mcc = qm_mc_start(&p->p);
2036 mcc->queryfq.fqid = fq->fqid;
2037 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2038 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2043 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2044 if (mcr->result == QM_MCR_RESULT_OK)
2045 *fqd = mcr->queryfq.fqd;
2049 put_affine_portal();
2053 static int qman_query_fq_np(struct qman_fq *fq,
2054 struct qm_mcr_queryfq_np *np)
2056 union qm_mc_command *mcc;
2057 union qm_mc_result *mcr;
2058 struct qman_portal *p = get_affine_portal();
2061 mcc = qm_mc_start(&p->p);
2062 mcc->queryfq.fqid = fq->fqid;
2063 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2064 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2069 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2070 if (mcr->result == QM_MCR_RESULT_OK)
2071 *np = mcr->queryfq_np;
2072 else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2077 put_affine_portal();
2081 static int qman_query_cgr(struct qman_cgr *cgr,
2082 struct qm_mcr_querycgr *cgrd)
2084 union qm_mc_command *mcc;
2085 union qm_mc_result *mcr;
2086 struct qman_portal *p = get_affine_portal();
2089 mcc = qm_mc_start(&p->p);
2090 mcc->querycgr.cgid = cgr->cgrid;
2091 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2092 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2096 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2097 if (mcr->result == QM_MCR_RESULT_OK)
2098 *cgrd = mcr->querycgr;
2100 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2101 mcr_result_str(mcr->result));
2105 put_affine_portal();
2109 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2111 struct qm_mcr_querycgr query_cgr;
2114 err = qman_query_cgr(cgr, &query_cgr);
2118 *result = !!query_cgr.cgr.cs;
2121 EXPORT_SYMBOL(qman_query_cgr_congested);
2123 /* internal function used as a wait_event() expression */
2124 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2126 unsigned long irqflags;
2129 local_irq_save(irqflags);
2132 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2135 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2136 p->vdqcr_owned = fq;
2137 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2140 local_irq_restore(irqflags);
2144 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2148 *p = get_affine_portal();
2149 ret = set_p_vdqcr(*p, fq, vdqcr);
2150 put_affine_portal();
2154 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2155 u32 vdqcr, u32 flags)
2159 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2160 ret = wait_event_interruptible(affine_queue,
2161 !set_vdqcr(p, fq, vdqcr));
2163 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2167 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2169 struct qman_portal *p;
2172 if (fq->state != qman_fq_state_parked &&
2173 fq->state != qman_fq_state_retired)
2175 if (vdqcr & QM_VDQCR_FQID_MASK)
2177 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2179 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2180 if (flags & QMAN_VOLATILE_FLAG_WAIT)
2181 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2183 ret = set_vdqcr(&p, fq, vdqcr);
2187 if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2188 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2190 * NB: don't propagate any error - the caller wouldn't
2191 * know whether the VDQCR was issued or not. A signal
2192 * could arrive after returning anyway, so the caller
2193 * can check signal_pending() if that's an issue.
2195 wait_event_interruptible(affine_queue,
2196 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2198 wait_event(affine_queue,
2199 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2203 EXPORT_SYMBOL(qman_volatile_dequeue);
2205 static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2208 qm_eqcr_cce_prefetch(&p->p);
2210 qm_eqcr_cce_update(&p->p);
2213 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2215 struct qman_portal *p;
2216 struct qm_eqcr_entry *eq;
2217 unsigned long irqflags;
2220 p = get_affine_portal();
2221 local_irq_save(irqflags);
2223 if (p->use_eqcr_ci_stashing) {
2225 * The stashing case is easy, only update if we need to in
2226 * order to try and liberate ring entries.
2228 eq = qm_eqcr_start_stash(&p->p);
2231 * The non-stashing case is harder, need to prefetch ahead of
2234 avail = qm_eqcr_get_avail(&p->p);
2236 update_eqcr_ci(p, avail);
2237 eq = qm_eqcr_start_no_stash(&p->p);
2243 eq->fqid = fq->fqid;
2244 eq->tag = fq_to_tag(fq);
2247 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2249 local_irq_restore(irqflags);
2250 put_affine_portal();
2253 EXPORT_SYMBOL(qman_enqueue);
2255 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2256 struct qm_mcc_initcgr *opts)
2258 union qm_mc_command *mcc;
2259 union qm_mc_result *mcr;
2260 struct qman_portal *p = get_affine_portal();
2261 u8 verb = QM_MCC_VERB_MODIFYCGR;
2264 mcc = qm_mc_start(&p->p);
2266 mcc->initcgr = *opts;
2267 mcc->initcgr.cgid = cgr->cgrid;
2268 if (flags & QMAN_CGR_FLAG_USE_INIT)
2269 verb = QM_MCC_VERB_INITCGR;
2270 qm_mc_commit(&p->p, verb);
2271 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2276 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2277 if (mcr->result != QM_MCR_RESULT_OK)
2281 put_affine_portal();
2285 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2286 #define TARG_MASK(n) (BIT(31) >> PORTAL_IDX(n))
2288 static u8 qman_cgr_cpus[CGR_NUM];
2290 void qman_init_cgr_all(void)
2292 struct qman_cgr cgr;
2295 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2296 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2301 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2302 err_cnt, (err_cnt > 1) ? "s" : "");
2305 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2306 struct qm_mcc_initcgr *opts)
2308 struct qm_mcr_querycgr cgr_state;
2309 struct qm_mcc_initcgr local_opts = {};
2311 struct qman_portal *p;
2314 * We have to check that the provided CGRID is within the limits of the
2315 * data-structures, for obvious reasons. However we'll let h/w take
2316 * care of determining whether it's within the limits of what exists on
2319 if (cgr->cgrid >= CGR_NUM)
2323 p = get_affine_portal();
2324 qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2327 cgr->chan = p->config->channel;
2328 spin_lock(&p->cgr_lock);
2331 ret = qman_query_cgr(cgr, &cgr_state);
2336 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2337 local_opts.cgr.cscn_targ_upd_ctrl =
2338 QM_CGR_TARG_UDP_CTRL_WRITE_BIT | PORTAL_IDX(p);
2340 /* Overwrite TARG */
2341 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ |
2343 local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
2345 /* send init if flags indicate so */
2346 if (opts && (flags & QMAN_CGR_FLAG_USE_INIT))
2347 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2350 ret = qm_modify_cgr(cgr, 0, &local_opts);
2355 list_add(&cgr->node, &p->cgr_cbs);
2357 /* Determine if newly added object requires its callback to be called */
2358 ret = qman_query_cgr(cgr, &cgr_state);
2360 /* we can't go back, so proceed and return success */
2361 dev_err(p->config->dev, "CGR HW state partially modified\n");
2365 if (cgr->cb && cgr_state.cgr.cscn_en &&
2366 qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2369 spin_unlock(&p->cgr_lock);
2370 put_affine_portal();
2373 EXPORT_SYMBOL(qman_create_cgr);
2375 int qman_delete_cgr(struct qman_cgr *cgr)
2377 unsigned long irqflags;
2378 struct qm_mcr_querycgr cgr_state;
2379 struct qm_mcc_initcgr local_opts;
2382 struct qman_portal *p = get_affine_portal();
2384 if (cgr->chan != p->config->channel) {
2385 /* attempt to delete from other portal than creator */
2386 dev_err(p->config->dev, "CGR not owned by current portal");
2387 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2388 cgr->chan, p->config->channel);
2393 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2394 spin_lock_irqsave(&p->cgr_lock, irqflags);
2395 list_del(&cgr->node);
2397 * If there are no other CGR objects for this CGRID in the list,
2398 * update CSCN_TARG accordingly
2400 list_for_each_entry(i, &p->cgr_cbs, node)
2401 if (i->cgrid == cgr->cgrid && i->cb)
2403 ret = qman_query_cgr(cgr, &cgr_state);
2405 /* add back to the list */
2406 list_add(&cgr->node, &p->cgr_cbs);
2409 /* Overwrite TARG */
2410 local_opts.we_mask = QM_CGR_WE_CSCN_TARG;
2411 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2412 local_opts.cgr.cscn_targ_upd_ctrl = PORTAL_IDX(p);
2414 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ &
2416 ret = qm_modify_cgr(cgr, 0, &local_opts);
2418 /* add back to the list */
2419 list_add(&cgr->node, &p->cgr_cbs);
2421 spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2423 put_affine_portal();
2426 EXPORT_SYMBOL(qman_delete_cgr);
2429 struct qman_cgr *cgr;
2430 struct completion completion;
2433 static void qman_delete_cgr_smp_call(void *p)
2435 qman_delete_cgr((struct qman_cgr *)p);
2438 void qman_delete_cgr_safe(struct qman_cgr *cgr)
2441 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2442 smp_call_function_single(qman_cgr_cpus[cgr->cgrid],
2443 qman_delete_cgr_smp_call, cgr, true);
2448 qman_delete_cgr(cgr);
2451 EXPORT_SYMBOL(qman_delete_cgr_safe);
2455 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2457 const union qm_mr_entry *msg;
2460 qm_mr_pvb_update(p);
2461 msg = qm_mr_current(p);
2463 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2466 qm_mr_cci_consume_to_current(p);
2467 qm_mr_pvb_update(p);
2468 msg = qm_mr_current(p);
2473 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2476 const struct qm_dqrr_entry *dqrr;
2480 qm_dqrr_pvb_update(p);
2481 dqrr = qm_dqrr_current(p);
2484 } while (wait && !dqrr);
2487 if (dqrr->fqid == fqid && (dqrr->stat & s))
2489 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2490 qm_dqrr_pvb_update(p);
2492 dqrr = qm_dqrr_current(p);
2497 #define qm_mr_drain(p, V) \
2498 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2500 #define qm_dqrr_drain(p, f, S) \
2501 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2503 #define qm_dqrr_drain_wait(p, f, S) \
2504 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2506 #define qm_dqrr_drain_nomatch(p) \
2507 _qm_dqrr_consume_and_match(p, 0, 0, false)
2509 static int qman_shutdown_fq(u32 fqid)
2511 struct qman_portal *p;
2513 union qm_mc_command *mcc;
2514 union qm_mc_result *mcr;
2515 int orl_empty, drain = 0, ret = 0;
2516 u32 channel, wq, res;
2519 p = get_affine_portal();
2520 dev = p->config->dev;
2521 /* Determine the state of the FQID */
2522 mcc = qm_mc_start(&p->p);
2523 mcc->queryfq_np.fqid = fqid;
2524 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2525 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2526 dev_err(dev, "QUERYFQ_NP timeout\n");
2531 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2532 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2533 if (state == QM_MCR_NP_STATE_OOS)
2534 goto out; /* Already OOS, no need to do anymore checks */
2536 /* Query which channel the FQ is using */
2537 mcc = qm_mc_start(&p->p);
2538 mcc->queryfq.fqid = fqid;
2539 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2540 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2541 dev_err(dev, "QUERYFQ timeout\n");
2546 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2547 /* Need to store these since the MCR gets reused */
2548 channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2549 wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2552 case QM_MCR_NP_STATE_TEN_SCHED:
2553 case QM_MCR_NP_STATE_TRU_SCHED:
2554 case QM_MCR_NP_STATE_ACTIVE:
2555 case QM_MCR_NP_STATE_PARKED:
2557 mcc = qm_mc_start(&p->p);
2558 mcc->alterfq.fqid = fqid;
2559 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2560 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2561 dev_err(dev, "QUERYFQ_NP timeout\n");
2565 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2566 QM_MCR_VERB_ALTER_RETIRE);
2567 res = mcr->result; /* Make a copy as we reuse MCR below */
2569 if (res == QM_MCR_RESULT_PENDING) {
2571 * Need to wait for the FQRN in the message ring, which
2572 * will only occur once the FQ has been drained. In
2573 * order for the FQ to drain the portal needs to be set
2574 * to dequeue from the channel the FQ is scheduled on
2579 /* Flag that we need to drain FQ */
2582 if (channel >= qm_channel_pool1 &&
2583 channel < qm_channel_pool1 + 15) {
2584 /* Pool channel, enable the bit in the portal */
2585 dequeue_wq = (channel -
2586 qm_channel_pool1 + 1)<<4 | wq;
2587 } else if (channel < qm_channel_pool1) {
2588 /* Dedicated channel */
2591 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2596 /* Set the sdqcr to drain this channel */
2597 if (channel < qm_channel_pool1)
2598 qm_dqrr_sdqcr_set(&p->p,
2599 QM_SDQCR_TYPE_ACTIVE |
2600 QM_SDQCR_CHANNELS_DEDICATED);
2602 qm_dqrr_sdqcr_set(&p->p,
2603 QM_SDQCR_TYPE_ACTIVE |
2604 QM_SDQCR_CHANNELS_POOL_CONV
2607 /* Keep draining DQRR while checking the MR*/
2608 qm_dqrr_drain_nomatch(&p->p);
2609 /* Process message ring too */
2610 found_fqrn = qm_mr_drain(&p->p, FQRN);
2612 } while (!found_fqrn);
2615 if (res != QM_MCR_RESULT_OK &&
2616 res != QM_MCR_RESULT_PENDING) {
2617 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2622 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2624 * ORL had no entries, no need to wait until the
2630 * Retirement succeeded, check to see if FQ needs
2633 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2634 /* FQ is Not Empty, drain using volatile DQ commands */
2636 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2638 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2640 * Wait for a dequeue and process the dequeues,
2641 * making sure to empty the ring completely
2643 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2645 qm_dqrr_sdqcr_set(&p->p, 0);
2647 while (!orl_empty) {
2648 /* Wait for the ORL to have been completely drained */
2649 orl_empty = qm_mr_drain(&p->p, FQRL);
2652 mcc = qm_mc_start(&p->p);
2653 mcc->alterfq.fqid = fqid;
2654 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2655 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2660 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2661 QM_MCR_VERB_ALTER_OOS);
2662 if (mcr->result != QM_MCR_RESULT_OK) {
2663 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2670 case QM_MCR_NP_STATE_RETIRED:
2671 /* Send OOS Command */
2672 mcc = qm_mc_start(&p->p);
2673 mcc->alterfq.fqid = fqid;
2674 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2675 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2680 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2681 QM_MCR_VERB_ALTER_OOS);
2683 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2690 case QM_MCR_NP_STATE_OOS:
2699 put_affine_portal();
2703 const struct qm_portal_config *qman_get_qm_portal_config(
2704 struct qman_portal *portal)
2706 return portal->config;
2709 struct gen_pool *qm_fqalloc; /* FQID allocator */
2710 struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2711 struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2713 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2720 addr = gen_pool_alloc(p, cnt);
2724 *result = addr & ~DPAA_GENALLOC_OFF;
2729 int qman_alloc_fqid_range(u32 *result, u32 count)
2731 return qman_alloc_range(qm_fqalloc, result, count);
2733 EXPORT_SYMBOL(qman_alloc_fqid_range);
2735 int qman_alloc_pool_range(u32 *result, u32 count)
2737 return qman_alloc_range(qm_qpalloc, result, count);
2739 EXPORT_SYMBOL(qman_alloc_pool_range);
2741 int qman_alloc_cgrid_range(u32 *result, u32 count)
2743 return qman_alloc_range(qm_cgralloc, result, count);
2745 EXPORT_SYMBOL(qman_alloc_cgrid_range);
2747 int qman_release_fqid(u32 fqid)
2749 int ret = qman_shutdown_fq(fqid);
2752 pr_debug("FQID %d leaked\n", fqid);
2756 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2759 EXPORT_SYMBOL(qman_release_fqid);
2761 static int qpool_cleanup(u32 qp)
2764 * We query all FQDs starting from
2765 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2766 * whose destination channel is the pool-channel being released.
2767 * When a non-OOS FQD is found we attempt to clean it up
2769 struct qman_fq fq = {
2770 .fqid = QM_FQID_RANGE_START
2775 struct qm_mcr_queryfq_np np;
2777 err = qman_query_fq_np(&fq, &np);
2779 /* FQID range exceeded, found no problems */
2781 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2784 err = qman_query_fq(&fq, &fqd);
2787 if (qm_fqd_get_chan(&fqd) == qp) {
2788 /* The channel is the FQ's target, clean it */
2789 err = qman_shutdown_fq(fq.fqid);
2792 * Couldn't shut down the FQ
2793 * so the pool must be leaked
2798 /* Move to the next FQID */
2803 int qman_release_pool(u32 qp)
2807 ret = qpool_cleanup(qp);
2809 pr_debug("CHID %d leaked\n", qp);
2813 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2816 EXPORT_SYMBOL(qman_release_pool);
2818 static int cgr_cleanup(u32 cgrid)
2821 * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2822 * error, looking for non-OOS FQDs whose CGR is the CGR being released
2824 struct qman_fq fq = {
2830 struct qm_mcr_queryfq_np np;
2832 err = qman_query_fq_np(&fq, &np);
2834 /* FQID range exceeded, found no problems */
2836 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2839 err = qman_query_fq(&fq, &fqd);
2842 if ((fqd.fq_ctrl & QM_FQCTRL_CGE) &&
2843 fqd.cgid == cgrid) {
2844 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2849 /* Move to the next FQID */
2854 int qman_release_cgrid(u32 cgrid)
2858 ret = cgr_cleanup(cgrid);
2860 pr_debug("CGRID %d leaked\n", cgrid);
2864 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2867 EXPORT_SYMBOL(qman_release_cgrid);