1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2019 Christoph Hellwig.
4 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
7 #include <linux/platform_device.h>
8 #include <linux/of_platform.h>
12 #include <soc/canaan/k210-sysctl.h>
14 static int k210_sysctl_probe(struct platform_device *pdev)
16 struct device *dev = &pdev->dev;
20 dev_info(dev, "K210 system controller\n");
22 /* Get power bus clock */
23 pclk = devm_clk_get(dev, NULL);
25 return dev_err_probe(dev, PTR_ERR(pclk),
26 "Get bus clock failed\n");
28 ret = clk_prepare_enable(pclk);
30 dev_err(dev, "Enable bus clock failed\n");
34 /* Populate children */
35 ret = devm_of_platform_populate(dev);
37 dev_err(dev, "Populate platform failed %d\n", ret);
42 static const struct of_device_id k210_sysctl_of_match[] = {
43 { .compatible = "canaan,k210-sysctl", },
47 static struct platform_driver k210_sysctl_driver = {
49 .name = "k210-sysctl",
50 .of_match_table = k210_sysctl_of_match,
52 .probe = k210_sysctl_probe,
54 builtin_platform_driver(k210_sysctl_driver);
57 * System controller registers base address and size.
59 #define K210_SYSCTL_BASE_ADDR 0x50440000ULL
60 #define K210_SYSCTL_BASE_SIZE 0x1000
63 * This needs to be called very early during initialization, given that
64 * PLL1 needs to be enabled to be able to use all SRAM.
66 static void __init k210_soc_early_init(const void *fdt)
68 void __iomem *sysctl_base;
70 sysctl_base = ioremap(K210_SYSCTL_BASE_ADDR, K210_SYSCTL_BASE_SIZE);
72 panic("k210-sysctl: ioremap failed");
74 k210_clk_early_init(sysctl_base);
78 SOC_EARLY_INIT_DECLARE(k210_soc, "canaan,kendryte-k210", k210_soc_early_init);