drivers/soc/bcm/brcmstb/pm/pm.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Definitions for Broadcom STB power management / Always ON (AON) block
   4  *
   5  * Copyright © 2016-2017 Broadcom
   6  */
   7
   8 #ifndef __BRCMSTB_PM_H__
   9 #define __BRCMSTB_PM_H__
  10
  11 #define AON_CTRL_RESET_CTRL             0x00
  12 #define AON_CTRL_PM_CTRL                0x04
  13 #define AON_CTRL_PM_STATUS              0x08
  14 #define AON_CTRL_PM_CPU_WAIT_COUNT      0x10
  15 #define AON_CTRL_PM_INITIATE            0x88
  16 #define AON_CTRL_HOST_MISC_CMDS         0x8c
  17 #define AON_CTRL_SYSTEM_DATA_RAM_OFS    0x200
  18
  19 /* MIPS PM constants */
  20 /* MEMC0 offsets */
  21 #define DDR40_PHY_CONTROL_REGS_0_PLL_STATUS     0x10
  22 #define DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL   0xa4
  23
  24 /* TIMER offsets */
  25 #define TIMER_TIMER1_CTRL               0x0c
  26 #define TIMER_TIMER1_STAT               0x1c
  27
  28 /* TIMER defines */
  29 #define RESET_TIMER                     0x0
  30 #define START_TIMER                     0xbfffffff
  31 #define TIMER_MASK                      0x3fffffff
  32
  33 /* PM_CTRL bitfield (Method #0) */
  34 #define PM_FAST_PWRDOWN                 (1 << 6)
  35 #define PM_WARM_BOOT                    (1 << 5)
  36 #define PM_DEEP_STANDBY                 (1 << 4)
  37 #define PM_CPU_PWR                      (1 << 3)
  38 #define PM_USE_CPU_RDY                  (1 << 2)
  39 #define PM_PLL_PWRDOWN                  (1 << 1)
  40 #define PM_PWR_DOWN                     (1 << 0)
  41
  42 /* PM_CTRL bitfield (Method #1) */
  43 #define PM_DPHY_STANDBY_CLEAR           (1 << 20)
  44 #define PM_MIN_S3_WIDTH_TIMER_BYPASS    (1 << 7)
  45
  46 #define PM_S2_COMMAND   (PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN)
  47
  48 /* Method 0 bitmasks */
  49 #define PM_COLD_CONFIG  (PM_PLL_PWRDOWN | PM_DEEP_STANDBY)
  50 #define PM_WARM_CONFIG  (PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT)
  51
  52 /* Method 1 bitmask */
  53 #define M1_PM_WARM_CONFIG (PM_DPHY_STANDBY_CLEAR | \
  54                            PM_MIN_S3_WIDTH_TIMER_BYPASS | \
  55                            PM_WARM_BOOT | PM_DEEP_STANDBY | \
  56                            PM_PLL_PWRDOWN | PM_PWR_DOWN)
  57
  58 #define M1_PM_COLD_CONFIG (PM_DPHY_STANDBY_CLEAR | \
  59                            PM_MIN_S3_WIDTH_TIMER_BYPASS | \
  60                            PM_DEEP_STANDBY | \
  61                            PM_PLL_PWRDOWN | PM_PWR_DOWN)
  62
  63 #ifndef __ASSEMBLY__
  64
  65 #ifndef CONFIG_MIPS
  66 extern const unsigned long brcmstb_pm_do_s2_sz;
  67 extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base,
  68                 void __iomem *ddr_phy_pll_status);
  69 #else
  70 /* s2 asm */
  71 extern asmlinkage int brcm_pm_do_s2(u32 *s2_params);
  72
  73 /* s3 asm */
  74 extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base,
  75                 int dcache_linesz);
  76 extern int s3_reentry;
  77 #endif /* CONFIG_MIPS */
  78
  79 #endif
  80
  81 #endif /* __BRCMSTB_PM_H__ */