GNU Linux-libre 5.10.215-gnu1
[releases.git] / drivers / soc / bcm / brcmstb / biuctrl.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Broadcom STB SoCs Bus Unit Interface controls
4  *
5  * Copyright (C) 2015, Broadcom Corporation
6  */
7
8 #define pr_fmt(fmt)     "brcmstb: " KBUILD_MODNAME ": " fmt
9
10 #include <linux/kernel.h>
11 #include <linux/io.h>
12 #include <linux/of_address.h>
13 #include <linux/syscore_ops.h>
14 #include <linux/soc/brcmstb/brcmstb.h>
15
16 #define RACENPREF_MASK                  0x3
17 #define RACPREFINST_SHIFT               0
18 #define RACENINST_SHIFT                 2
19 #define RACPREFDATA_SHIFT               4
20 #define RACENDATA_SHIFT                 6
21 #define RAC_CPU_SHIFT                   8
22 #define RACCFG_MASK                     0xff
23 #define DPREF_LINE_2_SHIFT              24
24 #define DPREF_LINE_2_MASK               0xff
25
26 /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
27 #define RAC_DATA_INST_EN_MASK           (1 << RACPREFINST_SHIFT | \
28                                          RACENPREF_MASK << RACENINST_SHIFT | \
29                                          1 << RACPREFDATA_SHIFT | \
30                                          RACENPREF_MASK << RACENDATA_SHIFT)
31
32 #define  CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
33 #define CPU_CREDIT_REG_MCPx_READ_CRED_MASK      0xf
34 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK     0xf
35 #define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x)  ((x) * 8)
36 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
37
38 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x)      ((x) * 8)
39 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK          0xff
40
41 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK       0xf
42 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK         0xf
43 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT        4
44 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE               BIT(8)
45
46 static void __iomem *cpubiuctrl_base;
47 static bool mcp_wr_pairing_en;
48 static const int *cpubiuctrl_regs;
49
50 enum cpubiuctrl_regs {
51         CPU_CREDIT_REG = 0,
52         CPU_MCP_FLOW_REG,
53         CPU_WRITEBACK_CTRL_REG,
54         RAC_CONFIG0_REG,
55         RAC_CONFIG1_REG,
56         NUM_CPU_BIUCTRL_REGS,
57 };
58
59 static inline u32 cbc_readl(int reg)
60 {
61         int offset = cpubiuctrl_regs[reg];
62
63         if (offset == -1 ||
64             (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
65                 return (u32)-1;
66
67         return readl_relaxed(cpubiuctrl_base + offset);
68 }
69
70 static inline void cbc_writel(u32 val, int reg)
71 {
72         int offset = cpubiuctrl_regs[reg];
73
74         if (offset == -1 ||
75             (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
76                 return;
77
78         writel(val, cpubiuctrl_base + offset);
79 }
80
81 static const int b15_cpubiuctrl_regs[] = {
82         [CPU_CREDIT_REG] = 0x184,
83         [CPU_MCP_FLOW_REG] = -1,
84         [CPU_WRITEBACK_CTRL_REG] = -1,
85         [RAC_CONFIG0_REG] = -1,
86         [RAC_CONFIG1_REG] = -1,
87 };
88
89 /* Odd cases, e.g: 7260A0 */
90 static const int b53_cpubiuctrl_no_wb_regs[] = {
91         [CPU_CREDIT_REG] = 0x0b0,
92         [CPU_MCP_FLOW_REG] = 0x0b4,
93         [CPU_WRITEBACK_CTRL_REG] = -1,
94         [RAC_CONFIG0_REG] = 0x78,
95         [RAC_CONFIG1_REG] = 0x7c,
96 };
97
98 static const int b53_cpubiuctrl_regs[] = {
99         [CPU_CREDIT_REG] = 0x0b0,
100         [CPU_MCP_FLOW_REG] = 0x0b4,
101         [CPU_WRITEBACK_CTRL_REG] = 0x22c,
102         [RAC_CONFIG0_REG] = 0x78,
103         [RAC_CONFIG1_REG] = 0x7c,
104 };
105
106 static const int a72_cpubiuctrl_regs[] = {
107         [CPU_CREDIT_REG] = 0x18,
108         [CPU_MCP_FLOW_REG] = 0x1c,
109         [CPU_WRITEBACK_CTRL_REG] = 0x20,
110         [RAC_CONFIG0_REG] = 0x08,
111         [RAC_CONFIG1_REG] = 0x0c,
112 };
113
114 static int __init mcp_write_pairing_set(void)
115 {
116         u32 creds = 0;
117
118         if (!cpubiuctrl_base)
119                 return -1;
120
121         creds = cbc_readl(CPU_CREDIT_REG);
122         if (mcp_wr_pairing_en) {
123                 pr_info("MCP: Enabling write pairing\n");
124                 cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
125                            CPU_CREDIT_REG);
126         } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
127                 pr_info("MCP: Disabling write pairing\n");
128                 cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
129                            CPU_CREDIT_REG);
130         } else {
131                 pr_info("MCP: Write pairing already disabled\n");
132         }
133
134         return 0;
135 }
136
137 static const u32 a72_b53_mach_compat[] = {
138         0x7211,
139         0x7216,
140         0x72164,
141         0x72165,
142         0x7255,
143         0x7260,
144         0x7268,
145         0x7271,
146         0x7278,
147 };
148
149 /* The read-ahead cache present in the Brahma-B53 CPU is a special piece of
150  * hardware after the integrated L2 cache of the B53 CPU complex whose purpose
151  * is to prefetch instruction and/or data with a line size of either 64 bytes
152  * or 256 bytes. The rationale is that the data-bus of the CPU interface is
153  * optimized for 256-byte transactions, and enabling the read-ahead cache
154  * provides a significant performance boost (typically twice the performance
155  * for a memcpy benchmark application).
156  *
157  * The read-ahead cache is transparent for Virtual Address cache maintenance
158  * operations: IC IVAU, DC IVAC, DC CVAC, DC CVAU and DC CIVAC.  So no special
159  * handling is needed for the DMA API above and beyond what is included in the
160  * arm64 implementation.
161  *
162  * In addition, since the Point of Unification is typically between L1 and L2
163  * for the Brahma-B53 processor no special read-ahead cache handling is needed
164  * for the IC IALLU and IC IALLUIS cache maintenance operations.
165  *
166  * However, it is not possible to specify the cache level (L3) for the cache
167  * maintenance instructions operating by set/way to operate on the read-ahead
168  * cache.  The read-ahead cache will maintain coherency when inner cache lines
169  * are cleaned by set/way, but if it is necessary to invalidate inner cache
170  * lines by set/way to maintain coherency with system masters operating on
171  * shared memory that does not have hardware support for coherency, then it
172  * will also be necessary to explicitly invalidate the read-ahead cache.
173  */
174 static void __init a72_b53_rac_enable_all(struct device_node *np)
175 {
176         unsigned int cpu;
177         u32 enable = 0, pref_dist, shift;
178
179         if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
180                 return;
181
182         if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
183                 return;
184
185         pref_dist = cbc_readl(RAC_CONFIG1_REG);
186         for_each_possible_cpu(cpu) {
187                 shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
188                 enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
189                 if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
190                         enable &= ~(RACENPREF_MASK << shift);
191                         enable |= 3 << shift;
192                         pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
193                 }
194         }
195
196         cbc_writel(enable, RAC_CONFIG0_REG);
197         cbc_writel(pref_dist, RAC_CONFIG1_REG);
198
199         pr_info("%pOF: Broadcom %s read-ahead cache\n",
200                 np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
201                 "Cortex-A72" : "Brahma-B53");
202 }
203
204 static void __init mcp_a72_b53_set(void)
205 {
206         unsigned int i;
207         u32 reg;
208
209         reg = brcmstb_get_family_id();
210
211         for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) {
212                 if (BRCM_ID(reg) == a72_b53_mach_compat[i])
213                         break;
214         }
215
216         if (i == ARRAY_SIZE(a72_b53_mach_compat))
217                 return;
218
219         /* Set all 3 MCP interfaces to 8 credits */
220         reg = cbc_readl(CPU_CREDIT_REG);
221         for (i = 0; i < 3; i++) {
222                 reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
223                          CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
224                 reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
225                          CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
226                 reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
227                 reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
228         }
229         cbc_writel(reg, CPU_CREDIT_REG);
230
231         /* Max out the number of in-flight Jwords reads on the MCP interface */
232         reg = cbc_readl(CPU_MCP_FLOW_REG);
233         for (i = 0; i < 3; i++)
234                 reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
235                         CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
236         cbc_writel(reg, CPU_MCP_FLOW_REG);
237
238         /* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
239          * threshold
240          */
241         reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
242         reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
243         reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
244         reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
245                  CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
246         reg |= 8;
247         reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
248         cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
249 }
250
251 static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
252 {
253         struct device_node *cpu_dn;
254         u32 family_id;
255         int ret = 0;
256
257         cpubiuctrl_base = of_iomap(np, 0);
258         if (!cpubiuctrl_base) {
259                 pr_err("failed to remap BIU control base\n");
260                 ret = -ENOMEM;
261                 goto out;
262         }
263
264         mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
265
266         cpu_dn = of_get_cpu_node(0, NULL);
267         if (!cpu_dn) {
268                 pr_err("failed to obtain CPU device node\n");
269                 ret = -ENODEV;
270                 goto out;
271         }
272
273         if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
274                 cpubiuctrl_regs = b15_cpubiuctrl_regs;
275         else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
276                 cpubiuctrl_regs = b53_cpubiuctrl_regs;
277         else if (of_device_is_compatible(cpu_dn, "arm,cortex-a72"))
278                 cpubiuctrl_regs = a72_cpubiuctrl_regs;
279         else {
280                 pr_err("unsupported CPU\n");
281                 ret = -EINVAL;
282         }
283         of_node_put(cpu_dn);
284
285         family_id = brcmstb_get_family_id();
286         if (BRCM_ID(family_id) == 0x7260 && BRCM_REV(family_id) == 0)
287                 cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
288 out:
289         of_node_put(np);
290         return ret;
291 }
292
293 #ifdef CONFIG_PM_SLEEP
294 static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
295
296 static int brcmstb_cpu_credit_reg_suspend(void)
297 {
298         unsigned int i;
299
300         if (!cpubiuctrl_base)
301                 return 0;
302
303         for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
304                 cpubiuctrl_reg_save[i] = cbc_readl(i);
305
306         return 0;
307 }
308
309 static void brcmstb_cpu_credit_reg_resume(void)
310 {
311         unsigned int i;
312
313         if (!cpubiuctrl_base)
314                 return;
315
316         for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
317                 cbc_writel(cpubiuctrl_reg_save[i], i);
318 }
319
320 static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
321         .suspend = brcmstb_cpu_credit_reg_suspend,
322         .resume = brcmstb_cpu_credit_reg_resume,
323 };
324 #endif
325
326
327 static int __init brcmstb_biuctrl_init(void)
328 {
329         struct device_node *np;
330         int ret;
331
332         /* We might be running on a multi-platform kernel, don't make this a
333          * fatal error, just bail out early
334          */
335         np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
336         if (!np)
337                 return 0;
338
339         ret = setup_hifcpubiuctrl_regs(np);
340         if (ret)
341                 return ret;
342
343         ret = mcp_write_pairing_set();
344         if (ret) {
345                 pr_err("MCP: Unable to disable write pairing!\n");
346                 return ret;
347         }
348
349         a72_b53_rac_enable_all(np);
350         mcp_a72_b53_set();
351 #ifdef CONFIG_PM_SLEEP
352         register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
353 #endif
354         return 0;
355 }
356 early_initcall(brcmstb_biuctrl_init);