2 * Broadcom STB SoCs Bus Unit Interface controls
4 * Copyright (C) 2015, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
18 #include <linux/kernel.h>
20 #include <linux/of_address.h>
21 #include <linux/syscore_ops.h>
22 #include <linux/soc/brcmstb/brcmstb.h>
24 #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
25 #define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
26 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
27 #define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
28 #define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
30 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
31 #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
33 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
34 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
35 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
36 #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
38 static void __iomem *cpubiuctrl_base;
39 static bool mcp_wr_pairing_en;
40 static const int *cpubiuctrl_regs;
42 static inline u32 cbc_readl(int reg)
44 int offset = cpubiuctrl_regs[reg];
49 return readl_relaxed(cpubiuctrl_base + offset);
52 static inline void cbc_writel(u32 val, int reg)
54 int offset = cpubiuctrl_regs[reg];
59 writel(val, cpubiuctrl_base + offset);
62 enum cpubiuctrl_regs {
65 CPU_WRITEBACK_CTRL_REG
68 static const int b15_cpubiuctrl_regs[] = {
69 [CPU_CREDIT_REG] = 0x184,
70 [CPU_MCP_FLOW_REG] = -1,
71 [CPU_WRITEBACK_CTRL_REG] = -1,
74 /* Odd cases, e.g: 7260 */
75 static const int b53_cpubiuctrl_no_wb_regs[] = {
76 [CPU_CREDIT_REG] = 0x0b0,
77 [CPU_MCP_FLOW_REG] = 0x0b4,
78 [CPU_WRITEBACK_CTRL_REG] = -1,
81 static const int b53_cpubiuctrl_regs[] = {
82 [CPU_CREDIT_REG] = 0x0b0,
83 [CPU_MCP_FLOW_REG] = 0x0b4,
84 [CPU_WRITEBACK_CTRL_REG] = 0x22c,
87 #define NUM_CPU_BIUCTRL_REGS 3
89 static int __init mcp_write_pairing_set(void)
96 creds = cbc_readl(CPU_CREDIT_REG);
97 if (mcp_wr_pairing_en) {
98 pr_info("MCP: Enabling write pairing\n");
99 cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
101 } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
102 pr_info("MCP: Disabling write pairing\n");
103 cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
106 pr_info("MCP: Write pairing already disabled\n");
112 static const u32 b53_mach_compat[] = {
118 static void __init mcp_b53_set(void)
123 reg = brcmstb_get_family_id();
125 for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
126 if (BRCM_ID(reg) == b53_mach_compat[i])
130 if (i == ARRAY_SIZE(b53_mach_compat))
133 /* Set all 3 MCP interfaces to 8 credits */
134 reg = cbc_readl(CPU_CREDIT_REG);
135 for (i = 0; i < 3; i++) {
136 reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
137 CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
138 reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
139 CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
140 reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
141 reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
143 cbc_writel(reg, CPU_CREDIT_REG);
145 /* Max out the number of in-flight Jwords reads on the MCP interface */
146 reg = cbc_readl(CPU_MCP_FLOW_REG);
147 for (i = 0; i < 3; i++)
148 reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
149 CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
150 cbc_writel(reg, CPU_MCP_FLOW_REG);
152 /* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
155 reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
156 reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
157 reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
158 reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
159 CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
161 reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
162 cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
165 static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
167 struct device_node *cpu_dn;
170 cpubiuctrl_base = of_iomap(np, 0);
171 if (!cpubiuctrl_base) {
172 pr_err("failed to remap BIU control base\n");
177 mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
179 cpu_dn = of_get_cpu_node(0, NULL);
181 pr_err("failed to obtain CPU device node\n");
186 if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
187 cpubiuctrl_regs = b15_cpubiuctrl_regs;
188 else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
189 cpubiuctrl_regs = b53_cpubiuctrl_regs;
191 pr_err("unsupported CPU\n");
196 if (BRCM_ID(brcmstb_get_family_id()) == 0x7260)
197 cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
203 #ifdef CONFIG_PM_SLEEP
204 static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
206 static int brcmstb_cpu_credit_reg_suspend(void)
210 if (!cpubiuctrl_base)
213 for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
214 cpubiuctrl_reg_save[i] = cbc_readl(i);
219 static void brcmstb_cpu_credit_reg_resume(void)
223 if (!cpubiuctrl_base)
226 for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
227 cbc_writel(cpubiuctrl_reg_save[i], i);
230 static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
231 .suspend = brcmstb_cpu_credit_reg_suspend,
232 .resume = brcmstb_cpu_credit_reg_resume,
237 static int __init brcmstb_biuctrl_init(void)
239 struct device_node *np;
242 /* We might be running on a multi-platform kernel, don't make this a
243 * fatal error, just bail out early
245 np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
249 ret = setup_hifcpubiuctrl_regs(np);
253 ret = mcp_write_pairing_set();
255 pr_err("MCP: Unable to disable write pairing!\n");
260 #ifdef CONFIG_PM_SLEEP
261 register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
265 early_initcall(brcmstb_biuctrl_init);