drivers/soc/amlogic/meson-canvas.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 BayLibre, SAS
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  * Copyright (C) 2014 Endless Mobile
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/mfd/syscon.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13 #include <linux/soc/amlogic/meson-canvas.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/io.h>
  17
  18 #define NUM_CANVAS 256
  19
  20 /* DMC Registers */
  21 #define DMC_CAV_LUT_DATAL       0x00
  22         #define CANVAS_WIDTH_LBIT       29
  23         #define CANVAS_WIDTH_LWID       3
  24 #define DMC_CAV_LUT_DATAH       0x04
  25         #define CANVAS_WIDTH_HBIT       0
  26         #define CANVAS_HEIGHT_BIT       9
  27         #define CANVAS_WRAP_BIT         22
  28         #define CANVAS_BLKMODE_BIT      24
  29         #define CANVAS_ENDIAN_BIT       26
  30 #define DMC_CAV_LUT_ADDR        0x08
  31         #define CANVAS_LUT_WR_EN        BIT(9)
  32         #define CANVAS_LUT_RD_EN        BIT(8)
  33
  34 struct meson_canvas {
  35         struct device *dev;
  36         void __iomem *reg_base;
  37         spinlock_t lock; /* canvas device lock */
  38         u8 used[NUM_CANVAS];
  39         bool supports_endianness;
  40 };
  41
  42 static void canvas_write(struct meson_canvas *canvas, u32 reg, u32 val)
  43 {
  44         writel_relaxed(val, canvas->reg_base + reg);
  45 }
  46
  47 static u32 canvas_read(struct meson_canvas *canvas, u32 reg)
  48 {
  49         return readl_relaxed(canvas->reg_base + reg);
  50 }
  51
  52 struct meson_canvas *meson_canvas_get(struct device *dev)
  53 {
  54         struct device_node *canvas_node;
  55         struct platform_device *canvas_pdev;
  56         struct meson_canvas *canvas;
  57
  58         canvas_node = of_parse_phandle(dev->of_node, "amlogic,canvas", 0);
  59         if (!canvas_node)
  60                 return ERR_PTR(-ENODEV);
  61
  62         canvas_pdev = of_find_device_by_node(canvas_node);
  63         if (!canvas_pdev) {
  64                 of_node_put(canvas_node);
  65                 return ERR_PTR(-EPROBE_DEFER);
  66         }
  67
  68         of_node_put(canvas_node);
  69
  70         /*
  71          * If priv is NULL, it's probably because the canvas hasn't
  72          * properly initialized. Bail out with -EINVAL because, in the
  73          * current state, this driver probe cannot return -EPROBE_DEFER
  74          */
  75         canvas = dev_get_drvdata(&canvas_pdev->dev);
  76         if (!canvas) {
  77                 put_device(&canvas_pdev->dev);
  78                 return ERR_PTR(-EINVAL);
  79         }
  80
  81         return canvas;
  82 }
  83 EXPORT_SYMBOL_GPL(meson_canvas_get);
  84
  85 int meson_canvas_config(struct meson_canvas *canvas, u8 canvas_index,
  86                         u32 addr, u32 stride, u32 height,
  87                         unsigned int wrap,
  88                         unsigned int blkmode,
  89                         unsigned int endian)
  90 {
  91         unsigned long flags;
  92
  93         if (endian && !canvas->supports_endianness) {
  94                 dev_err(canvas->dev,
  95                         "Endianness is not supported on this SoC\n");
  96                 return -EINVAL;
  97         }
  98
  99         spin_lock_irqsave(&canvas->lock, flags);
 100         if (!canvas->used[canvas_index]) {
 101                 dev_err(canvas->dev,
 102                         "Trying to setup non allocated canvas %u\n",
 103                         canvas_index);
 104                 spin_unlock_irqrestore(&canvas->lock, flags);
 105                 return -EINVAL;
 106         }
 107
 108         canvas_write(canvas, DMC_CAV_LUT_DATAL,
 109                      ((addr + 7) >> 3) |
 110                      (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
 111
 112         canvas_write(canvas, DMC_CAV_LUT_DATAH,
 113                      ((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
 114                                                 CANVAS_WIDTH_HBIT) |
 115                      (height << CANVAS_HEIGHT_BIT) |
 116                      (wrap << CANVAS_WRAP_BIT) |
 117                      (blkmode << CANVAS_BLKMODE_BIT) |
 118                      (endian << CANVAS_ENDIAN_BIT));
 119
 120         canvas_write(canvas, DMC_CAV_LUT_ADDR,
 121                      CANVAS_LUT_WR_EN | canvas_index);
 122
 123         /* Force a read-back to make sure everything is flushed. */
 124         canvas_read(canvas, DMC_CAV_LUT_DATAH);
 125         spin_unlock_irqrestore(&canvas->lock, flags);
 126
 127         return 0;
 128 }
 129 EXPORT_SYMBOL_GPL(meson_canvas_config);
 130
 131 int meson_canvas_alloc(struct meson_canvas *canvas, u8 *canvas_index)
 132 {
 133         int i;
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&canvas->lock, flags);
 137         for (i = 0; i < NUM_CANVAS; ++i) {
 138                 if (!canvas->used[i]) {
 139                         canvas->used[i] = 1;
 140                         spin_unlock_irqrestore(&canvas->lock, flags);
 141                         *canvas_index = i;
 142                         return 0;
 143                 }
 144         }
 145         spin_unlock_irqrestore(&canvas->lock, flags);
 146
 147         dev_err(canvas->dev, "No more canvas available\n");
 148         return -ENODEV;
 149 }
 150 EXPORT_SYMBOL_GPL(meson_canvas_alloc);
 151
 152 int meson_canvas_free(struct meson_canvas *canvas, u8 canvas_index)
 153 {
 154         unsigned long flags;
 155
 156         spin_lock_irqsave(&canvas->lock, flags);
 157         if (!canvas->used[canvas_index]) {
 158                 dev_err(canvas->dev,
 159                         "Trying to free unused canvas %u\n", canvas_index);
 160                 spin_unlock_irqrestore(&canvas->lock, flags);
 161                 return -EINVAL;
 162         }
 163         canvas->used[canvas_index] = 0;
 164         spin_unlock_irqrestore(&canvas->lock, flags);
 165
 166         return 0;
 167 }
 168 EXPORT_SYMBOL_GPL(meson_canvas_free);
 169
 170 static int meson_canvas_probe(struct platform_device *pdev)
 171 {
 172         struct meson_canvas *canvas;
 173         struct device *dev = &pdev->dev;
 174
 175         canvas = devm_kzalloc(dev, sizeof(*canvas), GFP_KERNEL);
 176         if (!canvas)
 177                 return -ENOMEM;
 178
 179         canvas->reg_base = devm_platform_ioremap_resource(pdev, 0);
 180         if (IS_ERR(canvas->reg_base))
 181                 return PTR_ERR(canvas->reg_base);
 182
 183         canvas->supports_endianness = of_device_get_match_data(dev);
 184
 185         canvas->dev = dev;
 186         spin_lock_init(&canvas->lock);
 187         dev_set_drvdata(dev, canvas);
 188
 189         return 0;
 190 }
 191
 192 static const struct of_device_id canvas_dt_match[] = {
 193         { .compatible = "amlogic,meson8-canvas", .data = (void *)false, },
 194         { .compatible = "amlogic,meson8b-canvas", .data = (void *)false, },
 195         { .compatible = "amlogic,meson8m2-canvas", .data = (void *)false, },
 196         { .compatible = "amlogic,canvas", .data = (void *)true, },
 197         {}
 198 };
 199 MODULE_DEVICE_TABLE(of, canvas_dt_match);
 200
 201 static struct platform_driver meson_canvas_driver = {
 202         .probe = meson_canvas_probe,
 203         .driver = {
 204                 .name = "amlogic-canvas",
 205                 .of_match_table = canvas_dt_match,
 206         },
 207 };
 208 module_platform_driver(meson_canvas_driver);
 209
 210 MODULE_DESCRIPTION("Amlogic Canvas driver");
 211 MODULE_AUTHOR("Maxime Jourdan <mjourdan@baylibre.com>");
 212 MODULE_LICENSE("GPL");