1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Universal Flash Storage Host controller PCI glue driver
5 * This code is based on drivers/scsi/ufs/ufshcd-pci.c
6 * Copyright (C) 2011-2013 Samsung India Software Operations
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
14 #include <linux/pci.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/pm_qos.h>
17 #include <linux/debugfs.h>
22 struct dentry *debugfs_root;
25 static int ufs_intel_disable_lcc(struct ufs_hba *hba)
27 u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
30 ufshcd_dme_get(hba, attr, &lcc_enable);
32 ufshcd_disable_host_tx_lcc(hba);
37 static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
38 enum ufs_notify_change_status status)
44 err = ufs_intel_disable_lcc(hba);
55 #define INTEL_ACTIVELTR 0x804
56 #define INTEL_IDLELTR 0x808
58 #define INTEL_LTR_REQ BIT(15)
59 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
60 #define INTEL_LTR_SCALE_1US (2 << 10)
61 #define INTEL_LTR_SCALE_32US (3 << 10)
62 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
64 static void intel_cache_ltr(struct ufs_hba *hba)
66 struct intel_host *host = ufshcd_get_variant(hba);
68 host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
69 host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
72 static void intel_ltr_set(struct device *dev, s32 val)
74 struct ufs_hba *hba = dev_get_drvdata(dev);
75 struct intel_host *host = ufshcd_get_variant(hba);
78 pm_runtime_get_sync(dev);
81 * Program latency tolerance (LTR) accordingly what has been asked
82 * by the PM QoS layer or disable it in case we were passed
83 * negative value or PM_QOS_LATENCY_ANY.
85 ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
87 if (val == PM_QOS_LATENCY_ANY || val < 0) {
88 ltr &= ~INTEL_LTR_REQ;
91 ltr &= ~INTEL_LTR_SCALE_MASK;
92 ltr &= ~INTEL_LTR_VALUE_MASK;
94 if (val > INTEL_LTR_VALUE_MASK) {
96 if (val > INTEL_LTR_VALUE_MASK)
97 val = INTEL_LTR_VALUE_MASK;
98 ltr |= INTEL_LTR_SCALE_32US | val;
100 ltr |= INTEL_LTR_SCALE_1US | val;
104 if (ltr == host->active_ltr)
107 writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
108 writel(ltr, hba->mmio_base + INTEL_IDLELTR);
110 /* Cache the values into intel_host structure */
111 intel_cache_ltr(hba);
116 static void intel_ltr_expose(struct device *dev)
118 dev->power.set_latency_tolerance = intel_ltr_set;
119 dev_pm_qos_expose_latency_tolerance(dev);
122 static void intel_ltr_hide(struct device *dev)
124 dev_pm_qos_hide_latency_tolerance(dev);
125 dev->power.set_latency_tolerance = NULL;
128 static void intel_add_debugfs(struct ufs_hba *hba)
130 struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
131 struct intel_host *host = ufshcd_get_variant(hba);
133 intel_cache_ltr(hba);
135 host->debugfs_root = dir;
136 debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
137 debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
140 static void intel_remove_debugfs(struct ufs_hba *hba)
142 struct intel_host *host = ufshcd_get_variant(hba);
144 debugfs_remove_recursive(host->debugfs_root);
147 static int ufs_intel_common_init(struct ufs_hba *hba)
149 struct intel_host *host;
151 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
153 host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
156 ufshcd_set_variant(hba, host);
157 intel_ltr_expose(hba->dev);
158 intel_add_debugfs(hba);
162 static void ufs_intel_common_exit(struct ufs_hba *hba)
164 intel_remove_debugfs(hba);
165 intel_ltr_hide(hba->dev);
168 static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op)
171 * To support S4 (suspend-to-disk) with spm_lvl other than 5, the base
172 * address registers must be restored because the restore kernel can
173 * have used different addresses.
175 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
176 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
177 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
178 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
179 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
180 REG_UTP_TASK_REQ_LIST_BASE_L);
181 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
182 REG_UTP_TASK_REQ_LIST_BASE_H);
184 if (ufshcd_is_link_hibern8(hba)) {
185 int ret = ufshcd_uic_hibern8_exit(hba);
188 ufshcd_set_link_active(hba);
190 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
193 * Force reset and restore. Any other actions can lead
194 * to an unrecoverable state.
196 ufshcd_set_link_off(hba);
203 static int ufs_intel_ehl_init(struct ufs_hba *hba)
205 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
206 return ufs_intel_common_init(hba);
209 static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
211 .init = ufs_intel_common_init,
212 .exit = ufs_intel_common_exit,
213 .link_startup_notify = ufs_intel_link_startup_notify,
214 .resume = ufs_intel_resume,
217 static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
219 .init = ufs_intel_ehl_init,
220 .exit = ufs_intel_common_exit,
221 .link_startup_notify = ufs_intel_link_startup_notify,
222 .resume = ufs_intel_resume,
225 #ifdef CONFIG_PM_SLEEP
227 * ufshcd_pci_suspend - suspend power management function
228 * @dev: pointer to PCI device handle
230 * Returns 0 if successful
231 * Returns non-zero otherwise
233 static int ufshcd_pci_suspend(struct device *dev)
235 return ufshcd_system_suspend(dev_get_drvdata(dev));
239 * ufshcd_pci_resume - resume power management function
240 * @dev: pointer to PCI device handle
242 * Returns 0 if successful
243 * Returns non-zero otherwise
245 static int ufshcd_pci_resume(struct device *dev)
247 return ufshcd_system_resume(dev_get_drvdata(dev));
251 * ufshcd_pci_poweroff - suspend-to-disk poweroff function
252 * @dev: pointer to PCI device handle
254 * Returns 0 if successful
255 * Returns non-zero otherwise
257 static int ufshcd_pci_poweroff(struct device *dev)
259 struct ufs_hba *hba = dev_get_drvdata(dev);
260 int spm_lvl = hba->spm_lvl;
264 * For poweroff we need to set the UFS device to PowerDown mode.
265 * Force spm_lvl to ensure that.
268 ret = ufshcd_system_suspend(hba);
269 hba->spm_lvl = spm_lvl;
273 #endif /* !CONFIG_PM_SLEEP */
276 static int ufshcd_pci_runtime_suspend(struct device *dev)
278 return ufshcd_runtime_suspend(dev_get_drvdata(dev));
280 static int ufshcd_pci_runtime_resume(struct device *dev)
282 return ufshcd_runtime_resume(dev_get_drvdata(dev));
284 static int ufshcd_pci_runtime_idle(struct device *dev)
286 return ufshcd_runtime_idle(dev_get_drvdata(dev));
288 #endif /* !CONFIG_PM */
291 * ufshcd_pci_shutdown - main function to put the controller in reset state
292 * @pdev: pointer to PCI device handle
294 static void ufshcd_pci_shutdown(struct pci_dev *pdev)
296 ufshcd_shutdown((struct ufs_hba *)pci_get_drvdata(pdev));
300 * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
301 * data structure memory
302 * @pdev: pointer to PCI handle
304 static void ufshcd_pci_remove(struct pci_dev *pdev)
306 struct ufs_hba *hba = pci_get_drvdata(pdev);
308 pm_runtime_forbid(&pdev->dev);
309 pm_runtime_get_noresume(&pdev->dev);
311 ufshcd_dealloc_host(hba);
315 * ufshcd_pci_probe - probe routine of the driver
316 * @pdev: pointer to PCI device handle
319 * Returns 0 on success, non-zero value on failure
322 ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
325 void __iomem *mmio_base;
328 err = pcim_enable_device(pdev);
330 dev_err(&pdev->dev, "pcim_enable_device failed\n");
334 pci_set_master(pdev);
336 err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD);
338 dev_err(&pdev->dev, "request and iomap failed\n");
342 mmio_base = pcim_iomap_table(pdev)[0];
344 err = ufshcd_alloc_host(&pdev->dev, &hba);
346 dev_err(&pdev->dev, "Allocation failed\n");
350 hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
352 err = ufshcd_init(hba, mmio_base, pdev->irq);
354 dev_err(&pdev->dev, "Initialization failed\n");
355 ufshcd_dealloc_host(hba);
359 pm_runtime_put_noidle(&pdev->dev);
360 pm_runtime_allow(&pdev->dev);
365 static const struct dev_pm_ops ufshcd_pci_pm_ops = {
366 #ifdef CONFIG_PM_SLEEP
367 .suspend = ufshcd_pci_suspend,
368 .resume = ufshcd_pci_resume,
369 .freeze = ufshcd_pci_suspend,
370 .thaw = ufshcd_pci_resume,
371 .poweroff = ufshcd_pci_poweroff,
372 .restore = ufshcd_pci_resume,
374 SET_RUNTIME_PM_OPS(ufshcd_pci_runtime_suspend,
375 ufshcd_pci_runtime_resume,
376 ufshcd_pci_runtime_idle)
379 static const struct pci_device_id ufshcd_pci_tbl[] = {
380 { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
381 { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
382 { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
383 { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
384 { } /* terminate list */
387 MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
389 static struct pci_driver ufshcd_pci_driver = {
391 .id_table = ufshcd_pci_tbl,
392 .probe = ufshcd_pci_probe,
393 .remove = ufshcd_pci_remove,
394 .shutdown = ufshcd_pci_shutdown,
396 .pm = &ufshcd_pci_pm_ops
400 module_pci_driver(ufshcd_pci_driver);
402 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
403 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
404 MODULE_DESCRIPTION("UFS host controller PCI glue driver");
405 MODULE_LICENSE("GPL");
406 MODULE_VERSION(UFSHCD_DRIVER_VERSION);