1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
6 #include <linux/acpi.h>
7 #include <linux/time.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/reset-controller.h>
13 #include <linux/devfreq.h>
16 #include "ufshcd-pltfrm.h"
20 #include "ufs_quirks.h"
21 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
22 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
40 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
48 return container_of(rcd, struct ufs_qcom_host, rcdev);
51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
52 const char *prefix, void *priv)
54 ufshcd_dump_regs(hba, offset, len * 4, prefix);
57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
61 err = ufshcd_dme_get(hba,
62 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
64 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
70 static int ufs_qcom_host_clk_get(struct device *dev,
71 const char *name, struct clk **clk_out, bool optional)
76 clk = devm_clk_get(dev, name);
84 if (optional && err == -ENOENT) {
89 if (err != -EPROBE_DEFER)
90 dev_err(dev, "failed to get %s err %d\n", name, err);
95 static int ufs_qcom_host_clk_enable(struct device *dev,
96 const char *name, struct clk *clk)
100 err = clk_prepare_enable(clk);
102 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
109 if (!host->is_lane_clks_enabled)
112 clk_disable_unprepare(host->tx_l1_sync_clk);
113 clk_disable_unprepare(host->tx_l0_sync_clk);
114 clk_disable_unprepare(host->rx_l1_sync_clk);
115 clk_disable_unprepare(host->rx_l0_sync_clk);
117 host->is_lane_clks_enabled = false;
120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
123 struct device *dev = host->hba->dev;
125 if (host->is_lane_clks_enabled)
128 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
129 host->rx_l0_sync_clk);
133 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
134 host->tx_l0_sync_clk);
138 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
139 host->rx_l1_sync_clk);
143 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
144 host->tx_l1_sync_clk);
148 host->is_lane_clks_enabled = true;
152 clk_disable_unprepare(host->rx_l1_sync_clk);
154 clk_disable_unprepare(host->tx_l0_sync_clk);
156 clk_disable_unprepare(host->rx_l0_sync_clk);
161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
164 struct device *dev = host->hba->dev;
166 if (has_acpi_companion(dev))
169 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
170 &host->rx_l0_sync_clk, false);
174 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
175 &host->tx_l0_sync_clk, false);
179 /* In case of single lane per direction, don't read lane1 clocks */
180 if (host->hba->lanes_per_direction > 1) {
181 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
182 &host->rx_l1_sync_clk, false);
186 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
187 &host->tx_l1_sync_clk, true);
193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
197 return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
204 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
207 err = ufshcd_dme_get(hba,
208 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
209 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
211 if (err || tx_fsm_val == TX_FSM_HIBERN8)
214 /* sleep for max. 200us */
215 usleep_range(100, 200);
216 } while (time_before(jiffies, timeout));
219 * we might have scheduled out for long during polling so
220 * check the state again.
222 if (time_after(jiffies, timeout))
223 err = ufshcd_dme_get(hba,
224 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
225 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
229 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
231 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
233 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
242 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
243 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
245 /* make sure above configuration is applied before we return */
250 * ufs_qcom_host_reset - reset host controller and PHY
252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
255 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
256 bool reenable_intr = false;
258 if (!host->core_reset) {
259 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
263 reenable_intr = hba->is_irq_enabled;
264 disable_irq(hba->irq);
265 hba->is_irq_enabled = false;
267 ret = reset_control_assert(host->core_reset);
269 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
275 * The hardware requirement for delay between assert/deassert
276 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
277 * ~125us (4/32768). To be on the safe side add 200us delay.
279 usleep_range(200, 210);
281 ret = reset_control_deassert(host->core_reset);
283 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
286 usleep_range(1000, 1100);
289 enable_irq(hba->irq);
290 hba->is_irq_enabled = true;
297 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
299 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
300 struct phy *phy = host->generic_phy;
302 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
305 /* Reset UFS Host Controller and PHY */
306 ret = ufs_qcom_host_reset(hba);
308 dev_warn(hba->dev, "%s: host reset returned %d\n",
312 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
314 /* phy initialization - calibrate the phy */
317 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
322 /* power on phy - start serdes and phy's power and clocks */
323 ret = phy_power_on(phy);
325 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
327 goto out_disable_phy;
330 ufs_qcom_select_unipro_mode(host);
341 * The UTP controller has a number of internal clock gating cells (CGCs).
342 * Internal hardware sub-modules within the UTP controller control the CGCs.
343 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
344 * in a specific operation, UTP controller CGCs are by default disabled and
345 * this function enables them (after every UFS link startup) to save some power
348 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
351 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
354 /* Ensure that HW clock gating is enabled before next operations */
358 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
359 enum ufs_notify_change_status status)
361 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
366 ufs_qcom_power_up_sequence(hba);
368 * The PHY PLL output is the source of tx/rx lane symbol
369 * clocks, hence, enable the lane clocks only after PHY
372 err = ufs_qcom_enable_lane_clks(host);
375 /* check if UFS PHY moved from DISABLED to HIBERN8 */
376 err = ufs_qcom_check_hibern8(hba);
377 ufs_qcom_enable_hw_clk_gating(hba);
378 ufs_qcom_ice_enable(host);
381 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
389 * Returns zero for success and non-zero in case of a failure
391 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
392 u32 hs, u32 rate, bool update_link_startup_timer)
395 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
396 struct ufs_clk_info *clki;
397 u32 core_clk_period_in_ns;
398 u32 tx_clk_cycles_per_us = 0;
399 unsigned long core_clk_rate = 0;
400 u32 core_clk_cycles_per_us = 0;
402 static u32 pwm_fr_table[][2] = {
409 static u32 hs_fr_table_rA[][2] = {
415 static u32 hs_fr_table_rB[][2] = {
422 * The Qunipro controller does not use following registers:
423 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
424 * UFS_REG_PA_LINK_STARTUP_TIMER
425 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
428 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
432 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
436 list_for_each_entry(clki, &hba->clk_list_head, list) {
437 if (!strcmp(clki->name, "core_clk"))
438 core_clk_rate = clk_get_rate(clki->clk);
441 /* If frequency is smaller than 1MHz, set to 1MHz */
442 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
443 core_clk_rate = DEFAULT_CLK_RATE_HZ;
445 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
446 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
447 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
449 * make sure above write gets applied before we return from
455 if (ufs_qcom_cap_qunipro(host))
458 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
459 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
460 core_clk_period_in_ns &= MASK_CLK_NS_REG;
465 if (rate == PA_HS_MODE_A) {
466 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
468 "%s: index %d exceeds table size %zu\n",
470 ARRAY_SIZE(hs_fr_table_rA));
473 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
474 } else if (rate == PA_HS_MODE_B) {
475 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
477 "%s: index %d exceeds table size %zu\n",
479 ARRAY_SIZE(hs_fr_table_rB));
482 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
484 dev_err(hba->dev, "%s: invalid rate = %d\n",
491 if (gear > ARRAY_SIZE(pwm_fr_table)) {
493 "%s: index %d exceeds table size %zu\n",
495 ARRAY_SIZE(pwm_fr_table));
498 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
502 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
506 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
507 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
508 /* this register 2 fields shall be written at once */
509 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
510 REG_UFS_TX_SYMBOL_CLK_NS_US);
512 * make sure above write gets applied before we return from
518 if (update_link_startup_timer) {
519 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
520 REG_UFS_PA_LINK_STARTUP_TIMER);
522 * make sure that this configuration is applied before
535 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
536 enum ufs_notify_change_status status)
539 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
543 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
545 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
551 if (ufs_qcom_cap_qunipro(host))
553 * set unipro core clock cycles to 150 & clear clock
556 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
560 * Some UFS devices (and may be host) have issues if LCC is
561 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
562 * before link startup which will make sure that both host
563 * and device TX LCC are disabled once link startup is
566 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
567 err = ufshcd_disable_host_tx_lcc(hba);
571 ufs_qcom_link_startup_post_change(hba);
581 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
583 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
585 /* reset gpio is optional */
586 if (!host->device_reset)
589 gpiod_set_value_cansleep(host->device_reset, asserted);
592 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
594 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
595 struct phy *phy = host->generic_phy;
597 if (ufs_qcom_is_link_off(hba)) {
599 * Disable the tx/rx lane symbol clocks before PHY is
600 * powered down as the PLL source should be disabled
601 * after downstream clocks are disabled.
603 ufs_qcom_disable_lane_clks(host);
606 /* reset the connected UFS device during power down */
607 ufs_qcom_device_reset_ctrl(hba, true);
609 } else if (!ufs_qcom_is_link_active(hba)) {
610 ufs_qcom_disable_lane_clks(host);
616 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
618 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
619 struct phy *phy = host->generic_phy;
622 if (ufs_qcom_is_link_off(hba)) {
623 err = phy_power_on(phy);
625 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
630 err = ufs_qcom_enable_lane_clks(host);
634 } else if (!ufs_qcom_is_link_active(hba)) {
635 err = ufs_qcom_enable_lane_clks(host);
640 return ufs_qcom_ice_resume(host);
643 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
645 if (host->dev_ref_clk_ctrl_mmio &&
646 (enable ^ host->is_dev_ref_clk_enabled)) {
647 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
650 temp |= host->dev_ref_clk_en_mask;
652 temp &= ~host->dev_ref_clk_en_mask;
655 * If we are here to disable this clock it might be immediately
656 * after entering into hibern8 in which case we need to make
657 * sure that device ref_clk is active for specific time after
661 unsigned long gating_wait;
663 gating_wait = host->hba->dev_info.clk_gating_wait_us;
668 * bRefClkGatingWaitTime defines the minimum
669 * time for which the reference clock is
670 * required by device during transition from
671 * HS-MODE to LS-MODE or HIBERN8 state. Give it
672 * more delay to be on the safe side.
675 usleep_range(gating_wait, gating_wait + 10);
679 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
682 * Make sure the write to ref_clk reaches the destination and
683 * not stored in a Write Buffer (WB).
685 readl(host->dev_ref_clk_ctrl_mmio);
688 * If we call hibern8 exit after this, we need to make sure that
689 * device ref_clk is stable for at least 1us before the hibern8
695 host->is_dev_ref_clk_enabled = enable;
699 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
700 enum ufs_notify_change_status status,
701 struct ufs_pa_layer_attr *dev_max_params,
702 struct ufs_pa_layer_attr *dev_req_params)
704 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
705 struct ufs_dev_params ufs_qcom_cap;
708 if (!dev_req_params) {
709 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
716 ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
717 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
719 if (host->hw_ver.major == 0x1) {
721 * HS-G3 operations may not reliably work on legacy QCOM
722 * UFS host controller hardware even though capability
723 * exchange during link startup phase may end up
724 * negotiating maximum supported gear as G3.
725 * Hence downgrade the maximum supported gear to HS-G2.
727 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
728 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
729 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
730 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
733 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
737 pr_err("%s: failed to determine capabilities\n",
742 /* enable the device ref clock before changing to HS mode */
743 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
744 ufshcd_is_hs_mode(dev_req_params))
745 ufs_qcom_dev_ref_clk_ctrl(host, true);
747 if (host->hw_ver.major >= 0x4) {
748 ufshcd_dme_configure_adapt(hba,
749 dev_req_params->gear_tx,
754 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
755 dev_req_params->pwr_rx,
756 dev_req_params->hs_rate, false)) {
757 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
760 * we return error code at the end of the routine,
761 * but continue to configure UFS_PHY_TX_LANE_ENABLE
762 * and bus voting as usual
767 /* cache the power mode parameters to use internally */
768 memcpy(&host->dev_req_params,
769 dev_req_params, sizeof(*dev_req_params));
771 /* disable the device ref clock if entered PWM mode */
772 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
773 !ufshcd_is_hs_mode(dev_req_params))
774 ufs_qcom_dev_ref_clk_ctrl(host, false);
784 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
787 u32 pa_vs_config_reg1;
789 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
794 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
795 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
796 (pa_vs_config_reg1 | (1 << 12)));
802 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
806 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
807 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
809 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
810 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
815 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
817 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
819 if (host->hw_ver.major == 0x1)
820 return ufshci_version(1, 1);
822 return ufshci_version(2, 0);
826 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
827 * @hba: host controller instance
829 * QCOM UFS host controller might have some non standard behaviours (quirks)
830 * than what is specified by UFSHCI specification. Advertise all such
831 * quirks to standard UFS host controller driver so standard takes them into
834 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
836 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
838 if (host->hw_ver.major == 0x01) {
839 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
840 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
841 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
843 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
844 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
846 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
849 if (host->hw_ver.major == 0x2) {
850 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
852 if (!ufs_qcom_cap_qunipro(host))
853 /* Legacy UniPro mode still need following quirks */
854 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
855 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
856 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
860 static void ufs_qcom_set_caps(struct ufs_hba *hba)
862 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
864 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
865 hba->caps |= UFSHCD_CAP_CLK_SCALING;
866 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
867 hba->caps |= UFSHCD_CAP_WB_EN;
868 hba->caps |= UFSHCD_CAP_CRYPTO;
869 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
871 if (host->hw_ver.major >= 0x2) {
872 host->caps = UFS_QCOM_CAP_QUNIPRO |
873 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
878 * ufs_qcom_setup_clocks - enables/disable clocks
879 * @hba: host controller instance
880 * @on: If true, enable clocks else disable them.
881 * @status: PRE_CHANGE or POST_CHANGE notify
883 * Returns 0 on success, non-zero on failure.
885 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
886 enum ufs_notify_change_status status)
888 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
892 * In case ufs_qcom_init() is not yet done, simply ignore.
893 * This ufs_qcom_setup_clocks() shall be called from
894 * ufs_qcom_init() after init is done.
902 if (!ufs_qcom_is_link_active(hba)) {
903 /* disable device ref_clk */
904 ufs_qcom_dev_ref_clk_ctrl(host, false);
910 /* enable the device ref clock for HS mode*/
911 if (ufshcd_is_hs_mode(&hba->pwr_info))
912 ufs_qcom_dev_ref_clk_ctrl(host, true);
921 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
923 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
925 /* Currently this code only knows about a single reset. */
927 ufs_qcom_assert_reset(host->hba);
928 /* provide 1ms delay to let the reset pulse propagate. */
929 usleep_range(1000, 1100);
934 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
936 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
938 /* Currently this code only knows about a single reset. */
940 ufs_qcom_deassert_reset(host->hba);
943 * after reset deassertion, phy will need all ref clocks,
944 * voltage, current to settle down before starting serdes.
946 usleep_range(1000, 1100);
950 static const struct reset_control_ops ufs_qcom_reset_ops = {
951 .assert = ufs_qcom_reset_assert,
952 .deassert = ufs_qcom_reset_deassert,
955 #define ANDROID_BOOT_DEV_MAX 30
956 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
959 static int __init get_android_boot_dev(char *str)
961 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
964 __setup("androidboot.bootdevice=", get_android_boot_dev);
968 * ufs_qcom_init - bind phy with controller
969 * @hba: host controller instance
971 * Binds PHY with controller and powers up PHY enabling clocks
974 * Returns -EPROBE_DEFER if binding fails, returns negative error
975 * on phy power up failure and returns zero on success.
977 static int ufs_qcom_init(struct ufs_hba *hba)
980 struct device *dev = hba->dev;
981 struct platform_device *pdev = to_platform_device(dev);
982 struct ufs_qcom_host *host;
983 struct resource *res;
984 struct ufs_clk_info *clki;
986 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
989 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
992 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
996 /* Make a two way bind between the qcom host and the hba */
998 ufshcd_set_variant(hba, host);
1000 /* Setup the reset control of HCI */
1001 host->core_reset = devm_reset_control_get(hba->dev, "rst");
1002 if (IS_ERR(host->core_reset)) {
1003 err = PTR_ERR(host->core_reset);
1004 dev_warn(dev, "Failed to get reset control %d\n", err);
1005 host->core_reset = NULL;
1009 /* Fire up the reset controller. Failure here is non-fatal. */
1010 host->rcdev.of_node = dev->of_node;
1011 host->rcdev.ops = &ufs_qcom_reset_ops;
1012 host->rcdev.owner = dev->driver->owner;
1013 host->rcdev.nr_resets = 1;
1014 err = devm_reset_controller_register(dev, &host->rcdev);
1016 dev_warn(dev, "Failed to register reset controller\n");
1021 * voting/devoting device ref_clk source is time consuming hence
1022 * skip devoting it during aggressive clock gating. This clock
1023 * will still be gated off during runtime suspend.
1025 host->generic_phy = devm_phy_get(dev, "ufsphy");
1027 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1029 * UFS driver might be probed before the phy driver does.
1030 * In that case we would like to return EPROBE_DEFER code.
1032 err = -EPROBE_DEFER;
1033 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1035 goto out_variant_clear;
1036 } else if (IS_ERR(host->generic_phy)) {
1037 if (has_acpi_companion(dev)) {
1038 host->generic_phy = NULL;
1040 err = PTR_ERR(host->generic_phy);
1041 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1042 goto out_variant_clear;
1046 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1048 if (IS_ERR(host->device_reset)) {
1049 err = PTR_ERR(host->device_reset);
1050 if (err != -EPROBE_DEFER)
1051 dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1052 goto out_variant_clear;
1055 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1056 &host->hw_ver.minor, &host->hw_ver.step);
1059 * for newer controllers, device reference clock control bit has
1060 * moved inside UFS controller register address space itself.
1062 if (host->hw_ver.major >= 0x02) {
1063 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1064 host->dev_ref_clk_en_mask = BIT(26);
1066 /* "dev_ref_clk_ctrl_mem" is optional resource */
1067 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1068 "dev_ref_clk_ctrl_mem");
1070 host->dev_ref_clk_ctrl_mmio =
1071 devm_ioremap_resource(dev, res);
1072 if (IS_ERR(host->dev_ref_clk_ctrl_mmio))
1073 host->dev_ref_clk_ctrl_mmio = NULL;
1074 host->dev_ref_clk_en_mask = BIT(5);
1078 list_for_each_entry(clki, &hba->clk_list_head, list) {
1079 if (!strcmp(clki->name, "core_clk_unipro"))
1080 clki->keep_link_active = true;
1083 err = ufs_qcom_init_lane_clks(host);
1085 goto out_variant_clear;
1087 ufs_qcom_set_caps(hba);
1088 ufs_qcom_advertise_quirks(hba);
1090 err = ufs_qcom_ice_init(host);
1092 goto out_variant_clear;
1094 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1096 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1097 ufs_qcom_hosts[hba->dev->id] = host;
1099 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1100 ufs_qcom_get_default_testbus_cfg(host);
1101 err = ufs_qcom_testbus_config(host);
1103 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1111 ufshcd_set_variant(hba, NULL);
1116 static void ufs_qcom_exit(struct ufs_hba *hba)
1118 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1120 ufs_qcom_disable_lane_clks(host);
1121 phy_power_off(host->generic_phy);
1122 phy_exit(host->generic_phy);
1125 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1129 u32 core_clk_ctrl_reg;
1131 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1134 err = ufshcd_dme_get(hba,
1135 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1136 &core_clk_ctrl_reg);
1140 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1141 core_clk_ctrl_reg |= clk_cycles;
1143 /* Clear CORE_CLK_DIV_EN */
1144 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1146 err = ufshcd_dme_set(hba,
1147 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1153 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1155 /* nothing to do as of now */
1159 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1161 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1163 if (!ufs_qcom_cap_qunipro(host))
1166 /* set unipro core clock cycles to 150 and clear clock divider */
1167 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1170 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1172 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1174 u32 core_clk_ctrl_reg;
1176 if (!ufs_qcom_cap_qunipro(host))
1179 err = ufshcd_dme_get(hba,
1180 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1181 &core_clk_ctrl_reg);
1183 /* make sure CORE_CLK_DIV_EN is cleared */
1185 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1186 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1187 err = ufshcd_dme_set(hba,
1188 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1195 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1197 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1199 if (!ufs_qcom_cap_qunipro(host))
1202 /* set unipro core clock cycles to 75 and clear clock divider */
1203 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1206 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1207 bool scale_up, enum ufs_notify_change_status status)
1209 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1210 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1213 if (status == PRE_CHANGE) {
1215 err = ufs_qcom_clk_scale_up_pre_change(hba);
1217 err = ufs_qcom_clk_scale_down_pre_change(hba);
1220 err = ufs_qcom_clk_scale_up_post_change(hba);
1222 err = ufs_qcom_clk_scale_down_post_change(hba);
1224 if (err || !dev_req_params)
1227 ufs_qcom_cfg_timers(hba,
1228 dev_req_params->gear_rx,
1229 dev_req_params->pwr_rx,
1230 dev_req_params->hs_rate,
1238 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1239 void *priv, void (*print_fn)(struct ufs_hba *hba,
1240 int offset, int num_regs, const char *str, void *priv))
1243 struct ufs_qcom_host *host;
1245 if (unlikely(!hba)) {
1246 pr_err("%s: hba is NULL\n", __func__);
1249 if (unlikely(!print_fn)) {
1250 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1254 host = ufshcd_get_variant(hba);
1255 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1258 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1259 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1261 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1262 reg |= UTP_DBG_RAMS_EN;
1263 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1265 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1266 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1268 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1269 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1271 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1272 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1274 /* clear bit 17 - UTP_DBG_RAMS_EN */
1275 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1277 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1278 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1280 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1281 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1283 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1284 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1286 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1287 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1289 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1290 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1292 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1293 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1295 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1296 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1299 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1301 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1302 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1303 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1304 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1306 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1307 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1311 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1313 /* provide a legal default configuration */
1314 host->testbus.select_major = TSTBUS_UNIPRO;
1315 host->testbus.select_minor = 37;
1318 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1320 if (host->testbus.select_major >= TSTBUS_MAX) {
1321 dev_err(host->hba->dev,
1322 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1323 __func__, host->testbus.select_major);
1330 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1334 u32 mask = TEST_BUS_SUB_SEL_MASK;
1339 if (!ufs_qcom_testbus_cfg_is_ok(host))
1342 switch (host->testbus.select_major) {
1344 reg = UFS_TEST_BUS_CTRL_0;
1348 reg = UFS_TEST_BUS_CTRL_0;
1352 reg = UFS_TEST_BUS_CTRL_0;
1356 reg = UFS_TEST_BUS_CTRL_0;
1360 reg = UFS_TEST_BUS_CTRL_1;
1364 reg = UFS_TEST_BUS_CTRL_1;
1368 reg = UFS_TEST_BUS_CTRL_1;
1372 reg = UFS_TEST_BUS_CTRL_1;
1375 case TSTBUS_WRAPPER:
1376 reg = UFS_TEST_BUS_CTRL_2;
1379 case TSTBUS_COMBINED:
1380 reg = UFS_TEST_BUS_CTRL_2;
1383 case TSTBUS_UTP_HCI:
1384 reg = UFS_TEST_BUS_CTRL_2;
1388 reg = UFS_UNIPRO_CFG;
1393 * No need for a default case, since
1394 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1399 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1400 (u32)host->testbus.select_major << 19,
1402 ufshcd_rmwl(host->hba, mask,
1403 (u32)host->testbus.select_minor << offset,
1405 ufs_qcom_enable_test_bus(host);
1407 * Make sure the test bus configuration is
1408 * committed before returning.
1415 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1417 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1418 "HCI Vendor Specific Registers ");
1420 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1424 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1425 * @hba: per-adapter instance
1427 * Toggles the (optional) reset line to reset the attached device.
1429 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1431 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1433 /* reset gpio is optional */
1434 if (!host->device_reset)
1438 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1439 * be on the safe side.
1441 ufs_qcom_device_reset_ctrl(hba, true);
1442 usleep_range(10, 15);
1444 ufs_qcom_device_reset_ctrl(hba, false);
1445 usleep_range(10, 15);
1450 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1451 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1452 struct devfreq_dev_profile *p,
1455 static struct devfreq_simple_ondemand_data *d;
1460 d = (struct devfreq_simple_ondemand_data *)data;
1462 d->upthreshold = 70;
1463 d->downdifferential = 5;
1466 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1467 struct devfreq_dev_profile *p,
1474 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1476 * The variant operations configure the necessary controller and PHY
1477 * handshake during initialization.
1479 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1481 .init = ufs_qcom_init,
1482 .exit = ufs_qcom_exit,
1483 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1484 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1485 .setup_clocks = ufs_qcom_setup_clocks,
1486 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1487 .link_startup_notify = ufs_qcom_link_startup_notify,
1488 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1489 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1490 .suspend = ufs_qcom_suspend,
1491 .resume = ufs_qcom_resume,
1492 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1493 .device_reset = ufs_qcom_device_reset,
1494 .config_scaling_param = ufs_qcom_config_scaling_param,
1495 .program_key = ufs_qcom_ice_program_key,
1499 * ufs_qcom_probe - probe routine of the driver
1500 * @pdev: pointer to Platform device handle
1502 * Return zero for success and non-zero for failure
1504 static int ufs_qcom_probe(struct platform_device *pdev)
1507 struct device *dev = &pdev->dev;
1509 /* Perform generic probe */
1510 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1512 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1518 * ufs_qcom_remove - set driver_data of the device to NULL
1519 * @pdev: pointer to platform device handle
1523 static int ufs_qcom_remove(struct platform_device *pdev)
1525 struct ufs_hba *hba = platform_get_drvdata(pdev);
1527 pm_runtime_get_sync(&(pdev)->dev);
1532 static const struct of_device_id ufs_qcom_of_match[] = {
1533 { .compatible = "qcom,ufshc"},
1536 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1539 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1543 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1546 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1547 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1548 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1549 .prepare = ufshcd_suspend_prepare,
1550 .complete = ufshcd_resume_complete,
1553 static struct platform_driver ufs_qcom_pltform = {
1554 .probe = ufs_qcom_probe,
1555 .remove = ufs_qcom_remove,
1556 .shutdown = ufshcd_pltfrm_shutdown,
1558 .name = "ufshcd-qcom",
1559 .pm = &ufs_qcom_pm_ops,
1560 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1561 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1564 module_platform_driver(ufs_qcom_pltform);
1566 MODULE_LICENSE("GPL v2");