2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/time.h>
17 #include <linux/platform_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-qcom-ufs.h>
22 #include "ufshcd-pltfrm.h"
26 #include "ufs_quirks.h"
27 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN \
28 (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
46 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
48 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
49 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
50 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
53 static void ufs_qcom_dump_regs(struct ufs_hba *hba, int offset, int len,
56 print_hex_dump(KERN_ERR, prefix,
57 len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,
58 16, 4, (void __force *)hba->mmio_base + offset,
62 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
63 char *prefix, void *priv)
65 ufs_qcom_dump_regs(hba, offset, len, prefix);
68 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
72 err = ufshcd_dme_get(hba,
73 UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
75 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
81 static int ufs_qcom_host_clk_get(struct device *dev,
82 const char *name, struct clk **clk_out)
87 clk = devm_clk_get(dev, name);
90 dev_err(dev, "%s: failed to get %s err %d",
99 static int ufs_qcom_host_clk_enable(struct device *dev,
100 const char *name, struct clk *clk)
104 err = clk_prepare_enable(clk);
106 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
111 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
113 if (!host->is_lane_clks_enabled)
116 if (host->hba->lanes_per_direction > 1)
117 clk_disable_unprepare(host->tx_l1_sync_clk);
118 clk_disable_unprepare(host->tx_l0_sync_clk);
119 if (host->hba->lanes_per_direction > 1)
120 clk_disable_unprepare(host->rx_l1_sync_clk);
121 clk_disable_unprepare(host->rx_l0_sync_clk);
123 host->is_lane_clks_enabled = false;
126 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
129 struct device *dev = host->hba->dev;
131 if (host->is_lane_clks_enabled)
134 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
135 host->rx_l0_sync_clk);
139 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
140 host->tx_l0_sync_clk);
144 if (host->hba->lanes_per_direction > 1) {
145 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
146 host->rx_l1_sync_clk);
150 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
151 host->tx_l1_sync_clk);
156 host->is_lane_clks_enabled = true;
160 if (host->hba->lanes_per_direction > 1)
161 clk_disable_unprepare(host->rx_l1_sync_clk);
163 clk_disable_unprepare(host->tx_l0_sync_clk);
165 clk_disable_unprepare(host->rx_l0_sync_clk);
170 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
173 struct device *dev = host->hba->dev;
175 err = ufs_qcom_host_clk_get(dev,
176 "rx_lane0_sync_clk", &host->rx_l0_sync_clk);
180 err = ufs_qcom_host_clk_get(dev,
181 "tx_lane0_sync_clk", &host->tx_l0_sync_clk);
185 /* In case of single lane per direction, don't read lane1 clocks */
186 if (host->hba->lanes_per_direction > 1) {
187 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
188 &host->rx_l1_sync_clk);
192 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
193 &host->tx_l1_sync_clk);
199 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
201 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
202 struct phy *phy = host->generic_phy;
206 err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
210 err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
212 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
219 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
223 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
226 err = ufshcd_dme_get(hba,
227 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
228 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
230 if (err || tx_fsm_val == TX_FSM_HIBERN8)
233 /* sleep for max. 200us */
234 usleep_range(100, 200);
235 } while (time_before(jiffies, timeout));
238 * we might have scheduled out for long during polling so
239 * check the state again.
241 if (time_after(jiffies, timeout))
242 err = ufshcd_dme_get(hba,
243 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
244 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
248 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
250 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
252 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
259 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
261 ufshcd_rmwl(host->hba, QUNIPRO_SEL,
262 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
264 /* make sure above configuration is applied before we return */
268 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
270 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
271 struct phy *phy = host->generic_phy;
273 bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
276 /* Assert PHY reset and apply PHY calibration values */
277 ufs_qcom_assert_reset(hba);
278 /* provide 1ms delay to let the reset pulse propagate */
279 usleep_range(1000, 1100);
281 ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B);
284 dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n",
289 /* De-assert PHY reset and start serdes */
290 ufs_qcom_deassert_reset(hba);
293 * after reset deassertion, phy will need all ref clocks,
294 * voltage, current to settle down before starting serdes.
296 usleep_range(1000, 1100);
297 ret = ufs_qcom_phy_start_serdes(phy);
299 dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, ret = %d\n",
304 ret = ufs_qcom_phy_is_pcs_ready(phy);
307 "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n",
310 ufs_qcom_select_unipro_mode(host);
317 * The UTP controller has a number of internal clock gating cells (CGCs).
318 * Internal hardware sub-modules within the UTP controller control the CGCs.
319 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
320 * in a specific operation, UTP controller CGCs are by default disabled and
321 * this function enables them (after every UFS link startup) to save some power
324 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
327 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
330 /* Ensure that HW clock gating is enabled before next operations */
334 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
335 enum ufs_notify_change_status status)
337 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
342 ufs_qcom_power_up_sequence(hba);
344 * The PHY PLL output is the source of tx/rx lane symbol
345 * clocks, hence, enable the lane clocks only after PHY
348 err = ufs_qcom_enable_lane_clks(host);
351 /* check if UFS PHY moved from DISABLED to HIBERN8 */
352 err = ufs_qcom_check_hibern8(hba);
353 ufs_qcom_enable_hw_clk_gating(hba);
357 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
365 * Returns zero for success and non-zero in case of a failure
367 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
368 u32 hs, u32 rate, bool update_link_startup_timer)
371 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
372 struct ufs_clk_info *clki;
373 u32 core_clk_period_in_ns;
374 u32 tx_clk_cycles_per_us = 0;
375 unsigned long core_clk_rate = 0;
376 u32 core_clk_cycles_per_us = 0;
378 static u32 pwm_fr_table[][2] = {
385 static u32 hs_fr_table_rA[][2] = {
391 static u32 hs_fr_table_rB[][2] = {
398 * The Qunipro controller does not use following registers:
399 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
400 * UFS_REG_PA_LINK_STARTUP_TIMER
401 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
404 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
408 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
412 list_for_each_entry(clki, &hba->clk_list_head, list) {
413 if (!strcmp(clki->name, "core_clk"))
414 core_clk_rate = clk_get_rate(clki->clk);
417 /* If frequency is smaller than 1MHz, set to 1MHz */
418 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
419 core_clk_rate = DEFAULT_CLK_RATE_HZ;
421 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
422 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
423 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
425 * make sure above write gets applied before we return from
431 if (ufs_qcom_cap_qunipro(host))
434 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
435 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
436 core_clk_period_in_ns &= MASK_CLK_NS_REG;
441 if (rate == PA_HS_MODE_A) {
442 if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
444 "%s: index %d exceeds table size %zu\n",
446 ARRAY_SIZE(hs_fr_table_rA));
449 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
450 } else if (rate == PA_HS_MODE_B) {
451 if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
453 "%s: index %d exceeds table size %zu\n",
455 ARRAY_SIZE(hs_fr_table_rB));
458 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
460 dev_err(hba->dev, "%s: invalid rate = %d\n",
467 if (gear > ARRAY_SIZE(pwm_fr_table)) {
469 "%s: index %d exceeds table size %zu\n",
471 ARRAY_SIZE(pwm_fr_table));
474 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
478 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
482 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
483 (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
484 /* this register 2 fields shall be written at once */
485 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
486 REG_UFS_TX_SYMBOL_CLK_NS_US);
488 * make sure above write gets applied before we return from
494 if (update_link_startup_timer) {
495 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
496 REG_UFS_PA_LINK_STARTUP_TIMER);
498 * make sure that this configuration is applied before
511 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
512 enum ufs_notify_change_status status)
515 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
519 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
521 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
527 if (ufs_qcom_cap_qunipro(host))
529 * set unipro core clock cycles to 150 & clear clock
532 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
536 * Some UFS devices (and may be host) have issues if LCC is
537 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
538 * before link startup which will make sure that both host
539 * and device TX LCC are disabled once link startup is
542 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
543 err = ufshcd_dme_set(hba,
544 UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
549 ufs_qcom_link_startup_post_change(hba);
559 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
561 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
562 struct phy *phy = host->generic_phy;
565 if (ufs_qcom_is_link_off(hba)) {
567 * Disable the tx/rx lane symbol clocks before PHY is
568 * powered down as the PLL source should be disabled
569 * after downstream clocks are disabled.
571 ufs_qcom_disable_lane_clks(host);
574 /* Assert PHY soft reset */
575 ufs_qcom_assert_reset(hba);
580 * If UniPro link is not active, PHY ref_clk, main PHY analog power
581 * rail and low noise analog power rail for PLL can be switched off.
583 if (!ufs_qcom_is_link_active(hba)) {
584 ufs_qcom_disable_lane_clks(host);
592 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
594 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
595 struct phy *phy = host->generic_phy;
598 err = phy_power_on(phy);
600 dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
605 err = ufs_qcom_enable_lane_clks(host);
609 hba->is_sys_suspended = false;
615 struct ufs_qcom_dev_params {
616 u32 pwm_rx_gear; /* pwm rx gear to work in */
617 u32 pwm_tx_gear; /* pwm tx gear to work in */
618 u32 hs_rx_gear; /* hs rx gear to work in */
619 u32 hs_tx_gear; /* hs tx gear to work in */
620 u32 rx_lanes; /* number of rx lanes */
621 u32 tx_lanes; /* number of tx lanes */
622 u32 rx_pwr_pwm; /* rx pwm working pwr */
623 u32 tx_pwr_pwm; /* tx pwm working pwr */
624 u32 rx_pwr_hs; /* rx hs working pwr */
625 u32 tx_pwr_hs; /* tx hs working pwr */
626 u32 hs_rate; /* rate A/B to work in HS */
627 u32 desired_working_mode;
630 static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
631 struct ufs_pa_layer_attr *dev_max,
632 struct ufs_pa_layer_attr *agreed_pwr)
636 bool is_dev_sup_hs = false;
637 bool is_qcom_max_hs = false;
639 if (dev_max->pwr_rx == FAST_MODE)
640 is_dev_sup_hs = true;
642 if (qcom_param->desired_working_mode == FAST) {
643 is_qcom_max_hs = true;
644 min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
645 qcom_param->hs_tx_gear);
647 min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
648 qcom_param->pwm_tx_gear);
652 * device doesn't support HS but qcom_param->desired_working_mode is
653 * HS, thus device and qcom_param don't agree
655 if (!is_dev_sup_hs && is_qcom_max_hs) {
656 pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
659 } else if (is_dev_sup_hs && is_qcom_max_hs) {
661 * since device supports HS, it supports FAST_MODE.
662 * since qcom_param->desired_working_mode is also HS
663 * then final decision (FAST/FASTAUTO) is done according
664 * to qcom_params as it is the restricting factor
666 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
667 qcom_param->rx_pwr_hs;
670 * here qcom_param->desired_working_mode is PWM.
671 * it doesn't matter whether device supports HS or PWM,
672 * in both cases qcom_param->desired_working_mode will
675 agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
676 qcom_param->rx_pwr_pwm;
680 * we would like tx to work in the minimum number of lanes
681 * between device capability and vendor preferences.
682 * the same decision will be made for rx
684 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
685 qcom_param->tx_lanes);
686 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
687 qcom_param->rx_lanes);
689 /* device maximum gear is the minimum between device rx and tx gears */
690 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
693 * if both device capabilities and vendor pre-defined preferences are
694 * both HS or both PWM then set the minimum gear to be the chosen
696 * if one is PWM and one is HS then the one that is PWM get to decide
697 * what is the gear, as it is the one that also decided previously what
698 * pwr the device will be configured to.
700 if ((is_dev_sup_hs && is_qcom_max_hs) ||
701 (!is_dev_sup_hs && !is_qcom_max_hs))
702 agreed_pwr->gear_rx = agreed_pwr->gear_tx =
703 min_t(u32, min_dev_gear, min_qcom_gear);
704 else if (!is_dev_sup_hs)
705 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
707 agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
709 agreed_pwr->hs_rate = qcom_param->hs_rate;
713 #ifdef CONFIG_MSM_BUS_SCALING
714 static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
715 const char *speed_mode)
717 struct device *dev = host->hba->dev;
718 struct device_node *np = dev->of_node;
720 const char *key = "qcom,bus-vector-names";
727 if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
728 err = of_property_match_string(np, key, "MAX");
730 err = of_property_match_string(np, key, speed_mode);
734 dev_err(dev, "%s: Invalid %s mode %d\n",
735 __func__, speed_mode, err);
739 static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
741 int gear = max_t(u32, p->gear_rx, p->gear_tx);
742 int lanes = max_t(u32, p->lane_rx, p->lane_tx);
745 /* default to PWM Gear 1, Lane 1 if power mode is not initialized */
752 if (!p->pwr_rx && !p->pwr_tx) {
754 snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
755 } else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
756 p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
758 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
759 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
762 snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
767 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
771 if (vote != host->bus_vote.curr_vote) {
772 err = msm_bus_scale_client_update_request(
773 host->bus_vote.client_handle, vote);
775 dev_err(host->hba->dev,
776 "%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n",
777 __func__, host->bus_vote.client_handle,
782 host->bus_vote.curr_vote = vote;
788 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
792 char mode[BUS_VECTOR_NAME_LEN];
794 ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
796 vote = ufs_qcom_get_bus_vote(host, mode);
798 err = ufs_qcom_set_bus_vote(host, vote);
803 dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
805 host->bus_vote.saved_vote = vote;
810 show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
813 struct ufs_hba *hba = dev_get_drvdata(dev);
814 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
816 return snprintf(buf, PAGE_SIZE, "%u\n",
817 host->bus_vote.is_max_bw_needed);
821 store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
822 const char *buf, size_t count)
824 struct ufs_hba *hba = dev_get_drvdata(dev);
825 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
828 if (!kstrtou32(buf, 0, &value)) {
829 host->bus_vote.is_max_bw_needed = !!value;
830 ufs_qcom_update_bus_bw_vote(host);
836 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
839 struct msm_bus_scale_pdata *bus_pdata;
840 struct device *dev = host->hba->dev;
841 struct platform_device *pdev = to_platform_device(dev);
842 struct device_node *np = dev->of_node;
844 bus_pdata = msm_bus_cl_get_pdata(pdev);
846 dev_err(dev, "%s: failed to get bus vectors\n", __func__);
851 err = of_property_count_strings(np, "qcom,bus-vector-names");
852 if (err < 0 || err != bus_pdata->num_usecases) {
853 dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
858 host->bus_vote.client_handle = msm_bus_scale_register_client(bus_pdata);
859 if (!host->bus_vote.client_handle) {
860 dev_err(dev, "%s: msm_bus_scale_register_client failed\n",
866 /* cache the vote index for minimum and maximum bandwidth */
867 host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
868 host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
870 host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
871 host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
872 sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
873 host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
874 host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
875 err = device_create_file(dev, &host->bus_vote.max_bus_bw);
879 #else /* CONFIG_MSM_BUS_SCALING */
880 static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
885 static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
890 static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
894 #endif /* CONFIG_MSM_BUS_SCALING */
896 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
898 if (host->dev_ref_clk_ctrl_mmio &&
899 (enable ^ host->is_dev_ref_clk_enabled)) {
900 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
903 temp |= host->dev_ref_clk_en_mask;
905 temp &= ~host->dev_ref_clk_en_mask;
908 * If we are here to disable this clock it might be immediately
909 * after entering into hibern8 in which case we need to make
910 * sure that device ref_clk is active at least 1us after the
916 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
919 * Make sure the write to ref_clk reaches the destination and
920 * not stored in a Write Buffer (WB).
922 readl(host->dev_ref_clk_ctrl_mmio);
925 * If we call hibern8 exit after this, we need to make sure that
926 * device ref_clk is stable for at least 1us before the hibern8
932 host->is_dev_ref_clk_enabled = enable;
936 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
937 enum ufs_notify_change_status status,
938 struct ufs_pa_layer_attr *dev_max_params,
939 struct ufs_pa_layer_attr *dev_req_params)
942 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
943 struct phy *phy = host->generic_phy;
944 struct ufs_qcom_dev_params ufs_qcom_cap;
948 if (!dev_req_params) {
949 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
956 ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
957 ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
958 ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
959 ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
960 ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
961 ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
962 ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
963 ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
964 ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
965 ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
966 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
967 ufs_qcom_cap.desired_working_mode =
968 UFS_QCOM_LIMIT_DESIRED_MODE;
970 if (host->hw_ver.major == 0x1) {
972 * HS-G3 operations may not reliably work on legacy QCOM
973 * UFS host controller hardware even though capability
974 * exchange during link startup phase may end up
975 * negotiating maximum supported gear as G3.
976 * Hence downgrade the maximum supported gear to HS-G2.
978 if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
979 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
980 if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
981 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
984 ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
988 pr_err("%s: failed to determine capabilities\n",
993 /* enable the device ref clock before changing to HS mode */
994 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
995 ufshcd_is_hs_mode(dev_req_params))
996 ufs_qcom_dev_ref_clk_ctrl(host, true);
999 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
1000 dev_req_params->pwr_rx,
1001 dev_req_params->hs_rate, false)) {
1002 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
1005 * we return error code at the end of the routine,
1006 * but continue to configure UFS_PHY_TX_LANE_ENABLE
1007 * and bus voting as usual
1012 val = ~(MAX_U32 << dev_req_params->lane_tx);
1013 res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
1015 dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
1020 /* cache the power mode parameters to use internally */
1021 memcpy(&host->dev_req_params,
1022 dev_req_params, sizeof(*dev_req_params));
1023 ufs_qcom_update_bus_bw_vote(host);
1025 /* disable the device ref clock if entered PWM mode */
1026 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
1027 !ufshcd_is_hs_mode(dev_req_params))
1028 ufs_qcom_dev_ref_clk_ctrl(host, false);
1038 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
1041 u32 pa_vs_config_reg1;
1043 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1044 &pa_vs_config_reg1);
1048 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
1049 err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
1050 (pa_vs_config_reg1 | (1 << 12)));
1056 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
1060 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
1061 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
1066 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
1068 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1070 if (host->hw_ver.major == 0x1)
1071 return UFSHCI_VERSION_11;
1073 return UFSHCI_VERSION_20;
1077 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1078 * @hba: host controller instance
1080 * QCOM UFS host controller might have some non standard behaviours (quirks)
1081 * than what is specified by UFSHCI specification. Advertise all such
1082 * quirks to standard UFS host controller driver so standard takes them into
1085 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
1087 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1089 if (host->hw_ver.major == 0x01) {
1090 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1091 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
1092 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
1094 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
1095 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
1097 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
1100 if (host->hw_ver.major == 0x2) {
1101 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
1103 if (!ufs_qcom_cap_qunipro(host))
1104 /* Legacy UniPro mode still need following quirks */
1105 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
1106 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
1107 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
1111 static void ufs_qcom_set_caps(struct ufs_hba *hba)
1113 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1115 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1116 hba->caps |= UFSHCD_CAP_CLK_SCALING;
1117 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1119 if (host->hw_ver.major >= 0x2) {
1120 host->caps = UFS_QCOM_CAP_QUNIPRO |
1121 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
1126 * ufs_qcom_setup_clocks - enables/disable clocks
1127 * @hba: host controller instance
1128 * @on: If true, enable clocks else disable them.
1129 * @status: PRE_CHANGE or POST_CHANGE notify
1131 * Returns 0 on success, non-zero on failure.
1133 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
1134 enum ufs_notify_change_status status)
1136 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1141 * In case ufs_qcom_init() is not yet done, simply ignore.
1142 * This ufs_qcom_setup_clocks() shall be called from
1143 * ufs_qcom_init() after init is done.
1148 if (on && (status == POST_CHANGE)) {
1149 phy_power_on(host->generic_phy);
1151 /* enable the device ref clock for HS mode*/
1152 if (ufshcd_is_hs_mode(&hba->pwr_info))
1153 ufs_qcom_dev_ref_clk_ctrl(host, true);
1154 vote = host->bus_vote.saved_vote;
1155 if (vote == host->bus_vote.min_bw_vote)
1156 ufs_qcom_update_bus_bw_vote(host);
1158 } else if (!on && (status == PRE_CHANGE)) {
1159 if (!ufs_qcom_is_link_active(hba)) {
1160 /* disable device ref_clk */
1161 ufs_qcom_dev_ref_clk_ctrl(host, false);
1163 /* powering off PHY during aggressive clk gating */
1164 phy_power_off(host->generic_phy);
1167 vote = host->bus_vote.min_bw_vote;
1170 err = ufs_qcom_set_bus_vote(host, vote);
1172 dev_err(hba->dev, "%s: set bus vote failed %d\n",
1178 #define ANDROID_BOOT_DEV_MAX 30
1179 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
1182 static int __init get_android_boot_dev(char *str)
1184 strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
1187 __setup("androidboot.bootdevice=", get_android_boot_dev);
1191 * ufs_qcom_init - bind phy with controller
1192 * @hba: host controller instance
1194 * Binds PHY with controller and powers up PHY enabling clocks
1197 * Returns -EPROBE_DEFER if binding fails, returns negative error
1198 * on phy power up failure and returns zero on success.
1200 static int ufs_qcom_init(struct ufs_hba *hba)
1203 struct device *dev = hba->dev;
1204 struct platform_device *pdev = to_platform_device(dev);
1205 struct ufs_qcom_host *host;
1206 struct resource *res;
1208 if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
1211 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1214 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
1218 /* Make a two way bind between the qcom host and the hba */
1220 ufshcd_set_variant(hba, host);
1223 * voting/devoting device ref_clk source is time consuming hence
1224 * skip devoting it during aggressive clock gating. This clock
1225 * will still be gated off during runtime suspend.
1227 host->generic_phy = devm_phy_get(dev, "ufsphy");
1229 if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1231 * UFS driver might be probed before the phy driver does.
1232 * In that case we would like to return EPROBE_DEFER code.
1234 err = -EPROBE_DEFER;
1235 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1237 goto out_variant_clear;
1238 } else if (IS_ERR(host->generic_phy)) {
1239 err = PTR_ERR(host->generic_phy);
1240 dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1241 goto out_variant_clear;
1244 err = ufs_qcom_bus_register(host);
1246 goto out_variant_clear;
1248 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1249 &host->hw_ver.minor, &host->hw_ver.step);
1252 * for newer controllers, device reference clock control bit has
1253 * moved inside UFS controller register address space itself.
1255 if (host->hw_ver.major >= 0x02) {
1256 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1257 host->dev_ref_clk_en_mask = BIT(26);
1259 /* "dev_ref_clk_ctrl_mem" is optional resource */
1260 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1262 host->dev_ref_clk_ctrl_mmio =
1263 devm_ioremap_resource(dev, res);
1264 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
1266 "%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
1268 PTR_ERR(host->dev_ref_clk_ctrl_mmio));
1269 host->dev_ref_clk_ctrl_mmio = NULL;
1271 host->dev_ref_clk_en_mask = BIT(5);
1275 /* update phy revision information before calling phy_init() */
1276 ufs_qcom_phy_save_controller_version(host->generic_phy,
1277 host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
1279 phy_init(host->generic_phy);
1280 err = phy_power_on(host->generic_phy);
1282 goto out_unregister_bus;
1284 err = ufs_qcom_init_lane_clks(host);
1286 goto out_disable_phy;
1288 ufs_qcom_set_caps(hba);
1289 ufs_qcom_advertise_quirks(hba);
1291 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1293 if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1294 ufs_qcom_hosts[hba->dev->id] = host;
1296 host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1297 ufs_qcom_get_default_testbus_cfg(host);
1298 err = ufs_qcom_testbus_config(host);
1300 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1308 phy_power_off(host->generic_phy);
1310 phy_exit(host->generic_phy);
1312 ufshcd_set_variant(hba, NULL);
1317 static void ufs_qcom_exit(struct ufs_hba *hba)
1319 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1321 ufs_qcom_disable_lane_clks(host);
1322 phy_power_off(host->generic_phy);
1323 phy_exit(host->generic_phy);
1326 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1330 u32 core_clk_ctrl_reg;
1332 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1335 err = ufshcd_dme_get(hba,
1336 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1337 &core_clk_ctrl_reg);
1341 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1342 core_clk_ctrl_reg |= clk_cycles;
1344 /* Clear CORE_CLK_DIV_EN */
1345 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1347 err = ufshcd_dme_set(hba,
1348 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1354 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1356 /* nothing to do as of now */
1360 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1362 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1364 if (!ufs_qcom_cap_qunipro(host))
1367 /* set unipro core clock cycles to 150 and clear clock divider */
1368 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1371 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1373 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1375 u32 core_clk_ctrl_reg;
1377 if (!ufs_qcom_cap_qunipro(host))
1380 err = ufshcd_dme_get(hba,
1381 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1382 &core_clk_ctrl_reg);
1384 /* make sure CORE_CLK_DIV_EN is cleared */
1386 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1387 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1388 err = ufshcd_dme_set(hba,
1389 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1396 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1398 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1400 if (!ufs_qcom_cap_qunipro(host))
1403 /* set unipro core clock cycles to 75 and clear clock divider */
1404 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1407 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1408 bool scale_up, enum ufs_notify_change_status status)
1410 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1411 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1414 if (status == PRE_CHANGE) {
1416 err = ufs_qcom_clk_scale_up_pre_change(hba);
1418 err = ufs_qcom_clk_scale_down_pre_change(hba);
1421 err = ufs_qcom_clk_scale_up_post_change(hba);
1423 err = ufs_qcom_clk_scale_down_post_change(hba);
1425 if (err || !dev_req_params)
1428 ufs_qcom_cfg_timers(hba,
1429 dev_req_params->gear_rx,
1430 dev_req_params->pwr_rx,
1431 dev_req_params->hs_rate,
1433 ufs_qcom_update_bus_bw_vote(host);
1440 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1441 void *priv, void (*print_fn)(struct ufs_hba *hba,
1442 int offset, int num_regs, char *str, void *priv))
1445 struct ufs_qcom_host *host;
1447 if (unlikely(!hba)) {
1448 pr_err("%s: hba is NULL\n", __func__);
1451 if (unlikely(!print_fn)) {
1452 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1456 host = ufshcd_get_variant(hba);
1457 if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1460 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1461 print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1463 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1465 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1467 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1468 print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1470 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1471 print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1473 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1474 print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1476 /* clear bit 17 - UTP_DBG_RAMS_EN */
1477 ufshcd_rmwl(hba, UFS_BIT(17), 0, REG_UFS_CFG1);
1479 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1480 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1482 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1483 print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1485 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1486 print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1488 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1489 print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1491 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1492 print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1494 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1495 print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1497 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1498 print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1501 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1503 if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1504 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1505 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1506 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1508 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1509 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1513 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1515 /* provide a legal default configuration */
1516 host->testbus.select_major = TSTBUS_UNIPRO;
1517 host->testbus.select_minor = 37;
1520 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1522 if (host->testbus.select_major >= TSTBUS_MAX) {
1523 dev_err(host->hba->dev,
1524 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1525 __func__, host->testbus.select_major);
1532 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1536 u32 mask = TEST_BUS_SUB_SEL_MASK;
1541 if (!ufs_qcom_testbus_cfg_is_ok(host))
1544 switch (host->testbus.select_major) {
1546 reg = UFS_TEST_BUS_CTRL_0;
1550 reg = UFS_TEST_BUS_CTRL_0;
1554 reg = UFS_TEST_BUS_CTRL_0;
1558 reg = UFS_TEST_BUS_CTRL_0;
1562 reg = UFS_TEST_BUS_CTRL_1;
1566 reg = UFS_TEST_BUS_CTRL_1;
1570 reg = UFS_TEST_BUS_CTRL_1;
1574 reg = UFS_TEST_BUS_CTRL_1;
1577 case TSTBUS_WRAPPER:
1578 reg = UFS_TEST_BUS_CTRL_2;
1581 case TSTBUS_COMBINED:
1582 reg = UFS_TEST_BUS_CTRL_2;
1585 case TSTBUS_UTP_HCI:
1586 reg = UFS_TEST_BUS_CTRL_2;
1590 reg = UFS_UNIPRO_CFG;
1595 * No need for a default case, since
1596 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1601 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1602 (u32)host->testbus.select_major << 19,
1604 ufshcd_rmwl(host->hba, mask,
1605 (u32)host->testbus.select_minor << offset,
1607 ufs_qcom_enable_test_bus(host);
1609 * Make sure the test bus configuration is
1610 * committed before returning.
1617 static void ufs_qcom_testbus_read(struct ufs_hba *hba)
1619 ufs_qcom_dump_regs(hba, UFS_TEST_BUS, 1, "UFS_TEST_BUS ");
1622 static void ufs_qcom_print_unipro_testbus(struct ufs_hba *hba)
1624 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1625 u32 *testbus = NULL;
1626 int i, nminor = 256, testbus_len = nminor * sizeof(u32);
1628 testbus = kmalloc(testbus_len, GFP_KERNEL);
1632 host->testbus.select_major = TSTBUS_UNIPRO;
1633 for (i = 0; i < nminor; i++) {
1634 host->testbus.select_minor = i;
1635 ufs_qcom_testbus_config(host);
1636 testbus[i] = ufshcd_readl(hba, UFS_TEST_BUS);
1638 print_hex_dump(KERN_ERR, "UNIPRO_TEST_BUS ", DUMP_PREFIX_OFFSET,
1639 16, 4, testbus, testbus_len, false);
1643 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1645 ufs_qcom_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16,
1646 "HCI Vendor Specific Registers ");
1648 /* sleep a bit intermittently as we are dumping too much data */
1649 ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1651 ufs_qcom_testbus_read(hba);
1653 ufs_qcom_print_unipro_testbus(hba);
1658 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1660 * The variant operations configure the necessary controller and PHY
1661 * handshake during initialization.
1663 static struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1665 .init = ufs_qcom_init,
1666 .exit = ufs_qcom_exit,
1667 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1668 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1669 .setup_clocks = ufs_qcom_setup_clocks,
1670 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1671 .link_startup_notify = ufs_qcom_link_startup_notify,
1672 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1673 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1674 .suspend = ufs_qcom_suspend,
1675 .resume = ufs_qcom_resume,
1676 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1680 * ufs_qcom_probe - probe routine of the driver
1681 * @pdev: pointer to Platform device handle
1683 * Return zero for success and non-zero for failure
1685 static int ufs_qcom_probe(struct platform_device *pdev)
1688 struct device *dev = &pdev->dev;
1690 /* Perform generic probe */
1691 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1693 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1699 * ufs_qcom_remove - set driver_data of the device to NULL
1700 * @pdev: pointer to platform device handle
1704 static int ufs_qcom_remove(struct platform_device *pdev)
1706 struct ufs_hba *hba = platform_get_drvdata(pdev);
1708 pm_runtime_get_sync(&(pdev)->dev);
1713 static const struct of_device_id ufs_qcom_of_match[] = {
1714 { .compatible = "qcom,ufshc"},
1717 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1719 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1720 .suspend = ufshcd_pltfrm_suspend,
1721 .resume = ufshcd_pltfrm_resume,
1722 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1723 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1724 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1727 static struct platform_driver ufs_qcom_pltform = {
1728 .probe = ufs_qcom_probe,
1729 .remove = ufs_qcom_remove,
1730 .shutdown = ufshcd_pltfrm_shutdown,
1732 .name = "ufshcd-qcom",
1733 .pm = &ufs_qcom_pm_ops,
1734 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1737 module_platform_driver(ufs_qcom_pltform);
1739 MODULE_LICENSE("GPL v2");