1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 MediaTek Inc.
5 * Stanley Chu <stanley.chu@mediatek.com>
6 * Peter Wang <peter.wang@mediatek.com>
9 #include <linux/arm-smccc.h>
10 #include <linux/bitfield.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset.h>
18 #include <linux/soc/mediatek/mtk_sip_svc.h>
21 #include "ufshcd-crypto.h"
22 #include "ufshcd-pltfrm.h"
23 #include "ufs_quirks.h"
25 #include "ufs-mediatek.h"
27 #define ufs_mtk_smc(cmd, val, res) \
28 arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
29 cmd, val, 0, 0, 0, 0, 0, &(res))
31 #define ufs_mtk_crypto_ctrl(res, enable) \
32 ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, enable, res)
34 #define ufs_mtk_ref_clk_notify(on, res) \
35 ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res)
37 #define ufs_mtk_device_reset_ctrl(high, res) \
38 ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res)
40 static struct ufs_dev_fix ufs_mtk_dev_fixups[] = {
41 UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
42 UFS_DEVICE_QUIRK_DELAY_AFTER_LPM),
43 UFS_FIX(UFS_VENDOR_SKHYNIX, "H9HQ21AFAMZDAR",
44 UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES),
48 static const struct ufs_mtk_host_cfg ufs_mtk_mt8192_cfg = {
49 .caps = UFS_MTK_CAP_BOOST_CRYPT_ENGINE,
52 static const struct of_device_id ufs_mtk_of_match[] = {
54 .compatible = "mediatek,mt8183-ufshci",
57 .compatible = "mediatek,mt8192-ufshci",
58 .data = &ufs_mtk_mt8192_cfg
63 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
65 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
67 return (host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
70 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
76 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
78 (1 << RX_SYMBOL_CLK_GATE_EN) |
79 (1 << SYS_CLK_GATE_EN) |
80 (1 << TX_CLK_GATE_EN);
82 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
85 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
86 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
88 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
91 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
92 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
93 (1 << SYS_CLK_GATE_EN) |
94 (1 << TX_CLK_GATE_EN));
96 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
99 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
100 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
102 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
106 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
108 struct arm_smccc_res res;
110 ufs_mtk_crypto_ctrl(res, 1);
112 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
114 hba->caps &= ~UFSHCD_CAP_CRYPTO;
118 static void ufs_mtk_host_reset(struct ufs_hba *hba)
120 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
122 reset_control_assert(host->hci_reset);
123 reset_control_assert(host->crypto_reset);
124 reset_control_assert(host->unipro_reset);
126 usleep_range(100, 110);
128 reset_control_deassert(host->unipro_reset);
129 reset_control_deassert(host->crypto_reset);
130 reset_control_deassert(host->hci_reset);
133 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
134 struct reset_control **rc,
137 *rc = devm_reset_control_get(hba->dev, str);
139 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
145 static void ufs_mtk_init_reset(struct ufs_hba *hba)
147 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
149 ufs_mtk_init_reset_control(hba, &host->hci_reset,
151 ufs_mtk_init_reset_control(hba, &host->unipro_reset,
153 ufs_mtk_init_reset_control(hba, &host->crypto_reset,
157 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
158 enum ufs_notify_change_status status)
160 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
162 if (status == PRE_CHANGE) {
163 if (host->unipro_lpm) {
164 hba->vps->hba_enable_delay_us = 0;
166 hba->vps->hba_enable_delay_us = 600;
167 ufs_mtk_host_reset(hba);
170 if (hba->caps & UFSHCD_CAP_CRYPTO)
171 ufs_mtk_crypto_enable(hba);
177 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
179 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
180 struct device *dev = hba->dev;
181 struct device_node *np = dev->of_node;
184 host->mphy = devm_of_phy_get_by_index(dev, np, 0);
186 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
188 * UFS driver might be probed before the phy driver does.
189 * In that case we would like to return EPROBE_DEFER code.
193 "%s: required phy hasn't probed yet. err = %d\n",
195 } else if (IS_ERR(host->mphy)) {
196 err = PTR_ERR(host->mphy);
197 if (err != -ENODEV) {
198 dev_info(dev, "%s: PHY get failed %d\n", __func__,
206 * Allow unbound mphy because not every platform needs specific
215 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
217 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
218 struct arm_smccc_res res;
219 ktime_t timeout, time_checked;
222 if (host->ref_clk_enabled == on)
226 ufs_mtk_ref_clk_notify(on, res);
227 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
228 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
230 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
234 timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
236 time_checked = ktime_get();
237 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
239 /* Wait until ack bit equals to req bit */
240 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
243 usleep_range(100, 200);
244 } while (ktime_before(time_checked, timeout));
246 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
248 ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
253 host->ref_clk_enabled = on;
255 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
256 ufs_mtk_ref_clk_notify(on, res);
262 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
263 u16 gating_us, u16 ungating_us)
265 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
267 if (hba->dev_info.clk_gating_wait_us) {
268 host->ref_clk_gating_wait_us =
269 hba->dev_info.clk_gating_wait_us;
271 host->ref_clk_gating_wait_us = gating_us;
274 host->ref_clk_ungating_wait_us = ungating_us;
277 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
278 unsigned long max_wait_ms)
280 ktime_t timeout, time_checked;
283 timeout = ktime_add_ms(ktime_get(), max_wait_ms);
285 time_checked = ktime_get();
286 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
287 val = ufshcd_readl(hba, REG_UFS_PROBE);
293 /* Sleep for max. 200us */
294 usleep_range(100, 200);
295 } while (ktime_before(time_checked, timeout));
303 static void ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
305 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
306 struct phy *mphy = host->mphy;
311 if (on && !host->mphy_powered_on)
313 else if (!on && host->mphy_powered_on)
317 host->mphy_powered_on = on;
320 static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
321 struct clk **clk_out)
326 clk = devm_clk_get(dev, name);
335 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
337 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
338 struct ufs_mtk_crypt_cfg *cfg;
339 struct regulator *reg;
342 if (!ufs_mtk_is_boost_crypt_enabled(hba))
346 volt = cfg->vcore_volt;
347 reg = cfg->reg_vcore;
349 ret = clk_prepare_enable(cfg->clk_crypt_mux);
351 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
357 ret = regulator_set_voltage(reg, volt, INT_MAX);
360 "failed to set vcore to %d\n", volt);
364 ret = clk_set_parent(cfg->clk_crypt_mux,
365 cfg->clk_crypt_perf);
368 "failed to set clk_crypt_perf\n");
369 regulator_set_voltage(reg, 0, INT_MAX);
373 ret = clk_set_parent(cfg->clk_crypt_mux,
377 "failed to set clk_crypt_lp\n");
381 ret = regulator_set_voltage(reg, 0, INT_MAX);
384 "failed to set vcore to MIN\n");
388 clk_disable_unprepare(cfg->clk_crypt_mux);
391 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
396 ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
398 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
405 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
407 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
408 struct ufs_mtk_crypt_cfg *cfg;
409 struct device *dev = hba->dev;
410 struct regulator *reg;
413 host->caps = host->cfg->caps;
415 if (!ufs_mtk_is_boost_crypt_enabled(hba))
418 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
423 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
425 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
430 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
432 dev_info(dev, "failed to get boost-crypt-vcore-min");
437 if (ufs_mtk_init_host_clk(hba, "crypt_mux",
438 &cfg->clk_crypt_mux))
441 if (ufs_mtk_init_host_clk(hba, "crypt_lp",
445 if (ufs_mtk_init_host_clk(hba, "crypt_perf",
446 &cfg->clk_crypt_perf))
449 cfg->reg_vcore = reg;
450 cfg->vcore_volt = volt;
451 dev_info(dev, "caps: boost-crypt");
455 host->caps &= ~UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
459 * ufs_mtk_setup_clocks - enables/disable clocks
460 * @hba: host controller instance
461 * @on: If true, enable clocks else disable them.
462 * @status: PRE_CHANGE or POST_CHANGE notify
464 * Returns 0 on success, non-zero on failure.
466 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
467 enum ufs_notify_change_status status)
469 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
471 bool clk_pwr_off = false;
474 * In case ufs_mtk_init() is not yet done, simply ignore.
475 * This ufs_mtk_setup_clocks() shall be called from
476 * ufs_mtk_init() after init is done.
481 if (!on && status == PRE_CHANGE) {
482 if (ufshcd_is_link_off(hba)) {
484 } else if (ufshcd_is_link_hibern8(hba) ||
485 (!ufshcd_can_hibern8_during_gating(hba) &&
486 ufshcd_is_auto_hibern8_enabled(hba))) {
488 * Gate ref-clk and poweroff mphy if link state is in
489 * OFF or Hibern8 by either Auto-Hibern8 or
490 * ufshcd_link_state_transition().
492 ret = ufs_mtk_wait_link_state(hba,
500 ufs_mtk_boost_crypt(hba, on);
501 ufs_mtk_setup_ref_clk(hba, on);
502 ufs_mtk_mphy_power_on(hba, on);
504 } else if (on && status == POST_CHANGE) {
505 ufs_mtk_mphy_power_on(hba, on);
506 ufs_mtk_setup_ref_clk(hba, on);
507 ufs_mtk_boost_crypt(hba, on);
514 * ufs_mtk_init - find other essential mmio bases
515 * @hba: host controller instance
517 * Binds PHY with controller and powers up PHY enabling clocks
520 * Returns -EPROBE_DEFER if binding fails, returns negative error
521 * on phy power up failure and returns zero on success.
523 static int ufs_mtk_init(struct ufs_hba *hba)
525 const struct of_device_id *id;
526 struct device *dev = hba->dev;
527 struct ufs_mtk_host *host;
530 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
533 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
538 ufshcd_set_variant(hba, host);
540 /* Get host capability and platform data */
541 id = of_match_device(ufs_mtk_of_match, dev);
548 host->cfg = (struct ufs_mtk_host_cfg *)id->data;
549 ufs_mtk_init_host_caps(hba);
552 err = ufs_mtk_bind_mphy(hba);
554 goto out_variant_clear;
556 ufs_mtk_init_reset(hba);
558 /* Enable runtime autosuspend */
559 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
561 /* Enable clock-gating */
562 hba->caps |= UFSHCD_CAP_CLK_GATING;
564 /* Enable inline encryption */
565 hba->caps |= UFSHCD_CAP_CRYPTO;
567 /* Enable WriteBooster */
568 hba->caps |= UFSHCD_CAP_WB_EN;
569 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
570 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
573 * ufshcd_vops_init() is invoked after
574 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
575 * phy clock setup is skipped.
577 * Enable phy clocks specifically here.
579 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
584 ufshcd_set_variant(hba, NULL);
589 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
590 struct ufs_pa_layer_attr *dev_max_params,
591 struct ufs_pa_layer_attr *dev_req_params)
593 struct ufs_dev_params host_cap;
596 host_cap.tx_lanes = UFS_MTK_LIMIT_NUM_LANES_TX;
597 host_cap.rx_lanes = UFS_MTK_LIMIT_NUM_LANES_RX;
598 host_cap.hs_rx_gear = UFS_MTK_LIMIT_HSGEAR_RX;
599 host_cap.hs_tx_gear = UFS_MTK_LIMIT_HSGEAR_TX;
600 host_cap.pwm_rx_gear = UFS_MTK_LIMIT_PWMGEAR_RX;
601 host_cap.pwm_tx_gear = UFS_MTK_LIMIT_PWMGEAR_TX;
602 host_cap.rx_pwr_pwm = UFS_MTK_LIMIT_RX_PWR_PWM;
603 host_cap.tx_pwr_pwm = UFS_MTK_LIMIT_TX_PWR_PWM;
604 host_cap.rx_pwr_hs = UFS_MTK_LIMIT_RX_PWR_HS;
605 host_cap.tx_pwr_hs = UFS_MTK_LIMIT_TX_PWR_HS;
606 host_cap.hs_rate = UFS_MTK_LIMIT_HS_RATE;
607 host_cap.desired_working_mode =
608 UFS_MTK_LIMIT_DESIRED_MODE;
610 ret = ufshcd_get_pwr_dev_param(&host_cap,
614 pr_info("%s: failed to determine capabilities\n",
621 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
622 enum ufs_notify_change_status stage,
623 struct ufs_pa_layer_attr *dev_max_params,
624 struct ufs_pa_layer_attr *dev_req_params)
630 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
643 static int ufs_mtk_unipro_set_pm(struct ufs_hba *hba, bool lpm)
646 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
648 ret = ufshcd_dme_set(hba,
649 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
653 * Forcibly set as non-LPM mode if UIC commands is failed
654 * to use default hba_enable_delay_us value for re-enabling
657 host->unipro_lpm = lpm;
663 static int ufs_mtk_pre_link(struct ufs_hba *hba)
668 ret = ufs_mtk_unipro_set_pm(hba, false);
673 * Setting PA_Local_TX_LCC_Enable to 0 before link startup
674 * to make sure that both host and device TX LCC are disabled
675 * once link startup is completed.
677 ret = ufshcd_disable_host_tx_lcc(hba);
681 /* disable deep stall */
682 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
688 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
693 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
698 if (ufshcd_is_clkgating_allowed(hba)) {
699 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
700 ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
704 spin_lock_irqsave(hba->host->host_lock, flags);
705 hba->clk_gating.delay_ms = ah_ms + 5;
706 spin_unlock_irqrestore(hba->host->host_lock, flags);
710 static int ufs_mtk_post_link(struct ufs_hba *hba)
712 /* enable unipro clock gating feature */
713 ufs_mtk_cfg_unipro_cg(hba, true);
715 /* configure auto-hibern8 timer to 10ms */
716 if (ufshcd_is_auto_hibern8_supported(hba)) {
717 ufshcd_auto_hibern8_update(hba,
718 FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
719 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
722 ufs_mtk_setup_clk_gating(hba);
727 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
728 enum ufs_notify_change_status stage)
734 ret = ufs_mtk_pre_link(hba);
737 ret = ufs_mtk_post_link(hba);
747 static int ufs_mtk_device_reset(struct ufs_hba *hba)
749 struct arm_smccc_res res;
751 ufs_mtk_device_reset_ctrl(0, res);
754 * The reset signal is active low. UFS devices shall detect
755 * more than or equal to 1us of positive or negative RST_n
758 * To be on safe side, keep the reset low for at least 10us.
760 usleep_range(10, 15);
762 ufs_mtk_device_reset_ctrl(1, res);
764 /* Some devices may need time to respond to rst_n */
765 usleep_range(10000, 15000);
767 dev_info(hba->dev, "device reset done\n");
772 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
776 err = ufshcd_hba_enable(hba);
780 err = ufs_mtk_unipro_set_pm(hba, false);
784 err = ufshcd_uic_hibern8_exit(hba);
786 ufshcd_set_link_active(hba);
790 err = ufshcd_make_hba_operational(hba);
797 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
801 err = ufs_mtk_unipro_set_pm(hba, true);
803 /* Resume UniPro state for following error recovery */
804 ufs_mtk_unipro_set_pm(hba, false);
811 static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
813 if (!hba->vreg_info.vccq2 || !hba->vreg_info.vcc)
816 if (lpm && !hba->vreg_info.vcc->enabled)
817 regulator_set_mode(hba->vreg_info.vccq2->reg,
818 REGULATOR_MODE_IDLE);
820 regulator_set_mode(hba->vreg_info.vccq2->reg,
821 REGULATOR_MODE_NORMAL);
824 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
827 struct arm_smccc_res res;
829 if (ufshcd_is_link_hibern8(hba)) {
830 err = ufs_mtk_link_set_lpm(hba);
833 * Set link as off state enforcedly to trigger
834 * ufshcd_host_reset_and_restore() in ufshcd_suspend()
835 * for completed host reset.
837 ufshcd_set_link_off(hba);
841 * Make sure no error will be returned to prevent
842 * ufshcd_suspend() re-enabling regulators while vreg is still
845 ufs_mtk_vreg_set_lpm(hba, true);
848 if (ufshcd_is_link_off(hba))
849 ufs_mtk_device_reset_ctrl(0, res);
854 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
858 if (ufshcd_is_link_hibern8(hba)) {
859 ufs_mtk_vreg_set_lpm(hba, false);
860 err = ufs_mtk_link_set_hpm(hba);
862 err = ufshcd_link_recovery(hba);
870 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
872 ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
874 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
876 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
877 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
880 /* Direct debugging information to REG_MTK_PROBE */
881 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
882 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
885 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
887 struct ufs_dev_info *dev_info = &hba->dev_info;
888 u16 mid = dev_info->wmanufacturerid;
890 if (mid == UFS_VENDOR_SAMSUNG)
891 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
894 * Decide waiting time before gating reference clock and
895 * after ungating reference clock according to vendors'
898 if (mid == UFS_VENDOR_SAMSUNG)
899 ufs_mtk_setup_ref_clk_wait_us(hba, 1, 1);
900 else if (mid == UFS_VENDOR_SKHYNIX)
901 ufs_mtk_setup_ref_clk_wait_us(hba, 30, 30);
902 else if (mid == UFS_VENDOR_TOSHIBA)
903 ufs_mtk_setup_ref_clk_wait_us(hba, 100, 32);
908 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
910 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
914 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
916 * The variant operations configure the necessary controller and PHY
917 * handshake during initialization.
919 static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
920 .name = "mediatek.ufshci",
921 .init = ufs_mtk_init,
922 .setup_clocks = ufs_mtk_setup_clocks,
923 .hce_enable_notify = ufs_mtk_hce_enable_notify,
924 .link_startup_notify = ufs_mtk_link_startup_notify,
925 .pwr_change_notify = ufs_mtk_pwr_change_notify,
926 .apply_dev_quirks = ufs_mtk_apply_dev_quirks,
927 .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks,
928 .suspend = ufs_mtk_suspend,
929 .resume = ufs_mtk_resume,
930 .dbg_register_dump = ufs_mtk_dbg_register_dump,
931 .device_reset = ufs_mtk_device_reset,
935 * ufs_mtk_probe - probe routine of the driver
936 * @pdev: pointer to Platform device handle
938 * Return zero for success and non-zero for failure
940 static int ufs_mtk_probe(struct platform_device *pdev)
943 struct device *dev = &pdev->dev;
945 /* perform generic probe */
946 err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
948 dev_info(dev, "probe failed %d\n", err);
954 * ufs_mtk_remove - set driver_data of the device to NULL
955 * @pdev: pointer to platform device handle
959 static int ufs_mtk_remove(struct platform_device *pdev)
961 struct ufs_hba *hba = platform_get_drvdata(pdev);
963 pm_runtime_get_sync(&(pdev)->dev);
968 static const struct dev_pm_ops ufs_mtk_pm_ops = {
969 .suspend = ufshcd_pltfrm_suspend,
970 .resume = ufshcd_pltfrm_resume,
971 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
972 .runtime_resume = ufshcd_pltfrm_runtime_resume,
973 .runtime_idle = ufshcd_pltfrm_runtime_idle,
976 static struct platform_driver ufs_mtk_pltform = {
977 .probe = ufs_mtk_probe,
978 .remove = ufs_mtk_remove,
979 .shutdown = ufshcd_pltfrm_shutdown,
981 .name = "ufshcd-mtk",
982 .pm = &ufs_mtk_pm_ops,
983 .of_match_table = ufs_mtk_of_match,
987 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
988 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
989 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
990 MODULE_LICENSE("GPL v2");
992 module_platform_driver(ufs_mtk_pltform);