drivers/scsi/stex.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * SuperTrak EX Series Storage Controller driver for Linux
   4  *
   5  *      Copyright (C) 2005-2015 Promise Technology Inc.
   6  *
   7  *      Written By:
   8  *              Ed Lin <promise_linux@promise.com>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <linux/slab.h>
  16 #include <linux/time.h>
  17 #include <linux/pci.h>
  18 #include <linux/blkdev.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/types.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/ktime.h>
  24 #include <linux/reboot.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27 #include <asm/byteorder.h>
  28 #include <scsi/scsi.h>
  29 #include <scsi/scsi_device.h>
  30 #include <scsi/scsi_cmnd.h>
  31 #include <scsi/scsi_host.h>
  32 #include <scsi/scsi_tcq.h>
  33 #include <scsi/scsi_dbg.h>
  34 #include <scsi/scsi_eh.h>
  35
  36 #define DRV_NAME "stex"
  37 #define ST_DRIVER_VERSION       "6.02.0000.01"
  38 #define ST_VER_MAJOR            6
  39 #define ST_VER_MINOR            02
  40 #define ST_OEM                          0000
  41 #define ST_BUILD_VER            01
  42
  43 enum {
  44         /* MU register offset */
  45         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  46         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  47         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  48         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  49         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  50         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  51         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  52         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  53         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  54         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  55
  56         YIOA_STATUS                             = 0x00,
  57         YH2I_INT                                = 0x20,
  58         YINT_EN                                 = 0x34,
  59         YI2H_INT                                = 0x9c,
  60         YI2H_INT_C                              = 0xa0,
  61         YH2I_REQ                                = 0xc0,
  62         YH2I_REQ_HI                             = 0xc4,
  63         PSCRATCH0                               = 0xb0,
  64         PSCRATCH1                               = 0xb4,
  65         PSCRATCH2                               = 0xb8,
  66         PSCRATCH3                               = 0xbc,
  67         PSCRATCH4                               = 0xc8,
  68         MAILBOX_BASE                    = 0x1000,
  69         MAILBOX_HNDSHK_STS              = 0x0,
  70
  71         /* MU register value */
  72         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  73         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  74         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  75         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  76         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  77
  78         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  79         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  80         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  81         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  82         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  83         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  84
  85         /* MU status code */
  86         MU_STATE_STARTING                       = 1,
  87         MU_STATE_STARTED                        = 2,
  88         MU_STATE_RESETTING                      = 3,
  89         MU_STATE_FAILED                         = 4,
  90         MU_STATE_STOP                           = 5,
  91         MU_STATE_NOCONNECT                      = 6,
  92
  93         MU_MAX_DELAY                            = 50,
  94         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  95         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  96         MU_HARD_RESET_WAIT                      = 30000,
  97         HMU_PARTNER_TYPE                        = 2,
  98
  99         /* firmware returned values */
 100         SRB_STATUS_SUCCESS                      = 0x01,
 101         SRB_STATUS_ERROR                        = 0x04,
 102         SRB_STATUS_BUSY                         = 0x05,
 103         SRB_STATUS_INVALID_REQUEST              = 0x06,
 104         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
 105         SRB_SEE_SENSE                           = 0x80,
 106
 107         /* task attribute */
 108         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 109         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 110         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 111         TASK_ATTRIBUTE_ACA                      = 0x4,
 112 };
 113
 114 enum {
 115         SS_STS_NORMAL                           = 0x80000000,
 116         SS_STS_DONE                             = 0x40000000,
 117         SS_STS_HANDSHAKE                        = 0x20000000,
 118
 119         SS_HEAD_HANDSHAKE                       = 0x80,
 120
 121         SS_H2I_INT_RESET                        = 0x100,
 122
 123         SS_I2H_REQUEST_RESET                    = 0x2000,
 124
 125         SS_MU_OPERATIONAL                       = 0x80000000,
 126 };
 127
 128 enum {
 129         STEX_CDB_LENGTH                         = 16,
 130         STATUS_VAR_LEN                          = 128,
 131
 132         /* sg flags */
 133         SG_CF_EOT                               = 0x80, /* end of table */
 134         SG_CF_64B                               = 0x40, /* 64 bit item */
 135         SG_CF_HOST                              = 0x20, /* sg in host memory */
 136         MSG_DATA_DIR_ND                         = 0,
 137         MSG_DATA_DIR_IN                         = 1,
 138         MSG_DATA_DIR_OUT                        = 2,
 139
 140         st_shasta                               = 0,
 141         st_vsc                                  = 1,
 142         st_yosemite                             = 2,
 143         st_seq                                  = 3,
 144         st_yel                                  = 4,
 145         st_P3                                   = 5,
 146
 147         PASSTHRU_REQ_TYPE                       = 0x00000001,
 148         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 149         ST_INTERNAL_TIMEOUT                     = 180,
 150
 151         ST_TO_CMD                               = 0,
 152         ST_FROM_CMD                             = 1,
 153
 154         /* vendor specific commands of Promise */
 155         MGT_CMD                                 = 0xd8,
 156         SINBAND_MGT_CMD                         = 0xd9,
 157         ARRAY_CMD                               = 0xe0,
 158         CONTROLLER_CMD                          = 0xe1,
 159         DEBUGGING_CMD                           = 0xe2,
 160         PASSTHRU_CMD                            = 0xe3,
 161
 162         PASSTHRU_GET_ADAPTER                    = 0x05,
 163         PASSTHRU_GET_DRVVER                     = 0x10,
 164
 165         CTLR_CONFIG_CMD                         = 0x03,
 166         CTLR_SHUTDOWN                           = 0x0d,
 167
 168         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 169         CTLR_POWER_SAVING                       = 0x01,
 170
 171         PASSTHRU_SIGNATURE                      = 0x4e415041,
 172         MGT_CMD_SIGNATURE                       = 0xba,
 173
 174         INQUIRY_EVPD                            = 0x01,
 175
 176         ST_ADDITIONAL_MEM                       = 0x200000,
 177         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 178         PMIC_SHUTDOWN                           = 0x0D,
 179         PMIC_REUMSE                                     = 0x10,
 180         ST_IGNORED                                      = -1,
 181         ST_NOTHANDLED                           = 7,
 182         ST_S3                                           = 3,
 183         ST_S4                                           = 4,
 184         ST_S5                                           = 5,
 185         ST_S6                                           = 6,
 186 };
 187
 188 struct st_sgitem {
 189         u8 ctrl;        /* SG_CF_xxx */
 190         u8 reserved[3];
 191         __le32 count;
 192         __le64 addr;
 193 };
 194
 195 struct st_ss_sgitem {
 196         __le32 addr;
 197         __le32 addr_hi;
 198         __le32 count;
 199 };
 200
 201 struct st_sgtable {
 202         __le16 sg_count;
 203         __le16 max_sg_count;
 204         __le32 sz_in_byte;
 205 };
 206
 207 struct st_msg_header {
 208         __le64 handle;
 209         u8 flag;
 210         u8 channel;
 211         __le16 timeout;
 212         u32 reserved;
 213 };
 214
 215 struct handshake_frame {
 216         __le64 rb_phy;          /* request payload queue physical address */
 217         __le16 req_sz;          /* size of each request payload */
 218         __le16 req_cnt;         /* count of reqs the buffer can hold */
 219         __le16 status_sz;       /* size of each status payload */
 220         __le16 status_cnt;      /* count of status the buffer can hold */
 221         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 222         u8 partner_type;        /* who sends this frame */
 223         u8 reserved0[7];
 224         __le32 partner_ver_major;
 225         __le32 partner_ver_minor;
 226         __le32 partner_ver_oem;
 227         __le32 partner_ver_build;
 228         __le32 extra_offset;    /* NEW */
 229         __le32 extra_size;      /* NEW */
 230         __le32 scratch_size;
 231         u32 reserved1;
 232 };
 233
 234 struct req_msg {
 235         __le16 tag;
 236         u8 lun;
 237         u8 target;
 238         u8 task_attr;
 239         u8 task_manage;
 240         u8 data_dir;
 241         u8 payload_sz;          /* payload size in 4-byte, not used */
 242         u8 cdb[STEX_CDB_LENGTH];
 243         u32 variable[];
 244 };
 245
 246 struct status_msg {
 247         __le16 tag;
 248         u8 lun;
 249         u8 target;
 250         u8 srb_status;
 251         u8 scsi_status;
 252         u8 reserved;
 253         u8 payload_sz;          /* payload size in 4-byte */
 254         u8 variable[STATUS_VAR_LEN];
 255 };
 256
 257 struct ver_info {
 258         u32 major;
 259         u32 minor;
 260         u32 oem;
 261         u32 build;
 262         u32 reserved[2];
 263 };
 264
 265 struct st_frame {
 266         u32 base[6];
 267         u32 rom_addr;
 268
 269         struct ver_info drv_ver;
 270         struct ver_info bios_ver;
 271
 272         u32 bus;
 273         u32 slot;
 274         u32 irq_level;
 275         u32 irq_vec;
 276         u32 id;
 277         u32 subid;
 278
 279         u32 dimm_size;
 280         u8 dimm_type;
 281         u8 reserved[3];
 282
 283         u32 channel;
 284         u32 reserved1;
 285 };
 286
 287 struct st_drvver {
 288         u32 major;
 289         u32 minor;
 290         u32 oem;
 291         u32 build;
 292         u32 signature[2];
 293         u8 console_id;
 294         u8 host_no;
 295         u8 reserved0[2];
 296         u32 reserved[3];
 297 };
 298
 299 struct st_ccb {
 300         struct req_msg *req;
 301         struct scsi_cmnd *cmd;
 302
 303         void *sense_buffer;
 304         unsigned int sense_bufflen;
 305         int sg_count;
 306
 307         u32 req_type;
 308         u8 srb_status;
 309         u8 scsi_status;
 310         u8 reserved[2];
 311 };
 312
 313 struct st_hba {
 314         void __iomem *mmio_base;        /* iomapped PCI memory space */
 315         void *dma_mem;
 316         dma_addr_t dma_handle;
 317         size_t dma_size;
 318
 319         struct Scsi_Host *host;
 320         struct pci_dev *pdev;
 321
 322         struct req_msg * (*alloc_rq) (struct st_hba *);
 323         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 324         void (*send) (struct st_hba *, struct req_msg *, u16);
 325
 326         u32 req_head;
 327         u32 req_tail;
 328         u32 status_head;
 329         u32 status_tail;
 330
 331         struct status_msg *status_buffer;
 332         void *copy_buffer; /* temp buffer for driver-handled commands */
 333         struct st_ccb *ccb;
 334         struct st_ccb *wait_ccb;
 335         __le32 *scratch;
 336
 337         char work_q_name[20];
 338         struct workqueue_struct *work_q;
 339         struct work_struct reset_work;
 340         wait_queue_head_t reset_waitq;
 341         unsigned int mu_status;
 342         unsigned int cardtype;
 343         int msi_enabled;
 344         int out_req_cnt;
 345         u32 extra_offset;
 346         u16 rq_count;
 347         u16 rq_size;
 348         u16 sts_count;
 349         u8  supports_pm;
 350         int msi_lock;
 351 };
 352
 353 struct st_card_info {
 354         struct req_msg * (*alloc_rq) (struct st_hba *);
 355         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 356         void (*send) (struct st_hba *, struct req_msg *, u16);
 357         unsigned int max_id;
 358         unsigned int max_lun;
 359         unsigned int max_channel;
 360         u16 rq_count;
 361         u16 rq_size;
 362         u16 sts_count;
 363 };
 364
 365 static int S6flag;
 366 static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
 367 static struct notifier_block stex_notifier = {
 368         stex_halt, NULL, 0
 369 };
 370
 371 static int msi;
 372 module_param(msi, int, 0);
 373 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 374
 375 static const char console_inq_page[] =
 376 {
 377         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 378         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 379         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 380         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 381         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 382         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 383         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 384         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 385 };
 386
 387 MODULE_AUTHOR("Ed Lin");
 388 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 389 MODULE_LICENSE("GPL");
 390 MODULE_VERSION(ST_DRIVER_VERSION);
 391
 392 static struct status_msg *stex_get_status(struct st_hba *hba)
 393 {
 394         struct status_msg *status = hba->status_buffer + hba->status_tail;
 395
 396         ++hba->status_tail;
 397         hba->status_tail %= hba->sts_count+1;
 398
 399         return status;
 400 }
 401
 402 static void stex_invalid_field(struct scsi_cmnd *cmd,
 403                                void (*done)(struct scsi_cmnd *))
 404 {
 405         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 406
 407         /* "Invalid field in cdb" */
 408         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 409                                 0x0);
 410         done(cmd);
 411 }
 412
 413 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 414 {
 415         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 416
 417         ++hba->req_head;
 418         hba->req_head %= hba->rq_count+1;
 419
 420         return req;
 421 }
 422
 423 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 424 {
 425         return (struct req_msg *)(hba->dma_mem +
 426                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 427 }
 428
 429 static int stex_map_sg(struct st_hba *hba,
 430         struct req_msg *req, struct st_ccb *ccb)
 431 {
 432         struct scsi_cmnd *cmd;
 433         struct scatterlist *sg;
 434         struct st_sgtable *dst;
 435         struct st_sgitem *table;
 436         int i, nseg;
 437
 438         cmd = ccb->cmd;
 439         nseg = scsi_dma_map(cmd);
 440         BUG_ON(nseg < 0);
 441         if (nseg) {
 442                 dst = (struct st_sgtable *)req->variable;
 443
 444                 ccb->sg_count = nseg;
 445                 dst->sg_count = cpu_to_le16((u16)nseg);
 446                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 447                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 448
 449                 table = (struct st_sgitem *)(dst + 1);
 450                 scsi_for_each_sg(cmd, sg, nseg, i) {
 451                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 452                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 453                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 454                 }
 455                 table[--i].ctrl |= SG_CF_EOT;
 456         }
 457
 458         return nseg;
 459 }
 460
 461 static int stex_ss_map_sg(struct st_hba *hba,
 462         struct req_msg *req, struct st_ccb *ccb)
 463 {
 464         struct scsi_cmnd *cmd;
 465         struct scatterlist *sg;
 466         struct st_sgtable *dst;
 467         struct st_ss_sgitem *table;
 468         int i, nseg;
 469
 470         cmd = ccb->cmd;
 471         nseg = scsi_dma_map(cmd);
 472         BUG_ON(nseg < 0);
 473         if (nseg) {
 474                 dst = (struct st_sgtable *)req->variable;
 475
 476                 ccb->sg_count = nseg;
 477                 dst->sg_count = cpu_to_le16((u16)nseg);
 478                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 479                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 480
 481                 table = (struct st_ss_sgitem *)(dst + 1);
 482                 scsi_for_each_sg(cmd, sg, nseg, i) {
 483                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 484                         table[i].addr =
 485                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 486                         table[i].addr_hi =
 487                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 488                 }
 489         }
 490
 491         return nseg;
 492 }
 493
 494 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 495 {
 496         struct st_frame *p;
 497         size_t count = sizeof(struct st_frame);
 498
 499         p = hba->copy_buffer;
 500         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 501         memset(p->base, 0, sizeof(u32)*6);
 502         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 503         p->rom_addr = 0;
 504
 505         p->drv_ver.major = ST_VER_MAJOR;
 506         p->drv_ver.minor = ST_VER_MINOR;
 507         p->drv_ver.oem = ST_OEM;
 508         p->drv_ver.build = ST_BUILD_VER;
 509
 510         p->bus = hba->pdev->bus->number;
 511         p->slot = hba->pdev->devfn;
 512         p->irq_level = 0;
 513         p->irq_vec = hba->pdev->irq;
 514         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 515         p->subid =
 516                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 517
 518         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 519 }
 520
 521 static void
 522 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 523 {
 524         req->tag = cpu_to_le16(tag);
 525
 526         hba->ccb[tag].req = req;
 527         hba->out_req_cnt++;
 528
 529         writel(hba->req_head, hba->mmio_base + IMR0);
 530         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 531         readl(hba->mmio_base + IDBL); /* flush */
 532 }
 533
 534 static void
 535 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 536 {
 537         struct scsi_cmnd *cmd;
 538         struct st_msg_header *msg_h;
 539         dma_addr_t addr;
 540
 541         req->tag = cpu_to_le16(tag);
 542
 543         hba->ccb[tag].req = req;
 544         hba->out_req_cnt++;
 545
 546         cmd = hba->ccb[tag].cmd;
 547         msg_h = (struct st_msg_header *)req - 1;
 548         if (likely(cmd)) {
 549                 msg_h->channel = (u8)cmd->device->channel;
 550                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 551         }
 552         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 553         addr += (hba->ccb[tag].sg_count+4)/11;
 554         msg_h->handle = cpu_to_le64(addr);
 555
 556         ++hba->req_head;
 557         hba->req_head %= hba->rq_count+1;
 558         if (hba->cardtype == st_P3) {
 559                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 560                 writel(addr, hba->mmio_base + YH2I_REQ);
 561         } else {
 562                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 563                 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 564                 writel(addr, hba->mmio_base + YH2I_REQ);
 565                 readl(hba->mmio_base + YH2I_REQ); /* flush */
 566         }
 567 }
 568
 569 static void return_abnormal_state(struct st_hba *hba, int status)
 570 {
 571         struct st_ccb *ccb;
 572         unsigned long flags;
 573         u16 tag;
 574
 575         spin_lock_irqsave(hba->host->host_lock, flags);
 576         for (tag = 0; tag < hba->host->can_queue; tag++) {
 577                 ccb = &hba->ccb[tag];
 578                 if (ccb->req == NULL)
 579                         continue;
 580                 ccb->req = NULL;
 581                 if (ccb->cmd) {
 582                         scsi_dma_unmap(ccb->cmd);
 583                         ccb->cmd->result = status << 16;
 584                         ccb->cmd->scsi_done(ccb->cmd);
 585                         ccb->cmd = NULL;
 586                 }
 587         }
 588         spin_unlock_irqrestore(hba->host->host_lock, flags);
 589 }
 590 static int
 591 stex_slave_config(struct scsi_device *sdev)
 592 {
 593         sdev->use_10_for_rw = 1;
 594         sdev->use_10_for_ms = 1;
 595         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 596
 597         return 0;
 598 }
 599
 600 static int
 601 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 602 {
 603         struct st_hba *hba;
 604         struct Scsi_Host *host;
 605         unsigned int id, lun;
 606         struct req_msg *req;
 607         u16 tag;
 608
 609         host = cmd->device->host;
 610         id = cmd->device->id;
 611         lun = cmd->device->lun;
 612         hba = (struct st_hba *) &host->hostdata[0];
 613         if (hba->mu_status == MU_STATE_NOCONNECT) {
 614                 cmd->result = DID_NO_CONNECT;
 615                 done(cmd);
 616                 return 0;
 617         }
 618         if (unlikely(hba->mu_status != MU_STATE_STARTED))
 619                 return SCSI_MLQUEUE_HOST_BUSY;
 620
 621         switch (cmd->cmnd[0]) {
 622         case MODE_SENSE_10:
 623         {
 624                 static char ms10_caching_page[12] =
 625                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 626                 unsigned char page;
 627
 628                 page = cmd->cmnd[2] & 0x3f;
 629                 if (page == 0x8 || page == 0x3f) {
 630                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 631                                                  sizeof(ms10_caching_page));
 632                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 633                         done(cmd);
 634                 } else
 635                         stex_invalid_field(cmd, done);
 636                 return 0;
 637         }
 638         case REPORT_LUNS:
 639                 /*
 640                  * The shasta firmware does not report actual luns in the
 641                  * target, so fail the command to force sequential lun scan.
 642                  * Also, the console device does not support this command.
 643                  */
 644                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 645                         stex_invalid_field(cmd, done);
 646                         return 0;
 647                 }
 648                 break;
 649         case TEST_UNIT_READY:
 650                 if (id == host->max_id - 1) {
 651                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 652                         done(cmd);
 653                         return 0;
 654                 }
 655                 break;
 656         case INQUIRY:
 657                 if (lun >= host->max_lun) {
 658                         cmd->result = DID_NO_CONNECT << 16;
 659                         done(cmd);
 660                         return 0;
 661                 }
 662                 if (id != host->max_id - 1)
 663                         break;
 664                 if (!lun && !cmd->device->channel &&
 665                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 666                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 667                                                  sizeof(console_inq_page));
 668                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 669                         done(cmd);
 670                 } else
 671                         stex_invalid_field(cmd, done);
 672                 return 0;
 673         case PASSTHRU_CMD:
 674                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 675                         const struct st_drvver ver = {
 676                                 .major = ST_VER_MAJOR,
 677                                 .minor = ST_VER_MINOR,
 678                                 .oem = ST_OEM,
 679                                 .build = ST_BUILD_VER,
 680                                 .signature[0] = PASSTHRU_SIGNATURE,
 681                                 .console_id = host->max_id - 1,
 682                                 .host_no = hba->host->host_no,
 683                         };
 684                         size_t cp_len = sizeof(ver);
 685
 686                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 687                         cmd->result = sizeof(ver) == cp_len ?
 688                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 689                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 690                         done(cmd);
 691                         return 0;
 692                 }
 693         default:
 694                 break;
 695         }
 696
 697         cmd->scsi_done = done;
 698
 699         tag = cmd->request->tag;
 700
 701         if (unlikely(tag >= host->can_queue))
 702                 return SCSI_MLQUEUE_HOST_BUSY;
 703
 704         req = hba->alloc_rq(hba);
 705
 706         req->lun = lun;
 707         req->target = id;
 708
 709         /* cdb */
 710         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 711
 712         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 713                 req->data_dir = MSG_DATA_DIR_IN;
 714         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 715                 req->data_dir = MSG_DATA_DIR_OUT;
 716         else
 717                 req->data_dir = MSG_DATA_DIR_ND;
 718
 719         hba->ccb[tag].cmd = cmd;
 720         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 721         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 722
 723         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 724                 hba->ccb[tag].sg_count = 0;
 725                 memset(&req->variable[0], 0, 8);
 726         }
 727
 728         hba->send(hba, req, tag);
 729         return 0;
 730 }
 731
 732 static DEF_SCSI_QCMD(stex_queuecommand)
 733
 734 static void stex_scsi_done(struct st_ccb *ccb)
 735 {
 736         struct scsi_cmnd *cmd = ccb->cmd;
 737         int result;
 738
 739         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 740                 result = ccb->scsi_status;
 741                 switch (ccb->scsi_status) {
 742                 case SAM_STAT_GOOD:
 743                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 744                         break;
 745                 case SAM_STAT_CHECK_CONDITION:
 746                         result |= DRIVER_SENSE << 24;
 747                         break;
 748                 case SAM_STAT_BUSY:
 749                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 750                         break;
 751                 default:
 752                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 753                         break;
 754                 }
 755         }
 756         else if (ccb->srb_status & SRB_SEE_SENSE)
 757                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 758         else switch (ccb->srb_status) {
 759                 case SRB_STATUS_SELECTION_TIMEOUT:
 760                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 761                         break;
 762                 case SRB_STATUS_BUSY:
 763                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 764                         break;
 765                 case SRB_STATUS_INVALID_REQUEST:
 766                 case SRB_STATUS_ERROR:
 767                 default:
 768                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 769                         break;
 770         }
 771
 772         cmd->result = result;
 773         cmd->scsi_done(cmd);
 774 }
 775
 776 static void stex_copy_data(struct st_ccb *ccb,
 777         struct status_msg *resp, unsigned int variable)
 778 {
 779         if (resp->scsi_status != SAM_STAT_GOOD) {
 780                 if (ccb->sense_buffer != NULL)
 781                         memcpy(ccb->sense_buffer, resp->variable,
 782                                 min(variable, ccb->sense_bufflen));
 783                 return;
 784         }
 785
 786         if (ccb->cmd == NULL)
 787                 return;
 788         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 789 }
 790
 791 static void stex_check_cmd(struct st_hba *hba,
 792         struct st_ccb *ccb, struct status_msg *resp)
 793 {
 794         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 795                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 796                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 797                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 798 }
 799
 800 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 801 {
 802         void __iomem *base = hba->mmio_base;
 803         struct status_msg *resp;
 804         struct st_ccb *ccb;
 805         unsigned int size;
 806         u16 tag;
 807
 808         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 809                 return;
 810
 811         /* status payloads */
 812         hba->status_head = readl(base + OMR1);
 813         if (unlikely(hba->status_head > hba->sts_count)) {
 814                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 815                         pci_name(hba->pdev));
 816                 return;
 817         }
 818
 819         /*
 820          * it's not a valid status payload if:
 821          * 1. there are no pending requests(e.g. during init stage)
 822          * 2. there are some pending requests, but the controller is in
 823          *     reset status, and its type is not st_yosemite
 824          * firmware of st_yosemite in reset status will return pending requests
 825          * to driver, so we allow it to pass
 826          */
 827         if (unlikely(hba->out_req_cnt <= 0 ||
 828                         (hba->mu_status == MU_STATE_RESETTING &&
 829                          hba->cardtype != st_yosemite))) {
 830                 hba->status_tail = hba->status_head;
 831                 goto update_status;
 832         }
 833
 834         while (hba->status_tail != hba->status_head) {
 835                 resp = stex_get_status(hba);
 836                 tag = le16_to_cpu(resp->tag);
 837                 if (unlikely(tag >= hba->host->can_queue)) {
 838                         printk(KERN_WARNING DRV_NAME
 839                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 840                         continue;
 841                 }
 842
 843                 hba->out_req_cnt--;
 844                 ccb = &hba->ccb[tag];
 845                 if (unlikely(hba->wait_ccb == ccb))
 846                         hba->wait_ccb = NULL;
 847                 if (unlikely(ccb->req == NULL)) {
 848                         printk(KERN_WARNING DRV_NAME
 849                                 "(%s): lagging req\n", pci_name(hba->pdev));
 850                         continue;
 851                 }
 852
 853                 size = resp->payload_sz * sizeof(u32); /* payload size */
 854                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 855                         size > sizeof(*resp))) {
 856                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 857                                 pci_name(hba->pdev));
 858                 } else {
 859                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 860                         if (size)
 861                                 stex_copy_data(ccb, resp, size);
 862                 }
 863
 864                 ccb->req = NULL;
 865                 ccb->srb_status = resp->srb_status;
 866                 ccb->scsi_status = resp->scsi_status;
 867
 868                 if (likely(ccb->cmd != NULL)) {
 869                         if (hba->cardtype == st_yosemite)
 870                                 stex_check_cmd(hba, ccb, resp);
 871
 872                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 873                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 874                                 stex_controller_info(hba, ccb);
 875
 876                         scsi_dma_unmap(ccb->cmd);
 877                         stex_scsi_done(ccb);
 878                 } else
 879                         ccb->req_type = 0;
 880         }
 881
 882 update_status:
 883         writel(hba->status_head, base + IMR1);
 884         readl(base + IMR1); /* flush */
 885 }
 886
 887 static irqreturn_t stex_intr(int irq, void *__hba)
 888 {
 889         struct st_hba *hba = __hba;
 890         void __iomem *base = hba->mmio_base;
 891         u32 data;
 892         unsigned long flags;
 893
 894         spin_lock_irqsave(hba->host->host_lock, flags);
 895
 896         data = readl(base + ODBL);
 897
 898         if (data && data != 0xffffffff) {
 899                 /* clear the interrupt */
 900                 writel(data, base + ODBL);
 901                 readl(base + ODBL); /* flush */
 902                 stex_mu_intr(hba, data);
 903                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 904                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 905                         hba->cardtype == st_shasta))
 906                         queue_work(hba->work_q, &hba->reset_work);
 907                 return IRQ_HANDLED;
 908         }
 909
 910         spin_unlock_irqrestore(hba->host->host_lock, flags);
 911
 912         return IRQ_NONE;
 913 }
 914
 915 static void stex_ss_mu_intr(struct st_hba *hba)
 916 {
 917         struct status_msg *resp;
 918         struct st_ccb *ccb;
 919         __le32 *scratch;
 920         unsigned int size;
 921         int count = 0;
 922         u32 value;
 923         u16 tag;
 924
 925         if (unlikely(hba->out_req_cnt <= 0 ||
 926                         hba->mu_status == MU_STATE_RESETTING))
 927                 return;
 928
 929         while (count < hba->sts_count) {
 930                 scratch = hba->scratch + hba->status_tail;
 931                 value = le32_to_cpu(*scratch);
 932                 if (unlikely(!(value & SS_STS_NORMAL)))
 933                         return;
 934
 935                 resp = hba->status_buffer + hba->status_tail;
 936                 *scratch = 0;
 937                 ++count;
 938                 ++hba->status_tail;
 939                 hba->status_tail %= hba->sts_count+1;
 940
 941                 tag = (u16)value;
 942                 if (unlikely(tag >= hba->host->can_queue)) {
 943                         printk(KERN_WARNING DRV_NAME
 944                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 945                         continue;
 946                 }
 947
 948                 hba->out_req_cnt--;
 949                 ccb = &hba->ccb[tag];
 950                 if (unlikely(hba->wait_ccb == ccb))
 951                         hba->wait_ccb = NULL;
 952                 if (unlikely(ccb->req == NULL)) {
 953                         printk(KERN_WARNING DRV_NAME
 954                                 "(%s): lagging req\n", pci_name(hba->pdev));
 955                         continue;
 956                 }
 957
 958                 ccb->req = NULL;
 959                 if (likely(value & SS_STS_DONE)) { /* normal case */
 960                         ccb->srb_status = SRB_STATUS_SUCCESS;
 961                         ccb->scsi_status = SAM_STAT_GOOD;
 962                 } else {
 963                         ccb->srb_status = resp->srb_status;
 964                         ccb->scsi_status = resp->scsi_status;
 965                         size = resp->payload_sz * sizeof(u32);
 966                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 967                                 size > sizeof(*resp))) {
 968                                 printk(KERN_WARNING DRV_NAME
 969                                         "(%s): bad status size\n",
 970                                         pci_name(hba->pdev));
 971                         } else {
 972                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 973                                 if (size)
 974                                         stex_copy_data(ccb, resp, size);
 975                         }
 976                         if (likely(ccb->cmd != NULL))
 977                                 stex_check_cmd(hba, ccb, resp);
 978                 }
 979
 980                 if (likely(ccb->cmd != NULL)) {
 981                         scsi_dma_unmap(ccb->cmd);
 982                         stex_scsi_done(ccb);
 983                 } else
 984                         ccb->req_type = 0;
 985         }
 986 }
 987
 988 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 989 {
 990         struct st_hba *hba = __hba;
 991         void __iomem *base = hba->mmio_base;
 992         u32 data;
 993         unsigned long flags;
 994
 995         spin_lock_irqsave(hba->host->host_lock, flags);
 996
 997         if (hba->cardtype == st_yel) {
 998                 data = readl(base + YI2H_INT);
 999                 if (data && data != 0xffffffff) {
1000                         /* clear the interrupt */
1001                         writel(data, base + YI2H_INT_C);
1002                         stex_ss_mu_intr(hba);
1003                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1004                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1005                                 queue_work(hba->work_q, &hba->reset_work);
1006                         return IRQ_HANDLED;
1007                 }
1008         } else {
1009                 data = readl(base + PSCRATCH4);
1010                 if (data != 0xffffffff) {
1011                         if (data != 0) {
1012                                 /* clear the interrupt */
1013                                 writel(data, base + PSCRATCH1);
1014                                 writel((1 << 22), base + YH2I_INT);
1015                         }
1016                         stex_ss_mu_intr(hba);
1017                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1018                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1019                                 queue_work(hba->work_q, &hba->reset_work);
1020                         return IRQ_HANDLED;
1021                 }
1022         }
1023
1024         spin_unlock_irqrestore(hba->host->host_lock, flags);
1025
1026         return IRQ_NONE;
1027 }
1028
1029 static int stex_common_handshake(struct st_hba *hba)
1030 {
1031         void __iomem *base = hba->mmio_base;
1032         struct handshake_frame *h;
1033         dma_addr_t status_phys;
1034         u32 data;
1035         unsigned long before;
1036
1037         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1038                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1039                 readl(base + IDBL);
1040                 before = jiffies;
1041                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1042                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1043                                 printk(KERN_ERR DRV_NAME
1044                                         "(%s): no handshake signature\n",
1045                                         pci_name(hba->pdev));
1046                                 return -1;
1047                         }
1048                         rmb();
1049                         msleep(1);
1050                 }
1051         }
1052
1053         udelay(10);
1054
1055         data = readl(base + OMR1);
1056         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1057                 data &= 0x0000ffff;
1058                 if (hba->host->can_queue > data) {
1059                         hba->host->can_queue = data;
1060                         hba->host->cmd_per_lun = data;
1061                 }
1062         }
1063
1064         h = (struct handshake_frame *)hba->status_buffer;
1065         h->rb_phy = cpu_to_le64(hba->dma_handle);
1066         h->req_sz = cpu_to_le16(hba->rq_size);
1067         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1068         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1069         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1070         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1071         h->partner_type = HMU_PARTNER_TYPE;
1072         if (hba->extra_offset) {
1073                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1074                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1075         } else
1076                 h->extra_offset = h->extra_size = 0;
1077
1078         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1079         writel(status_phys, base + IMR0);
1080         readl(base + IMR0);
1081         writel((status_phys >> 16) >> 16, base + IMR1);
1082         readl(base + IMR1);
1083
1084         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1085         readl(base + OMR0);
1086         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1087         readl(base + IDBL); /* flush */
1088
1089         udelay(10);
1090         before = jiffies;
1091         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1092                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1093                         printk(KERN_ERR DRV_NAME
1094                                 "(%s): no signature after handshake frame\n",
1095                                 pci_name(hba->pdev));
1096                         return -1;
1097                 }
1098                 rmb();
1099                 msleep(1);
1100         }
1101
1102         writel(0, base + IMR0);
1103         readl(base + IMR0);
1104         writel(0, base + OMR0);
1105         readl(base + OMR0);
1106         writel(0, base + IMR1);
1107         readl(base + IMR1);
1108         writel(0, base + OMR1);
1109         readl(base + OMR1); /* flush */
1110         return 0;
1111 }
1112
1113 static int stex_ss_handshake(struct st_hba *hba)
1114 {
1115         void __iomem *base = hba->mmio_base;
1116         struct st_msg_header *msg_h;
1117         struct handshake_frame *h;
1118         __le32 *scratch;
1119         u32 data, scratch_size, mailboxdata, operationaldata;
1120         unsigned long before;
1121         int ret = 0;
1122
1123         before = jiffies;
1124
1125         if (hba->cardtype == st_yel) {
1126                 operationaldata = readl(base + YIOA_STATUS);
1127                 while (operationaldata != SS_MU_OPERATIONAL) {
1128                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1129                                 printk(KERN_ERR DRV_NAME
1130                                         "(%s): firmware not operational\n",
1131                                         pci_name(hba->pdev));
1132                                 return -1;
1133                         }
1134                         msleep(1);
1135                         operationaldata = readl(base + YIOA_STATUS);
1136                 }
1137         } else {
1138                 operationaldata = readl(base + PSCRATCH3);
1139                 while (operationaldata != SS_MU_OPERATIONAL) {
1140                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1141                                 printk(KERN_ERR DRV_NAME
1142                                         "(%s): firmware not operational\n",
1143                                         pci_name(hba->pdev));
1144                                 return -1;
1145                         }
1146                         msleep(1);
1147                         operationaldata = readl(base + PSCRATCH3);
1148                 }
1149         }
1150
1151         msg_h = (struct st_msg_header *)hba->dma_mem;
1152         msg_h->handle = cpu_to_le64(hba->dma_handle);
1153         msg_h->flag = SS_HEAD_HANDSHAKE;
1154
1155         h = (struct handshake_frame *)(msg_h + 1);
1156         h->rb_phy = cpu_to_le64(hba->dma_handle);
1157         h->req_sz = cpu_to_le16(hba->rq_size);
1158         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1159         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1160         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1161         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1162         h->partner_type = HMU_PARTNER_TYPE;
1163         h->extra_offset = h->extra_size = 0;
1164         scratch_size = (hba->sts_count+1)*sizeof(u32);
1165         h->scratch_size = cpu_to_le32(scratch_size);
1166
1167         if (hba->cardtype == st_yel) {
1168                 data = readl(base + YINT_EN);
1169                 data &= ~4;
1170                 writel(data, base + YINT_EN);
1171                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1172                 readl(base + YH2I_REQ_HI);
1173                 writel(hba->dma_handle, base + YH2I_REQ);
1174                 readl(base + YH2I_REQ); /* flush */
1175         } else {
1176                 data = readl(base + YINT_EN);
1177                 data &= ~(1 << 0);
1178                 data &= ~(1 << 2);
1179                 writel(data, base + YINT_EN);
1180                 if (hba->msi_lock == 0) {
1181                         /* P3 MSI Register cannot access twice */
1182                         writel((1 << 6), base + YH2I_INT);
1183                         hba->msi_lock  = 1;
1184                 }
1185                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1186                 writel(hba->dma_handle, base + YH2I_REQ);
1187         }
1188
1189         before = jiffies;
1190         scratch = hba->scratch;
1191         if (hba->cardtype == st_yel) {
1192                 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1193                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1194                                 printk(KERN_ERR DRV_NAME
1195                                         "(%s): no signature after handshake frame\n",
1196                                         pci_name(hba->pdev));
1197                                 ret = -1;
1198                                 break;
1199                         }
1200                         rmb();
1201                         msleep(1);
1202                 }
1203         } else {
1204                 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1205                 while (mailboxdata != SS_STS_HANDSHAKE) {
1206                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1207                                 printk(KERN_ERR DRV_NAME
1208                                         "(%s): no signature after handshake frame\n",
1209                                         pci_name(hba->pdev));
1210                                 ret = -1;
1211                                 break;
1212                         }
1213                         rmb();
1214                         msleep(1);
1215                         mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1216                 }
1217         }
1218         memset(scratch, 0, scratch_size);
1219         msg_h->flag = 0;
1220
1221         return ret;
1222 }
1223
1224 static int stex_handshake(struct st_hba *hba)
1225 {
1226         int err;
1227         unsigned long flags;
1228         unsigned int mu_status;
1229
1230         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1231                 err = stex_ss_handshake(hba);
1232         else
1233                 err = stex_common_handshake(hba);
1234         spin_lock_irqsave(hba->host->host_lock, flags);
1235         mu_status = hba->mu_status;
1236         if (err == 0) {
1237                 hba->req_head = 0;
1238                 hba->req_tail = 0;
1239                 hba->status_head = 0;
1240                 hba->status_tail = 0;
1241                 hba->out_req_cnt = 0;
1242                 hba->mu_status = MU_STATE_STARTED;
1243         } else
1244                 hba->mu_status = MU_STATE_FAILED;
1245         if (mu_status == MU_STATE_RESETTING)
1246                 wake_up_all(&hba->reset_waitq);
1247         spin_unlock_irqrestore(hba->host->host_lock, flags);
1248         return err;
1249 }
1250
1251 static int stex_abort(struct scsi_cmnd *cmd)
1252 {
1253         struct Scsi_Host *host = cmd->device->host;
1254         struct st_hba *hba = (struct st_hba *)host->hostdata;
1255         u16 tag = cmd->request->tag;
1256         void __iomem *base;
1257         u32 data;
1258         int result = SUCCESS;
1259         unsigned long flags;
1260
1261         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1262
1263         base = hba->mmio_base;
1264         spin_lock_irqsave(host->host_lock, flags);
1265         if (tag < host->can_queue &&
1266                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1267                 hba->wait_ccb = &hba->ccb[tag];
1268         else
1269                 goto out;
1270
1271         if (hba->cardtype == st_yel) {
1272                 data = readl(base + YI2H_INT);
1273                 if (data == 0 || data == 0xffffffff)
1274                         goto fail_out;
1275
1276                 writel(data, base + YI2H_INT_C);
1277                 stex_ss_mu_intr(hba);
1278         } else if (hba->cardtype == st_P3) {
1279                 data = readl(base + PSCRATCH4);
1280                 if (data == 0xffffffff)
1281                         goto fail_out;
1282                 if (data != 0) {
1283                         writel(data, base + PSCRATCH1);
1284                         writel((1 << 22), base + YH2I_INT);
1285                 }
1286                 stex_ss_mu_intr(hba);
1287         } else {
1288                 data = readl(base + ODBL);
1289                 if (data == 0 || data == 0xffffffff)
1290                         goto fail_out;
1291
1292                 writel(data, base + ODBL);
1293                 readl(base + ODBL); /* flush */
1294                 stex_mu_intr(hba, data);
1295         }
1296         if (hba->wait_ccb == NULL) {
1297                 printk(KERN_WARNING DRV_NAME
1298                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1299                 goto out;
1300         }
1301
1302 fail_out:
1303         scsi_dma_unmap(cmd);
1304         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1305         hba->wait_ccb = NULL;
1306         result = FAILED;
1307 out:
1308         spin_unlock_irqrestore(host->host_lock, flags);
1309         return result;
1310 }
1311
1312 static void stex_hard_reset(struct st_hba *hba)
1313 {
1314         struct pci_bus *bus;
1315         int i;
1316         u16 pci_cmd;
1317         u8 pci_bctl;
1318
1319         for (i = 0; i < 16; i++)
1320                 pci_read_config_dword(hba->pdev, i * 4,
1321                         &hba->pdev->saved_config_space[i]);
1322
1323         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1324            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1325         bus = hba->pdev->bus;
1326         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1327         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1328         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1329
1330         /*
1331          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1332          * require more time to finish bus reset. Use 100 ms here for safety
1333          */
1334         msleep(100);
1335         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1336         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1337
1338         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1339                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1340                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1341                         break;
1342                 msleep(1);
1343         }
1344
1345         ssleep(5);
1346         for (i = 0; i < 16; i++)
1347                 pci_write_config_dword(hba->pdev, i * 4,
1348                         hba->pdev->saved_config_space[i]);
1349 }
1350
1351 static int stex_yos_reset(struct st_hba *hba)
1352 {
1353         void __iomem *base;
1354         unsigned long flags, before;
1355         int ret = 0;
1356
1357         base = hba->mmio_base;
1358         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1359         readl(base + IDBL); /* flush */
1360         before = jiffies;
1361         while (hba->out_req_cnt > 0) {
1362                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1363                         printk(KERN_WARNING DRV_NAME
1364                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1365                         ret = -1;
1366                         break;
1367                 }
1368                 msleep(1);
1369         }
1370
1371         spin_lock_irqsave(hba->host->host_lock, flags);
1372         if (ret == -1)
1373                 hba->mu_status = MU_STATE_FAILED;
1374         else
1375                 hba->mu_status = MU_STATE_STARTED;
1376         wake_up_all(&hba->reset_waitq);
1377         spin_unlock_irqrestore(hba->host->host_lock, flags);
1378
1379         return ret;
1380 }
1381
1382 static void stex_ss_reset(struct st_hba *hba)
1383 {
1384         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1385         readl(hba->mmio_base + YH2I_INT);
1386         ssleep(5);
1387 }
1388
1389 static void stex_p3_reset(struct st_hba *hba)
1390 {
1391         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1392         ssleep(5);
1393 }
1394
1395 static int stex_do_reset(struct st_hba *hba)
1396 {
1397         unsigned long flags;
1398         unsigned int mu_status = MU_STATE_RESETTING;
1399
1400         spin_lock_irqsave(hba->host->host_lock, flags);
1401         if (hba->mu_status == MU_STATE_STARTING) {
1402                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1403                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1404                         pci_name(hba->pdev));
1405                 return 0;
1406         }
1407         while (hba->mu_status == MU_STATE_RESETTING) {
1408                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1409                 wait_event_timeout(hba->reset_waitq,
1410                                    hba->mu_status != MU_STATE_RESETTING,
1411                                    MU_MAX_DELAY * HZ);
1412                 spin_lock_irqsave(hba->host->host_lock, flags);
1413                 mu_status = hba->mu_status;
1414         }
1415
1416         if (mu_status != MU_STATE_RESETTING) {
1417                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1418                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1419         }
1420
1421         hba->mu_status = MU_STATE_RESETTING;
1422         spin_unlock_irqrestore(hba->host->host_lock, flags);
1423
1424         if (hba->cardtype == st_yosemite)
1425                 return stex_yos_reset(hba);
1426
1427         if (hba->cardtype == st_shasta)
1428                 stex_hard_reset(hba);
1429         else if (hba->cardtype == st_yel)
1430                 stex_ss_reset(hba);
1431         else if (hba->cardtype == st_P3)
1432                 stex_p3_reset(hba);
1433
1434         return_abnormal_state(hba, DID_RESET);
1435
1436         if (stex_handshake(hba) == 0)
1437                 return 0;
1438
1439         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1440                 pci_name(hba->pdev));
1441         return -1;
1442 }
1443
1444 static int stex_reset(struct scsi_cmnd *cmd)
1445 {
1446         struct st_hba *hba;
1447
1448         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1449
1450         shost_printk(KERN_INFO, cmd->device->host,
1451                      "resetting host\n");
1452
1453         return stex_do_reset(hba) ? FAILED : SUCCESS;
1454 }
1455
1456 static void stex_reset_work(struct work_struct *work)
1457 {
1458         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1459
1460         stex_do_reset(hba);
1461 }
1462
1463 static int stex_biosparam(struct scsi_device *sdev,
1464         struct block_device *bdev, sector_t capacity, int geom[])
1465 {
1466         int heads = 255, sectors = 63;
1467
1468         if (capacity < 0x200000) {
1469                 heads = 64;
1470                 sectors = 32;
1471         }
1472
1473         sector_div(capacity, heads * sectors);
1474
1475         geom[0] = heads;
1476         geom[1] = sectors;
1477         geom[2] = capacity;
1478
1479         return 0;
1480 }
1481
1482 static struct scsi_host_template driver_template = {
1483         .module                         = THIS_MODULE,
1484         .name                           = DRV_NAME,
1485         .proc_name                      = DRV_NAME,
1486         .bios_param                     = stex_biosparam,
1487         .queuecommand                   = stex_queuecommand,
1488         .slave_configure                = stex_slave_config,
1489         .eh_abort_handler               = stex_abort,
1490         .eh_host_reset_handler          = stex_reset,
1491         .this_id                        = -1,
1492         .dma_boundary                   = PAGE_SIZE - 1,
1493 };
1494
1495 static struct pci_device_id stex_pci_tbl[] = {
1496         /* st_shasta */
1497         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1498                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1499         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1500                 st_shasta }, /* SuperTrak EX12350 */
1501         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1502                 st_shasta }, /* SuperTrak EX4350 */
1503         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1504                 st_shasta }, /* SuperTrak EX24350 */
1505
1506         /* st_vsc */
1507         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1508
1509         /* st_yosemite */
1510         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1511
1512         /* st_seq */
1513         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1514
1515         /* st_yel */
1516         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1517         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1518
1519         /* st_P3, pluto */
1520         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1521                 0x8870, 0, 0, st_P3 },
1522         /* st_P3, p3 */
1523         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1524                 0x4300, 0, 0, st_P3 },
1525
1526         /* st_P3, SymplyStor4E */
1527         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1528                 0x4311, 0, 0, st_P3 },
1529         /* st_P3, SymplyStor8E */
1530         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1531                 0x4312, 0, 0, st_P3 },
1532         /* st_P3, SymplyStor4 */
1533         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1534                 0x4321, 0, 0, st_P3 },
1535         /* st_P3, SymplyStor8 */
1536         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1537                 0x4322, 0, 0, st_P3 },
1538         { }     /* terminate list */
1539 };
1540
1541 static struct st_card_info stex_card_info[] = {
1542         /* st_shasta */
1543         {
1544                 .max_id         = 17,
1545                 .max_lun        = 8,
1546                 .max_channel    = 0,
1547                 .rq_count       = 32,
1548                 .rq_size        = 1048,
1549                 .sts_count      = 32,
1550                 .alloc_rq       = stex_alloc_req,
1551                 .map_sg         = stex_map_sg,
1552                 .send           = stex_send_cmd,
1553         },
1554
1555         /* st_vsc */
1556         {
1557                 .max_id         = 129,
1558                 .max_lun        = 1,
1559                 .max_channel    = 0,
1560                 .rq_count       = 32,
1561                 .rq_size        = 1048,
1562                 .sts_count      = 32,
1563                 .alloc_rq       = stex_alloc_req,
1564                 .map_sg         = stex_map_sg,
1565                 .send           = stex_send_cmd,
1566         },
1567
1568         /* st_yosemite */
1569         {
1570                 .max_id         = 2,
1571                 .max_lun        = 256,
1572                 .max_channel    = 0,
1573                 .rq_count       = 256,
1574                 .rq_size        = 1048,
1575                 .sts_count      = 256,
1576                 .alloc_rq       = stex_alloc_req,
1577                 .map_sg         = stex_map_sg,
1578                 .send           = stex_send_cmd,
1579         },
1580
1581         /* st_seq */
1582         {
1583                 .max_id         = 129,
1584                 .max_lun        = 1,
1585                 .max_channel    = 0,
1586                 .rq_count       = 32,
1587                 .rq_size        = 1048,
1588                 .sts_count      = 32,
1589                 .alloc_rq       = stex_alloc_req,
1590                 .map_sg         = stex_map_sg,
1591                 .send           = stex_send_cmd,
1592         },
1593
1594         /* st_yel */
1595         {
1596                 .max_id         = 129,
1597                 .max_lun        = 256,
1598                 .max_channel    = 3,
1599                 .rq_count       = 801,
1600                 .rq_size        = 512,
1601                 .sts_count      = 801,
1602                 .alloc_rq       = stex_ss_alloc_req,
1603                 .map_sg         = stex_ss_map_sg,
1604                 .send           = stex_ss_send_cmd,
1605         },
1606
1607         /* st_P3 */
1608         {
1609                 .max_id         = 129,
1610                 .max_lun        = 256,
1611                 .max_channel    = 0,
1612                 .rq_count       = 801,
1613                 .rq_size        = 512,
1614                 .sts_count      = 801,
1615                 .alloc_rq       = stex_ss_alloc_req,
1616                 .map_sg         = stex_ss_map_sg,
1617                 .send           = stex_ss_send_cmd,
1618         },
1619 };
1620
1621 static int stex_request_irq(struct st_hba *hba)
1622 {
1623         struct pci_dev *pdev = hba->pdev;
1624         int status;
1625
1626         if (msi || hba->cardtype == st_P3) {
1627                 status = pci_enable_msi(pdev);
1628                 if (status != 0)
1629                         printk(KERN_ERR DRV_NAME
1630                                 "(%s): error %d setting up MSI\n",
1631                                 pci_name(pdev), status);
1632                 else
1633                         hba->msi_enabled = 1;
1634         } else
1635                 hba->msi_enabled = 0;
1636
1637         status = request_irq(pdev->irq,
1638                 (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1639                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1640
1641         if (status != 0) {
1642                 if (hba->msi_enabled)
1643                         pci_disable_msi(pdev);
1644         }
1645         return status;
1646 }
1647
1648 static void stex_free_irq(struct st_hba *hba)
1649 {
1650         struct pci_dev *pdev = hba->pdev;
1651
1652         free_irq(pdev->irq, hba);
1653         if (hba->msi_enabled)
1654                 pci_disable_msi(pdev);
1655 }
1656
1657 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1658 {
1659         struct st_hba *hba;
1660         struct Scsi_Host *host;
1661         const struct st_card_info *ci = NULL;
1662         u32 sts_offset, cp_offset, scratch_offset;
1663         int err;
1664
1665         err = pci_enable_device(pdev);
1666         if (err)
1667                 return err;
1668
1669         pci_set_master(pdev);
1670
1671         S6flag = 0;
1672         register_reboot_notifier(&stex_notifier);
1673
1674         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1675
1676         if (!host) {
1677                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1678                         pci_name(pdev));
1679                 err = -ENOMEM;
1680                 goto out_disable;
1681         }
1682
1683         hba = (struct st_hba *)host->hostdata;
1684         memset(hba, 0, sizeof(struct st_hba));
1685
1686         err = pci_request_regions(pdev, DRV_NAME);
1687         if (err < 0) {
1688                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1689                         pci_name(pdev));
1690                 goto out_scsi_host_put;
1691         }
1692
1693         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1694         if ( !hba->mmio_base) {
1695                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1696                         pci_name(pdev));
1697                 err = -ENOMEM;
1698                 goto out_release_regions;
1699         }
1700
1701         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1702         if (err)
1703                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1704         if (err) {
1705                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1706                         pci_name(pdev));
1707                 goto out_iounmap;
1708         }
1709
1710         hba->cardtype = (unsigned int) id->driver_data;
1711         ci = &stex_card_info[hba->cardtype];
1712         switch (id->subdevice) {
1713         case 0x4221:
1714         case 0x4222:
1715         case 0x4223:
1716         case 0x4224:
1717         case 0x4225:
1718         case 0x4226:
1719         case 0x4227:
1720         case 0x4261:
1721         case 0x4262:
1722         case 0x4263:
1723         case 0x4264:
1724         case 0x4265:
1725                 break;
1726         default:
1727                 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1728                         hba->supports_pm = 1;
1729         }
1730
1731         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1732         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1733                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1734         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1735         hba->dma_size = cp_offset + sizeof(struct st_frame);
1736         if (hba->cardtype == st_seq ||
1737                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1738                 hba->extra_offset = hba->dma_size;
1739                 hba->dma_size += ST_ADDITIONAL_MEM;
1740         }
1741         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1742                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1743         if (!hba->dma_mem) {
1744                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1745                 if (hba->cardtype == st_seq ||
1746                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1747                         printk(KERN_WARNING DRV_NAME
1748                                 "(%s): allocating min buffer for controller\n",
1749                                 pci_name(pdev));
1750                         hba->dma_size = hba->extra_offset
1751                                 + ST_ADDITIONAL_MEM_MIN;
1752                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1753                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1754                 }
1755
1756                 if (!hba->dma_mem) {
1757                         err = -ENOMEM;
1758                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1759                                 pci_name(pdev));
1760                         goto out_iounmap;
1761                 }
1762         }
1763
1764         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1765         if (!hba->ccb) {
1766                 err = -ENOMEM;
1767                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1768                         pci_name(pdev));
1769                 goto out_pci_free;
1770         }
1771
1772         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1773                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1774         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1775         hba->copy_buffer = hba->dma_mem + cp_offset;
1776         hba->rq_count = ci->rq_count;
1777         hba->rq_size = ci->rq_size;
1778         hba->sts_count = ci->sts_count;
1779         hba->alloc_rq = ci->alloc_rq;
1780         hba->map_sg = ci->map_sg;
1781         hba->send = ci->send;
1782         hba->mu_status = MU_STATE_STARTING;
1783         hba->msi_lock = 0;
1784
1785         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1786                 host->sg_tablesize = 38;
1787         else
1788                 host->sg_tablesize = 32;
1789         host->can_queue = ci->rq_count;
1790         host->cmd_per_lun = ci->rq_count;
1791         host->max_id = ci->max_id;
1792         host->max_lun = ci->max_lun;
1793         host->max_channel = ci->max_channel;
1794         host->unique_id = host->host_no;
1795         host->max_cmd_len = STEX_CDB_LENGTH;
1796
1797         hba->host = host;
1798         hba->pdev = pdev;
1799         init_waitqueue_head(&hba->reset_waitq);
1800
1801         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1802                  "stex_wq_%d", host->host_no);
1803         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1804         if (!hba->work_q) {
1805                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1806                         pci_name(pdev));
1807                 err = -ENOMEM;
1808                 goto out_ccb_free;
1809         }
1810         INIT_WORK(&hba->reset_work, stex_reset_work);
1811
1812         err = stex_request_irq(hba);
1813         if (err) {
1814                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1815                         pci_name(pdev));
1816                 goto out_free_wq;
1817         }
1818
1819         err = stex_handshake(hba);
1820         if (err)
1821                 goto out_free_irq;
1822
1823         pci_set_drvdata(pdev, hba);
1824
1825         err = scsi_add_host(host, &pdev->dev);
1826         if (err) {
1827                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1828                         pci_name(pdev));
1829                 goto out_free_irq;
1830         }
1831
1832         scsi_scan_host(host);
1833
1834         return 0;
1835
1836 out_free_irq:
1837         stex_free_irq(hba);
1838 out_free_wq:
1839         destroy_workqueue(hba->work_q);
1840 out_ccb_free:
1841         kfree(hba->ccb);
1842 out_pci_free:
1843         dma_free_coherent(&pdev->dev, hba->dma_size,
1844                           hba->dma_mem, hba->dma_handle);
1845 out_iounmap:
1846         iounmap(hba->mmio_base);
1847 out_release_regions:
1848         pci_release_regions(pdev);
1849 out_scsi_host_put:
1850         scsi_host_put(host);
1851 out_disable:
1852         pci_disable_device(pdev);
1853
1854         return err;
1855 }
1856
1857 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1858 {
1859         struct req_msg *req;
1860         struct st_msg_header *msg_h;
1861         unsigned long flags;
1862         unsigned long before;
1863         u16 tag = 0;
1864
1865         spin_lock_irqsave(hba->host->host_lock, flags);
1866
1867         if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1868                 hba->supports_pm == 1) {
1869                 if (st_sleep_mic == ST_NOTHANDLED) {
1870                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1871                         return;
1872                 }
1873         }
1874         req = hba->alloc_rq(hba);
1875         if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1876                 msg_h = (struct st_msg_header *)req - 1;
1877                 memset(msg_h, 0, hba->rq_size);
1878         } else
1879                 memset(req, 0, hba->rq_size);
1880
1881         if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1882                 || hba->cardtype == st_P3)
1883                 && st_sleep_mic == ST_IGNORED) {
1884                 req->cdb[0] = MGT_CMD;
1885                 req->cdb[1] = MGT_CMD_SIGNATURE;
1886                 req->cdb[2] = CTLR_CONFIG_CMD;
1887                 req->cdb[3] = CTLR_SHUTDOWN;
1888         } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1889                 && st_sleep_mic != ST_IGNORED) {
1890                 req->cdb[0] = MGT_CMD;
1891                 req->cdb[1] = MGT_CMD_SIGNATURE;
1892                 req->cdb[2] = CTLR_CONFIG_CMD;
1893                 req->cdb[3] = PMIC_SHUTDOWN;
1894                 req->cdb[4] = st_sleep_mic;
1895         } else {
1896                 req->cdb[0] = CONTROLLER_CMD;
1897                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1898                 req->cdb[2] = CTLR_POWER_SAVING;
1899         }
1900         hba->ccb[tag].cmd = NULL;
1901         hba->ccb[tag].sg_count = 0;
1902         hba->ccb[tag].sense_bufflen = 0;
1903         hba->ccb[tag].sense_buffer = NULL;
1904         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1905         hba->send(hba, req, tag);
1906         spin_unlock_irqrestore(hba->host->host_lock, flags);
1907         before = jiffies;
1908         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1909                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1910                         hba->ccb[tag].req_type = 0;
1911                         hba->mu_status = MU_STATE_STOP;
1912                         return;
1913                 }
1914                 msleep(1);
1915         }
1916         hba->mu_status = MU_STATE_STOP;
1917 }
1918
1919 static void stex_hba_free(struct st_hba *hba)
1920 {
1921         stex_free_irq(hba);
1922
1923         destroy_workqueue(hba->work_q);
1924
1925         iounmap(hba->mmio_base);
1926
1927         pci_release_regions(hba->pdev);
1928
1929         kfree(hba->ccb);
1930
1931         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1932                           hba->dma_mem, hba->dma_handle);
1933 }
1934
1935 static void stex_remove(struct pci_dev *pdev)
1936 {
1937         struct st_hba *hba = pci_get_drvdata(pdev);
1938
1939         hba->mu_status = MU_STATE_NOCONNECT;
1940         return_abnormal_state(hba, DID_NO_CONNECT);
1941         scsi_remove_host(hba->host);
1942
1943         scsi_block_requests(hba->host);
1944
1945         stex_hba_free(hba);
1946
1947         scsi_host_put(hba->host);
1948
1949         pci_disable_device(pdev);
1950
1951         unregister_reboot_notifier(&stex_notifier);
1952 }
1953
1954 static void stex_shutdown(struct pci_dev *pdev)
1955 {
1956         struct st_hba *hba = pci_get_drvdata(pdev);
1957
1958         if (hba->supports_pm == 0) {
1959                 stex_hba_stop(hba, ST_IGNORED);
1960         } else if (hba->supports_pm == 1 && S6flag) {
1961                 unregister_reboot_notifier(&stex_notifier);
1962                 stex_hba_stop(hba, ST_S6);
1963         } else
1964                 stex_hba_stop(hba, ST_S5);
1965 }
1966
1967 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1968 {
1969         switch (state.event) {
1970         case PM_EVENT_SUSPEND:
1971                 return ST_S3;
1972         case PM_EVENT_HIBERNATE:
1973                 hba->msi_lock = 0;
1974                 return ST_S4;
1975         default:
1976                 return ST_NOTHANDLED;
1977         }
1978 }
1979
1980 static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1981 {
1982         struct st_hba *hba = pci_get_drvdata(pdev);
1983
1984         if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1985                 && hba->supports_pm == 1)
1986                 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
1987         else
1988                 stex_hba_stop(hba, ST_IGNORED);
1989         return 0;
1990 }
1991
1992 static int stex_resume(struct pci_dev *pdev)
1993 {
1994         struct st_hba *hba = pci_get_drvdata(pdev);
1995
1996         hba->mu_status = MU_STATE_STARTING;
1997         stex_handshake(hba);
1998         return 0;
1999 }
2000
2001 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
2002 {
2003         S6flag = 1;
2004         return NOTIFY_OK;
2005 }
2006 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
2007
2008 static struct pci_driver stex_pci_driver = {
2009         .name           = DRV_NAME,
2010         .id_table       = stex_pci_tbl,
2011         .probe          = stex_probe,
2012         .remove         = stex_remove,
2013         .shutdown       = stex_shutdown,
2014         .suspend        = stex_suspend,
2015         .resume         = stex_resume,
2016 };
2017
2018 static int __init stex_init(void)
2019 {
2020         printk(KERN_INFO DRV_NAME
2021                 ": Promise SuperTrak EX Driver version: %s\n",
2022                  ST_DRIVER_VERSION);
2023
2024         return pci_register_driver(&stex_pci_driver);
2025 }
2026
2027 static void __exit stex_exit(void)
2028 {
2029         pci_unregister_driver(&stex_pci_driver);
2030 }
2031
2032 module_init(stex_init);
2033 module_exit(stex_exit);