drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2015 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/ktime.h>
  29 #include <linux/reboot.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/byteorder.h>
  33 #include <scsi/scsi.h>
  34 #include <scsi/scsi_device.h>
  35 #include <scsi/scsi_cmnd.h>
  36 #include <scsi/scsi_host.h>
  37 #include <scsi/scsi_tcq.h>
  38 #include <scsi/scsi_dbg.h>
  39 #include <scsi/scsi_eh.h>
  40
  41 #define DRV_NAME "stex"
  42 #define ST_DRIVER_VERSION       "6.02.0000.01"
  43 #define ST_VER_MAJOR            6
  44 #define ST_VER_MINOR            02
  45 #define ST_OEM                          0000
  46 #define ST_BUILD_VER            01
  47
  48 enum {
  49         /* MU register offset */
  50         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  51         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  52         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  53         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  54         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  55         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  56         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  57         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  58         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  59         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  60
  61         YIOA_STATUS                             = 0x00,
  62         YH2I_INT                                = 0x20,
  63         YINT_EN                                 = 0x34,
  64         YI2H_INT                                = 0x9c,
  65         YI2H_INT_C                              = 0xa0,
  66         YH2I_REQ                                = 0xc0,
  67         YH2I_REQ_HI                             = 0xc4,
  68         PSCRATCH0                               = 0xb0,
  69         PSCRATCH1                               = 0xb4,
  70         PSCRATCH2                               = 0xb8,
  71         PSCRATCH3                               = 0xbc,
  72         PSCRATCH4                               = 0xc8,
  73         MAILBOX_BASE                    = 0x1000,
  74         MAILBOX_HNDSHK_STS              = 0x0,
  75
  76         /* MU register value */
  77         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  78         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  79         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  80         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  81         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  82
  83         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  84         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  85         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  86         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  87         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  88         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  89
  90         /* MU status code */
  91         MU_STATE_STARTING                       = 1,
  92         MU_STATE_STARTED                        = 2,
  93         MU_STATE_RESETTING                      = 3,
  94         MU_STATE_FAILED                         = 4,
  95         MU_STATE_STOP                           = 5,
  96         MU_STATE_NOCONNECT                      = 6,
  97
  98         MU_MAX_DELAY                            = 50,
  99         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
 100         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
 101         MU_HARD_RESET_WAIT                      = 30000,
 102         HMU_PARTNER_TYPE                        = 2,
 103
 104         /* firmware returned values */
 105         SRB_STATUS_SUCCESS                      = 0x01,
 106         SRB_STATUS_ERROR                        = 0x04,
 107         SRB_STATUS_BUSY                         = 0x05,
 108         SRB_STATUS_INVALID_REQUEST              = 0x06,
 109         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
 110         SRB_SEE_SENSE                           = 0x80,
 111
 112         /* task attribute */
 113         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 114         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 115         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 116         TASK_ATTRIBUTE_ACA                      = 0x4,
 117
 118         SS_STS_NORMAL                           = 0x80000000,
 119         SS_STS_DONE                             = 0x40000000,
 120         SS_STS_HANDSHAKE                        = 0x20000000,
 121
 122         SS_HEAD_HANDSHAKE                       = 0x80,
 123
 124         SS_H2I_INT_RESET                        = 0x100,
 125
 126         SS_I2H_REQUEST_RESET                    = 0x2000,
 127
 128         SS_MU_OPERATIONAL                       = 0x80000000,
 129
 130         STEX_CDB_LENGTH                         = 16,
 131         STATUS_VAR_LEN                          = 128,
 132
 133         /* sg flags */
 134         SG_CF_EOT                               = 0x80, /* end of table */
 135         SG_CF_64B                               = 0x40, /* 64 bit item */
 136         SG_CF_HOST                              = 0x20, /* sg in host memory */
 137         MSG_DATA_DIR_ND                         = 0,
 138         MSG_DATA_DIR_IN                         = 1,
 139         MSG_DATA_DIR_OUT                        = 2,
 140
 141         st_shasta                               = 0,
 142         st_vsc                                  = 1,
 143         st_yosemite                             = 2,
 144         st_seq                                  = 3,
 145         st_yel                                  = 4,
 146         st_P3                                   = 5,
 147
 148         PASSTHRU_REQ_TYPE                       = 0x00000001,
 149         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 150         ST_INTERNAL_TIMEOUT                     = 180,
 151
 152         ST_TO_CMD                               = 0,
 153         ST_FROM_CMD                             = 1,
 154
 155         /* vendor specific commands of Promise */
 156         MGT_CMD                                 = 0xd8,
 157         SINBAND_MGT_CMD                         = 0xd9,
 158         ARRAY_CMD                               = 0xe0,
 159         CONTROLLER_CMD                          = 0xe1,
 160         DEBUGGING_CMD                           = 0xe2,
 161         PASSTHRU_CMD                            = 0xe3,
 162
 163         PASSTHRU_GET_ADAPTER                    = 0x05,
 164         PASSTHRU_GET_DRVVER                     = 0x10,
 165
 166         CTLR_CONFIG_CMD                         = 0x03,
 167         CTLR_SHUTDOWN                           = 0x0d,
 168
 169         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 170         CTLR_POWER_SAVING                       = 0x01,
 171
 172         PASSTHRU_SIGNATURE                      = 0x4e415041,
 173         MGT_CMD_SIGNATURE                       = 0xba,
 174
 175         INQUIRY_EVPD                            = 0x01,
 176
 177         ST_ADDITIONAL_MEM                       = 0x200000,
 178         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 179         PMIC_SHUTDOWN                           = 0x0D,
 180         PMIC_REUMSE                                     = 0x10,
 181         ST_IGNORED                                      = -1,
 182         ST_NOTHANDLED                           = 7,
 183         ST_S3                                           = 3,
 184         ST_S4                                           = 4,
 185         ST_S5                                           = 5,
 186         ST_S6                                           = 6,
 187 };
 188
 189 struct st_sgitem {
 190         u8 ctrl;        /* SG_CF_xxx */
 191         u8 reserved[3];
 192         __le32 count;
 193         __le64 addr;
 194 };
 195
 196 struct st_ss_sgitem {
 197         __le32 addr;
 198         __le32 addr_hi;
 199         __le32 count;
 200 };
 201
 202 struct st_sgtable {
 203         __le16 sg_count;
 204         __le16 max_sg_count;
 205         __le32 sz_in_byte;
 206 };
 207
 208 struct st_msg_header {
 209         __le64 handle;
 210         u8 flag;
 211         u8 channel;
 212         __le16 timeout;
 213         u32 reserved;
 214 };
 215
 216 struct handshake_frame {
 217         __le64 rb_phy;          /* request payload queue physical address */
 218         __le16 req_sz;          /* size of each request payload */
 219         __le16 req_cnt;         /* count of reqs the buffer can hold */
 220         __le16 status_sz;       /* size of each status payload */
 221         __le16 status_cnt;      /* count of status the buffer can hold */
 222         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 223         u8 partner_type;        /* who sends this frame */
 224         u8 reserved0[7];
 225         __le32 partner_ver_major;
 226         __le32 partner_ver_minor;
 227         __le32 partner_ver_oem;
 228         __le32 partner_ver_build;
 229         __le32 extra_offset;    /* NEW */
 230         __le32 extra_size;      /* NEW */
 231         __le32 scratch_size;
 232         u32 reserved1;
 233 };
 234
 235 struct req_msg {
 236         __le16 tag;
 237         u8 lun;
 238         u8 target;
 239         u8 task_attr;
 240         u8 task_manage;
 241         u8 data_dir;
 242         u8 payload_sz;          /* payload size in 4-byte, not used */
 243         u8 cdb[STEX_CDB_LENGTH];
 244         u32 variable[0];
 245 };
 246
 247 struct status_msg {
 248         __le16 tag;
 249         u8 lun;
 250         u8 target;
 251         u8 srb_status;
 252         u8 scsi_status;
 253         u8 reserved;
 254         u8 payload_sz;          /* payload size in 4-byte */
 255         u8 variable[STATUS_VAR_LEN];
 256 };
 257
 258 struct ver_info {
 259         u32 major;
 260         u32 minor;
 261         u32 oem;
 262         u32 build;
 263         u32 reserved[2];
 264 };
 265
 266 struct st_frame {
 267         u32 base[6];
 268         u32 rom_addr;
 269
 270         struct ver_info drv_ver;
 271         struct ver_info bios_ver;
 272
 273         u32 bus;
 274         u32 slot;
 275         u32 irq_level;
 276         u32 irq_vec;
 277         u32 id;
 278         u32 subid;
 279
 280         u32 dimm_size;
 281         u8 dimm_type;
 282         u8 reserved[3];
 283
 284         u32 channel;
 285         u32 reserved1;
 286 };
 287
 288 struct st_drvver {
 289         u32 major;
 290         u32 minor;
 291         u32 oem;
 292         u32 build;
 293         u32 signature[2];
 294         u8 console_id;
 295         u8 host_no;
 296         u8 reserved0[2];
 297         u32 reserved[3];
 298 };
 299
 300 struct st_ccb {
 301         struct req_msg *req;
 302         struct scsi_cmnd *cmd;
 303
 304         void *sense_buffer;
 305         unsigned int sense_bufflen;
 306         int sg_count;
 307
 308         u32 req_type;
 309         u8 srb_status;
 310         u8 scsi_status;
 311         u8 reserved[2];
 312 };
 313
 314 struct st_hba {
 315         void __iomem *mmio_base;        /* iomapped PCI memory space */
 316         void *dma_mem;
 317         dma_addr_t dma_handle;
 318         size_t dma_size;
 319
 320         struct Scsi_Host *host;
 321         struct pci_dev *pdev;
 322
 323         struct req_msg * (*alloc_rq) (struct st_hba *);
 324         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 325         void (*send) (struct st_hba *, struct req_msg *, u16);
 326
 327         u32 req_head;
 328         u32 req_tail;
 329         u32 status_head;
 330         u32 status_tail;
 331
 332         struct status_msg *status_buffer;
 333         void *copy_buffer; /* temp buffer for driver-handled commands */
 334         struct st_ccb *ccb;
 335         struct st_ccb *wait_ccb;
 336         __le32 *scratch;
 337
 338         char work_q_name[20];
 339         struct workqueue_struct *work_q;
 340         struct work_struct reset_work;
 341         wait_queue_head_t reset_waitq;
 342         unsigned int mu_status;
 343         unsigned int cardtype;
 344         int msi_enabled;
 345         int out_req_cnt;
 346         u32 extra_offset;
 347         u16 rq_count;
 348         u16 rq_size;
 349         u16 sts_count;
 350         u8  supports_pm;
 351         int msi_lock;
 352 };
 353
 354 struct st_card_info {
 355         struct req_msg * (*alloc_rq) (struct st_hba *);
 356         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 357         void (*send) (struct st_hba *, struct req_msg *, u16);
 358         unsigned int max_id;
 359         unsigned int max_lun;
 360         unsigned int max_channel;
 361         u16 rq_count;
 362         u16 rq_size;
 363         u16 sts_count;
 364 };
 365
 366 static int S6flag;
 367 static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
 368 static struct notifier_block stex_notifier = {
 369         stex_halt, NULL, 0
 370 };
 371
 372 static int msi;
 373 module_param(msi, int, 0);
 374 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 375
 376 static const char console_inq_page[] =
 377 {
 378         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 379         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 380         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 381         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 382         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 383         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 384         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 385         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 386 };
 387
 388 MODULE_AUTHOR("Ed Lin");
 389 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 390 MODULE_LICENSE("GPL");
 391 MODULE_VERSION(ST_DRIVER_VERSION);
 392
 393 static struct status_msg *stex_get_status(struct st_hba *hba)
 394 {
 395         struct status_msg *status = hba->status_buffer + hba->status_tail;
 396
 397         ++hba->status_tail;
 398         hba->status_tail %= hba->sts_count+1;
 399
 400         return status;
 401 }
 402
 403 static void stex_invalid_field(struct scsi_cmnd *cmd,
 404                                void (*done)(struct scsi_cmnd *))
 405 {
 406         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 407
 408         /* "Invalid field in cdb" */
 409         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 410                                 0x0);
 411         done(cmd);
 412 }
 413
 414 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 415 {
 416         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 417
 418         ++hba->req_head;
 419         hba->req_head %= hba->rq_count+1;
 420
 421         return req;
 422 }
 423
 424 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 425 {
 426         return (struct req_msg *)(hba->dma_mem +
 427                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 428 }
 429
 430 static int stex_map_sg(struct st_hba *hba,
 431         struct req_msg *req, struct st_ccb *ccb)
 432 {
 433         struct scsi_cmnd *cmd;
 434         struct scatterlist *sg;
 435         struct st_sgtable *dst;
 436         struct st_sgitem *table;
 437         int i, nseg;
 438
 439         cmd = ccb->cmd;
 440         nseg = scsi_dma_map(cmd);
 441         BUG_ON(nseg < 0);
 442         if (nseg) {
 443                 dst = (struct st_sgtable *)req->variable;
 444
 445                 ccb->sg_count = nseg;
 446                 dst->sg_count = cpu_to_le16((u16)nseg);
 447                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 448                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 449
 450                 table = (struct st_sgitem *)(dst + 1);
 451                 scsi_for_each_sg(cmd, sg, nseg, i) {
 452                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 453                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 454                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 455                 }
 456                 table[--i].ctrl |= SG_CF_EOT;
 457         }
 458
 459         return nseg;
 460 }
 461
 462 static int stex_ss_map_sg(struct st_hba *hba,
 463         struct req_msg *req, struct st_ccb *ccb)
 464 {
 465         struct scsi_cmnd *cmd;
 466         struct scatterlist *sg;
 467         struct st_sgtable *dst;
 468         struct st_ss_sgitem *table;
 469         int i, nseg;
 470
 471         cmd = ccb->cmd;
 472         nseg = scsi_dma_map(cmd);
 473         BUG_ON(nseg < 0);
 474         if (nseg) {
 475                 dst = (struct st_sgtable *)req->variable;
 476
 477                 ccb->sg_count = nseg;
 478                 dst->sg_count = cpu_to_le16((u16)nseg);
 479                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 480                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 481
 482                 table = (struct st_ss_sgitem *)(dst + 1);
 483                 scsi_for_each_sg(cmd, sg, nseg, i) {
 484                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 485                         table[i].addr =
 486                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 487                         table[i].addr_hi =
 488                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 489                 }
 490         }
 491
 492         return nseg;
 493 }
 494
 495 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 496 {
 497         struct st_frame *p;
 498         size_t count = sizeof(struct st_frame);
 499
 500         p = hba->copy_buffer;
 501         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 502         memset(p->base, 0, sizeof(u32)*6);
 503         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 504         p->rom_addr = 0;
 505
 506         p->drv_ver.major = ST_VER_MAJOR;
 507         p->drv_ver.minor = ST_VER_MINOR;
 508         p->drv_ver.oem = ST_OEM;
 509         p->drv_ver.build = ST_BUILD_VER;
 510
 511         p->bus = hba->pdev->bus->number;
 512         p->slot = hba->pdev->devfn;
 513         p->irq_level = 0;
 514         p->irq_vec = hba->pdev->irq;
 515         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 516         p->subid =
 517                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 518
 519         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 520 }
 521
 522 static void
 523 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 524 {
 525         req->tag = cpu_to_le16(tag);
 526
 527         hba->ccb[tag].req = req;
 528         hba->out_req_cnt++;
 529
 530         writel(hba->req_head, hba->mmio_base + IMR0);
 531         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 532         readl(hba->mmio_base + IDBL); /* flush */
 533 }
 534
 535 static void
 536 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 537 {
 538         struct scsi_cmnd *cmd;
 539         struct st_msg_header *msg_h;
 540         dma_addr_t addr;
 541
 542         req->tag = cpu_to_le16(tag);
 543
 544         hba->ccb[tag].req = req;
 545         hba->out_req_cnt++;
 546
 547         cmd = hba->ccb[tag].cmd;
 548         msg_h = (struct st_msg_header *)req - 1;
 549         if (likely(cmd)) {
 550                 msg_h->channel = (u8)cmd->device->channel;
 551                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 552         }
 553         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 554         addr += (hba->ccb[tag].sg_count+4)/11;
 555         msg_h->handle = cpu_to_le64(addr);
 556
 557         ++hba->req_head;
 558         hba->req_head %= hba->rq_count+1;
 559         if (hba->cardtype == st_P3) {
 560                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 561                 writel(addr, hba->mmio_base + YH2I_REQ);
 562         } else {
 563                 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 564                 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 565                 writel(addr, hba->mmio_base + YH2I_REQ);
 566                 readl(hba->mmio_base + YH2I_REQ); /* flush */
 567         }
 568 }
 569
 570 static void return_abnormal_state(struct st_hba *hba, int status)
 571 {
 572         struct st_ccb *ccb;
 573         unsigned long flags;
 574         u16 tag;
 575
 576         spin_lock_irqsave(hba->host->host_lock, flags);
 577         for (tag = 0; tag < hba->host->can_queue; tag++) {
 578                 ccb = &hba->ccb[tag];
 579                 if (ccb->req == NULL)
 580                         continue;
 581                 ccb->req = NULL;
 582                 if (ccb->cmd) {
 583                         scsi_dma_unmap(ccb->cmd);
 584                         ccb->cmd->result = status << 16;
 585                         ccb->cmd->scsi_done(ccb->cmd);
 586                         ccb->cmd = NULL;
 587                 }
 588         }
 589         spin_unlock_irqrestore(hba->host->host_lock, flags);
 590 }
 591 static int
 592 stex_slave_config(struct scsi_device *sdev)
 593 {
 594         sdev->use_10_for_rw = 1;
 595         sdev->use_10_for_ms = 1;
 596         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 597
 598         return 0;
 599 }
 600
 601 static int
 602 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 603 {
 604         struct st_hba *hba;
 605         struct Scsi_Host *host;
 606         unsigned int id, lun;
 607         struct req_msg *req;
 608         u16 tag;
 609
 610         host = cmd->device->host;
 611         id = cmd->device->id;
 612         lun = cmd->device->lun;
 613         hba = (struct st_hba *) &host->hostdata[0];
 614         if (hba->mu_status == MU_STATE_NOCONNECT) {
 615                 cmd->result = DID_NO_CONNECT;
 616                 done(cmd);
 617                 return 0;
 618         }
 619         if (unlikely(hba->mu_status != MU_STATE_STARTED))
 620                 return SCSI_MLQUEUE_HOST_BUSY;
 621
 622         switch (cmd->cmnd[0]) {
 623         case MODE_SENSE_10:
 624         {
 625                 static char ms10_caching_page[12] =
 626                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 627                 unsigned char page;
 628
 629                 page = cmd->cmnd[2] & 0x3f;
 630                 if (page == 0x8 || page == 0x3f) {
 631                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 632                                                  sizeof(ms10_caching_page));
 633                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 634                         done(cmd);
 635                 } else
 636                         stex_invalid_field(cmd, done);
 637                 return 0;
 638         }
 639         case REPORT_LUNS:
 640                 /*
 641                  * The shasta firmware does not report actual luns in the
 642                  * target, so fail the command to force sequential lun scan.
 643                  * Also, the console device does not support this command.
 644                  */
 645                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 646                         stex_invalid_field(cmd, done);
 647                         return 0;
 648                 }
 649                 break;
 650         case TEST_UNIT_READY:
 651                 if (id == host->max_id - 1) {
 652                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 653                         done(cmd);
 654                         return 0;
 655                 }
 656                 break;
 657         case INQUIRY:
 658                 if (lun >= host->max_lun) {
 659                         cmd->result = DID_NO_CONNECT << 16;
 660                         done(cmd);
 661                         return 0;
 662                 }
 663                 if (id != host->max_id - 1)
 664                         break;
 665                 if (!lun && !cmd->device->channel &&
 666                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 667                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 668                                                  sizeof(console_inq_page));
 669                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 670                         done(cmd);
 671                 } else
 672                         stex_invalid_field(cmd, done);
 673                 return 0;
 674         case PASSTHRU_CMD:
 675                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 676                         const struct st_drvver ver = {
 677                                 .major = ST_VER_MAJOR,
 678                                 .minor = ST_VER_MINOR,
 679                                 .oem = ST_OEM,
 680                                 .build = ST_BUILD_VER,
 681                                 .signature[0] = PASSTHRU_SIGNATURE,
 682                                 .console_id = host->max_id - 1,
 683                                 .host_no = hba->host->host_no,
 684                         };
 685                         size_t cp_len = sizeof(ver);
 686
 687                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 688                         cmd->result = sizeof(ver) == cp_len ?
 689                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 690                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 691                         done(cmd);
 692                         return 0;
 693                 }
 694         default:
 695                 break;
 696         }
 697
 698         cmd->scsi_done = done;
 699
 700         tag = cmd->request->tag;
 701
 702         if (unlikely(tag >= host->can_queue))
 703                 return SCSI_MLQUEUE_HOST_BUSY;
 704
 705         req = hba->alloc_rq(hba);
 706
 707         req->lun = lun;
 708         req->target = id;
 709
 710         /* cdb */
 711         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 712
 713         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 714                 req->data_dir = MSG_DATA_DIR_IN;
 715         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 716                 req->data_dir = MSG_DATA_DIR_OUT;
 717         else
 718                 req->data_dir = MSG_DATA_DIR_ND;
 719
 720         hba->ccb[tag].cmd = cmd;
 721         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 722         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 723
 724         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 725                 hba->ccb[tag].sg_count = 0;
 726                 memset(&req->variable[0], 0, 8);
 727         }
 728
 729         hba->send(hba, req, tag);
 730         return 0;
 731 }
 732
 733 static DEF_SCSI_QCMD(stex_queuecommand)
 734
 735 static void stex_scsi_done(struct st_ccb *ccb)
 736 {
 737         struct scsi_cmnd *cmd = ccb->cmd;
 738         int result;
 739
 740         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 741                 result = ccb->scsi_status;
 742                 switch (ccb->scsi_status) {
 743                 case SAM_STAT_GOOD:
 744                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 745                         break;
 746                 case SAM_STAT_CHECK_CONDITION:
 747                         result |= DRIVER_SENSE << 24;
 748                         break;
 749                 case SAM_STAT_BUSY:
 750                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 751                         break;
 752                 default:
 753                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 754                         break;
 755                 }
 756         }
 757         else if (ccb->srb_status & SRB_SEE_SENSE)
 758                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 759         else switch (ccb->srb_status) {
 760                 case SRB_STATUS_SELECTION_TIMEOUT:
 761                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 762                         break;
 763                 case SRB_STATUS_BUSY:
 764                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 765                         break;
 766                 case SRB_STATUS_INVALID_REQUEST:
 767                 case SRB_STATUS_ERROR:
 768                 default:
 769                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 770                         break;
 771         }
 772
 773         cmd->result = result;
 774         cmd->scsi_done(cmd);
 775 }
 776
 777 static void stex_copy_data(struct st_ccb *ccb,
 778         struct status_msg *resp, unsigned int variable)
 779 {
 780         if (resp->scsi_status != SAM_STAT_GOOD) {
 781                 if (ccb->sense_buffer != NULL)
 782                         memcpy(ccb->sense_buffer, resp->variable,
 783                                 min(variable, ccb->sense_bufflen));
 784                 return;
 785         }
 786
 787         if (ccb->cmd == NULL)
 788                 return;
 789         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 790 }
 791
 792 static void stex_check_cmd(struct st_hba *hba,
 793         struct st_ccb *ccb, struct status_msg *resp)
 794 {
 795         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 796                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 797                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 798                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 799 }
 800
 801 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 802 {
 803         void __iomem *base = hba->mmio_base;
 804         struct status_msg *resp;
 805         struct st_ccb *ccb;
 806         unsigned int size;
 807         u16 tag;
 808
 809         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 810                 return;
 811
 812         /* status payloads */
 813         hba->status_head = readl(base + OMR1);
 814         if (unlikely(hba->status_head > hba->sts_count)) {
 815                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 816                         pci_name(hba->pdev));
 817                 return;
 818         }
 819
 820         /*
 821          * it's not a valid status payload if:
 822          * 1. there are no pending requests(e.g. during init stage)
 823          * 2. there are some pending requests, but the controller is in
 824          *     reset status, and its type is not st_yosemite
 825          * firmware of st_yosemite in reset status will return pending requests
 826          * to driver, so we allow it to pass
 827          */
 828         if (unlikely(hba->out_req_cnt <= 0 ||
 829                         (hba->mu_status == MU_STATE_RESETTING &&
 830                          hba->cardtype != st_yosemite))) {
 831                 hba->status_tail = hba->status_head;
 832                 goto update_status;
 833         }
 834
 835         while (hba->status_tail != hba->status_head) {
 836                 resp = stex_get_status(hba);
 837                 tag = le16_to_cpu(resp->tag);
 838                 if (unlikely(tag >= hba->host->can_queue)) {
 839                         printk(KERN_WARNING DRV_NAME
 840                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 841                         continue;
 842                 }
 843
 844                 hba->out_req_cnt--;
 845                 ccb = &hba->ccb[tag];
 846                 if (unlikely(hba->wait_ccb == ccb))
 847                         hba->wait_ccb = NULL;
 848                 if (unlikely(ccb->req == NULL)) {
 849                         printk(KERN_WARNING DRV_NAME
 850                                 "(%s): lagging req\n", pci_name(hba->pdev));
 851                         continue;
 852                 }
 853
 854                 size = resp->payload_sz * sizeof(u32); /* payload size */
 855                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 856                         size > sizeof(*resp))) {
 857                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 858                                 pci_name(hba->pdev));
 859                 } else {
 860                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 861                         if (size)
 862                                 stex_copy_data(ccb, resp, size);
 863                 }
 864
 865                 ccb->req = NULL;
 866                 ccb->srb_status = resp->srb_status;
 867                 ccb->scsi_status = resp->scsi_status;
 868
 869                 if (likely(ccb->cmd != NULL)) {
 870                         if (hba->cardtype == st_yosemite)
 871                                 stex_check_cmd(hba, ccb, resp);
 872
 873                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 874                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 875                                 stex_controller_info(hba, ccb);
 876
 877                         scsi_dma_unmap(ccb->cmd);
 878                         stex_scsi_done(ccb);
 879                 } else
 880                         ccb->req_type = 0;
 881         }
 882
 883 update_status:
 884         writel(hba->status_head, base + IMR1);
 885         readl(base + IMR1); /* flush */
 886 }
 887
 888 static irqreturn_t stex_intr(int irq, void *__hba)
 889 {
 890         struct st_hba *hba = __hba;
 891         void __iomem *base = hba->mmio_base;
 892         u32 data;
 893         unsigned long flags;
 894
 895         spin_lock_irqsave(hba->host->host_lock, flags);
 896
 897         data = readl(base + ODBL);
 898
 899         if (data && data != 0xffffffff) {
 900                 /* clear the interrupt */
 901                 writel(data, base + ODBL);
 902                 readl(base + ODBL); /* flush */
 903                 stex_mu_intr(hba, data);
 904                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 905                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 906                         hba->cardtype == st_shasta))
 907                         queue_work(hba->work_q, &hba->reset_work);
 908                 return IRQ_HANDLED;
 909         }
 910
 911         spin_unlock_irqrestore(hba->host->host_lock, flags);
 912
 913         return IRQ_NONE;
 914 }
 915
 916 static void stex_ss_mu_intr(struct st_hba *hba)
 917 {
 918         struct status_msg *resp;
 919         struct st_ccb *ccb;
 920         __le32 *scratch;
 921         unsigned int size;
 922         int count = 0;
 923         u32 value;
 924         u16 tag;
 925
 926         if (unlikely(hba->out_req_cnt <= 0 ||
 927                         hba->mu_status == MU_STATE_RESETTING))
 928                 return;
 929
 930         while (count < hba->sts_count) {
 931                 scratch = hba->scratch + hba->status_tail;
 932                 value = le32_to_cpu(*scratch);
 933                 if (unlikely(!(value & SS_STS_NORMAL)))
 934                         return;
 935
 936                 resp = hba->status_buffer + hba->status_tail;
 937                 *scratch = 0;
 938                 ++count;
 939                 ++hba->status_tail;
 940                 hba->status_tail %= hba->sts_count+1;
 941
 942                 tag = (u16)value;
 943                 if (unlikely(tag >= hba->host->can_queue)) {
 944                         printk(KERN_WARNING DRV_NAME
 945                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 946                         continue;
 947                 }
 948
 949                 hba->out_req_cnt--;
 950                 ccb = &hba->ccb[tag];
 951                 if (unlikely(hba->wait_ccb == ccb))
 952                         hba->wait_ccb = NULL;
 953                 if (unlikely(ccb->req == NULL)) {
 954                         printk(KERN_WARNING DRV_NAME
 955                                 "(%s): lagging req\n", pci_name(hba->pdev));
 956                         continue;
 957                 }
 958
 959                 ccb->req = NULL;
 960                 if (likely(value & SS_STS_DONE)) { /* normal case */
 961                         ccb->srb_status = SRB_STATUS_SUCCESS;
 962                         ccb->scsi_status = SAM_STAT_GOOD;
 963                 } else {
 964                         ccb->srb_status = resp->srb_status;
 965                         ccb->scsi_status = resp->scsi_status;
 966                         size = resp->payload_sz * sizeof(u32);
 967                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 968                                 size > sizeof(*resp))) {
 969                                 printk(KERN_WARNING DRV_NAME
 970                                         "(%s): bad status size\n",
 971                                         pci_name(hba->pdev));
 972                         } else {
 973                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 974                                 if (size)
 975                                         stex_copy_data(ccb, resp, size);
 976                         }
 977                         if (likely(ccb->cmd != NULL))
 978                                 stex_check_cmd(hba, ccb, resp);
 979                 }
 980
 981                 if (likely(ccb->cmd != NULL)) {
 982                         scsi_dma_unmap(ccb->cmd);
 983                         stex_scsi_done(ccb);
 984                 } else
 985                         ccb->req_type = 0;
 986         }
 987 }
 988
 989 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 990 {
 991         struct st_hba *hba = __hba;
 992         void __iomem *base = hba->mmio_base;
 993         u32 data;
 994         unsigned long flags;
 995
 996         spin_lock_irqsave(hba->host->host_lock, flags);
 997
 998         if (hba->cardtype == st_yel) {
 999                 data = readl(base + YI2H_INT);
1000                 if (data && data != 0xffffffff) {
1001                         /* clear the interrupt */
1002                         writel(data, base + YI2H_INT_C);
1003                         stex_ss_mu_intr(hba);
1004                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1005                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1006                                 queue_work(hba->work_q, &hba->reset_work);
1007                         return IRQ_HANDLED;
1008                 }
1009         } else {
1010                 data = readl(base + PSCRATCH4);
1011                 if (data != 0xffffffff) {
1012                         if (data != 0) {
1013                                 /* clear the interrupt */
1014                                 writel(data, base + PSCRATCH1);
1015                                 writel((1 << 22), base + YH2I_INT);
1016                         }
1017                         stex_ss_mu_intr(hba);
1018                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1019                         if (unlikely(data & SS_I2H_REQUEST_RESET))
1020                                 queue_work(hba->work_q, &hba->reset_work);
1021                         return IRQ_HANDLED;
1022                 }
1023         }
1024
1025         spin_unlock_irqrestore(hba->host->host_lock, flags);
1026
1027         return IRQ_NONE;
1028 }
1029
1030 static int stex_common_handshake(struct st_hba *hba)
1031 {
1032         void __iomem *base = hba->mmio_base;
1033         struct handshake_frame *h;
1034         dma_addr_t status_phys;
1035         u32 data;
1036         unsigned long before;
1037
1038         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1039                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1040                 readl(base + IDBL);
1041                 before = jiffies;
1042                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1043                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1044                                 printk(KERN_ERR DRV_NAME
1045                                         "(%s): no handshake signature\n",
1046                                         pci_name(hba->pdev));
1047                                 return -1;
1048                         }
1049                         rmb();
1050                         msleep(1);
1051                 }
1052         }
1053
1054         udelay(10);
1055
1056         data = readl(base + OMR1);
1057         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1058                 data &= 0x0000ffff;
1059                 if (hba->host->can_queue > data) {
1060                         hba->host->can_queue = data;
1061                         hba->host->cmd_per_lun = data;
1062                 }
1063         }
1064
1065         h = (struct handshake_frame *)hba->status_buffer;
1066         h->rb_phy = cpu_to_le64(hba->dma_handle);
1067         h->req_sz = cpu_to_le16(hba->rq_size);
1068         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1069         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1070         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1071         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1072         h->partner_type = HMU_PARTNER_TYPE;
1073         if (hba->extra_offset) {
1074                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1075                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1076         } else
1077                 h->extra_offset = h->extra_size = 0;
1078
1079         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1080         writel(status_phys, base + IMR0);
1081         readl(base + IMR0);
1082         writel((status_phys >> 16) >> 16, base + IMR1);
1083         readl(base + IMR1);
1084
1085         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1086         readl(base + OMR0);
1087         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1088         readl(base + IDBL); /* flush */
1089
1090         udelay(10);
1091         before = jiffies;
1092         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1093                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1094                         printk(KERN_ERR DRV_NAME
1095                                 "(%s): no signature after handshake frame\n",
1096                                 pci_name(hba->pdev));
1097                         return -1;
1098                 }
1099                 rmb();
1100                 msleep(1);
1101         }
1102
1103         writel(0, base + IMR0);
1104         readl(base + IMR0);
1105         writel(0, base + OMR0);
1106         readl(base + OMR0);
1107         writel(0, base + IMR1);
1108         readl(base + IMR1);
1109         writel(0, base + OMR1);
1110         readl(base + OMR1); /* flush */
1111         return 0;
1112 }
1113
1114 static int stex_ss_handshake(struct st_hba *hba)
1115 {
1116         void __iomem *base = hba->mmio_base;
1117         struct st_msg_header *msg_h;
1118         struct handshake_frame *h;
1119         __le32 *scratch;
1120         u32 data, scratch_size, mailboxdata, operationaldata;
1121         unsigned long before;
1122         int ret = 0;
1123
1124         before = jiffies;
1125
1126         if (hba->cardtype == st_yel) {
1127                 operationaldata = readl(base + YIOA_STATUS);
1128                 while (operationaldata != SS_MU_OPERATIONAL) {
1129                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1130                                 printk(KERN_ERR DRV_NAME
1131                                         "(%s): firmware not operational\n",
1132                                         pci_name(hba->pdev));
1133                                 return -1;
1134                         }
1135                         msleep(1);
1136                         operationaldata = readl(base + YIOA_STATUS);
1137                 }
1138         } else {
1139                 operationaldata = readl(base + PSCRATCH3);
1140                 while (operationaldata != SS_MU_OPERATIONAL) {
1141                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1142                                 printk(KERN_ERR DRV_NAME
1143                                         "(%s): firmware not operational\n",
1144                                         pci_name(hba->pdev));
1145                                 return -1;
1146                         }
1147                         msleep(1);
1148                         operationaldata = readl(base + PSCRATCH3);
1149                 }
1150         }
1151
1152         msg_h = (struct st_msg_header *)hba->dma_mem;
1153         msg_h->handle = cpu_to_le64(hba->dma_handle);
1154         msg_h->flag = SS_HEAD_HANDSHAKE;
1155
1156         h = (struct handshake_frame *)(msg_h + 1);
1157         h->rb_phy = cpu_to_le64(hba->dma_handle);
1158         h->req_sz = cpu_to_le16(hba->rq_size);
1159         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1160         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1161         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1162         h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1163         h->partner_type = HMU_PARTNER_TYPE;
1164         h->extra_offset = h->extra_size = 0;
1165         scratch_size = (hba->sts_count+1)*sizeof(u32);
1166         h->scratch_size = cpu_to_le32(scratch_size);
1167
1168         if (hba->cardtype == st_yel) {
1169                 data = readl(base + YINT_EN);
1170                 data &= ~4;
1171                 writel(data, base + YINT_EN);
1172                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1173                 readl(base + YH2I_REQ_HI);
1174                 writel(hba->dma_handle, base + YH2I_REQ);
1175                 readl(base + YH2I_REQ); /* flush */
1176         } else {
1177                 data = readl(base + YINT_EN);
1178                 data &= ~(1 << 0);
1179                 data &= ~(1 << 2);
1180                 writel(data, base + YINT_EN);
1181                 if (hba->msi_lock == 0) {
1182                         /* P3 MSI Register cannot access twice */
1183                         writel((1 << 6), base + YH2I_INT);
1184                         hba->msi_lock  = 1;
1185                 }
1186                 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1187                 writel(hba->dma_handle, base + YH2I_REQ);
1188         }
1189
1190         before = jiffies;
1191         scratch = hba->scratch;
1192         if (hba->cardtype == st_yel) {
1193                 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1194                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1195                                 printk(KERN_ERR DRV_NAME
1196                                         "(%s): no signature after handshake frame\n",
1197                                         pci_name(hba->pdev));
1198                                 ret = -1;
1199                                 break;
1200                         }
1201                         rmb();
1202                         msleep(1);
1203                 }
1204         } else {
1205                 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1206                 while (mailboxdata != SS_STS_HANDSHAKE) {
1207                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1208                                 printk(KERN_ERR DRV_NAME
1209                                         "(%s): no signature after handshake frame\n",
1210                                         pci_name(hba->pdev));
1211                                 ret = -1;
1212                                 break;
1213                         }
1214                         rmb();
1215                         msleep(1);
1216                         mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1217                 }
1218         }
1219         memset(scratch, 0, scratch_size);
1220         msg_h->flag = 0;
1221
1222         return ret;
1223 }
1224
1225 static int stex_handshake(struct st_hba *hba)
1226 {
1227         int err;
1228         unsigned long flags;
1229         unsigned int mu_status;
1230
1231         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1232                 err = stex_ss_handshake(hba);
1233         else
1234                 err = stex_common_handshake(hba);
1235         spin_lock_irqsave(hba->host->host_lock, flags);
1236         mu_status = hba->mu_status;
1237         if (err == 0) {
1238                 hba->req_head = 0;
1239                 hba->req_tail = 0;
1240                 hba->status_head = 0;
1241                 hba->status_tail = 0;
1242                 hba->out_req_cnt = 0;
1243                 hba->mu_status = MU_STATE_STARTED;
1244         } else
1245                 hba->mu_status = MU_STATE_FAILED;
1246         if (mu_status == MU_STATE_RESETTING)
1247                 wake_up_all(&hba->reset_waitq);
1248         spin_unlock_irqrestore(hba->host->host_lock, flags);
1249         return err;
1250 }
1251
1252 static int stex_abort(struct scsi_cmnd *cmd)
1253 {
1254         struct Scsi_Host *host = cmd->device->host;
1255         struct st_hba *hba = (struct st_hba *)host->hostdata;
1256         u16 tag = cmd->request->tag;
1257         void __iomem *base;
1258         u32 data;
1259         int result = SUCCESS;
1260         unsigned long flags;
1261
1262         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1263
1264         base = hba->mmio_base;
1265         spin_lock_irqsave(host->host_lock, flags);
1266         if (tag < host->can_queue &&
1267                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1268                 hba->wait_ccb = &hba->ccb[tag];
1269         else
1270                 goto out;
1271
1272         if (hba->cardtype == st_yel) {
1273                 data = readl(base + YI2H_INT);
1274                 if (data == 0 || data == 0xffffffff)
1275                         goto fail_out;
1276
1277                 writel(data, base + YI2H_INT_C);
1278                 stex_ss_mu_intr(hba);
1279         } else if (hba->cardtype == st_P3) {
1280                 data = readl(base + PSCRATCH4);
1281                 if (data == 0xffffffff)
1282                         goto fail_out;
1283                 if (data != 0) {
1284                         writel(data, base + PSCRATCH1);
1285                         writel((1 << 22), base + YH2I_INT);
1286                 }
1287                 stex_ss_mu_intr(hba);
1288         } else {
1289                 data = readl(base + ODBL);
1290                 if (data == 0 || data == 0xffffffff)
1291                         goto fail_out;
1292
1293                 writel(data, base + ODBL);
1294                 readl(base + ODBL); /* flush */
1295                 stex_mu_intr(hba, data);
1296         }
1297         if (hba->wait_ccb == NULL) {
1298                 printk(KERN_WARNING DRV_NAME
1299                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1300                 goto out;
1301         }
1302
1303 fail_out:
1304         scsi_dma_unmap(cmd);
1305         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1306         hba->wait_ccb = NULL;
1307         result = FAILED;
1308 out:
1309         spin_unlock_irqrestore(host->host_lock, flags);
1310         return result;
1311 }
1312
1313 static void stex_hard_reset(struct st_hba *hba)
1314 {
1315         struct pci_bus *bus;
1316         int i;
1317         u16 pci_cmd;
1318         u8 pci_bctl;
1319
1320         for (i = 0; i < 16; i++)
1321                 pci_read_config_dword(hba->pdev, i * 4,
1322                         &hba->pdev->saved_config_space[i]);
1323
1324         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1325            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1326         bus = hba->pdev->bus;
1327         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1328         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1329         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1330
1331         /*
1332          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1333          * require more time to finish bus reset. Use 100 ms here for safety
1334          */
1335         msleep(100);
1336         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1337         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1338
1339         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1340                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1341                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1342                         break;
1343                 msleep(1);
1344         }
1345
1346         ssleep(5);
1347         for (i = 0; i < 16; i++)
1348                 pci_write_config_dword(hba->pdev, i * 4,
1349                         hba->pdev->saved_config_space[i]);
1350 }
1351
1352 static int stex_yos_reset(struct st_hba *hba)
1353 {
1354         void __iomem *base;
1355         unsigned long flags, before;
1356         int ret = 0;
1357
1358         base = hba->mmio_base;
1359         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1360         readl(base + IDBL); /* flush */
1361         before = jiffies;
1362         while (hba->out_req_cnt > 0) {
1363                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1364                         printk(KERN_WARNING DRV_NAME
1365                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1366                         ret = -1;
1367                         break;
1368                 }
1369                 msleep(1);
1370         }
1371
1372         spin_lock_irqsave(hba->host->host_lock, flags);
1373         if (ret == -1)
1374                 hba->mu_status = MU_STATE_FAILED;
1375         else
1376                 hba->mu_status = MU_STATE_STARTED;
1377         wake_up_all(&hba->reset_waitq);
1378         spin_unlock_irqrestore(hba->host->host_lock, flags);
1379
1380         return ret;
1381 }
1382
1383 static void stex_ss_reset(struct st_hba *hba)
1384 {
1385         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1386         readl(hba->mmio_base + YH2I_INT);
1387         ssleep(5);
1388 }
1389
1390 static void stex_p3_reset(struct st_hba *hba)
1391 {
1392         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1393         ssleep(5);
1394 }
1395
1396 static int stex_do_reset(struct st_hba *hba)
1397 {
1398         unsigned long flags;
1399         unsigned int mu_status = MU_STATE_RESETTING;
1400
1401         spin_lock_irqsave(hba->host->host_lock, flags);
1402         if (hba->mu_status == MU_STATE_STARTING) {
1403                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1404                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1405                         pci_name(hba->pdev));
1406                 return 0;
1407         }
1408         while (hba->mu_status == MU_STATE_RESETTING) {
1409                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1410                 wait_event_timeout(hba->reset_waitq,
1411                                    hba->mu_status != MU_STATE_RESETTING,
1412                                    MU_MAX_DELAY * HZ);
1413                 spin_lock_irqsave(hba->host->host_lock, flags);
1414                 mu_status = hba->mu_status;
1415         }
1416
1417         if (mu_status != MU_STATE_RESETTING) {
1418                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1419                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1420         }
1421
1422         hba->mu_status = MU_STATE_RESETTING;
1423         spin_unlock_irqrestore(hba->host->host_lock, flags);
1424
1425         if (hba->cardtype == st_yosemite)
1426                 return stex_yos_reset(hba);
1427
1428         if (hba->cardtype == st_shasta)
1429                 stex_hard_reset(hba);
1430         else if (hba->cardtype == st_yel)
1431                 stex_ss_reset(hba);
1432         else if (hba->cardtype == st_P3)
1433                 stex_p3_reset(hba);
1434
1435         return_abnormal_state(hba, DID_RESET);
1436
1437         if (stex_handshake(hba) == 0)
1438                 return 0;
1439
1440         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1441                 pci_name(hba->pdev));
1442         return -1;
1443 }
1444
1445 static int stex_reset(struct scsi_cmnd *cmd)
1446 {
1447         struct st_hba *hba;
1448
1449         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1450
1451         shost_printk(KERN_INFO, cmd->device->host,
1452                      "resetting host\n");
1453
1454         return stex_do_reset(hba) ? FAILED : SUCCESS;
1455 }
1456
1457 static void stex_reset_work(struct work_struct *work)
1458 {
1459         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1460
1461         stex_do_reset(hba);
1462 }
1463
1464 static int stex_biosparam(struct scsi_device *sdev,
1465         struct block_device *bdev, sector_t capacity, int geom[])
1466 {
1467         int heads = 255, sectors = 63;
1468
1469         if (capacity < 0x200000) {
1470                 heads = 64;
1471                 sectors = 32;
1472         }
1473
1474         sector_div(capacity, heads * sectors);
1475
1476         geom[0] = heads;
1477         geom[1] = sectors;
1478         geom[2] = capacity;
1479
1480         return 0;
1481 }
1482
1483 static struct scsi_host_template driver_template = {
1484         .module                         = THIS_MODULE,
1485         .name                           = DRV_NAME,
1486         .proc_name                      = DRV_NAME,
1487         .bios_param                     = stex_biosparam,
1488         .queuecommand                   = stex_queuecommand,
1489         .slave_configure                = stex_slave_config,
1490         .eh_abort_handler               = stex_abort,
1491         .eh_host_reset_handler          = stex_reset,
1492         .this_id                        = -1,
1493 };
1494
1495 static struct pci_device_id stex_pci_tbl[] = {
1496         /* st_shasta */
1497         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1498                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1499         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1500                 st_shasta }, /* SuperTrak EX12350 */
1501         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1502                 st_shasta }, /* SuperTrak EX4350 */
1503         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1504                 st_shasta }, /* SuperTrak EX24350 */
1505
1506         /* st_vsc */
1507         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1508
1509         /* st_yosemite */
1510         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1511
1512         /* st_seq */
1513         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1514
1515         /* st_yel */
1516         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1517         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1518
1519         /* st_P3, pluto */
1520         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1521                 0x8870, 0, 0, st_P3 },
1522         /* st_P3, p3 */
1523         { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1524                 0x4300, 0, 0, st_P3 },
1525
1526         /* st_P3, SymplyStor4E */
1527         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1528                 0x4311, 0, 0, st_P3 },
1529         /* st_P3, SymplyStor8E */
1530         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1531                 0x4312, 0, 0, st_P3 },
1532         /* st_P3, SymplyStor4 */
1533         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1534                 0x4321, 0, 0, st_P3 },
1535         /* st_P3, SymplyStor8 */
1536         { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1537                 0x4322, 0, 0, st_P3 },
1538         { }     /* terminate list */
1539 };
1540
1541 static struct st_card_info stex_card_info[] = {
1542         /* st_shasta */
1543         {
1544                 .max_id         = 17,
1545                 .max_lun        = 8,
1546                 .max_channel    = 0,
1547                 .rq_count       = 32,
1548                 .rq_size        = 1048,
1549                 .sts_count      = 32,
1550                 .alloc_rq       = stex_alloc_req,
1551                 .map_sg         = stex_map_sg,
1552                 .send           = stex_send_cmd,
1553         },
1554
1555         /* st_vsc */
1556         {
1557                 .max_id         = 129,
1558                 .max_lun        = 1,
1559                 .max_channel    = 0,
1560                 .rq_count       = 32,
1561                 .rq_size        = 1048,
1562                 .sts_count      = 32,
1563                 .alloc_rq       = stex_alloc_req,
1564                 .map_sg         = stex_map_sg,
1565                 .send           = stex_send_cmd,
1566         },
1567
1568         /* st_yosemite */
1569         {
1570                 .max_id         = 2,
1571                 .max_lun        = 256,
1572                 .max_channel    = 0,
1573                 .rq_count       = 256,
1574                 .rq_size        = 1048,
1575                 .sts_count      = 256,
1576                 .alloc_rq       = stex_alloc_req,
1577                 .map_sg         = stex_map_sg,
1578                 .send           = stex_send_cmd,
1579         },
1580
1581         /* st_seq */
1582         {
1583                 .max_id         = 129,
1584                 .max_lun        = 1,
1585                 .max_channel    = 0,
1586                 .rq_count       = 32,
1587                 .rq_size        = 1048,
1588                 .sts_count      = 32,
1589                 .alloc_rq       = stex_alloc_req,
1590                 .map_sg         = stex_map_sg,
1591                 .send           = stex_send_cmd,
1592         },
1593
1594         /* st_yel */
1595         {
1596                 .max_id         = 129,
1597                 .max_lun        = 256,
1598                 .max_channel    = 3,
1599                 .rq_count       = 801,
1600                 .rq_size        = 512,
1601                 .sts_count      = 801,
1602                 .alloc_rq       = stex_ss_alloc_req,
1603                 .map_sg         = stex_ss_map_sg,
1604                 .send           = stex_ss_send_cmd,
1605         },
1606
1607         /* st_P3 */
1608         {
1609                 .max_id         = 129,
1610                 .max_lun        = 256,
1611                 .max_channel    = 0,
1612                 .rq_count       = 801,
1613                 .rq_size        = 512,
1614                 .sts_count      = 801,
1615                 .alloc_rq       = stex_ss_alloc_req,
1616                 .map_sg         = stex_ss_map_sg,
1617                 .send           = stex_ss_send_cmd,
1618         },
1619 };
1620
1621 static int stex_set_dma_mask(struct pci_dev * pdev)
1622 {
1623         int ret;
1624
1625         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1626                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1627                 return 0;
1628         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1629         if (!ret)
1630                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1631         return ret;
1632 }
1633
1634 static int stex_request_irq(struct st_hba *hba)
1635 {
1636         struct pci_dev *pdev = hba->pdev;
1637         int status;
1638
1639         if (msi || hba->cardtype == st_P3) {
1640                 status = pci_enable_msi(pdev);
1641                 if (status != 0)
1642                         printk(KERN_ERR DRV_NAME
1643                                 "(%s): error %d setting up MSI\n",
1644                                 pci_name(pdev), status);
1645                 else
1646                         hba->msi_enabled = 1;
1647         } else
1648                 hba->msi_enabled = 0;
1649
1650         status = request_irq(pdev->irq,
1651                 (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1652                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1653
1654         if (status != 0) {
1655                 if (hba->msi_enabled)
1656                         pci_disable_msi(pdev);
1657         }
1658         return status;
1659 }
1660
1661 static void stex_free_irq(struct st_hba *hba)
1662 {
1663         struct pci_dev *pdev = hba->pdev;
1664
1665         free_irq(pdev->irq, hba);
1666         if (hba->msi_enabled)
1667                 pci_disable_msi(pdev);
1668 }
1669
1670 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1671 {
1672         struct st_hba *hba;
1673         struct Scsi_Host *host;
1674         const struct st_card_info *ci = NULL;
1675         u32 sts_offset, cp_offset, scratch_offset;
1676         int err;
1677
1678         err = pci_enable_device(pdev);
1679         if (err)
1680                 return err;
1681
1682         pci_set_master(pdev);
1683
1684         S6flag = 0;
1685         register_reboot_notifier(&stex_notifier);
1686
1687         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1688
1689         if (!host) {
1690                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1691                         pci_name(pdev));
1692                 err = -ENOMEM;
1693                 goto out_disable;
1694         }
1695
1696         hba = (struct st_hba *)host->hostdata;
1697         memset(hba, 0, sizeof(struct st_hba));
1698
1699         err = pci_request_regions(pdev, DRV_NAME);
1700         if (err < 0) {
1701                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1702                         pci_name(pdev));
1703                 goto out_scsi_host_put;
1704         }
1705
1706         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1707         if ( !hba->mmio_base) {
1708                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1709                         pci_name(pdev));
1710                 err = -ENOMEM;
1711                 goto out_release_regions;
1712         }
1713
1714         err = stex_set_dma_mask(pdev);
1715         if (err) {
1716                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1717                         pci_name(pdev));
1718                 goto out_iounmap;
1719         }
1720
1721         hba->cardtype = (unsigned int) id->driver_data;
1722         ci = &stex_card_info[hba->cardtype];
1723         switch (id->subdevice) {
1724         case 0x4221:
1725         case 0x4222:
1726         case 0x4223:
1727         case 0x4224:
1728         case 0x4225:
1729         case 0x4226:
1730         case 0x4227:
1731         case 0x4261:
1732         case 0x4262:
1733         case 0x4263:
1734         case 0x4264:
1735         case 0x4265:
1736                 break;
1737         default:
1738                 if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1739                         hba->supports_pm = 1;
1740         }
1741
1742         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1743         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1744                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1745         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1746         hba->dma_size = cp_offset + sizeof(struct st_frame);
1747         if (hba->cardtype == st_seq ||
1748                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1749                 hba->extra_offset = hba->dma_size;
1750                 hba->dma_size += ST_ADDITIONAL_MEM;
1751         }
1752         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1753                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1754         if (!hba->dma_mem) {
1755                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1756                 if (hba->cardtype == st_seq ||
1757                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1758                         printk(KERN_WARNING DRV_NAME
1759                                 "(%s): allocating min buffer for controller\n",
1760                                 pci_name(pdev));
1761                         hba->dma_size = hba->extra_offset
1762                                 + ST_ADDITIONAL_MEM_MIN;
1763                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1764                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1765                 }
1766
1767                 if (!hba->dma_mem) {
1768                         err = -ENOMEM;
1769                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1770                                 pci_name(pdev));
1771                         goto out_iounmap;
1772                 }
1773         }
1774
1775         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1776         if (!hba->ccb) {
1777                 err = -ENOMEM;
1778                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1779                         pci_name(pdev));
1780                 goto out_pci_free;
1781         }
1782
1783         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1784                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1785         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1786         hba->copy_buffer = hba->dma_mem + cp_offset;
1787         hba->rq_count = ci->rq_count;
1788         hba->rq_size = ci->rq_size;
1789         hba->sts_count = ci->sts_count;
1790         hba->alloc_rq = ci->alloc_rq;
1791         hba->map_sg = ci->map_sg;
1792         hba->send = ci->send;
1793         hba->mu_status = MU_STATE_STARTING;
1794         hba->msi_lock = 0;
1795
1796         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1797                 host->sg_tablesize = 38;
1798         else
1799                 host->sg_tablesize = 32;
1800         host->can_queue = ci->rq_count;
1801         host->cmd_per_lun = ci->rq_count;
1802         host->max_id = ci->max_id;
1803         host->max_lun = ci->max_lun;
1804         host->max_channel = ci->max_channel;
1805         host->unique_id = host->host_no;
1806         host->max_cmd_len = STEX_CDB_LENGTH;
1807
1808         hba->host = host;
1809         hba->pdev = pdev;
1810         init_waitqueue_head(&hba->reset_waitq);
1811
1812         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1813                  "stex_wq_%d", host->host_no);
1814         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1815         if (!hba->work_q) {
1816                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1817                         pci_name(pdev));
1818                 err = -ENOMEM;
1819                 goto out_ccb_free;
1820         }
1821         INIT_WORK(&hba->reset_work, stex_reset_work);
1822
1823         err = stex_request_irq(hba);
1824         if (err) {
1825                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1826                         pci_name(pdev));
1827                 goto out_free_wq;
1828         }
1829
1830         err = stex_handshake(hba);
1831         if (err)
1832                 goto out_free_irq;
1833
1834         pci_set_drvdata(pdev, hba);
1835
1836         err = scsi_add_host(host, &pdev->dev);
1837         if (err) {
1838                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1839                         pci_name(pdev));
1840                 goto out_free_irq;
1841         }
1842
1843         scsi_scan_host(host);
1844
1845         return 0;
1846
1847 out_free_irq:
1848         stex_free_irq(hba);
1849 out_free_wq:
1850         destroy_workqueue(hba->work_q);
1851 out_ccb_free:
1852         kfree(hba->ccb);
1853 out_pci_free:
1854         dma_free_coherent(&pdev->dev, hba->dma_size,
1855                           hba->dma_mem, hba->dma_handle);
1856 out_iounmap:
1857         iounmap(hba->mmio_base);
1858 out_release_regions:
1859         pci_release_regions(pdev);
1860 out_scsi_host_put:
1861         scsi_host_put(host);
1862 out_disable:
1863         pci_disable_device(pdev);
1864
1865         return err;
1866 }
1867
1868 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1869 {
1870         struct req_msg *req;
1871         struct st_msg_header *msg_h;
1872         unsigned long flags;
1873         unsigned long before;
1874         u16 tag = 0;
1875
1876         spin_lock_irqsave(hba->host->host_lock, flags);
1877
1878         if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1879                 hba->supports_pm == 1) {
1880                 if (st_sleep_mic == ST_NOTHANDLED) {
1881                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1882                         return;
1883                 }
1884         }
1885         req = hba->alloc_rq(hba);
1886         if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1887                 msg_h = (struct st_msg_header *)req - 1;
1888                 memset(msg_h, 0, hba->rq_size);
1889         } else
1890                 memset(req, 0, hba->rq_size);
1891
1892         if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1893                 || hba->cardtype == st_P3)
1894                 && st_sleep_mic == ST_IGNORED) {
1895                 req->cdb[0] = MGT_CMD;
1896                 req->cdb[1] = MGT_CMD_SIGNATURE;
1897                 req->cdb[2] = CTLR_CONFIG_CMD;
1898                 req->cdb[3] = CTLR_SHUTDOWN;
1899         } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1900                 && st_sleep_mic != ST_IGNORED) {
1901                 req->cdb[0] = MGT_CMD;
1902                 req->cdb[1] = MGT_CMD_SIGNATURE;
1903                 req->cdb[2] = CTLR_CONFIG_CMD;
1904                 req->cdb[3] = PMIC_SHUTDOWN;
1905                 req->cdb[4] = st_sleep_mic;
1906         } else {
1907                 req->cdb[0] = CONTROLLER_CMD;
1908                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1909                 req->cdb[2] = CTLR_POWER_SAVING;
1910         }
1911         hba->ccb[tag].cmd = NULL;
1912         hba->ccb[tag].sg_count = 0;
1913         hba->ccb[tag].sense_bufflen = 0;
1914         hba->ccb[tag].sense_buffer = NULL;
1915         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1916         hba->send(hba, req, tag);
1917         spin_unlock_irqrestore(hba->host->host_lock, flags);
1918         before = jiffies;
1919         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1920                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1921                         hba->ccb[tag].req_type = 0;
1922                         hba->mu_status = MU_STATE_STOP;
1923                         return;
1924                 }
1925                 msleep(1);
1926         }
1927         hba->mu_status = MU_STATE_STOP;
1928 }
1929
1930 static void stex_hba_free(struct st_hba *hba)
1931 {
1932         stex_free_irq(hba);
1933
1934         destroy_workqueue(hba->work_q);
1935
1936         iounmap(hba->mmio_base);
1937
1938         pci_release_regions(hba->pdev);
1939
1940         kfree(hba->ccb);
1941
1942         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1943                           hba->dma_mem, hba->dma_handle);
1944 }
1945
1946 static void stex_remove(struct pci_dev *pdev)
1947 {
1948         struct st_hba *hba = pci_get_drvdata(pdev);
1949
1950         hba->mu_status = MU_STATE_NOCONNECT;
1951         return_abnormal_state(hba, DID_NO_CONNECT);
1952         scsi_remove_host(hba->host);
1953
1954         scsi_block_requests(hba->host);
1955
1956         stex_hba_free(hba);
1957
1958         scsi_host_put(hba->host);
1959
1960         pci_disable_device(pdev);
1961
1962         unregister_reboot_notifier(&stex_notifier);
1963 }
1964
1965 static void stex_shutdown(struct pci_dev *pdev)
1966 {
1967         struct st_hba *hba = pci_get_drvdata(pdev);
1968
1969         if (hba->supports_pm == 0) {
1970                 stex_hba_stop(hba, ST_IGNORED);
1971         } else if (hba->supports_pm == 1 && S6flag) {
1972                 unregister_reboot_notifier(&stex_notifier);
1973                 stex_hba_stop(hba, ST_S6);
1974         } else
1975                 stex_hba_stop(hba, ST_S5);
1976 }
1977
1978 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1979 {
1980         switch (state.event) {
1981         case PM_EVENT_SUSPEND:
1982                 return ST_S3;
1983         case PM_EVENT_HIBERNATE:
1984                 hba->msi_lock = 0;
1985                 return ST_S4;
1986         default:
1987                 return ST_NOTHANDLED;
1988         }
1989 }
1990
1991 static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1992 {
1993         struct st_hba *hba = pci_get_drvdata(pdev);
1994
1995         if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1996                 && hba->supports_pm == 1)
1997                 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
1998         else
1999                 stex_hba_stop(hba, ST_IGNORED);
2000         return 0;
2001 }
2002
2003 static int stex_resume(struct pci_dev *pdev)
2004 {
2005         struct st_hba *hba = pci_get_drvdata(pdev);
2006
2007         hba->mu_status = MU_STATE_STARTING;
2008         stex_handshake(hba);
2009         return 0;
2010 }
2011
2012 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
2013 {
2014         S6flag = 1;
2015         return NOTIFY_OK;
2016 }
2017 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
2018
2019 static struct pci_driver stex_pci_driver = {
2020         .name           = DRV_NAME,
2021         .id_table       = stex_pci_tbl,
2022         .probe          = stex_probe,
2023         .remove         = stex_remove,
2024         .shutdown       = stex_shutdown,
2025         .suspend        = stex_suspend,
2026         .resume         = stex_resume,
2027 };
2028
2029 static int __init stex_init(void)
2030 {
2031         printk(KERN_INFO DRV_NAME
2032                 ": Promise SuperTrak EX Driver version: %s\n",
2033                  ST_DRIVER_VERSION);
2034
2035         return pci_register_driver(&stex_pci_driver);
2036 }
2037
2038 static void __exit stex_exit(void)
2039 {
2040         pci_unregister_driver(&stex_pci_driver);
2041 }
2042
2043 module_init(stex_init);
2044 module_exit(stex_exit);