1 // SPDX-License-Identifier: GPL-2.0
3 * driver for Microchip PQI-based storage controllers
4 * Copyright (c) 2019-2021 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
8 * Questions/Comments/Bugfixes to storagedev@microchip.com
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/pci.h>
16 #include <scsi/scsi_device.h>
17 #include <asm/unaligned.h>
19 #include "smartpqi_sis.h"
21 /* legacy SIS interface commands */
22 #define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
23 #define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
24 #define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
26 /* for submission of legacy SIS commands */
27 #define SIS_REENABLE_SIS_MODE 0x1
28 #define SIS_ENABLE_MSIX 0x40
29 #define SIS_ENABLE_INTX 0x80
30 #define SIS_SOFT_RESET 0x100
31 #define SIS_CMD_READY 0x200
32 #define SIS_TRIGGER_SHUTDOWN 0x800000
33 #define SIS_PQI_RESET_QUIESCE 0x1000000
35 #define SIS_CMD_COMPLETE 0x1000
36 #define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000
38 #define SIS_CMD_STATUS_SUCCESS 0x1
39 #define SIS_CMD_COMPLETE_TIMEOUT_SECS 30
40 #define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10
42 /* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */
43 #define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000
44 #define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2
45 #define SIS_PQI_MODE_SUPPORTED 0x4
46 #define SIS_PQI_RESET_QUIESCE_SUPPORTED 0x8
47 #define SIS_REQUIRED_EXTENDED_PROPERTIES \
48 (SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
50 /* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
51 #define SIS_BASE_STRUCT_REVISION 9
52 #define SIS_BASE_STRUCT_ALIGNMENT 16
54 #define SIS_CTRL_KERNEL_FW_TRIAGE 0x3
55 #define SIS_CTRL_KERNEL_UP 0x80
56 #define SIS_CTRL_KERNEL_PANIC 0x100
57 #define SIS_CTRL_READY_TIMEOUT_SECS 180
58 #define SIS_CTRL_READY_RESUME_TIMEOUT_SECS 90
59 #define SIS_CTRL_READY_POLL_INTERVAL_MSECS 10
61 enum sis_fw_triage_status {
62 FW_TRIAGE_NOT_STARTED = 0,
64 FW_TRIAGE_COND_INVALID,
70 /* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
71 struct sis_base_struct {
72 __le32 revision; /* revision of this structure */
73 __le32 flags; /* reserved */
74 __le32 error_buffer_paddr_low; /* lower 32 bits of physical memory */
75 /* buffer for PQI error response */
77 __le32 error_buffer_paddr_high; /* upper 32 bits of physical */
78 /* memory buffer for PQI */
79 /* error response data */
80 __le32 error_buffer_element_length; /* length of each PQI error */
81 /* response buffer element */
83 __le32 error_buffer_num_elements; /* total number of PQI error */
84 /* response buffers available */
89 static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info *ctrl_info,
90 unsigned int timeout_secs)
92 unsigned long timeout;
95 timeout = (timeout_secs * HZ) + jiffies;
98 status = readl(&ctrl_info->registers->sis_firmware_status);
100 if (status & SIS_CTRL_KERNEL_PANIC) {
101 dev_err(&ctrl_info->pci_dev->dev,
102 "controller is offline: status code 0x%x\n",
104 &ctrl_info->registers->sis_mailbox[7]));
107 if (status & SIS_CTRL_KERNEL_UP)
110 if (time_after(jiffies, timeout)) {
111 dev_err(&ctrl_info->pci_dev->dev,
112 "controller not ready after %u seconds\n",
116 msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS);
122 int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info)
124 return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
125 SIS_CTRL_READY_TIMEOUT_SECS);
128 int sis_wait_for_ctrl_ready_resume(struct pqi_ctrl_info *ctrl_info)
130 return sis_wait_for_ctrl_ready_with_timeout(ctrl_info,
131 SIS_CTRL_READY_RESUME_TIMEOUT_SECS);
134 bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info)
139 status = readl(&ctrl_info->registers->sis_firmware_status);
141 if (status & SIS_CTRL_KERNEL_PANIC)
147 dev_err(&ctrl_info->pci_dev->dev,
148 "controller is offline: status code 0x%x\n",
149 readl(&ctrl_info->registers->sis_mailbox[7]));
154 bool sis_is_kernel_up(struct pqi_ctrl_info *ctrl_info)
156 return readl(&ctrl_info->registers->sis_firmware_status) &
160 u32 sis_get_product_id(struct pqi_ctrl_info *ctrl_info)
162 return readl(&ctrl_info->registers->sis_product_identifier);
165 /* used for passing command parameters/results when issuing SIS commands */
166 struct sis_sync_cmd_params {
167 u32 mailbox[6]; /* mailboxes 0-5 */
170 static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
171 u32 cmd, struct sis_sync_cmd_params *params)
173 struct pqi_ctrl_registers __iomem *registers;
175 unsigned long timeout;
179 registers = ctrl_info->registers;
181 /* Write the command to mailbox 0. */
182 writel(cmd, ®isters->sis_mailbox[0]);
185 * Write the command parameters to mailboxes 1-4 (mailbox 5 is not used
186 * when sending a command to the controller).
188 for (i = 1; i <= 4; i++)
189 writel(params->mailbox[i], ®isters->sis_mailbox[i]);
191 /* Clear the command doorbell. */
192 writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL,
193 ®isters->sis_ctrl_to_host_doorbell_clear);
195 /* Disable doorbell interrupts by masking all interrupts. */
196 writel(~0, ®isters->sis_interrupt_mask);
199 * Force the completion of the interrupt mask register write before
200 * submitting the command.
202 readl(®isters->sis_interrupt_mask);
204 /* Submit the command to the controller. */
205 writel(SIS_CMD_READY, ®isters->sis_host_to_ctrl_doorbell);
208 * Poll for command completion. Note that the call to msleep() is at
209 * the top of the loop in order to give the controller time to start
210 * processing the command before we start polling.
212 timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * HZ) + jiffies;
214 msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS);
215 doorbell = readl(®isters->sis_ctrl_to_host_doorbell);
216 if (doorbell & SIS_CMD_COMPLETE)
218 if (time_after(jiffies, timeout))
222 /* Read the command status from mailbox 0. */
223 cmd_status = readl(®isters->sis_mailbox[0]);
224 if (cmd_status != SIS_CMD_STATUS_SUCCESS) {
225 dev_err(&ctrl_info->pci_dev->dev,
226 "SIS command failed for command 0x%x: status = 0x%x\n",
232 * The command completed successfully, so save the command status and
233 * read the values returned in mailboxes 1-5.
235 params->mailbox[0] = cmd_status;
236 for (i = 1; i < ARRAY_SIZE(params->mailbox); i++)
237 params->mailbox[i] = readl(®isters->sis_mailbox[i]);
243 * This function verifies that we are talking to a controller that speaks PQI.
246 int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
250 u32 extended_properties;
251 struct sis_sync_cmd_params params;
253 memset(¶ms, 0, sizeof(params));
255 rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES,
260 properties = params.mailbox[1];
262 if (!(properties & SIS_EXTENDED_PROPERTIES_SUPPORTED))
265 extended_properties = params.mailbox[4];
267 if ((extended_properties & SIS_REQUIRED_EXTENDED_PROPERTIES) !=
268 SIS_REQUIRED_EXTENDED_PROPERTIES)
271 if (extended_properties & SIS_PQI_RESET_QUIESCE_SUPPORTED)
272 ctrl_info->pqi_reset_quiesce_supported = true;
277 int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info)
280 struct sis_sync_cmd_params params;
282 memset(¶ms, 0, sizeof(params));
284 rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES,
289 ctrl_info->max_sg_entries = params.mailbox[1];
290 ctrl_info->max_transfer_size = params.mailbox[2];
291 ctrl_info->max_outstanding_requests = params.mailbox[3];
292 ctrl_info->config_table_offset = params.mailbox[4];
293 ctrl_info->config_table_length = params.mailbox[5];
298 int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
301 void *base_struct_unaligned;
302 struct sis_base_struct *base_struct;
303 struct sis_sync_cmd_params params;
304 unsigned long error_buffer_paddr;
305 dma_addr_t bus_address;
307 base_struct_unaligned = kzalloc(sizeof(*base_struct)
308 + SIS_BASE_STRUCT_ALIGNMENT - 1, GFP_KERNEL);
309 if (!base_struct_unaligned)
312 base_struct = PTR_ALIGN(base_struct_unaligned,
313 SIS_BASE_STRUCT_ALIGNMENT);
314 error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle;
316 put_unaligned_le32(SIS_BASE_STRUCT_REVISION, &base_struct->revision);
317 put_unaligned_le32(lower_32_bits(error_buffer_paddr),
318 &base_struct->error_buffer_paddr_low);
319 put_unaligned_le32(upper_32_bits(error_buffer_paddr),
320 &base_struct->error_buffer_paddr_high);
321 put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH,
322 &base_struct->error_buffer_element_length);
323 put_unaligned_le32(ctrl_info->max_io_slots,
324 &base_struct->error_buffer_num_elements);
326 bus_address = dma_map_single(&ctrl_info->pci_dev->dev, base_struct,
327 sizeof(*base_struct), DMA_TO_DEVICE);
328 if (dma_mapping_error(&ctrl_info->pci_dev->dev, bus_address)) {
333 memset(¶ms, 0, sizeof(params));
334 params.mailbox[1] = lower_32_bits((u64)bus_address);
335 params.mailbox[2] = upper_32_bits((u64)bus_address);
336 params.mailbox[3] = sizeof(*base_struct);
338 rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
341 dma_unmap_single(&ctrl_info->pci_dev->dev, bus_address,
342 sizeof(*base_struct), DMA_TO_DEVICE);
344 kfree(base_struct_unaligned);
349 #define SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS 30
351 static int sis_wait_for_doorbell_bit_to_clear(
352 struct pqi_ctrl_info *ctrl_info, u32 bit)
355 u32 doorbell_register;
356 unsigned long timeout;
358 timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * HZ) + jiffies;
362 readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
363 if ((doorbell_register & bit) == 0)
365 if (readl(&ctrl_info->registers->sis_firmware_status) &
366 SIS_CTRL_KERNEL_PANIC) {
370 if (time_after(jiffies, timeout)) {
371 dev_err(&ctrl_info->pci_dev->dev,
372 "doorbell register bit 0x%x not cleared\n",
377 usleep_range(1000, 2000);
383 static inline int sis_set_doorbell_bit(struct pqi_ctrl_info *ctrl_info, u32 bit)
385 writel(bit, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
387 return sis_wait_for_doorbell_bit_to_clear(ctrl_info, bit);
390 void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
392 sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_MSIX);
395 void sis_enable_intx(struct pqi_ctrl_info *ctrl_info)
397 sis_set_doorbell_bit(ctrl_info, SIS_ENABLE_INTX);
400 void sis_shutdown_ctrl(struct pqi_ctrl_info *ctrl_info,
401 enum pqi_ctrl_shutdown_reason ctrl_shutdown_reason)
403 if (readl(&ctrl_info->registers->sis_firmware_status) &
404 SIS_CTRL_KERNEL_PANIC)
407 if (ctrl_info->firmware_triage_supported)
408 writel(ctrl_shutdown_reason, &ctrl_info->registers->sis_ctrl_shutdown_reason_code);
410 writel(SIS_TRIGGER_SHUTDOWN, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
413 int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info)
415 return sis_set_doorbell_bit(ctrl_info, SIS_PQI_RESET_QUIESCE);
418 int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
420 return sis_set_doorbell_bit(ctrl_info, SIS_REENABLE_SIS_MODE);
423 void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value)
425 writel(value, &ctrl_info->registers->sis_driver_scratch);
428 u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info)
430 return readl(&ctrl_info->registers->sis_driver_scratch);
433 static inline enum sis_fw_triage_status
434 sis_read_firmware_triage_status(struct pqi_ctrl_info *ctrl_info)
436 return ((enum sis_fw_triage_status)(readl(&ctrl_info->registers->sis_firmware_status) &
437 SIS_CTRL_KERNEL_FW_TRIAGE));
440 void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
442 writel(SIS_SOFT_RESET,
443 &ctrl_info->registers->sis_host_to_ctrl_doorbell);
446 #define SIS_FW_TRIAGE_STATUS_TIMEOUT_SECS 300
447 #define SIS_FW_TRIAGE_STATUS_POLL_INTERVAL_SECS 1
449 int sis_wait_for_fw_triage_completion(struct pqi_ctrl_info *ctrl_info)
452 enum sis_fw_triage_status status;
453 unsigned long timeout;
455 timeout = (SIS_FW_TRIAGE_STATUS_TIMEOUT_SECS * HZ) + jiffies;
457 status = sis_read_firmware_triage_status(ctrl_info);
458 if (status == FW_TRIAGE_COND_INVALID) {
459 dev_err(&ctrl_info->pci_dev->dev,
460 "firmware triage condition invalid\n");
463 } else if (status == FW_TRIAGE_NOT_STARTED ||
464 status == FW_TRIAGE_COMPLETED) {
469 if (time_after(jiffies, timeout)) {
470 dev_err(&ctrl_info->pci_dev->dev,
471 "timed out waiting for firmware triage status\n");
476 ssleep(SIS_FW_TRIAGE_STATUS_POLL_INTERVAL_SECS);
482 void sis_verify_structures(void)
484 BUILD_BUG_ON(offsetof(struct sis_base_struct,
486 BUILD_BUG_ON(offsetof(struct sis_base_struct,
488 BUILD_BUG_ON(offsetof(struct sis_base_struct,
489 error_buffer_paddr_low) != 0x8);
490 BUILD_BUG_ON(offsetof(struct sis_base_struct,
491 error_buffer_paddr_high) != 0xc);
492 BUILD_BUG_ON(offsetof(struct sis_base_struct,
493 error_buffer_element_length) != 0x10);
494 BUILD_BUG_ON(offsetof(struct sis_base_struct,
495 error_buffer_num_elements) != 0x14);
496 BUILD_BUG_ON(sizeof(struct sis_base_struct) != 0x18);