drivers/scsi/qla4xxx/ql4_nx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * QLogic iSCSI HBA Driver
   4  * Copyright (c)  2003-2013 QLogic Corporation
   5  */
   6 #include <linux/delay.h>
   7 #include <linux/io.h>
   8 #include <linux/pci.h>
   9 #include <linux/ratelimit.h>
  10 #include "ql4_def.h"
  11 #include "ql4_glbl.h"
  12 #include "ql4_inline.h"
  13
  14 #include <linux/io-64-nonatomic-lo-hi.h>
  15
  16 #define TIMEOUT_100_MS  100
  17 #define MASK(n)         DMA_BIT_MASK(n)
  18 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  19 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  20 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  21 #define QLA82XX_PCI_MN_2M       (0)
  22 #define QLA82XX_PCI_MS_2M       (0x80000)
  23 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  24 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  25 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  26
  27 /* CRB window related */
  28 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  30 #define CRB_WINDOW_2M   (0x130060)
  31 #define CRB_HI(off)     ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  32                         ((off) & 0xf0000))
  33 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  34 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  35 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  36
  37 static inline void __iomem *
  38 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  39 {
  40         if ((off < ha->first_page_group_end) &&
  41             (off >= ha->first_page_group_start))
  42                 return (void __iomem *)(ha->nx_pcibase + off);
  43
  44         return NULL;
  45 }
  46
  47 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8,
  48                                 0x410000AC, 0x410000B8, 0x410000BC };
  49 #define MAX_CRB_XFORM 60
  50 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  51 static int qla4_8xxx_crb_table_initialized;
  52
  53 #define qla4_8xxx_crb_addr_transform(name) \
  54         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  55          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  56 static void
  57 qla4_82xx_crb_addr_transform_setup(void)
  58 {
  59         qla4_8xxx_crb_addr_transform(XDMA);
  60         qla4_8xxx_crb_addr_transform(TIMR);
  61         qla4_8xxx_crb_addr_transform(SRE);
  62         qla4_8xxx_crb_addr_transform(SQN3);
  63         qla4_8xxx_crb_addr_transform(SQN2);
  64         qla4_8xxx_crb_addr_transform(SQN1);
  65         qla4_8xxx_crb_addr_transform(SQN0);
  66         qla4_8xxx_crb_addr_transform(SQS3);
  67         qla4_8xxx_crb_addr_transform(SQS2);
  68         qla4_8xxx_crb_addr_transform(SQS1);
  69         qla4_8xxx_crb_addr_transform(SQS0);
  70         qla4_8xxx_crb_addr_transform(RPMX7);
  71         qla4_8xxx_crb_addr_transform(RPMX6);
  72         qla4_8xxx_crb_addr_transform(RPMX5);
  73         qla4_8xxx_crb_addr_transform(RPMX4);
  74         qla4_8xxx_crb_addr_transform(RPMX3);
  75         qla4_8xxx_crb_addr_transform(RPMX2);
  76         qla4_8xxx_crb_addr_transform(RPMX1);
  77         qla4_8xxx_crb_addr_transform(RPMX0);
  78         qla4_8xxx_crb_addr_transform(ROMUSB);
  79         qla4_8xxx_crb_addr_transform(SN);
  80         qla4_8xxx_crb_addr_transform(QMN);
  81         qla4_8xxx_crb_addr_transform(QMS);
  82         qla4_8xxx_crb_addr_transform(PGNI);
  83         qla4_8xxx_crb_addr_transform(PGND);
  84         qla4_8xxx_crb_addr_transform(PGN3);
  85         qla4_8xxx_crb_addr_transform(PGN2);
  86         qla4_8xxx_crb_addr_transform(PGN1);
  87         qla4_8xxx_crb_addr_transform(PGN0);
  88         qla4_8xxx_crb_addr_transform(PGSI);
  89         qla4_8xxx_crb_addr_transform(PGSD);
  90         qla4_8xxx_crb_addr_transform(PGS3);
  91         qla4_8xxx_crb_addr_transform(PGS2);
  92         qla4_8xxx_crb_addr_transform(PGS1);
  93         qla4_8xxx_crb_addr_transform(PGS0);
  94         qla4_8xxx_crb_addr_transform(PS);
  95         qla4_8xxx_crb_addr_transform(PH);
  96         qla4_8xxx_crb_addr_transform(NIU);
  97         qla4_8xxx_crb_addr_transform(I2Q);
  98         qla4_8xxx_crb_addr_transform(EG);
  99         qla4_8xxx_crb_addr_transform(MN);
 100         qla4_8xxx_crb_addr_transform(MS);
 101         qla4_8xxx_crb_addr_transform(CAS2);
 102         qla4_8xxx_crb_addr_transform(CAS1);
 103         qla4_8xxx_crb_addr_transform(CAS0);
 104         qla4_8xxx_crb_addr_transform(CAM);
 105         qla4_8xxx_crb_addr_transform(C2C1);
 106         qla4_8xxx_crb_addr_transform(C2C0);
 107         qla4_8xxx_crb_addr_transform(SMB);
 108         qla4_8xxx_crb_addr_transform(OCM0);
 109         qla4_8xxx_crb_addr_transform(I2C0);
 110
 111         qla4_8xxx_crb_table_initialized = 1;
 112 }
 113
 114 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 115         {{{0, 0,         0,         0} } },             /* 0: PCI */
 116         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 117                 {1, 0x0110000, 0x0120000, 0x130000},
 118                 {1, 0x0120000, 0x0122000, 0x124000},
 119                 {1, 0x0130000, 0x0132000, 0x126000},
 120                 {1, 0x0140000, 0x0142000, 0x128000},
 121                 {1, 0x0150000, 0x0152000, 0x12a000},
 122                 {1, 0x0160000, 0x0170000, 0x110000},
 123                 {1, 0x0170000, 0x0172000, 0x12e000},
 124                 {0, 0x0000000, 0x0000000, 0x000000},
 125                 {0, 0x0000000, 0x0000000, 0x000000},
 126                 {0, 0x0000000, 0x0000000, 0x000000},
 127                 {0, 0x0000000, 0x0000000, 0x000000},
 128                 {0, 0x0000000, 0x0000000, 0x000000},
 129                 {0, 0x0000000, 0x0000000, 0x000000},
 130                 {1, 0x01e0000, 0x01e0800, 0x122000},
 131                 {0, 0x0000000, 0x0000000, 0x000000} } },
 132         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 133         {{{0, 0,         0,         0} } },         /* 3: */
 134         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 135         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 136         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 137         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 138         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {0, 0x0000000, 0x0000000, 0x000000},
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {0, 0x0000000, 0x0000000, 0x000000},
 151                 {0, 0x0000000, 0x0000000, 0x000000},
 152                 {0, 0x0000000, 0x0000000, 0x000000},
 153                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 154         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {0, 0x0000000, 0x0000000, 0x000000},
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {0, 0x0000000, 0x0000000, 0x000000},
 167                 {0, 0x0000000, 0x0000000, 0x000000},
 168                 {0, 0x0000000, 0x0000000, 0x000000},
 169                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 170         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {0, 0x0000000, 0x0000000, 0x000000},
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {0, 0x0000000, 0x0000000, 0x000000},
 183                 {0, 0x0000000, 0x0000000, 0x000000},
 184                 {0, 0x0000000, 0x0000000, 0x000000},
 185                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 186         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {0, 0x0000000, 0x0000000, 0x000000},
 196                 {0, 0x0000000, 0x0000000, 0x000000},
 197                 {0, 0x0000000, 0x0000000, 0x000000},
 198                 {0, 0x0000000, 0x0000000, 0x000000},
 199                 {0, 0x0000000, 0x0000000, 0x000000},
 200                 {0, 0x0000000, 0x0000000, 0x000000},
 201                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 202         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 203         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 204         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 205         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 206         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 207         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 208         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 209         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 210         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 211         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 212         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 213         {{{0, 0,         0,         0} } },     /* 23: */
 214         {{{0, 0,         0,         0} } },     /* 24: */
 215         {{{0, 0,         0,         0} } },     /* 25: */
 216         {{{0, 0,         0,         0} } },     /* 26: */
 217         {{{0, 0,         0,         0} } },     /* 27: */
 218         {{{0, 0,         0,         0} } },     /* 28: */
 219         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 220         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 221         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 222         {{{0} } },                              /* 32: PCI */
 223         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 224                 {1, 0x2110000, 0x2120000, 0x130000},
 225                 {1, 0x2120000, 0x2122000, 0x124000},
 226                 {1, 0x2130000, 0x2132000, 0x126000},
 227                 {1, 0x2140000, 0x2142000, 0x128000},
 228                 {1, 0x2150000, 0x2152000, 0x12a000},
 229                 {1, 0x2160000, 0x2170000, 0x110000},
 230                 {1, 0x2170000, 0x2172000, 0x12e000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000},
 233                 {0, 0x0000000, 0x0000000, 0x000000},
 234                 {0, 0x0000000, 0x0000000, 0x000000},
 235                 {0, 0x0000000, 0x0000000, 0x000000},
 236                 {0, 0x0000000, 0x0000000, 0x000000},
 237                 {0, 0x0000000, 0x0000000, 0x000000},
 238                 {0, 0x0000000, 0x0000000, 0x000000} } },
 239         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 240         {{{0} } },                              /* 35: */
 241         {{{0} } },                              /* 36: */
 242         {{{0} } },                              /* 37: */
 243         {{{0} } },                              /* 38: */
 244         {{{0} } },                              /* 39: */
 245         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 246         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 247         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 248         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 249         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 250         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 251         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 252         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 253         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 254         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 255         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 256         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 257         {{{0} } },                              /* 52: */
 258         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 259         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 260         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 261         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 262         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 263         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 264         {{{0} } },                              /* 59: I2C0 */
 265         {{{0} } },                              /* 60: I2C1 */
 266         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 267         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 268         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 269 };
 270
 271 /*
 272  * top 12 bits of crb internal address (hub, agent)
 273  */
 274 static unsigned qla4_82xx_crb_hub_agt[64] = {
 275         0,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 279         0,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 302         0,
 303         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 304         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 305         0,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 307         0,
 308         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 309         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 310         0,
 311         0,
 312         0,
 313         0,
 314         0,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 316         0,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 327         0,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 329         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 330         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 332         0,
 333         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 334         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 335         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 336         0,
 337         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 338         0,
 339 };
 340
 341 /* Device states */
 342 static char *qdev_state[] = {
 343         "Unknown",
 344         "Cold",
 345         "Initializing",
 346         "Ready",
 347         "Need Reset",
 348         "Need Quiescent",
 349         "Failed",
 350         "Quiescent",
 351 };
 352
 353 /*
 354  * In: 'off' is offset from CRB space in 128M pci map
 355  * Out: 'off' is 2M pci map addr
 356  * side effect: lock crb window
 357  */
 358 static void
 359 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 360 {
 361         u32 win_read;
 362
 363         ha->crb_win = CRB_HI(*off);
 364         writel(ha->crb_win,
 365                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 366
 367         /* Read back value to make sure write has gone through before trying
 368         * to use it. */
 369         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 370         if (win_read != ha->crb_win) {
 371                 DEBUG2(ql4_printk(KERN_INFO, ha,
 372                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 373                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 374         }
 375         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 376 }
 377
 378 void
 379 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 380 {
 381         unsigned long flags = 0;
 382         int rv;
 383
 384         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 385
 386         BUG_ON(rv == -1);
 387
 388         if (rv == 1) {
 389                 write_lock_irqsave(&ha->hw_lock, flags);
 390                 qla4_82xx_crb_win_lock(ha);
 391                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 392         }
 393
 394         writel(data, (void __iomem *)off);
 395
 396         if (rv == 1) {
 397                 qla4_82xx_crb_win_unlock(ha);
 398                 write_unlock_irqrestore(&ha->hw_lock, flags);
 399         }
 400 }
 401
 402 uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
 403 {
 404         unsigned long flags = 0;
 405         int rv;
 406         u32 data;
 407
 408         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 409
 410         BUG_ON(rv == -1);
 411
 412         if (rv == 1) {
 413                 write_lock_irqsave(&ha->hw_lock, flags);
 414                 qla4_82xx_crb_win_lock(ha);
 415                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 416         }
 417         data = readl((void __iomem *)off);
 418
 419         if (rv == 1) {
 420                 qla4_82xx_crb_win_unlock(ha);
 421                 write_unlock_irqrestore(&ha->hw_lock, flags);
 422         }
 423         return data;
 424 }
 425
 426 /* Minidump related functions */
 427 int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data)
 428 {
 429         uint32_t win_read, off_value;
 430         int rval = QLA_SUCCESS;
 431
 432         off_value  = off & 0xFFFF0000;
 433         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 434
 435         /*
 436          * Read back value to make sure write has gone through before trying
 437          * to use it.
 438          */
 439         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 440         if (win_read != off_value) {
 441                 DEBUG2(ql4_printk(KERN_INFO, ha,
 442                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 443                                   __func__, off_value, win_read, off));
 444                 rval = QLA_ERROR;
 445         } else {
 446                 off_value  = off & 0x0000FFFF;
 447                 *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
 448                                                ha->nx_pcibase));
 449         }
 450         return rval;
 451 }
 452
 453 int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data)
 454 {
 455         uint32_t win_read, off_value;
 456         int rval = QLA_SUCCESS;
 457
 458         off_value  = off & 0xFFFF0000;
 459         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 460
 461         /* Read back value to make sure write has gone through before trying
 462          * to use it.
 463          */
 464         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 465         if (win_read != off_value) {
 466                 DEBUG2(ql4_printk(KERN_INFO, ha,
 467                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 468                                   __func__, off_value, win_read, off));
 469                 rval = QLA_ERROR;
 470         } else {
 471                 off_value  = off & 0x0000FFFF;
 472                 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
 473                                               ha->nx_pcibase));
 474         }
 475         return rval;
 476 }
 477
 478 #define CRB_WIN_LOCK_TIMEOUT 100000000
 479
 480 int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
 481 {
 482         int i;
 483         int done = 0, timeout = 0;
 484
 485         while (!done) {
 486                 /* acquire semaphore3 from PCI HW block */
 487                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 488                 if (done == 1)
 489                         break;
 490                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 491                         return -1;
 492
 493                 timeout++;
 494
 495                 /* Yield CPU */
 496                 if (!in_interrupt())
 497                         schedule();
 498                 else {
 499                         for (i = 0; i < 20; i++)
 500                                 cpu_relax();    /*This a nop instr on i386*/
 501                 }
 502         }
 503         qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 504         return 0;
 505 }
 506
 507 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
 508 {
 509         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 510 }
 511
 512 #define IDC_LOCK_TIMEOUT 100000000
 513
 514 /**
 515  * qla4_82xx_idc_lock - hw_lock
 516  * @ha: pointer to adapter structure
 517  *
 518  * General purpose lock used to synchronize access to
 519  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 520  **/
 521 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
 522 {
 523         int i;
 524         int done = 0, timeout = 0;
 525
 526         while (!done) {
 527                 /* acquire semaphore5 from PCI HW block */
 528                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 529                 if (done == 1)
 530                         break;
 531                 if (timeout >= IDC_LOCK_TIMEOUT)
 532                         return -1;
 533
 534                 timeout++;
 535
 536                 /* Yield CPU */
 537                 if (!in_interrupt())
 538                         schedule();
 539                 else {
 540                         for (i = 0; i < 20; i++)
 541                                 cpu_relax();    /*This a nop instr on i386*/
 542                 }
 543         }
 544         return 0;
 545 }
 546
 547 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
 548 {
 549         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 550 }
 551
 552 int
 553 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 554 {
 555         struct crb_128M_2M_sub_block_map *m;
 556
 557         if (*off >= QLA82XX_CRB_MAX)
 558                 return -1;
 559
 560         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 561                 *off = (*off - QLA82XX_PCI_CAMQM) +
 562                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 563                 return 0;
 564         }
 565
 566         if (*off < QLA82XX_PCI_CRBSPACE)
 567                 return -1;
 568
 569         *off -= QLA82XX_PCI_CRBSPACE;
 570         /*
 571          * Try direct map
 572          */
 573
 574         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 575
 576         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 577                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 578                 return 0;
 579         }
 580
 581         /*
 582          * Not in direct map, use crb window
 583          */
 584         return 1;
 585 }
 586
 587 /*
 588 * check memory access boundary.
 589 * used by test agent. support ddr access only for now
 590 */
 591 static unsigned long
 592 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
 593                 unsigned long long addr, int size)
 594 {
 595         if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 596             QLA8XXX_ADDR_DDR_NET_MAX) ||
 597             !QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
 598             QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
 599             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 600                 return 0;
 601         }
 602         return 1;
 603 }
 604
 605 static int qla4_82xx_pci_set_window_warning_count;
 606
 607 static unsigned long
 608 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 609 {
 610         int window;
 611         u32 win_read;
 612
 613         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 614             QLA8XXX_ADDR_DDR_NET_MAX)) {
 615                 /* DDR network side */
 616                 window = MN_WIN(addr);
 617                 ha->ddr_mn_window = window;
 618                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 619                     QLA82XX_PCI_CRBSPACE, window);
 620                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 621                     QLA82XX_PCI_CRBSPACE);
 622                 if ((win_read << 17) != window) {
 623                         ql4_printk(KERN_WARNING, ha,
 624                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 625                         __func__, window, win_read);
 626                 }
 627                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 628         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 629                                 QLA8XXX_ADDR_OCM0_MAX)) {
 630                 unsigned int temp1;
 631                 /* if bits 19:18&17:11 are on */
 632                 if ((addr & 0x00ff800) == 0xff800) {
 633                         printk("%s: QM access not handled.\n", __func__);
 634                         addr = -1UL;
 635                 }
 636
 637                 window = OCM_WIN(addr);
 638                 ha->ddr_mn_window = window;
 639                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 640                     QLA82XX_PCI_CRBSPACE, window);
 641                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 642                     QLA82XX_PCI_CRBSPACE);
 643                 temp1 = ((window & 0x1FF) << 7) |
 644                     ((window & 0x0FFFE0000) >> 17);
 645                 if (win_read != temp1) {
 646                         printk("%s: Written OCMwin (0x%x) != Read"
 647                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 648                 }
 649                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 650
 651         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 652                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 653                 /* QDR network side */
 654                 window = MS_WIN(addr);
 655                 ha->qdr_sn_window = window;
 656                 qla4_82xx_wr_32(ha, ha->ms_win_crb |
 657                     QLA82XX_PCI_CRBSPACE, window);
 658                 win_read = qla4_82xx_rd_32(ha,
 659                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 660                 if (win_read != window) {
 661                         printk("%s: Written MSwin (0x%x) != Read "
 662                             "MSwin (0x%x)\n", __func__, window, win_read);
 663                 }
 664                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 665
 666         } else {
 667                 /*
 668                  * peg gdb frequently accesses memory that doesn't exist,
 669                  * this limits the chit chat so debugging isn't slowed down.
 670                  */
 671                 if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
 672                     (qla4_82xx_pci_set_window_warning_count%64 == 0)) {
 673                         printk("%s: Warning:%s Unknown address range!\n",
 674                             __func__, DRIVER_NAME);
 675                 }
 676                 addr = -1UL;
 677         }
 678         return addr;
 679 }
 680
 681 /* check if address is in the same windows as the previous access */
 682 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
 683                 unsigned long long addr)
 684 {
 685         int window;
 686         unsigned long long qdr_max;
 687
 688         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 689
 690         if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
 691             QLA8XXX_ADDR_DDR_NET_MAX)) {
 692                 /* DDR network side */
 693                 BUG();  /* MN access can not come here */
 694         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
 695              QLA8XXX_ADDR_OCM0_MAX)) {
 696                 return 1;
 697         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
 698              QLA8XXX_ADDR_OCM1_MAX)) {
 699                 return 1;
 700         } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
 701             qdr_max)) {
 702                 /* QDR network side */
 703                 window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
 704                 if (ha->qdr_sn_window == window)
 705                         return 1;
 706         }
 707
 708         return 0;
 709 }
 710
 711 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
 712                 u64 off, void *data, int size)
 713 {
 714         unsigned long flags;
 715         void __iomem *addr;
 716         int ret = 0;
 717         u64 start;
 718         void __iomem *mem_ptr = NULL;
 719         unsigned long mem_base;
 720         unsigned long mem_page;
 721
 722         write_lock_irqsave(&ha->hw_lock, flags);
 723
 724         /*
 725          * If attempting to access unknown address or straddle hw windows,
 726          * do not access.
 727          */
 728         start = qla4_82xx_pci_set_window(ha, off);
 729         if ((start == -1UL) ||
 730             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 731                 write_unlock_irqrestore(&ha->hw_lock, flags);
 732                 printk(KERN_ERR"%s out of bound pci memory access. "
 733                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 734                 return -1;
 735         }
 736
 737         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 738         if (!addr) {
 739                 write_unlock_irqrestore(&ha->hw_lock, flags);
 740                 mem_base = pci_resource_start(ha->pdev, 0);
 741                 mem_page = start & PAGE_MASK;
 742                 /* Map two pages whenever user tries to access addresses in two
 743                    consecutive pages.
 744                  */
 745                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 746                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 747                 else
 748                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 749
 750                 if (mem_ptr == NULL) {
 751                         *(u8 *)data = 0;
 752                         return -1;
 753                 }
 754                 addr = mem_ptr;
 755                 addr += start & (PAGE_SIZE - 1);
 756                 write_lock_irqsave(&ha->hw_lock, flags);
 757         }
 758
 759         switch (size) {
 760         case 1:
 761                 *(u8  *)data = readb(addr);
 762                 break;
 763         case 2:
 764                 *(u16 *)data = readw(addr);
 765                 break;
 766         case 4:
 767                 *(u32 *)data = readl(addr);
 768                 break;
 769         case 8:
 770                 *(u64 *)data = readq(addr);
 771                 break;
 772         default:
 773                 ret = -1;
 774                 break;
 775         }
 776         write_unlock_irqrestore(&ha->hw_lock, flags);
 777
 778         if (mem_ptr)
 779                 iounmap(mem_ptr);
 780         return ret;
 781 }
 782
 783 static int
 784 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 785                 void *data, int size)
 786 {
 787         unsigned long flags;
 788         void __iomem *addr;
 789         int ret = 0;
 790         u64 start;
 791         void __iomem *mem_ptr = NULL;
 792         unsigned long mem_base;
 793         unsigned long mem_page;
 794
 795         write_lock_irqsave(&ha->hw_lock, flags);
 796
 797         /*
 798          * If attempting to access unknown address or straddle hw windows,
 799          * do not access.
 800          */
 801         start = qla4_82xx_pci_set_window(ha, off);
 802         if ((start == -1UL) ||
 803             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 804                 write_unlock_irqrestore(&ha->hw_lock, flags);
 805                 printk(KERN_ERR"%s out of bound pci memory access. "
 806                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 807                 return -1;
 808         }
 809
 810         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 811         if (!addr) {
 812                 write_unlock_irqrestore(&ha->hw_lock, flags);
 813                 mem_base = pci_resource_start(ha->pdev, 0);
 814                 mem_page = start & PAGE_MASK;
 815                 /* Map two pages whenever user tries to access addresses in two
 816                    consecutive pages.
 817                  */
 818                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 819                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 820                 else
 821                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 822                 if (mem_ptr == NULL)
 823                         return -1;
 824
 825                 addr = mem_ptr;
 826                 addr += start & (PAGE_SIZE - 1);
 827                 write_lock_irqsave(&ha->hw_lock, flags);
 828         }
 829
 830         switch (size) {
 831         case 1:
 832                 writeb(*(u8 *)data, addr);
 833                 break;
 834         case 2:
 835                 writew(*(u16 *)data, addr);
 836                 break;
 837         case 4:
 838                 writel(*(u32 *)data, addr);
 839                 break;
 840         case 8:
 841                 writeq(*(u64 *)data, addr);
 842                 break;
 843         default:
 844                 ret = -1;
 845                 break;
 846         }
 847         write_unlock_irqrestore(&ha->hw_lock, flags);
 848         if (mem_ptr)
 849                 iounmap(mem_ptr);
 850         return ret;
 851 }
 852
 853 #define MTU_FUDGE_FACTOR 100
 854
 855 static unsigned long
 856 qla4_82xx_decode_crb_addr(unsigned long addr)
 857 {
 858         int i;
 859         unsigned long base_addr, offset, pci_base;
 860
 861         if (!qla4_8xxx_crb_table_initialized)
 862                 qla4_82xx_crb_addr_transform_setup();
 863
 864         pci_base = ADDR_ERROR;
 865         base_addr = addr & 0xfff00000;
 866         offset = addr & 0x000fffff;
 867
 868         for (i = 0; i < MAX_CRB_XFORM; i++) {
 869                 if (crb_addr_xform[i] == base_addr) {
 870                         pci_base = i << 20;
 871                         break;
 872                 }
 873         }
 874         if (pci_base == ADDR_ERROR)
 875                 return pci_base;
 876         else
 877                 return pci_base + offset;
 878 }
 879
 880 static long rom_max_timeout = 100;
 881 static long qla4_82xx_rom_lock_timeout = 100;
 882
 883 static int
 884 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
 885 {
 886         int i;
 887         int done = 0, timeout = 0;
 888
 889         while (!done) {
 890                 /* acquire semaphore2 from PCI HW block */
 891
 892                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 893                 if (done == 1)
 894                         break;
 895                 if (timeout >= qla4_82xx_rom_lock_timeout)
 896                         return -1;
 897
 898                 timeout++;
 899
 900                 /* Yield CPU */
 901                 if (!in_interrupt())
 902                         schedule();
 903                 else {
 904                         for (i = 0; i < 20; i++)
 905                                 cpu_relax();    /*This a nop instr on i386*/
 906                 }
 907         }
 908         qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 909         return 0;
 910 }
 911
 912 static void
 913 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
 914 {
 915         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 916 }
 917
 918 static int
 919 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
 920 {
 921         long timeout = 0;
 922         long done = 0 ;
 923
 924         while (done == 0) {
 925                 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 926                 done &= 2;
 927                 timeout++;
 928                 if (timeout >= rom_max_timeout) {
 929                         printk("%s: Timeout reached  waiting for rom done",
 930                                         DRIVER_NAME);
 931                         return -1;
 932                 }
 933         }
 934         return 0;
 935 }
 936
 937 static int
 938 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 939 {
 940         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 941         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 942         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 943         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 944         if (qla4_82xx_wait_rom_done(ha)) {
 945                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 946                 return -1;
 947         }
 948         /* reset abyte_cnt and dummy_byte_cnt */
 949         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 950         udelay(10);
 951         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 952
 953         *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 954         return 0;
 955 }
 956
 957 static int
 958 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 959 {
 960         int ret, loops = 0;
 961
 962         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 963                 udelay(100);
 964                 loops++;
 965         }
 966         if (loops >= 50000) {
 967                 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
 968                            DRIVER_NAME);
 969                 return -1;
 970         }
 971         ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
 972         qla4_82xx_rom_unlock(ha);
 973         return ret;
 974 }
 975
 976 /*
 977  * This routine does CRB initialize sequence
 978  * to put the ISP into operational state
 979  */
 980 static int
 981 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 982 {
 983         int addr, val;
 984         int i ;
 985         struct crb_addr_pair *buf;
 986         unsigned long off;
 987         unsigned offset, n;
 988
 989         struct crb_addr_pair {
 990                 long addr;
 991                 long data;
 992         };
 993
 994         /* Halt all the indiviual PEGs and other blocks of the ISP */
 995         qla4_82xx_rom_lock(ha);
 996
 997         /* disable all I2Q */
 998         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 999         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1000         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1001         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1002         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1003         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1004
1005         /* disable all niu interrupts */
1006         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1007         /* disable xge rx/tx */
1008         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1009         /* disable xg1 rx/tx */
1010         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1011         /* disable sideband mac */
1012         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1013         /* disable ap0 mac */
1014         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1015         /* disable ap1 mac */
1016         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1017
1018         /* halt sre */
1019         val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1020         qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1021
1022         /* halt epg */
1023         qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1024
1025         /* halt timers */
1026         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1027         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1028         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1029         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1030         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1031         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1032
1033         /* halt pegs */
1034         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1035         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1036         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1037         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1038         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1039         msleep(5);
1040
1041         /* big hammer */
1042         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1043                 /* don't reset CAM block on reset */
1044                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1045         else
1046                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1047
1048         qla4_82xx_rom_unlock(ha);
1049
1050         /* Read the signature value from the flash.
1051          * Offset 0: Contain signature (0xcafecafe)
1052          * Offset 4: Offset and number of addr/value pairs
1053          * that present in CRB initialize sequence
1054          */
1055         if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1056             qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1057                 ql4_printk(KERN_WARNING, ha,
1058                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1059                 return -1;
1060         }
1061
1062         /* Offset in flash = lower 16 bits
1063          * Number of enteries = upper 16 bits
1064          */
1065         offset = n & 0xffffU;
1066         n = (n >> 16) & 0xffffU;
1067
1068         /* number of addr/value pair should not exceed 1024 enteries */
1069         if (n  >= 1024) {
1070                 ql4_printk(KERN_WARNING, ha,
1071                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1072                     DRIVER_NAME, __func__, n);
1073                 return -1;
1074         }
1075
1076         ql4_printk(KERN_INFO, ha,
1077                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1078
1079         buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1080         if (buf == NULL) {
1081                 ql4_printk(KERN_WARNING, ha,
1082                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1083                 return -1;
1084         }
1085
1086         for (i = 0; i < n; i++) {
1087                 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1088                     qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1089                     0) {
1090                         kfree(buf);
1091                         return -1;
1092                 }
1093
1094                 buf[i].addr = addr;
1095                 buf[i].data = val;
1096         }
1097
1098         for (i = 0; i < n; i++) {
1099                 /* Translate internal CRB initialization
1100                  * address to PCI bus address
1101                  */
1102                 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1103                     QLA82XX_PCI_CRBSPACE;
1104                 /* Not all CRB  addr/value pair to be written,
1105                  * some of them are skipped
1106                  */
1107
1108                 /* skip if LS bit is set*/
1109                 if (off & 0x1) {
1110                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1111                             "Skip CRB init replay for offset = 0x%lx\n", off));
1112                         continue;
1113                 }
1114
1115                 /* skipping cold reboot MAGIC */
1116                 if (off == QLA82XX_CAM_RAM(0x1fc))
1117                         continue;
1118
1119                 /* do not reset PCI */
1120                 if (off == (ROMUSB_GLB + 0xbc))
1121                         continue;
1122
1123                 /* skip core clock, so that firmware can increase the clock */
1124                 if (off == (ROMUSB_GLB + 0xc8))
1125                         continue;
1126
1127                 /* skip the function enable register */
1128                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1129                         continue;
1130
1131                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1132                         continue;
1133
1134                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1135                         continue;
1136
1137                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1138                         continue;
1139
1140                 if (off == ADDR_ERROR) {
1141                         ql4_printk(KERN_WARNING, ha,
1142                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1143                             DRIVER_NAME, buf[i].addr);
1144                         continue;
1145                 }
1146
1147                 qla4_82xx_wr_32(ha, off, buf[i].data);
1148
1149                 /* ISP requires much bigger delay to settle down,
1150                  * else crb_window returns 0xffffffff
1151                  */
1152                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1153                         msleep(1000);
1154
1155                 /* ISP requires millisec delay between
1156                  * successive CRB register updation
1157                  */
1158                 msleep(1);
1159         }
1160
1161         kfree(buf);
1162
1163         /* Resetting the data and instruction cache */
1164         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1165         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1166         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1167
1168         /* Clear all protocol processing engines */
1169         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1170         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1171         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1172         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1173         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1174         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1175         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1176         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1177
1178         return 0;
1179 }
1180
1181 /**
1182  * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory
1183  * @ha: Pointer to adapter structure
1184  * @addr: Flash address to write to
1185  * @data: Data to be written
1186  * @count: word_count to be written
1187  *
1188  * Return: On success return QLA_SUCCESS
1189  *         On error return QLA_ERROR
1190  **/
1191 int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr,
1192                                 uint32_t *data, uint32_t count)
1193 {
1194         int i, j;
1195         uint32_t agt_ctrl;
1196         unsigned long flags;
1197         int ret_val = QLA_SUCCESS;
1198
1199         /* Only 128-bit aligned access */
1200         if (addr & 0xF) {
1201                 ret_val = QLA_ERROR;
1202                 goto exit_ms_mem_write;
1203         }
1204
1205         write_lock_irqsave(&ha->hw_lock, flags);
1206
1207         /* Write address */
1208         ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0);
1209         if (ret_val == QLA_ERROR) {
1210                 ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n",
1211                            __func__);
1212                 goto exit_ms_mem_write_unlock;
1213         }
1214
1215         for (i = 0; i < count; i++, addr += 16) {
1216                 if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
1217                                              QLA8XXX_ADDR_QDR_NET_MAX)) ||
1218                       (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
1219                                              QLA8XXX_ADDR_DDR_NET_MAX)))) {
1220                         ret_val = QLA_ERROR;
1221                         goto exit_ms_mem_write_unlock;
1222                 }
1223
1224                 ret_val = ha->isp_ops->wr_reg_indirect(ha,
1225                                                        MD_MIU_TEST_AGT_ADDR_LO,
1226                                                        addr);
1227                 /* Write data */
1228                 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1229                                                 MD_MIU_TEST_AGT_WRDATA_LO,
1230                                                 *data++);
1231                 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1232                                                 MD_MIU_TEST_AGT_WRDATA_HI,
1233                                                 *data++);
1234                 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1235                                                 MD_MIU_TEST_AGT_WRDATA_ULO,
1236                                                 *data++);
1237                 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1238                                                 MD_MIU_TEST_AGT_WRDATA_UHI,
1239                                                 *data++);
1240                 if (ret_val == QLA_ERROR) {
1241                         ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n",
1242                                    __func__);
1243                         goto exit_ms_mem_write_unlock;
1244                 }
1245
1246                 /* Check write status */
1247                 ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
1248                                                        MIU_TA_CTL_WRITE_ENABLE);
1249                 ret_val |= ha->isp_ops->wr_reg_indirect(ha,
1250                                                         MD_MIU_TEST_AGT_CTRL,
1251                                                         MIU_TA_CTL_WRITE_START);
1252                 if (ret_val == QLA_ERROR) {
1253                         ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n",
1254                                    __func__);
1255                         goto exit_ms_mem_write_unlock;
1256                 }
1257
1258                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1259                         ret_val = ha->isp_ops->rd_reg_indirect(ha,
1260                                                         MD_MIU_TEST_AGT_CTRL,
1261                                                         &agt_ctrl);
1262                         if (ret_val == QLA_ERROR) {
1263                                 ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n",
1264                                            __func__);
1265                                 goto exit_ms_mem_write_unlock;
1266                         }
1267                         if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
1268                                 break;
1269                 }
1270
1271                 /* Status check failed */
1272                 if (j >= MAX_CTL_CHECK) {
1273                         printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n",
1274                                            __func__);
1275                         ret_val = QLA_ERROR;
1276                         goto exit_ms_mem_write_unlock;
1277                 }
1278         }
1279
1280 exit_ms_mem_write_unlock:
1281         write_unlock_irqrestore(&ha->hw_lock, flags);
1282
1283 exit_ms_mem_write:
1284         return ret_val;
1285 }
1286
1287 static int
1288 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1289 {
1290         int  i, rval = 0;
1291         long size = 0;
1292         long flashaddr, memaddr;
1293         u64 data;
1294         u32 high, low;
1295
1296         flashaddr = memaddr = ha->hw.flt_region_bootload;
1297         size = (image_start - flashaddr) / 8;
1298
1299         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1300             ha->host_no, __func__, flashaddr, image_start));
1301
1302         for (i = 0; i < size; i++) {
1303                 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1304                     (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1305                     (int *)&high))) {
1306                         rval = -1;
1307                         goto exit_load_from_flash;
1308                 }
1309                 data = ((u64)high << 32) | low ;
1310                 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1311                 if (rval)
1312                         goto exit_load_from_flash;
1313
1314                 flashaddr += 8;
1315                 memaddr   += 8;
1316
1317                 if (i % 0x1000 == 0)
1318                         msleep(1);
1319
1320         }
1321
1322         udelay(100);
1323
1324         read_lock(&ha->hw_lock);
1325         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1326         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1327         read_unlock(&ha->hw_lock);
1328
1329 exit_load_from_flash:
1330         return rval;
1331 }
1332
1333 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1334 {
1335         u32 rst;
1336
1337         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1338         if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1339                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1340                     __func__);
1341                 return QLA_ERROR;
1342         }
1343
1344         udelay(500);
1345
1346         /* at this point, QM is in reset. This could be a problem if there are
1347          * incoming d* transition queue messages. QM/PCIE could wedge.
1348          * To get around this, QM is brought out of reset.
1349          */
1350
1351         rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1352         /* unreset qm */
1353         rst &= ~(1 << 28);
1354         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1355
1356         if (qla4_82xx_load_from_flash(ha, image_start)) {
1357                 printk("%s: Error trying to load fw from flash!\n", __func__);
1358                 return QLA_ERROR;
1359         }
1360
1361         return QLA_SUCCESS;
1362 }
1363
1364 int
1365 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1366                 u64 off, void *data, int size)
1367 {
1368         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1369         int shift_amount;
1370         uint32_t temp;
1371         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1372
1373         /*
1374          * If not MN, go check for MS or invalid.
1375          */
1376
1377         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1378                 mem_crb = QLA82XX_CRB_QDR_NET;
1379         else {
1380                 mem_crb = QLA82XX_CRB_DDR_NET;
1381                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1382                         return qla4_82xx_pci_mem_read_direct(ha,
1383                                         off, data, size);
1384         }
1385
1386
1387         off8 = off & 0xfffffff0;
1388         off0[0] = off & 0xf;
1389         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1390         shift_amount = 4;
1391
1392         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1393         off0[1] = 0;
1394         sz[1] = size - sz[0];
1395
1396         for (i = 0; i < loop; i++) {
1397                 temp = off8 + (i << shift_amount);
1398                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1399                 temp = 0;
1400                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1401                 temp = MIU_TA_CTL_ENABLE;
1402                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1403                 temp = MIU_TA_CTL_START_ENABLE;
1404                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1405
1406                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1407                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1408                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1409                                 break;
1410                 }
1411
1412                 if (j >= MAX_CTL_CHECK) {
1413                         printk_ratelimited(KERN_ERR
1414                                            "%s: failed to read through agent\n",
1415                                            __func__);
1416                         break;
1417                 }
1418
1419                 start = off0[i] >> 2;
1420                 end   = (off0[i] + sz[i] - 1) >> 2;
1421                 for (k = start; k <= end; k++) {
1422                         temp = qla4_82xx_rd_32(ha,
1423                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1424                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1425                 }
1426         }
1427
1428         if (j >= MAX_CTL_CHECK)
1429                 return -1;
1430
1431         if ((off0[0] & 7) == 0) {
1432                 val = word[0];
1433         } else {
1434                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1435                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1436         }
1437
1438         switch (size) {
1439         case 1:
1440                 *(uint8_t  *)data = val;
1441                 break;
1442         case 2:
1443                 *(uint16_t *)data = val;
1444                 break;
1445         case 4:
1446                 *(uint32_t *)data = val;
1447                 break;
1448         case 8:
1449                 *(uint64_t *)data = val;
1450                 break;
1451         }
1452         return 0;
1453 }
1454
1455 int
1456 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1457                 u64 off, void *data, int size)
1458 {
1459         int i, j, ret = 0, loop, sz[2], off0;
1460         int scale, shift_amount, startword;
1461         uint32_t temp;
1462         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1463
1464         /*
1465          * If not MN, go check for MS or invalid.
1466          */
1467         if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1468                 mem_crb = QLA82XX_CRB_QDR_NET;
1469         else {
1470                 mem_crb = QLA82XX_CRB_DDR_NET;
1471                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1472                         return qla4_82xx_pci_mem_write_direct(ha,
1473                                         off, data, size);
1474         }
1475
1476         off0 = off & 0x7;
1477         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1478         sz[1] = size - sz[0];
1479
1480         off8 = off & 0xfffffff0;
1481         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1482         shift_amount = 4;
1483         scale = 2;
1484         startword = (off & 0xf)/8;
1485
1486         for (i = 0; i < loop; i++) {
1487                 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1488                     (i << shift_amount), &word[i * scale], 8))
1489                         return -1;
1490         }
1491
1492         switch (size) {
1493         case 1:
1494                 tmpw = *((uint8_t *)data);
1495                 break;
1496         case 2:
1497                 tmpw = *((uint16_t *)data);
1498                 break;
1499         case 4:
1500                 tmpw = *((uint32_t *)data);
1501                 break;
1502         case 8:
1503         default:
1504                 tmpw = *((uint64_t *)data);
1505                 break;
1506         }
1507
1508         if (sz[0] == 8)
1509                 word[startword] = tmpw;
1510         else {
1511                 word[startword] &=
1512                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1513                 word[startword] |= tmpw << (off0 * 8);
1514         }
1515
1516         if (sz[1] != 0) {
1517                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1518                 word[startword+1] |= tmpw >> (sz[0] * 8);
1519         }
1520
1521         for (i = 0; i < loop; i++) {
1522                 temp = off8 + (i << shift_amount);
1523                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1524                 temp = 0;
1525                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1526                 temp = word[i * scale] & 0xffffffff;
1527                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1528                 temp = (word[i * scale] >> 32) & 0xffffffff;
1529                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1530                 temp = word[i*scale + 1] & 0xffffffff;
1531                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1532                     temp);
1533                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1534                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1535                     temp);
1536
1537                 temp = MIU_TA_CTL_WRITE_ENABLE;
1538                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1539                 temp = MIU_TA_CTL_WRITE_START;
1540                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1541
1542                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1543                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1544                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1545                                 break;
1546                 }
1547
1548                 if (j >= MAX_CTL_CHECK) {
1549                         if (printk_ratelimit())
1550                                 ql4_printk(KERN_ERR, ha,
1551                                            "%s: failed to read through agent\n",
1552                                            __func__);
1553                         ret = -1;
1554                         break;
1555                 }
1556         }
1557
1558         return ret;
1559 }
1560
1561 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1562 {
1563         u32 val = 0;
1564         int retries = 60;
1565
1566         if (!pegtune_val) {
1567                 do {
1568                         val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1569                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1570                             (val == PHAN_INITIALIZE_ACK))
1571                                 return 0;
1572                         set_current_state(TASK_UNINTERRUPTIBLE);
1573                         schedule_timeout(500);
1574
1575                 } while (--retries);
1576
1577                 if (!retries) {
1578                         pegtune_val = qla4_82xx_rd_32(ha,
1579                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1580                         printk(KERN_WARNING "%s: init failed, "
1581                                 "pegtune_val = %x\n", __func__, pegtune_val);
1582                         return -1;
1583                 }
1584         }
1585         return 0;
1586 }
1587
1588 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1589 {
1590         uint32_t state = 0;
1591         int loops = 0;
1592
1593         /* Window 1 call */
1594         read_lock(&ha->hw_lock);
1595         state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1596         read_unlock(&ha->hw_lock);
1597
1598         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1599                 udelay(100);
1600                 /* Window 1 call */
1601                 read_lock(&ha->hw_lock);
1602                 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1603                 read_unlock(&ha->hw_lock);
1604
1605                 loops++;
1606         }
1607
1608         if (loops >= 30000) {
1609                 DEBUG2(ql4_printk(KERN_INFO, ha,
1610                     "Receive Peg initialization not complete: 0x%x.\n", state));
1611                 return QLA_ERROR;
1612         }
1613
1614         return QLA_SUCCESS;
1615 }
1616
1617 void
1618 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1619 {
1620         uint32_t drv_active;
1621
1622         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1623
1624         /*
1625          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1626          * shift 1 by func_num to set a bit for the function.
1627          * For ISP8022, drv_active has 4 bits per function
1628          */
1629         if (is_qla8032(ha) || is_qla8042(ha))
1630                 drv_active |= (1 << ha->func_num);
1631         else
1632                 drv_active |= (1 << (ha->func_num * 4));
1633
1634         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1635                    __func__, ha->host_no, drv_active);
1636         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1637 }
1638
1639 void
1640 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1641 {
1642         uint32_t drv_active;
1643
1644         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1645
1646         /*
1647          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1648          * shift 1 by func_num to set a bit for the function.
1649          * For ISP8022, drv_active has 4 bits per function
1650          */
1651         if (is_qla8032(ha) || is_qla8042(ha))
1652                 drv_active &= ~(1 << (ha->func_num));
1653         else
1654                 drv_active &= ~(1 << (ha->func_num * 4));
1655
1656         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1657                    __func__, ha->host_no, drv_active);
1658         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active);
1659 }
1660
1661 inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1662 {
1663         uint32_t drv_state, drv_active;
1664         int rval;
1665
1666         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
1667         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1668
1669         /*
1670          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1671          * shift 1 by func_num to set a bit for the function.
1672          * For ISP8022, drv_active has 4 bits per function
1673          */
1674         if (is_qla8032(ha) || is_qla8042(ha))
1675                 rval = drv_state & (1 << ha->func_num);
1676         else
1677                 rval = drv_state & (1 << (ha->func_num * 4));
1678
1679         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1680                 rval = 1;
1681
1682         return rval;
1683 }
1684
1685 void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1686 {
1687         uint32_t drv_state;
1688
1689         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1690
1691         /*
1692          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1693          * shift 1 by func_num to set a bit for the function.
1694          * For ISP8022, drv_active has 4 bits per function
1695          */
1696         if (is_qla8032(ha) || is_qla8042(ha))
1697                 drv_state |= (1 << ha->func_num);
1698         else
1699                 drv_state |= (1 << (ha->func_num * 4));
1700
1701         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1702                    __func__, ha->host_no, drv_state);
1703         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1704 }
1705
1706 void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1707 {
1708         uint32_t drv_state;
1709
1710         drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1711
1712         /*
1713          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1714          * shift 1 by func_num to set a bit for the function.
1715          * For ISP8022, drv_active has 4 bits per function
1716          */
1717         if (is_qla8032(ha) || is_qla8042(ha))
1718                 drv_state &= ~(1 << ha->func_num);
1719         else
1720                 drv_state &= ~(1 << (ha->func_num * 4));
1721
1722         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1723                    __func__, ha->host_no, drv_state);
1724         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state);
1725 }
1726
1727 static inline void
1728 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1729 {
1730         uint32_t qsnt_state;
1731
1732         qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE);
1733
1734         /*
1735          * For ISP8324 and ISP8042, drv_active register has 1 bit per function,
1736          * shift 1 by func_num to set a bit for the function.
1737          * For ISP8022, drv_active has 4 bits per function.
1738          */
1739         if (is_qla8032(ha) || is_qla8042(ha))
1740                 qsnt_state |= (1 << ha->func_num);
1741         else
1742                 qsnt_state |= (2 << (ha->func_num * 4));
1743
1744         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state);
1745 }
1746
1747
1748 static int
1749 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1750 {
1751         uint16_t lnk;
1752
1753         /* scrub dma mask expansion register */
1754         qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1755
1756         /* Overwrite stale initialization register values */
1757         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1758         qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1759         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1760         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1761
1762         if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1763                 printk("%s: Error trying to start fw!\n", __func__);
1764                 return QLA_ERROR;
1765         }
1766
1767         /* Handshake with the card before we register the devices. */
1768         if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1769                 printk("%s: Error during card handshake!\n", __func__);
1770                 return QLA_ERROR;
1771         }
1772
1773         /* Negotiated Link width */
1774         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1775         ha->link_width = (lnk >> 4) & 0x3f;
1776
1777         /* Synchronize with Receive peg */
1778         return qla4_82xx_rcvpeg_ready(ha);
1779 }
1780
1781 int qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1782 {
1783         int rval = QLA_ERROR;
1784
1785         /*
1786          * FW Load priority:
1787          * 1) Operational firmware residing in flash.
1788          * 2) Fail
1789          */
1790
1791         ql4_printk(KERN_INFO, ha,
1792             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1793         rval = qla4_8xxx_get_flash_info(ha);
1794         if (rval != QLA_SUCCESS)
1795                 return rval;
1796
1797         ql4_printk(KERN_INFO, ha,
1798             "FW: Attempting to load firmware from flash...\n");
1799         rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1800
1801         if (rval != QLA_SUCCESS) {
1802                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1803                     " FAILED...\n");
1804                 return rval;
1805         }
1806
1807         return rval;
1808 }
1809
1810 void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1811 {
1812         if (qla4_82xx_rom_lock(ha)) {
1813                 /* Someone else is holding the lock. */
1814                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1815         }
1816
1817         /*
1818          * Either we got the lock, or someone
1819          * else died while holding it.
1820          * In either case, unlock.
1821          */
1822         qla4_82xx_rom_unlock(ha);
1823 }
1824
1825 static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha,
1826                                              uint32_t addr1, uint32_t mask)
1827 {
1828         unsigned long timeout;
1829         uint32_t rval = QLA_SUCCESS;
1830         uint32_t temp;
1831
1832         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1833         do {
1834                 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
1835                 if ((temp & mask) != 0)
1836                         break;
1837
1838                 if (time_after_eq(jiffies, timeout)) {
1839                         ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n");
1840                         return QLA_ERROR;
1841                 }
1842         } while (1);
1843
1844         return rval;
1845 }
1846
1847 static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1,
1848                                 uint32_t addr3, uint32_t mask, uint32_t addr,
1849                                 uint32_t *data_ptr)
1850 {
1851         int rval = QLA_SUCCESS;
1852         uint32_t temp;
1853         uint32_t data;
1854
1855         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1856         if (rval)
1857                 goto exit_ipmdio_rd_reg;
1858
1859         temp = (0x40000000 | addr);
1860         ha->isp_ops->wr_reg_indirect(ha, addr1, temp);
1861
1862         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1863         if (rval)
1864                 goto exit_ipmdio_rd_reg;
1865
1866         ha->isp_ops->rd_reg_indirect(ha, addr3, &data);
1867         *data_ptr = data;
1868
1869 exit_ipmdio_rd_reg:
1870         return rval;
1871 }
1872
1873
1874 static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha,
1875                                                     uint32_t addr1,
1876                                                     uint32_t addr2,
1877                                                     uint32_t addr3,
1878                                                     uint32_t mask)
1879 {
1880         unsigned long timeout;
1881         uint32_t temp;
1882         uint32_t rval = QLA_SUCCESS;
1883
1884         timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
1885         do {
1886                 ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp);
1887                 if ((temp & 0x1) != 1)
1888                         break;
1889                 if (time_after_eq(jiffies, timeout)) {
1890                         ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n");
1891                         return QLA_ERROR;
1892                 }
1893         } while (1);
1894
1895         return rval;
1896 }
1897
1898 static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha,
1899                                   uint32_t addr1, uint32_t addr3,
1900                                   uint32_t mask, uint32_t addr,
1901                                   uint32_t value)
1902 {
1903         int rval = QLA_SUCCESS;
1904
1905         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1906         if (rval)
1907                 goto exit_ipmdio_wr_reg;
1908
1909         ha->isp_ops->wr_reg_indirect(ha, addr3, value);
1910         ha->isp_ops->wr_reg_indirect(ha, addr1, addr);
1911
1912         rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask);
1913         if (rval)
1914                 goto exit_ipmdio_wr_reg;
1915
1916 exit_ipmdio_wr_reg:
1917         return rval;
1918 }
1919
1920 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1921                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
1922                                 uint32_t **d_ptr)
1923 {
1924         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1925         struct qla8xxx_minidump_entry_crb *crb_hdr;
1926         uint32_t *data_ptr = *d_ptr;
1927
1928         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1929         crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
1930         r_addr = crb_hdr->addr;
1931         r_stride = crb_hdr->crb_strd.addr_stride;
1932         loop_cnt = crb_hdr->op_count;
1933
1934         for (i = 0; i < loop_cnt; i++) {
1935                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
1936                 *data_ptr++ = cpu_to_le32(r_addr);
1937                 *data_ptr++ = cpu_to_le32(r_value);
1938                 r_addr += r_stride;
1939         }
1940         *d_ptr = data_ptr;
1941 }
1942
1943 static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha)
1944 {
1945         int rval = QLA_SUCCESS;
1946         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1947         uint64_t dma_base_addr = 0;
1948         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1949
1950         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1951                                                         ha->fw_dump_tmplt_hdr;
1952         dma_eng_num =
1953                 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1954         dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1955                                 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1956
1957         /* Read the pex-dma's command-status-and-control register. */
1958         rval = ha->isp_ops->rd_reg_indirect(ha,
1959                         (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
1960                         &cmd_sts_and_cntrl);
1961
1962         if (rval)
1963                 return QLA_ERROR;
1964
1965         /* Check if requested pex-dma engine is available. */
1966         if (cmd_sts_and_cntrl & BIT_31)
1967                 return QLA_SUCCESS;
1968         else
1969                 return QLA_ERROR;
1970 }
1971
1972 static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha,
1973                            struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr)
1974 {
1975         int rval = QLA_SUCCESS, wait = 0;
1976         uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
1977         uint64_t dma_base_addr = 0;
1978         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL;
1979
1980         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1981                                                         ha->fw_dump_tmplt_hdr;
1982         dma_eng_num =
1983                 tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX];
1984         dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
1985                                 (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET);
1986
1987         rval = ha->isp_ops->wr_reg_indirect(ha,
1988                                 dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
1989                                 m_hdr->desc_card_addr);
1990         if (rval)
1991                 goto error_exit;
1992
1993         rval = ha->isp_ops->wr_reg_indirect(ha,
1994                               dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
1995         if (rval)
1996                 goto error_exit;
1997
1998         rval = ha->isp_ops->wr_reg_indirect(ha,
1999                               dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
2000                               m_hdr->start_dma_cmd);
2001         if (rval)
2002                 goto error_exit;
2003
2004         /* Wait for dma operation to complete. */
2005         for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) {
2006                 rval = ha->isp_ops->rd_reg_indirect(ha,
2007                             (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
2008                             &cmd_sts_and_cntrl);
2009                 if (rval)
2010                         goto error_exit;
2011
2012                 if ((cmd_sts_and_cntrl & BIT_1) == 0)
2013                         break;
2014                 else
2015                         udelay(10);
2016         }
2017
2018         /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
2019         if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) {
2020                 rval = QLA_ERROR;
2021                 goto error_exit;
2022         }
2023
2024 error_exit:
2025         return rval;
2026 }
2027
2028 static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha,
2029                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2030                                 uint32_t **d_ptr)
2031 {
2032         int rval = QLA_SUCCESS;
2033         struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
2034         uint32_t size, read_size;
2035         uint8_t *data_ptr = (uint8_t *)*d_ptr;
2036         void *rdmem_buffer = NULL;
2037         dma_addr_t rdmem_dma;
2038         struct qla4_83xx_pex_dma_descriptor dma_desc;
2039
2040         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2041
2042         rval = qla4_83xx_check_dma_engine_state(ha);
2043         if (rval != QLA_SUCCESS) {
2044                 DEBUG2(ql4_printk(KERN_INFO, ha,
2045                                   "%s: DMA engine not available. Fallback to rdmem-read.\n",
2046                                   __func__));
2047                 return QLA_ERROR;
2048         }
2049
2050         m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr;
2051         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
2052                                           QLA83XX_PEX_DMA_READ_SIZE,
2053                                           &rdmem_dma, GFP_KERNEL);
2054         if (!rdmem_buffer) {
2055                 DEBUG2(ql4_printk(KERN_INFO, ha,
2056                                   "%s: Unable to allocate rdmem dma buffer\n",
2057                                   __func__));
2058                 return QLA_ERROR;
2059         }
2060
2061         /* Prepare pex-dma descriptor to be written to MS memory. */
2062         /* dma-desc-cmd layout:
2063          *              0-3: dma-desc-cmd 0-3
2064          *              4-7: pcid function number
2065          *              8-15: dma-desc-cmd 8-15
2066          */
2067         dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
2068         dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
2069         dma_desc.dma_bus_addr = rdmem_dma;
2070
2071         size = 0;
2072         read_size = 0;
2073         /*
2074          * Perform rdmem operation using pex-dma.
2075          * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE.
2076          */
2077         while (read_size < m_hdr->read_data_size) {
2078                 if (m_hdr->read_data_size - read_size >=
2079                     QLA83XX_PEX_DMA_READ_SIZE)
2080                         size = QLA83XX_PEX_DMA_READ_SIZE;
2081                 else {
2082                         size = (m_hdr->read_data_size - read_size);
2083
2084                         if (rdmem_buffer)
2085                                 dma_free_coherent(&ha->pdev->dev,
2086                                                   QLA83XX_PEX_DMA_READ_SIZE,
2087                                                   rdmem_buffer, rdmem_dma);
2088
2089                         rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size,
2090                                                           &rdmem_dma,
2091                                                           GFP_KERNEL);
2092                         if (!rdmem_buffer) {
2093                                 DEBUG2(ql4_printk(KERN_INFO, ha,
2094                                                   "%s: Unable to allocate rdmem dma buffer\n",
2095                                                   __func__));
2096                                 return QLA_ERROR;
2097                         }
2098                         dma_desc.dma_bus_addr = rdmem_dma;
2099                 }
2100
2101                 dma_desc.src_addr = m_hdr->read_addr + read_size;
2102                 dma_desc.cmd.read_data_size = size;
2103
2104                 /* Prepare: Write pex-dma descriptor to MS memory. */
2105                 rval = qla4_8xxx_ms_mem_write_128b(ha,
2106                               (uint64_t)m_hdr->desc_card_addr,
2107                               (uint32_t *)&dma_desc,
2108                               (sizeof(struct qla4_83xx_pex_dma_descriptor)/16));
2109                 if (rval != QLA_SUCCESS) {
2110                         ql4_printk(KERN_INFO, ha,
2111                                    "%s: Error writing rdmem-dma-init to MS !!!\n",
2112                                    __func__);
2113                         goto error_exit;
2114                 }
2115
2116                 DEBUG2(ql4_printk(KERN_INFO, ha,
2117                                   "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n",
2118                                   __func__, size));
2119                 /* Execute: Start pex-dma operation. */
2120                 rval = qla4_83xx_start_pex_dma(ha, m_hdr);
2121                 if (rval != QLA_SUCCESS) {
2122                         DEBUG2(ql4_printk(KERN_INFO, ha,
2123                                           "scsi(%ld): start-pex-dma failed rval=0x%x\n",
2124                                           ha->host_no, rval));
2125                         goto error_exit;
2126                 }
2127
2128                 memcpy(data_ptr, rdmem_buffer, size);
2129                 data_ptr += size;
2130                 read_size += size;
2131         }
2132
2133         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2134
2135         *d_ptr = (uint32_t *)data_ptr;
2136
2137 error_exit:
2138         if (rdmem_buffer)
2139                 dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer,
2140                                   rdmem_dma);
2141
2142         return rval;
2143 }
2144
2145 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
2146                                  struct qla8xxx_minidump_entry_hdr *entry_hdr,
2147                                  uint32_t **d_ptr)
2148 {
2149         uint32_t addr, r_addr, c_addr, t_r_addr;
2150         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2151         unsigned long p_wait, w_time, p_mask;
2152         uint32_t c_value_w, c_value_r;
2153         struct qla8xxx_minidump_entry_cache *cache_hdr;
2154         int rval = QLA_ERROR;
2155         uint32_t *data_ptr = *d_ptr;
2156
2157         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2158         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
2159
2160         loop_count = cache_hdr->op_count;
2161         r_addr = cache_hdr->read_addr;
2162         c_addr = cache_hdr->control_addr;
2163         c_value_w = cache_hdr->cache_ctrl.write_value;
2164
2165         t_r_addr = cache_hdr->tag_reg_addr;
2166         t_value = cache_hdr->addr_ctrl.init_tag_value;
2167         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2168         p_wait = cache_hdr->cache_ctrl.poll_wait;
2169         p_mask = cache_hdr->cache_ctrl.poll_mask;
2170
2171         for (i = 0; i < loop_count; i++) {
2172                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2173
2174                 if (c_value_w)
2175                         ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2176
2177                 if (p_mask) {
2178                         w_time = jiffies + p_wait;
2179                         do {
2180                                 ha->isp_ops->rd_reg_indirect(ha, c_addr,
2181                                                              &c_value_r);
2182                                 if ((c_value_r & p_mask) == 0) {
2183                                         break;
2184                                 } else if (time_after_eq(jiffies, w_time)) {
2185                                         /* capturing dump failed */
2186                                         return rval;
2187                                 }
2188                         } while (1);
2189                 }
2190
2191                 addr = r_addr;
2192                 for (k = 0; k < r_cnt; k++) {
2193                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2194                         *data_ptr++ = cpu_to_le32(r_value);
2195                         addr += cache_hdr->read_ctrl.read_addr_stride;
2196                 }
2197
2198                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2199         }
2200         *d_ptr = data_ptr;
2201         return QLA_SUCCESS;
2202 }
2203
2204 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
2205                                 struct qla8xxx_minidump_entry_hdr *entry_hdr)
2206 {
2207         struct qla8xxx_minidump_entry_crb *crb_entry;
2208         uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
2209         uint32_t crb_addr;
2210         unsigned long wtime;
2211         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2212         int i;
2213
2214         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2215         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2216                                                 ha->fw_dump_tmplt_hdr;
2217         crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr;
2218
2219         crb_addr = crb_entry->addr;
2220         for (i = 0; i < crb_entry->op_count; i++) {
2221                 opcode = crb_entry->crb_ctrl.opcode;
2222                 if (opcode & QLA8XXX_DBG_OPCODE_WR) {
2223                         ha->isp_ops->wr_reg_indirect(ha, crb_addr,
2224                                                      crb_entry->value_1);
2225                         opcode &= ~QLA8XXX_DBG_OPCODE_WR;
2226                 }
2227                 if (opcode & QLA8XXX_DBG_OPCODE_RW) {
2228                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2229                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2230                         opcode &= ~QLA8XXX_DBG_OPCODE_RW;
2231                 }
2232                 if (opcode & QLA8XXX_DBG_OPCODE_AND) {
2233                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2234                         read_value &= crb_entry->value_2;
2235                         opcode &= ~QLA8XXX_DBG_OPCODE_AND;
2236                         if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2237                                 read_value |= crb_entry->value_3;
2238                                 opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2239                         }
2240                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2241                 }
2242                 if (opcode & QLA8XXX_DBG_OPCODE_OR) {
2243                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2244                         read_value |= crb_entry->value_3;
2245                         ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value);
2246                         opcode &= ~QLA8XXX_DBG_OPCODE_OR;
2247                 }
2248                 if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
2249                         poll_time = crb_entry->crb_strd.poll_timeout;
2250                         wtime = jiffies + poll_time;
2251                         ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value);
2252
2253                         do {
2254                                 if ((read_value & crb_entry->value_2) ==
2255                                     crb_entry->value_1) {
2256                                         break;
2257                                 } else if (time_after_eq(jiffies, wtime)) {
2258                                         /* capturing dump failed */
2259                                         rval = QLA_ERROR;
2260                                         break;
2261                                 } else {
2262                                         ha->isp_ops->rd_reg_indirect(ha,
2263                                                         crb_addr, &read_value);
2264                                 }
2265                         } while (1);
2266                         opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
2267                 }
2268
2269                 if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
2270                         if (crb_entry->crb_strd.state_index_a) {
2271                                 index = crb_entry->crb_strd.state_index_a;
2272                                 addr = tmplt_hdr->saved_state_array[index];
2273                         } else {
2274                                 addr = crb_addr;
2275                         }
2276
2277                         ha->isp_ops->rd_reg_indirect(ha, addr, &read_value);
2278                         index = crb_entry->crb_ctrl.state_index_v;
2279                         tmplt_hdr->saved_state_array[index] = read_value;
2280                         opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
2281                 }
2282
2283                 if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
2284                         if (crb_entry->crb_strd.state_index_a) {
2285                                 index = crb_entry->crb_strd.state_index_a;
2286                                 addr = tmplt_hdr->saved_state_array[index];
2287                         } else {
2288                                 addr = crb_addr;
2289                         }
2290
2291                         if (crb_entry->crb_ctrl.state_index_v) {
2292                                 index = crb_entry->crb_ctrl.state_index_v;
2293                                 read_value =
2294                                         tmplt_hdr->saved_state_array[index];
2295                         } else {
2296                                 read_value = crb_entry->value_1;
2297                         }
2298
2299                         ha->isp_ops->wr_reg_indirect(ha, addr, read_value);
2300                         opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
2301                 }
2302
2303                 if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
2304                         index = crb_entry->crb_ctrl.state_index_v;
2305                         read_value = tmplt_hdr->saved_state_array[index];
2306                         read_value <<= crb_entry->crb_ctrl.shl;
2307                         read_value >>= crb_entry->crb_ctrl.shr;
2308                         if (crb_entry->value_2)
2309                                 read_value &= crb_entry->value_2;
2310                         read_value |= crb_entry->value_3;
2311                         read_value += crb_entry->value_1;
2312                         tmplt_hdr->saved_state_array[index] = read_value;
2313                         opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
2314                 }
2315                 crb_addr += crb_entry->crb_strd.addr_stride;
2316         }
2317         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
2318         return rval;
2319 }
2320
2321 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
2322                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2323                                 uint32_t **d_ptr)
2324 {
2325         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
2326         struct qla8xxx_minidump_entry_rdocm *ocm_hdr;
2327         uint32_t *data_ptr = *d_ptr;
2328
2329         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2330         ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr;
2331         r_addr = ocm_hdr->read_addr;
2332         r_stride = ocm_hdr->read_addr_stride;
2333         loop_cnt = ocm_hdr->op_count;
2334
2335         DEBUG2(ql4_printk(KERN_INFO, ha,
2336                           "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
2337                           __func__, r_addr, r_stride, loop_cnt));
2338
2339         for (i = 0; i < loop_cnt; i++) {
2340                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
2341                 *data_ptr++ = cpu_to_le32(r_value);
2342                 r_addr += r_stride;
2343         }
2344         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
2345                 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
2346         *d_ptr = data_ptr;
2347 }
2348
2349 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
2350                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2351                                 uint32_t **d_ptr)
2352 {
2353         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
2354         struct qla8xxx_minidump_entry_mux *mux_hdr;
2355         uint32_t *data_ptr = *d_ptr;
2356
2357         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2358         mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr;
2359         r_addr = mux_hdr->read_addr;
2360         s_addr = mux_hdr->select_addr;
2361         s_stride = mux_hdr->select_value_stride;
2362         s_value = mux_hdr->select_value;
2363         loop_cnt = mux_hdr->op_count;
2364
2365         for (i = 0; i < loop_cnt; i++) {
2366                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2367                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2368                 *data_ptr++ = cpu_to_le32(s_value);
2369                 *data_ptr++ = cpu_to_le32(r_value);
2370                 s_value += s_stride;
2371         }
2372         *d_ptr = data_ptr;
2373 }
2374
2375 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
2376                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2377                                 uint32_t **d_ptr)
2378 {
2379         uint32_t addr, r_addr, c_addr, t_r_addr;
2380         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
2381         uint32_t c_value_w;
2382         struct qla8xxx_minidump_entry_cache *cache_hdr;
2383         uint32_t *data_ptr = *d_ptr;
2384
2385         cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr;
2386         loop_count = cache_hdr->op_count;
2387         r_addr = cache_hdr->read_addr;
2388         c_addr = cache_hdr->control_addr;
2389         c_value_w = cache_hdr->cache_ctrl.write_value;
2390
2391         t_r_addr = cache_hdr->tag_reg_addr;
2392         t_value = cache_hdr->addr_ctrl.init_tag_value;
2393         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
2394
2395         for (i = 0; i < loop_count; i++) {
2396                 ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value);
2397                 ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w);
2398                 addr = r_addr;
2399                 for (k = 0; k < r_cnt; k++) {
2400                         ha->isp_ops->rd_reg_indirect(ha, addr, &r_value);
2401                         *data_ptr++ = cpu_to_le32(r_value);
2402                         addr += cache_hdr->read_ctrl.read_addr_stride;
2403                 }
2404                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
2405         }
2406         *d_ptr = data_ptr;
2407 }
2408
2409 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
2410                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2411                                 uint32_t **d_ptr)
2412 {
2413         uint32_t s_addr, r_addr;
2414         uint32_t r_stride, r_value, r_cnt, qid = 0;
2415         uint32_t i, k, loop_cnt;
2416         struct qla8xxx_minidump_entry_queue *q_hdr;
2417         uint32_t *data_ptr = *d_ptr;
2418
2419         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2420         q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr;
2421         s_addr = q_hdr->select_addr;
2422         r_cnt = q_hdr->rd_strd.read_addr_cnt;
2423         r_stride = q_hdr->rd_strd.read_addr_stride;
2424         loop_cnt = q_hdr->op_count;
2425
2426         for (i = 0; i < loop_cnt; i++) {
2427                 ha->isp_ops->wr_reg_indirect(ha, s_addr, qid);
2428                 r_addr = q_hdr->read_addr;
2429                 for (k = 0; k < r_cnt; k++) {
2430                         ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2431                         *data_ptr++ = cpu_to_le32(r_value);
2432                         r_addr += r_stride;
2433                 }
2434                 qid += q_hdr->q_strd.queue_id_stride;
2435         }
2436         *d_ptr = data_ptr;
2437 }
2438
2439 #define MD_DIRECT_ROM_WINDOW            0x42110030
2440 #define MD_DIRECT_ROM_READ_BASE         0x42150000
2441
2442 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2443                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2444                                 uint32_t **d_ptr)
2445 {
2446         uint32_t r_addr, r_value;
2447         uint32_t i, loop_cnt;
2448         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2449         uint32_t *data_ptr = *d_ptr;
2450
2451         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2452         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2453         r_addr = rom_hdr->read_addr;
2454         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
2455
2456         DEBUG2(ql4_printk(KERN_INFO, ha,
2457                           "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
2458                            __func__, r_addr, loop_cnt));
2459
2460         for (i = 0; i < loop_cnt; i++) {
2461                 ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW,
2462                                              (r_addr & 0xFFFF0000));
2463                 ha->isp_ops->rd_reg_indirect(ha,
2464                                 MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF),
2465                                 &r_value);
2466                 *data_ptr++ = cpu_to_le32(r_value);
2467                 r_addr += sizeof(uint32_t);
2468         }
2469         *d_ptr = data_ptr;
2470 }
2471
2472 #define MD_MIU_TEST_AGT_CTRL            0x41000090
2473 #define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
2474 #define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
2475
2476 static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2477                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2478                                 uint32_t **d_ptr)
2479 {
2480         uint32_t r_addr, r_value, r_data;
2481         uint32_t i, j, loop_cnt;
2482         struct qla8xxx_minidump_entry_rdmem *m_hdr;
2483         unsigned long flags;
2484         uint32_t *data_ptr = *d_ptr;
2485
2486         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2487         m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr;
2488         r_addr = m_hdr->read_addr;
2489         loop_cnt = m_hdr->read_data_size/16;
2490
2491         DEBUG2(ql4_printk(KERN_INFO, ha,
2492                           "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2493                           __func__, r_addr, m_hdr->read_data_size));
2494
2495         if (r_addr & 0xf) {
2496                 DEBUG2(ql4_printk(KERN_INFO, ha,
2497                                   "[%s]: Read addr 0x%x not 16 bytes aligned\n",
2498                                   __func__, r_addr));
2499                 return QLA_ERROR;
2500         }
2501
2502         if (m_hdr->read_data_size % 16) {
2503                 DEBUG2(ql4_printk(KERN_INFO, ha,
2504                                   "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2505                                   __func__, m_hdr->read_data_size));
2506                 return QLA_ERROR;
2507         }
2508
2509         DEBUG2(ql4_printk(KERN_INFO, ha,
2510                           "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2511                           __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2512
2513         write_lock_irqsave(&ha->hw_lock, flags);
2514         for (i = 0; i < loop_cnt; i++) {
2515                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO,
2516                                              r_addr);
2517                 r_value = 0;
2518                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI,
2519                                              r_value);
2520                 r_value = MIU_TA_CTL_ENABLE;
2521                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2522                 r_value = MIU_TA_CTL_START_ENABLE;
2523                 ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value);
2524
2525                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2526                         ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL,
2527                                                      &r_value);
2528                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2529                                 break;
2530                 }
2531
2532                 if (j >= MAX_CTL_CHECK) {
2533                         printk_ratelimited(KERN_ERR
2534                                            "%s: failed to read through agent\n",
2535                                             __func__);
2536                         write_unlock_irqrestore(&ha->hw_lock, flags);
2537                         return QLA_SUCCESS;
2538                 }
2539
2540                 for (j = 0; j < 4; j++) {
2541                         ha->isp_ops->rd_reg_indirect(ha,
2542                                                      MD_MIU_TEST_AGT_RDDATA[j],
2543                                                      &r_data);
2544                         *data_ptr++ = cpu_to_le32(r_data);
2545                 }
2546
2547                 r_addr += 16;
2548         }
2549         write_unlock_irqrestore(&ha->hw_lock, flags);
2550
2551         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2552                           __func__, (loop_cnt * 16)));
2553
2554         *d_ptr = data_ptr;
2555         return QLA_SUCCESS;
2556 }
2557
2558 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2559                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2560                                 uint32_t **d_ptr)
2561 {
2562         uint32_t *data_ptr = *d_ptr;
2563         int rval = QLA_SUCCESS;
2564
2565         rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr);
2566         if (rval != QLA_SUCCESS)
2567                 rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2568                                                           &data_ptr);
2569         *d_ptr = data_ptr;
2570         return rval;
2571 }
2572
2573 static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2574                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2575                                 int index)
2576 {
2577         entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
2578         DEBUG2(ql4_printk(KERN_INFO, ha,
2579                           "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2580                           ha->host_no, index, entry_hdr->entry_type,
2581                           entry_hdr->d_ctrl.entry_capture_mask));
2582         /* If driver encounters a new entry type that it cannot process,
2583          * it should just skip the entry and adjust the total buffer size by
2584          * from subtracting the skipped bytes from it
2585          */
2586         ha->fw_dump_skip_size += entry_hdr->entry_capture_size;
2587 }
2588
2589 /* ISP83xx functions to process new minidump entries... */
2590 static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha,
2591                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2592                                 uint32_t **d_ptr)
2593 {
2594         uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
2595         uint16_t s_stride, i;
2596         uint32_t *data_ptr = *d_ptr;
2597         uint32_t rval = QLA_SUCCESS;
2598         struct qla83xx_minidump_entry_pollrd *pollrd_hdr;
2599
2600         pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr;
2601         s_addr = le32_to_cpu(pollrd_hdr->select_addr);
2602         r_addr = le32_to_cpu(pollrd_hdr->read_addr);
2603         s_value = le32_to_cpu(pollrd_hdr->select_value);
2604         s_stride = le32_to_cpu(pollrd_hdr->select_value_stride);
2605
2606         poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2607         poll_mask = le32_to_cpu(pollrd_hdr->poll_mask);
2608
2609         for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) {
2610                 ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value);
2611                 poll_wait = le32_to_cpu(pollrd_hdr->poll_wait);
2612                 while (1) {
2613                         ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value);
2614
2615                         if ((r_value & poll_mask) != 0) {
2616                                 break;
2617                         } else {
2618                                 msleep(1);
2619                                 if (--poll_wait == 0) {
2620                                         ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2621                                                    __func__);
2622                                         rval = QLA_ERROR;
2623                                         goto exit_process_pollrd;
2624                                 }
2625                         }
2626                 }
2627                 ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value);
2628                 *data_ptr++ = cpu_to_le32(s_value);
2629                 *data_ptr++ = cpu_to_le32(r_value);
2630                 s_value += s_stride;
2631         }
2632
2633         *d_ptr = data_ptr;
2634
2635 exit_process_pollrd:
2636         return rval;
2637 }
2638
2639 static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha,
2640                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2641                                 uint32_t **d_ptr)
2642 {
2643         int loop_cnt;
2644         uint32_t addr1, addr2, value, data, temp, wrval;
2645         uint8_t stride, stride2;
2646         uint16_t count;
2647         uint32_t poll, mask, modify_mask;
2648         uint32_t wait_count = 0;
2649         uint32_t *data_ptr = *d_ptr;
2650         struct qla8044_minidump_entry_rddfe *rddfe;
2651         uint32_t rval = QLA_SUCCESS;
2652
2653         rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr;
2654         addr1 = le32_to_cpu(rddfe->addr_1);
2655         value = le32_to_cpu(rddfe->value);
2656         stride = le32_to_cpu(rddfe->stride);
2657         stride2 = le32_to_cpu(rddfe->stride2);
2658         count = le32_to_cpu(rddfe->count);
2659
2660         poll = le32_to_cpu(rddfe->poll);
2661         mask = le32_to_cpu(rddfe->mask);
2662         modify_mask = le32_to_cpu(rddfe->modify_mask);
2663
2664         addr2 = addr1 + stride;
2665
2666         for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
2667                 ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value));
2668
2669                 wait_count = 0;
2670                 while (wait_count < poll) {
2671                         ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2672                         if ((temp & mask) != 0)
2673                                 break;
2674                         wait_count++;
2675                 }
2676
2677                 if (wait_count == poll) {
2678                         ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2679                         rval = QLA_ERROR;
2680                         goto exit_process_rddfe;
2681                 } else {
2682                         ha->isp_ops->rd_reg_indirect(ha, addr2, &temp);
2683                         temp = temp & modify_mask;
2684                         temp = (temp | ((loop_cnt << 16) | loop_cnt));
2685                         wrval = ((temp << 16) | temp);
2686
2687                         ha->isp_ops->wr_reg_indirect(ha, addr2, wrval);
2688                         ha->isp_ops->wr_reg_indirect(ha, addr1, value);
2689
2690                         wait_count = 0;
2691                         while (wait_count < poll) {
2692                                 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2693                                 if ((temp & mask) != 0)
2694                                         break;
2695                                 wait_count++;
2696                         }
2697                         if (wait_count == poll) {
2698                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2699                                            __func__);
2700                                 rval = QLA_ERROR;
2701                                 goto exit_process_rddfe;
2702                         }
2703
2704                         ha->isp_ops->wr_reg_indirect(ha, addr1,
2705                                                      ((0x40000000 | value) +
2706                                                      stride2));
2707                         wait_count = 0;
2708                         while (wait_count < poll) {
2709                                 ha->isp_ops->rd_reg_indirect(ha, addr1, &temp);
2710                                 if ((temp & mask) != 0)
2711                                         break;
2712                                 wait_count++;
2713                         }
2714
2715                         if (wait_count == poll) {
2716                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n",
2717                                            __func__);
2718                                 rval = QLA_ERROR;
2719                                 goto exit_process_rddfe;
2720                         }
2721
2722                         ha->isp_ops->rd_reg_indirect(ha, addr2, &data);
2723
2724                         *data_ptr++ = cpu_to_le32(wrval);
2725                         *data_ptr++ = cpu_to_le32(data);
2726                 }
2727         }
2728
2729         *d_ptr = data_ptr;
2730 exit_process_rddfe:
2731         return rval;
2732 }
2733
2734 static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha,
2735                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2736                                 uint32_t **d_ptr)
2737 {
2738         int rval = QLA_SUCCESS;
2739         uint32_t addr1, addr2, value1, value2, data, selval;
2740         uint8_t stride1, stride2;
2741         uint32_t addr3, addr4, addr5, addr6, addr7;
2742         uint16_t count, loop_cnt;
2743         uint32_t mask;
2744         uint32_t *data_ptr = *d_ptr;
2745         struct qla8044_minidump_entry_rdmdio *rdmdio;
2746
2747         rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr;
2748         addr1 = le32_to_cpu(rdmdio->addr_1);
2749         addr2 = le32_to_cpu(rdmdio->addr_2);
2750         value1 = le32_to_cpu(rdmdio->value_1);
2751         stride1 = le32_to_cpu(rdmdio->stride_1);
2752         stride2 = le32_to_cpu(rdmdio->stride_2);
2753         count = le32_to_cpu(rdmdio->count);
2754
2755         mask = le32_to_cpu(rdmdio->mask);
2756         value2 = le32_to_cpu(rdmdio->value_2);
2757
2758         addr3 = addr1 + stride1;
2759
2760         for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
2761                 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2762                                                          addr3, mask);
2763                 if (rval)
2764                         goto exit_process_rdmdio;
2765
2766                 addr4 = addr2 - stride1;
2767                 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4,
2768                                              value2);
2769                 if (rval)
2770                         goto exit_process_rdmdio;
2771
2772                 addr5 = addr2 - (2 * stride1);
2773                 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5,
2774                                              value1);
2775                 if (rval)
2776                         goto exit_process_rdmdio;
2777
2778                 addr6 = addr2 - (3 * stride1);
2779                 rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask,
2780                                              addr6, 0x2);
2781                 if (rval)
2782                         goto exit_process_rdmdio;
2783
2784                 rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2,
2785                                                          addr3, mask);
2786                 if (rval)
2787                         goto exit_process_rdmdio;
2788
2789                 addr7 = addr2 - (4 * stride1);
2790                 rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3,
2791                                                       mask, addr7, &data);
2792                 if (rval)
2793                         goto exit_process_rdmdio;
2794
2795                 selval = (value2 << 18) | (value1 << 2) | 2;
2796
2797                 stride2 = le32_to_cpu(rdmdio->stride_2);
2798                 *data_ptr++ = cpu_to_le32(selval);
2799                 *data_ptr++ = cpu_to_le32(data);
2800
2801                 value1 = value1 + stride2;
2802                 *d_ptr = data_ptr;
2803         }
2804
2805 exit_process_rdmdio:
2806         return rval;
2807 }
2808
2809 static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha,
2810                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2811                                 uint32_t **d_ptr)
2812 {
2813         uint32_t addr1, addr2, value1, value2, poll, r_value;
2814         struct qla8044_minidump_entry_pollwr *pollwr_hdr;
2815         uint32_t wait_count = 0;
2816         uint32_t rval = QLA_SUCCESS;
2817
2818         pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
2819         addr1 = le32_to_cpu(pollwr_hdr->addr_1);
2820         addr2 = le32_to_cpu(pollwr_hdr->addr_2);
2821         value1 = le32_to_cpu(pollwr_hdr->value_1);
2822         value2 = le32_to_cpu(pollwr_hdr->value_2);
2823
2824         poll = le32_to_cpu(pollwr_hdr->poll);
2825
2826         while (wait_count < poll) {
2827                 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2828
2829                 if ((r_value & poll) != 0)
2830                         break;
2831
2832                 wait_count++;
2833         }
2834
2835         if (wait_count == poll) {
2836                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__);
2837                 rval = QLA_ERROR;
2838                 goto exit_process_pollwr;
2839         }
2840
2841         ha->isp_ops->wr_reg_indirect(ha, addr2, value2);
2842         ha->isp_ops->wr_reg_indirect(ha, addr1, value1);
2843
2844         wait_count = 0;
2845         while (wait_count < poll) {
2846                 ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value);
2847
2848                 if ((r_value & poll) != 0)
2849                         break;
2850                 wait_count++;
2851         }
2852
2853 exit_process_pollwr:
2854         return rval;
2855 }
2856
2857 static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha,
2858                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2859                                 uint32_t **d_ptr)
2860 {
2861         uint32_t sel_val1, sel_val2, t_sel_val, data, i;
2862         uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
2863         struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr;
2864         uint32_t *data_ptr = *d_ptr;
2865
2866         rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr;
2867         sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1);
2868         sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2);
2869         sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1);
2870         sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2);
2871         sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask);
2872         read_addr = le32_to_cpu(rdmux2_hdr->read_addr);
2873
2874         for (i = 0; i < rdmux2_hdr->op_count; i++) {
2875                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1);
2876                 t_sel_val = sel_val1 & sel_val_mask;
2877                 *data_ptr++ = cpu_to_le32(t_sel_val);
2878
2879                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2880                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2881
2882                 *data_ptr++ = cpu_to_le32(data);
2883
2884                 ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2);
2885                 t_sel_val = sel_val2 & sel_val_mask;
2886                 *data_ptr++ = cpu_to_le32(t_sel_val);
2887
2888                 ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val);
2889                 ha->isp_ops->rd_reg_indirect(ha, read_addr, &data);
2890
2891                 *data_ptr++ = cpu_to_le32(data);
2892
2893                 sel_val1 += rdmux2_hdr->select_value_stride;
2894                 sel_val2 += rdmux2_hdr->select_value_stride;
2895         }
2896
2897         *d_ptr = data_ptr;
2898 }
2899
2900 static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha,
2901                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2902                                 uint32_t **d_ptr)
2903 {
2904         uint32_t poll_wait, poll_mask, r_value, data;
2905         uint32_t addr_1, addr_2, value_1, value_2;
2906         uint32_t *data_ptr = *d_ptr;
2907         uint32_t rval = QLA_SUCCESS;
2908         struct qla83xx_minidump_entry_pollrdmwr *poll_hdr;
2909
2910         poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr;
2911         addr_1 = le32_to_cpu(poll_hdr->addr_1);
2912         addr_2 = le32_to_cpu(poll_hdr->addr_2);
2913         value_1 = le32_to_cpu(poll_hdr->value_1);
2914         value_2 = le32_to_cpu(poll_hdr->value_2);
2915         poll_mask = le32_to_cpu(poll_hdr->poll_mask);
2916
2917         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1);
2918
2919         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2920         while (1) {
2921                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2922
2923                 if ((r_value & poll_mask) != 0) {
2924                         break;
2925                 } else {
2926                         msleep(1);
2927                         if (--poll_wait == 0) {
2928                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n",
2929                                            __func__);
2930                                 rval = QLA_ERROR;
2931                                 goto exit_process_pollrdmwr;
2932                         }
2933                 }
2934         }
2935
2936         ha->isp_ops->rd_reg_indirect(ha, addr_2, &data);
2937         data &= le32_to_cpu(poll_hdr->modify_mask);
2938         ha->isp_ops->wr_reg_indirect(ha, addr_2, data);
2939         ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2);
2940
2941         poll_wait = le32_to_cpu(poll_hdr->poll_wait);
2942         while (1) {
2943                 ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value);
2944
2945                 if ((r_value & poll_mask) != 0) {
2946                         break;
2947                 } else {
2948                         msleep(1);
2949                         if (--poll_wait == 0) {
2950                                 ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n",
2951                                            __func__);
2952                                 rval = QLA_ERROR;
2953                                 goto exit_process_pollrdmwr;
2954                         }
2955                 }
2956         }
2957
2958         *data_ptr++ = cpu_to_le32(addr_2);
2959         *data_ptr++ = cpu_to_le32(data);
2960         *d_ptr = data_ptr;
2961
2962 exit_process_pollrdmwr:
2963         return rval;
2964 }
2965
2966 static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha,
2967                                 struct qla8xxx_minidump_entry_hdr *entry_hdr,
2968                                 uint32_t **d_ptr)
2969 {
2970         uint32_t fl_addr, u32_count, rval;
2971         struct qla8xxx_minidump_entry_rdrom *rom_hdr;
2972         uint32_t *data_ptr = *d_ptr;
2973
2974         rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr;
2975         fl_addr = le32_to_cpu(rom_hdr->read_addr);
2976         u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t);
2977
2978         DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
2979                           __func__, fl_addr, u32_count));
2980
2981         rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr,
2982                                                  (u8 *)(data_ptr), u32_count);
2983
2984         if (rval == QLA_ERROR) {
2985                 ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n",
2986                            __func__, u32_count);
2987                 goto exit_process_rdrom;
2988         }
2989
2990         data_ptr += u32_count;
2991         *d_ptr = data_ptr;
2992
2993 exit_process_rdrom:
2994         return rval;
2995 }
2996
2997 /**
2998  * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2999  * @ha: pointer to adapter structure
3000  **/
3001 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
3002 {
3003         int num_entry_hdr = 0;
3004         struct qla8xxx_minidump_entry_hdr *entry_hdr;
3005         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
3006         uint32_t *data_ptr;
3007         uint32_t data_collected = 0;
3008         int i, rval = QLA_ERROR;
3009         uint64_t now;
3010         uint32_t timestamp;
3011
3012         ha->fw_dump_skip_size = 0;
3013         if (!ha->fw_dump) {
3014                 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
3015                            __func__, ha->host_no);
3016                 return rval;
3017         }
3018
3019         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
3020                                                 ha->fw_dump_tmplt_hdr;
3021         data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
3022                                                 ha->fw_dump_tmplt_size);
3023         data_collected += ha->fw_dump_tmplt_size;
3024
3025         num_entry_hdr = tmplt_hdr->num_of_entries;
3026         ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
3027                    __func__, data_ptr);
3028         ql4_printk(KERN_INFO, ha,
3029                    "[%s]: no of entry headers in Template: 0x%x\n",
3030                    __func__, num_entry_hdr);
3031         ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
3032                    __func__, ha->fw_dump_capture_mask);
3033         ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
3034                    __func__, ha->fw_dump_size, ha->fw_dump_size);
3035
3036         /* Update current timestamp before taking dump */
3037         now = get_jiffies_64();
3038         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
3039         tmplt_hdr->driver_timestamp = timestamp;
3040
3041         entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
3042                                         (((uint8_t *)ha->fw_dump_tmplt_hdr) +
3043                                          tmplt_hdr->first_entry_offset);
3044
3045         if (is_qla8032(ha) || is_qla8042(ha))
3046                 tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] =
3047                                         tmplt_hdr->ocm_window_reg[ha->func_num];
3048
3049         /* Walk through the entry headers - validate/perform required action */
3050         for (i = 0; i < num_entry_hdr; i++) {
3051                 if (data_collected > ha->fw_dump_size) {
3052                         ql4_printk(KERN_INFO, ha,
3053                                    "Data collected: [0x%x], Total Dump size: [0x%x]\n",
3054                                    data_collected, ha->fw_dump_size);
3055                         return rval;
3056                 }
3057
3058                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
3059                       ha->fw_dump_capture_mask)) {
3060                         entry_hdr->d_ctrl.driver_flags |=
3061                                                 QLA8XXX_DBG_SKIPPED_FLAG;
3062                         goto skip_nxt_entry;
3063                 }
3064
3065                 DEBUG2(ql4_printk(KERN_INFO, ha,
3066                                   "Data collected: [0x%x], Dump size left:[0x%x]\n",
3067                                   data_collected,
3068                                   (ha->fw_dump_size - data_collected)));
3069
3070                 /* Decode the entry type and take required action to capture
3071                  * debug data
3072                  */
3073                 switch (entry_hdr->entry_type) {
3074                 case QLA8XXX_RDEND:
3075                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3076                         break;
3077                 case QLA8XXX_CNTRL:
3078                         rval = qla4_8xxx_minidump_process_control(ha,
3079                                                                   entry_hdr);
3080                         if (rval != QLA_SUCCESS) {
3081                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3082                                 goto md_failed;
3083                         }
3084                         break;
3085                 case QLA8XXX_RDCRB:
3086                         qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
3087                                                          &data_ptr);
3088                         break;
3089                 case QLA8XXX_RDMEM:
3090                         rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
3091                                                                 &data_ptr);
3092                         if (rval != QLA_SUCCESS) {
3093                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3094                                 goto md_failed;
3095                         }
3096                         break;
3097                 case QLA8XXX_BOARD:
3098                 case QLA8XXX_RDROM:
3099                         if (is_qla8022(ha)) {
3100                                 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
3101                                                                  &data_ptr);
3102                         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3103                                 rval = qla4_83xx_minidump_process_rdrom(ha,
3104                                                                     entry_hdr,
3105                                                                     &data_ptr);
3106                                 if (rval != QLA_SUCCESS)
3107                                         qla4_8xxx_mark_entry_skipped(ha,
3108                                                                      entry_hdr,
3109                                                                      i);
3110                         }
3111                         break;
3112                 case QLA8XXX_L2DTG:
3113                 case QLA8XXX_L2ITG:
3114                 case QLA8XXX_L2DAT:
3115                 case QLA8XXX_L2INS:
3116                         rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
3117                                                                 &data_ptr);
3118                         if (rval != QLA_SUCCESS) {
3119                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3120                                 goto md_failed;
3121                         }
3122                         break;
3123                 case QLA8XXX_L1DTG:
3124                 case QLA8XXX_L1ITG:
3125                 case QLA8XXX_L1DAT:
3126                 case QLA8XXX_L1INS:
3127                         qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
3128                                                            &data_ptr);
3129                         break;
3130                 case QLA8XXX_RDOCM:
3131                         qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
3132                                                          &data_ptr);
3133                         break;
3134                 case QLA8XXX_RDMUX:
3135                         qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
3136                                                          &data_ptr);
3137                         break;
3138                 case QLA8XXX_QUEUE:
3139                         qla4_8xxx_minidump_process_queue(ha, entry_hdr,
3140                                                          &data_ptr);
3141                         break;
3142                 case QLA83XX_POLLRD:
3143                         if (is_qla8022(ha)) {
3144                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3145                                 break;
3146                         }
3147                         rval = qla83xx_minidump_process_pollrd(ha, entry_hdr,
3148                                                                &data_ptr);
3149                         if (rval != QLA_SUCCESS)
3150                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3151                         break;
3152                 case QLA83XX_RDMUX2:
3153                         if (is_qla8022(ha)) {
3154                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3155                                 break;
3156                         }
3157                         qla83xx_minidump_process_rdmux2(ha, entry_hdr,
3158                                                         &data_ptr);
3159                         break;
3160                 case QLA83XX_POLLRDMWR:
3161                         if (is_qla8022(ha)) {
3162                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3163                                 break;
3164                         }
3165                         rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr,
3166                                                                   &data_ptr);
3167                         if (rval != QLA_SUCCESS)
3168                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3169                         break;
3170                 case QLA8044_RDDFE:
3171                         rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr,
3172                                                                 &data_ptr);
3173                         if (rval != QLA_SUCCESS)
3174                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3175                         break;
3176                 case QLA8044_RDMDIO:
3177                         rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr,
3178                                                                  &data_ptr);
3179                         if (rval != QLA_SUCCESS)
3180                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3181                         break;
3182                 case QLA8044_POLLWR:
3183                         rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr,
3184                                                                  &data_ptr);
3185                         if (rval != QLA_SUCCESS)
3186                                 qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3187                         break;
3188                 case QLA8XXX_RDNOP:
3189                 default:
3190                         qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
3191                         break;
3192                 }
3193
3194                 data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump;
3195 skip_nxt_entry:
3196                 /*  next entry in the template */
3197                 entry_hdr = (struct qla8xxx_minidump_entry_hdr *)
3198                                 (((uint8_t *)entry_hdr) +
3199                                  entry_hdr->entry_size);
3200         }
3201
3202         if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) {
3203                 ql4_printk(KERN_INFO, ha,
3204                            "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
3205                            data_collected, ha->fw_dump_size);
3206                 rval = QLA_ERROR;
3207                 goto md_failed;
3208         }
3209
3210         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
3211                           __func__, i));
3212 md_failed:
3213         return rval;
3214 }
3215
3216 /**
3217  * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
3218  * @ha: pointer to adapter structure
3219  * @code: uevent code to act upon
3220  **/
3221 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
3222 {
3223         char event_string[40];
3224         char *envp[] = { event_string, NULL };
3225
3226         switch (code) {
3227         case QL4_UEVENT_CODE_FW_DUMP:
3228                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
3229                          ha->host_no);
3230                 break;
3231         default:
3232                 /*do nothing*/
3233                 break;
3234         }
3235
3236         kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
3237 }
3238
3239 void qla4_8xxx_get_minidump(struct scsi_qla_host *ha)
3240 {
3241         if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
3242             !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
3243                 if (!qla4_8xxx_collect_md_data(ha)) {
3244                         qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
3245                         set_bit(AF_82XX_FW_DUMPED, &ha->flags);
3246                 } else {
3247                         ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n",
3248                                    __func__);
3249                 }
3250         }
3251 }
3252
3253 /**
3254  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
3255  * @ha: pointer to adapter structure
3256  *
3257  * Note: IDC lock must be held upon entry
3258  **/
3259 int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
3260 {
3261         int rval = QLA_ERROR;
3262         int i;
3263         uint32_t old_count, count;
3264         int need_reset = 0;
3265
3266         need_reset = ha->isp_ops->need_reset(ha);
3267
3268         if (need_reset) {
3269                 /* We are trying to perform a recovery here. */
3270                 if (test_bit(AF_FW_RECOVERY, &ha->flags))
3271                         ha->isp_ops->rom_lock_recovery(ha);
3272         } else  {
3273                 old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
3274                 for (i = 0; i < 10; i++) {
3275                         msleep(200);
3276                         count = qla4_8xxx_rd_direct(ha,
3277                                                     QLA8XXX_PEG_ALIVE_COUNTER);
3278                         if (count != old_count) {
3279                                 rval = QLA_SUCCESS;
3280                                 goto dev_ready;
3281                         }
3282                 }
3283                 ha->isp_ops->rom_lock_recovery(ha);
3284         }
3285
3286         /* set to DEV_INITIALIZING */
3287         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
3288         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3289                             QLA8XXX_DEV_INITIALIZING);
3290
3291         ha->isp_ops->idc_unlock(ha);
3292
3293         if (is_qla8022(ha))
3294                 qla4_8xxx_get_minidump(ha);
3295
3296         rval = ha->isp_ops->restart_firmware(ha);
3297         ha->isp_ops->idc_lock(ha);
3298
3299         if (rval != QLA_SUCCESS) {
3300                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
3301                 qla4_8xxx_clear_drv_active(ha);
3302                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3303                                     QLA8XXX_DEV_FAILED);
3304                 return rval;
3305         }
3306
3307 dev_ready:
3308         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
3309         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
3310
3311         return rval;
3312 }
3313
3314 /**
3315  * qla4_82xx_need_reset_handler - Code to start reset sequence
3316  * @ha: pointer to adapter structure
3317  *
3318  * Note: IDC lock must be held upon entry
3319  **/
3320 static void
3321 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
3322 {
3323         uint32_t dev_state, drv_state, drv_active;
3324         uint32_t active_mask = 0xFFFFFFFF;
3325         unsigned long reset_timeout;
3326
3327         ql4_printk(KERN_INFO, ha,
3328                 "Performing ISP error recovery\n");
3329
3330         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
3331                 qla4_82xx_idc_unlock(ha);
3332                 ha->isp_ops->disable_intrs(ha);
3333                 qla4_82xx_idc_lock(ha);
3334         }
3335
3336         if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
3337                 DEBUG2(ql4_printk(KERN_INFO, ha,
3338                                   "%s(%ld): reset acknowledged\n",
3339                                   __func__, ha->host_no));
3340                 qla4_8xxx_set_rst_ready(ha);
3341         } else {
3342                 active_mask = (~(1 << (ha->func_num * 4)));
3343         }
3344
3345         /* wait for 10 seconds for reset ack from all functions */
3346         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3347
3348         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3349         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3350
3351         ql4_printk(KERN_INFO, ha,
3352                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3353                 __func__, ha->host_no, drv_state, drv_active);
3354
3355         while (drv_state != (drv_active & active_mask)) {
3356                 if (time_after_eq(jiffies, reset_timeout)) {
3357                         ql4_printk(KERN_INFO, ha,
3358                                    "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
3359                                    DRIVER_NAME, drv_state, drv_active);
3360                         break;
3361                 }
3362
3363                 /*
3364                  * When reset_owner times out, check which functions
3365                  * acked/did not ack
3366                  */
3367                 if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
3368                         ql4_printk(KERN_INFO, ha,
3369                                    "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
3370                                    __func__, ha->host_no, drv_state,
3371                                    drv_active);
3372                 }
3373                 qla4_82xx_idc_unlock(ha);
3374                 msleep(1000);
3375                 qla4_82xx_idc_lock(ha);
3376
3377                 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3378                 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3379         }
3380
3381         /* Clear RESET OWNER as we are not going to use it any further */
3382         clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
3383
3384         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3385         ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
3386                    dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3387
3388         /* Force to DEV_COLD unless someone else is starting a reset */
3389         if (dev_state != QLA8XXX_DEV_INITIALIZING) {
3390                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
3391                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3392                 qla4_8xxx_set_rst_ready(ha);
3393         }
3394 }
3395
3396 /**
3397  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
3398  * @ha: pointer to adapter structure
3399  **/
3400 void
3401 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
3402 {
3403         ha->isp_ops->idc_lock(ha);
3404         qla4_8xxx_set_qsnt_ready(ha);
3405         ha->isp_ops->idc_unlock(ha);
3406 }
3407
3408 static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha)
3409 {
3410         int idc_ver;
3411         uint32_t drv_active;
3412
3413         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3414         if (drv_active == (1 << (ha->func_num * 4))) {
3415                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION,
3416                                     QLA82XX_IDC_VERSION);
3417                 ql4_printk(KERN_INFO, ha,
3418                            "%s: IDC version updated to %d\n", __func__,
3419                            QLA82XX_IDC_VERSION);
3420         } else {
3421                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3422                 if (QLA82XX_IDC_VERSION != idc_ver) {
3423                         ql4_printk(KERN_INFO, ha,
3424                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3425                                    __func__, QLA82XX_IDC_VERSION, idc_ver);
3426                 }
3427         }
3428 }
3429
3430 static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha)
3431 {
3432         int idc_ver;
3433         uint32_t drv_active;
3434         int rval = QLA_SUCCESS;
3435
3436         drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3437         if (drv_active == (1 << ha->func_num)) {
3438                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3439                 idc_ver &= (~0xFF);
3440                 idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE;
3441                 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver);
3442                 ql4_printk(KERN_INFO, ha,
3443                            "%s: IDC version updated to %d\n", __func__,
3444                            idc_ver);
3445         } else {
3446                 idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION);
3447                 idc_ver &= 0xFF;
3448                 if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) {
3449                         ql4_printk(KERN_INFO, ha,
3450                                    "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n",
3451                                    __func__, QLA83XX_IDC_VER_MAJ_VALUE,
3452                                    idc_ver);
3453                         rval = QLA_ERROR;
3454                         goto exit_set_idc_ver;
3455                 }
3456         }
3457
3458         /* Update IDC_MINOR_VERSION */
3459         idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR);
3460         idc_ver &= ~(0x03 << (ha->func_num * 2));
3461         idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2));
3462         qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver);
3463
3464 exit_set_idc_ver:
3465         return rval;
3466 }
3467
3468 int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha)
3469 {
3470         uint32_t drv_active;
3471         int rval = QLA_SUCCESS;
3472
3473         if (test_bit(AF_INIT_DONE, &ha->flags))
3474                 goto exit_update_idc_reg;
3475
3476         ha->isp_ops->idc_lock(ha);
3477         qla4_8xxx_set_drv_active(ha);
3478
3479         /*
3480          * If we are the first driver to load and
3481          * ql4xdontresethba is not set, clear IDC_CTRL BIT0.
3482          */
3483         if (is_qla8032(ha) || is_qla8042(ha)) {
3484                 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE);
3485                 if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba)
3486                         qla4_83xx_clear_idc_dontreset(ha);
3487         }
3488
3489         if (is_qla8022(ha)) {
3490                 qla4_82xx_set_idc_ver(ha);
3491         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3492                 rval = qla4_83xx_set_idc_ver(ha);
3493                 if (rval == QLA_ERROR)
3494                         qla4_8xxx_clear_drv_active(ha);
3495         }
3496
3497         ha->isp_ops->idc_unlock(ha);
3498
3499 exit_update_idc_reg:
3500         return rval;
3501 }
3502
3503 /**
3504  * qla4_8xxx_device_state_handler - Adapter state machine
3505  * @ha: pointer to host adapter structure.
3506  *
3507  * Note: IDC lock must be UNLOCKED upon entry
3508  **/
3509 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
3510 {
3511         uint32_t dev_state;
3512         int rval = QLA_SUCCESS;
3513         unsigned long dev_init_timeout;
3514
3515         rval = qla4_8xxx_update_idc_reg(ha);
3516         if (rval == QLA_ERROR)
3517                 goto exit_state_handler;
3518
3519         dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3520         DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3521                           dev_state, dev_state < MAX_STATES ?
3522                           qdev_state[dev_state] : "Unknown"));
3523
3524         /* wait for 30 seconds for device to go ready */
3525         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3526
3527         ha->isp_ops->idc_lock(ha);
3528         while (1) {
3529
3530                 if (time_after_eq(jiffies, dev_init_timeout)) {
3531                         ql4_printk(KERN_WARNING, ha,
3532                                    "%s: Device Init Failed 0x%x = %s\n",
3533                                    DRIVER_NAME,
3534                                    dev_state, dev_state < MAX_STATES ?
3535                                    qdev_state[dev_state] : "Unknown");
3536                         qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE,
3537                                             QLA8XXX_DEV_FAILED);
3538                 }
3539
3540                 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
3541                 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
3542                            dev_state, dev_state < MAX_STATES ?
3543                            qdev_state[dev_state] : "Unknown");
3544
3545                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
3546                 switch (dev_state) {
3547                 case QLA8XXX_DEV_READY:
3548                         goto exit;
3549                 case QLA8XXX_DEV_COLD:
3550                         rval = qla4_8xxx_device_bootstrap(ha);
3551                         goto exit;
3552                 case QLA8XXX_DEV_INITIALIZING:
3553                         ha->isp_ops->idc_unlock(ha);
3554                         msleep(1000);
3555                         ha->isp_ops->idc_lock(ha);
3556                         break;
3557                 case QLA8XXX_DEV_NEED_RESET:
3558                         /*
3559                          * For ISP8324 and ISP8042, if NEED_RESET is set by any
3560                          * driver, it should be honored, irrespective of
3561                          * IDC_CTRL DONTRESET_BIT0
3562                          */
3563                         if (is_qla8032(ha) || is_qla8042(ha)) {
3564                                 qla4_83xx_need_reset_handler(ha);
3565                         } else if (is_qla8022(ha)) {
3566                                 if (!ql4xdontresethba) {
3567                                         qla4_82xx_need_reset_handler(ha);
3568                                         /* Update timeout value after need
3569                                          * reset handler */
3570                                         dev_init_timeout = jiffies +
3571                                                 (ha->nx_dev_init_timeout * HZ);
3572                                 } else {
3573                                         ha->isp_ops->idc_unlock(ha);
3574                                         msleep(1000);
3575                                         ha->isp_ops->idc_lock(ha);
3576                                 }
3577                         }
3578                         break;
3579                 case QLA8XXX_DEV_NEED_QUIESCENT:
3580                         /* idc locked/unlocked in handler */
3581                         qla4_8xxx_need_qsnt_handler(ha);
3582                         break;
3583                 case QLA8XXX_DEV_QUIESCENT:
3584                         ha->isp_ops->idc_unlock(ha);
3585                         msleep(1000);
3586                         ha->isp_ops->idc_lock(ha);
3587                         break;
3588                 case QLA8XXX_DEV_FAILED:
3589                         ha->isp_ops->idc_unlock(ha);
3590                         qla4xxx_dead_adapter_cleanup(ha);
3591                         rval = QLA_ERROR;
3592                         ha->isp_ops->idc_lock(ha);
3593                         goto exit;
3594                 default:
3595                         ha->isp_ops->idc_unlock(ha);
3596                         qla4xxx_dead_adapter_cleanup(ha);
3597                         rval = QLA_ERROR;
3598                         ha->isp_ops->idc_lock(ha);
3599                         goto exit;
3600                 }
3601         }
3602 exit:
3603         ha->isp_ops->idc_unlock(ha);
3604 exit_state_handler:
3605         return rval;
3606 }
3607
3608 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
3609 {
3610         int retval;
3611
3612         /* clear the interrupt */
3613         if (is_qla8032(ha) || is_qla8042(ha)) {
3614                 writel(0, &ha->qla4_83xx_reg->risc_intr);
3615                 readl(&ha->qla4_83xx_reg->risc_intr);
3616         } else if (is_qla8022(ha)) {
3617                 writel(0, &ha->qla4_82xx_reg->host_int);
3618                 readl(&ha->qla4_82xx_reg->host_int);
3619         }
3620
3621         retval = qla4_8xxx_device_state_handler(ha);
3622
3623         /* Initialize request and response queues. */
3624         if (retval == QLA_SUCCESS)
3625                 qla4xxx_init_rings(ha);
3626
3627         if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags))
3628                 retval = qla4xxx_request_irqs(ha);
3629
3630         return retval;
3631 }
3632
3633 /*****************************************************************************/
3634 /* Flash Manipulation Routines                                               */
3635 /*****************************************************************************/
3636
3637 #define OPTROM_BURST_SIZE       0x1000
3638 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
3639
3640 #define FARX_DATA_FLAG  BIT_31
3641 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
3642 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
3643
3644 static inline uint32_t
3645 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3646 {
3647         return hw->flash_conf_off | faddr;
3648 }
3649
3650 static inline uint32_t
3651 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
3652 {
3653         return hw->flash_data_off | faddr;
3654 }
3655
3656 static uint32_t *
3657 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
3658     uint32_t faddr, uint32_t length)
3659 {
3660         uint32_t i;
3661         uint32_t val;
3662         int loops = 0;
3663         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
3664                 udelay(100);
3665                 cond_resched();
3666                 loops++;
3667         }
3668         if (loops >= 50000) {
3669                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
3670                 return dwptr;
3671         }
3672
3673         /* Dword reads to flash. */
3674         for (i = 0; i < length/4; i++, faddr += 4) {
3675                 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
3676                         ql4_printk(KERN_WARNING, ha,
3677                             "Do ROM fast read failed\n");
3678                         goto done_read;
3679                 }
3680                 dwptr[i] = __constant_cpu_to_le32(val);
3681         }
3682
3683 done_read:
3684         qla4_82xx_rom_unlock(ha);
3685         return dwptr;
3686 }
3687
3688 /*
3689  * Address and length are byte address
3690  */
3691 static uint8_t *
3692 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
3693                 uint32_t offset, uint32_t length)
3694 {
3695         qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
3696         return buf;
3697 }
3698
3699 static int
3700 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
3701 {
3702         const char *loc, *locations[] = { "DEF", "PCI" };
3703
3704         /*
3705          * FLT-location structure resides after the last PCI region.
3706          */
3707
3708         /* Begin with sane defaults. */
3709         loc = locations[0];
3710         *start = FA_FLASH_LAYOUT_ADDR_82;
3711
3712         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
3713         return QLA_SUCCESS;
3714 }
3715
3716 static void
3717 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
3718 {
3719         const char *loc, *locations[] = { "DEF", "FLT" };
3720         uint16_t *wptr;
3721         uint16_t cnt, chksum;
3722         uint32_t start, status;
3723         struct qla_flt_header *flt;
3724         struct qla_flt_region *region;
3725         struct ql82xx_hw_data *hw = &ha->hw;
3726
3727         hw->flt_region_flt = flt_addr;
3728         wptr = (uint16_t *)ha->request_ring;
3729         flt = (struct qla_flt_header *)ha->request_ring;
3730         region = (struct qla_flt_region *)&flt[1];
3731
3732         if (is_qla8022(ha)) {
3733                 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3734                                            flt_addr << 2, OPTROM_BURST_SIZE);
3735         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3736                 status = qla4_83xx_flash_read_u32(ha, flt_addr << 2,
3737                                                   (uint8_t *)ha->request_ring,
3738                                                   0x400);
3739                 if (status != QLA_SUCCESS)
3740                         goto no_flash_data;
3741         }
3742
3743         if (*wptr == __constant_cpu_to_le16(0xffff))
3744                 goto no_flash_data;
3745         if (flt->version != __constant_cpu_to_le16(1)) {
3746                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
3747                         "version=0x%x length=0x%x checksum=0x%x.\n",
3748                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3749                         le16_to_cpu(flt->checksum)));
3750                 goto no_flash_data;
3751         }
3752
3753         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
3754         for (chksum = 0; cnt; cnt--)
3755                 chksum += le16_to_cpu(*wptr++);
3756         if (chksum) {
3757                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
3758                         "version=0x%x length=0x%x checksum=0x%x.\n",
3759                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
3760                         chksum));
3761                 goto no_flash_data;
3762         }
3763
3764         loc = locations[1];
3765         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
3766         for ( ; cnt; cnt--, region++) {
3767                 /* Store addresses as DWORD offsets. */
3768                 start = le32_to_cpu(region->start) >> 2;
3769
3770                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
3771                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
3772                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
3773
3774                 switch (le32_to_cpu(region->code) & 0xff) {
3775                 case FLT_REG_FDT:
3776                         hw->flt_region_fdt = start;
3777                         break;
3778                 case FLT_REG_BOOT_CODE_82:
3779                         hw->flt_region_boot = start;
3780                         break;
3781                 case FLT_REG_FW_82:
3782                 case FLT_REG_FW_82_1:
3783                         hw->flt_region_fw = start;
3784                         break;
3785                 case FLT_REG_BOOTLOAD_82:
3786                         hw->flt_region_bootload = start;
3787                         break;
3788                 case FLT_REG_ISCSI_PARAM:
3789                         hw->flt_iscsi_param =  start;
3790                         break;
3791                 case FLT_REG_ISCSI_CHAP:
3792                         hw->flt_region_chap =  start;
3793                         hw->flt_chap_size =  le32_to_cpu(region->size);
3794                         break;
3795                 case FLT_REG_ISCSI_DDB:
3796                         hw->flt_region_ddb =  start;
3797                         hw->flt_ddb_size =  le32_to_cpu(region->size);
3798                         break;
3799                 }
3800         }
3801         goto done;
3802
3803 no_flash_data:
3804         /* Use hardcoded defaults. */
3805         loc = locations[0];
3806
3807         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
3808         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
3809         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
3810         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
3811         hw->flt_region_chap     = FA_FLASH_ISCSI_CHAP >> 2;
3812         hw->flt_chap_size       = FA_FLASH_CHAP_SIZE;
3813         hw->flt_region_ddb      = FA_FLASH_ISCSI_DDB >> 2;
3814         hw->flt_ddb_size        = FA_FLASH_DDB_SIZE;
3815
3816 done:
3817         DEBUG2(ql4_printk(KERN_INFO, ha,
3818                           "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x  ddb_size=0x%x\n",
3819                           loc, hw->flt_region_flt, hw->flt_region_fdt,
3820                           hw->flt_region_boot, hw->flt_region_bootload,
3821                           hw->flt_region_fw, hw->flt_region_chap,
3822                           hw->flt_chap_size, hw->flt_region_ddb,
3823                           hw->flt_ddb_size));
3824 }
3825
3826 static void
3827 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
3828 {
3829 #define FLASH_BLK_SIZE_4K       0x1000
3830 #define FLASH_BLK_SIZE_32K      0x8000
3831 #define FLASH_BLK_SIZE_64K      0x10000
3832         const char *loc, *locations[] = { "MID", "FDT" };
3833         uint16_t cnt, chksum;
3834         uint16_t *wptr;
3835         struct qla_fdt_layout *fdt;
3836         uint16_t mid = 0;
3837         uint16_t fid = 0;
3838         struct ql82xx_hw_data *hw = &ha->hw;
3839
3840         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3841         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
3842
3843         wptr = (uint16_t *)ha->request_ring;
3844         fdt = (struct qla_fdt_layout *)ha->request_ring;
3845         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3846             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
3847
3848         if (*wptr == __constant_cpu_to_le16(0xffff))
3849                 goto no_flash_data;
3850
3851         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
3852             fdt->sig[3] != 'D')
3853                 goto no_flash_data;
3854
3855         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
3856             cnt++)
3857                 chksum += le16_to_cpu(*wptr++);
3858
3859         if (chksum) {
3860                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
3861                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
3862                     le16_to_cpu(fdt->version)));
3863                 goto no_flash_data;
3864         }
3865
3866         loc = locations[1];
3867         mid = le16_to_cpu(fdt->man_id);
3868         fid = le16_to_cpu(fdt->id);
3869         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
3870         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
3871         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
3872
3873         if (fdt->unprotect_sec_cmd) {
3874                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
3875                     fdt->unprotect_sec_cmd);
3876                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3877                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
3878                     flash_conf_addr(hw, 0x0336);
3879         }
3880         goto done;
3881
3882 no_flash_data:
3883         loc = locations[0];
3884         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
3885 done:
3886         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
3887                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
3888                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
3889                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
3890                 hw->fdt_block_size));
3891 }
3892
3893 static void
3894 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
3895 {
3896 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
3897         uint32_t *wptr;
3898
3899         if (!is_qla8022(ha))
3900                 return;
3901         wptr = (uint32_t *)ha->request_ring;
3902         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
3903                         QLA82XX_IDC_PARAM_ADDR , 8);
3904
3905         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
3906                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
3907                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
3908         } else {
3909                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
3910                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
3911         }
3912
3913         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3914                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
3915         DEBUG2(ql4_printk(KERN_DEBUG, ha,
3916                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
3917         return;
3918 }
3919
3920 void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
3921                               int in_count)
3922 {
3923         int i;
3924
3925         /* Load all mailbox registers, except mailbox 0. */
3926         for (i = 1; i < in_count; i++)
3927                 writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
3928
3929         /* Wakeup firmware  */
3930         writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
3931         readl(&ha->qla4_82xx_reg->mailbox_in[0]);
3932         writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
3933         readl(&ha->qla4_82xx_reg->hint);
3934 }
3935
3936 void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
3937 {
3938         int intr_status;
3939
3940         intr_status = readl(&ha->qla4_82xx_reg->host_int);
3941         if (intr_status & ISRX_82XX_RISC_INT) {
3942                 ha->mbox_status_count = out_count;
3943                 intr_status = readl(&ha->qla4_82xx_reg->host_status);
3944                 ha->isp_ops->interrupt_service_routine(ha, intr_status);
3945
3946                 if (test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
3947                     (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled))
3948                         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
3949                                         0xfbff);
3950         }
3951 }
3952
3953 int
3954 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
3955 {
3956         int ret;
3957         uint32_t flt_addr;
3958
3959         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
3960         if (ret != QLA_SUCCESS)
3961                 return ret;
3962
3963         qla4_8xxx_get_flt_info(ha, flt_addr);
3964         if (is_qla8022(ha)) {
3965                 qla4_82xx_get_fdt_info(ha);
3966                 qla4_82xx_get_idc_param(ha);
3967         } else if (is_qla8032(ha) || is_qla8042(ha)) {
3968                 qla4_83xx_get_idc_param(ha);
3969         }
3970
3971         return QLA_SUCCESS;
3972 }
3973
3974 /**
3975  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
3976  * @ha: pointer to host adapter structure.
3977  *
3978  * Remarks:
3979  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
3980  * not be available after successful return.  Driver must cleanup potential
3981  * outstanding I/O's after calling this funcion.
3982  **/
3983 int
3984 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
3985 {
3986         int status;
3987         uint32_t mbox_cmd[MBOX_REG_COUNT];
3988         uint32_t mbox_sts[MBOX_REG_COUNT];
3989
3990         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3991         memset(&mbox_sts, 0, sizeof(mbox_sts));
3992
3993         mbox_cmd[0] = MBOX_CMD_STOP_FW;
3994         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
3995             &mbox_cmd[0], &mbox_sts[0]);
3996
3997         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
3998             __func__, status));
3999         return status;
4000 }
4001
4002 /**
4003  * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
4004  * @ha: pointer to host adapter structure.
4005  **/
4006 int
4007 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
4008 {
4009         int rval;
4010         uint32_t dev_state;
4011
4012         qla4_82xx_idc_lock(ha);
4013         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
4014
4015         if (dev_state == QLA8XXX_DEV_READY) {
4016                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
4017                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4018                     QLA8XXX_DEV_NEED_RESET);
4019                 set_bit(AF_8XXX_RST_OWNER, &ha->flags);
4020         } else
4021                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
4022
4023         qla4_82xx_idc_unlock(ha);
4024
4025         rval = qla4_8xxx_device_state_handler(ha);
4026
4027         qla4_82xx_idc_lock(ha);
4028         qla4_8xxx_clear_rst_ready(ha);
4029         qla4_82xx_idc_unlock(ha);
4030
4031         if (rval == QLA_SUCCESS) {
4032                 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
4033                 clear_bit(AF_FW_RECOVERY, &ha->flags);
4034         }
4035
4036         return rval;
4037 }
4038
4039 /**
4040  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
4041  * @ha: pointer to host adapter structure.
4042  *
4043  **/
4044 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
4045 {
4046         uint32_t mbox_cmd[MBOX_REG_COUNT];
4047         uint32_t mbox_sts[MBOX_REG_COUNT];
4048         struct mbx_sys_info *sys_info;
4049         dma_addr_t sys_info_dma;
4050         int status = QLA_ERROR;
4051
4052         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
4053                                       &sys_info_dma, GFP_KERNEL);
4054         if (sys_info == NULL) {
4055                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
4056                     ha->host_no, __func__));
4057                 return status;
4058         }
4059
4060         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4061         memset(&mbox_sts, 0, sizeof(mbox_sts));
4062
4063         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
4064         mbox_cmd[1] = LSDW(sys_info_dma);
4065         mbox_cmd[2] = MSDW(sys_info_dma);
4066         mbox_cmd[4] = sizeof(*sys_info);
4067
4068         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
4069             &mbox_sts[0]) != QLA_SUCCESS) {
4070                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
4071                     ha->host_no, __func__));
4072                 goto exit_validate_mac82;
4073         }
4074
4075         /* Make sure we receive the minimum required data to cache internally */
4076         if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) <
4077             offsetof(struct mbx_sys_info, reserved)) {
4078                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
4079                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
4080                 goto exit_validate_mac82;
4081         }
4082
4083         /* Save M.A.C. address & serial_number */
4084         ha->port_num = sys_info->port_num;
4085         memcpy(ha->my_mac, &sys_info->mac_addr[0],
4086             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
4087         memcpy(ha->serial_number, &sys_info->serial_number,
4088             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
4089         memcpy(ha->model_name, &sys_info->board_id_str,
4090                min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
4091         ha->phy_port_cnt = sys_info->phys_port_cnt;
4092         ha->phy_port_num = sys_info->port_num;
4093         ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
4094
4095         DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n",
4096             ha->host_no, __func__, ha->my_mac, ha->serial_number));
4097
4098         status = QLA_SUCCESS;
4099
4100 exit_validate_mac82:
4101         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
4102                           sys_info_dma);
4103         return status;
4104 }
4105
4106 /* Interrupt handling helpers. */
4107
4108 int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
4109 {
4110         uint32_t mbox_cmd[MBOX_REG_COUNT];
4111         uint32_t mbox_sts[MBOX_REG_COUNT];
4112
4113         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4114
4115         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4116         memset(&mbox_sts, 0, sizeof(mbox_sts));
4117         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4118         mbox_cmd[1] = INTR_ENABLE;
4119         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4120                 &mbox_sts[0]) != QLA_SUCCESS) {
4121                 DEBUG2(ql4_printk(KERN_INFO, ha,
4122                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4123                     __func__, mbox_sts[0]));
4124                 return QLA_ERROR;
4125         }
4126         return QLA_SUCCESS;
4127 }
4128
4129 int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
4130 {
4131         uint32_t mbox_cmd[MBOX_REG_COUNT];
4132         uint32_t mbox_sts[MBOX_REG_COUNT];
4133
4134         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
4135
4136         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
4137         memset(&mbox_sts, 0, sizeof(mbox_sts));
4138         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
4139         mbox_cmd[1] = INTR_DISABLE;
4140         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
4141             &mbox_sts[0]) != QLA_SUCCESS) {
4142                 DEBUG2(ql4_printk(KERN_INFO, ha,
4143                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
4144                         __func__, mbox_sts[0]));
4145                 return QLA_ERROR;
4146         }
4147
4148         return QLA_SUCCESS;
4149 }
4150
4151 void
4152 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
4153 {
4154         qla4_8xxx_intr_enable(ha);
4155
4156         spin_lock_irq(&ha->hardware_lock);
4157         /* BIT 10 - reset */
4158         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
4159         spin_unlock_irq(&ha->hardware_lock);
4160         set_bit(AF_INTERRUPTS_ON, &ha->flags);
4161 }
4162
4163 void
4164 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
4165 {
4166         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
4167                 qla4_8xxx_intr_disable(ha);
4168
4169         spin_lock_irq(&ha->hardware_lock);
4170         /* BIT 10 - set */
4171         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
4172         spin_unlock_irq(&ha->hardware_lock);
4173 }
4174
4175 int
4176 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
4177 {
4178         int ret;
4179
4180         ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES,
4181                         QLA_MSIX_ENTRIES, PCI_IRQ_MSIX);
4182         if (ret < 0) {
4183                 ql4_printk(KERN_WARNING, ha,
4184                     "MSI-X: Failed to enable support -- %d/%d\n",
4185                     QLA_MSIX_ENTRIES, ret);
4186                 return ret;
4187         }
4188
4189         ret = request_irq(pci_irq_vector(ha->pdev, 0),
4190                         qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)",
4191                         ha);
4192         if (ret)
4193                 goto out_free_vectors;
4194
4195         ret = request_irq(pci_irq_vector(ha->pdev, 1),
4196                         qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha);
4197         if (ret)
4198                 goto out_free_default_irq;
4199
4200         return 0;
4201
4202 out_free_default_irq:
4203         free_irq(pci_irq_vector(ha->pdev, 0), ha);
4204 out_free_vectors:
4205         pci_free_irq_vectors(ha->pdev);
4206         return ret;
4207 }
4208
4209 int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha)
4210 {
4211         int status = QLA_SUCCESS;
4212
4213         /* Dont retry adapter initialization if IRQ allocation failed */
4214         if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) {
4215                 ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n",
4216                            __func__);
4217                 status = QLA_ERROR;
4218                 goto exit_init_adapter_failure;
4219         }
4220
4221         /* Since interrupts are registered in start_firmware for
4222          * 8xxx, release them here if initialize_adapter fails
4223          * and retry adapter initialization */
4224         qla4xxx_free_irqs(ha);
4225
4226 exit_init_adapter_failure:
4227         return status;
4228 }