1 // SPDX-License-Identifier: GPL-2.0-only
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
8 #include <linux/delay.h>
9 #include <linux/slab.h>
10 #include <linux/vmalloc.h>
11 #include <linux/uaccess.h>
14 * NVRAM support routines
18 * qla2x00_lock_nvram_access() -
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = rd_reg_word(®->nvram);
29 while (data & NVR_BUSY) {
31 data = rd_reg_word(®->nvram);
35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1);
36 rd_reg_word(®->u.isp2300.host_semaphore);
38 data = rd_reg_word(®->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1);
43 rd_reg_word(®->u.isp2300.host_semaphore);
45 data = rd_reg_word(®->u.isp2300.host_semaphore);
51 * qla2x00_unlock_nvram_access() -
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 wrt_reg_word(®->u.isp2300.host_semaphore, 0);
61 rd_reg_word(®->u.isp2300.host_semaphore);
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @data: Serial interface selector
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 rd_reg_word(®->nvram); /* PCI Posting. */
78 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK |
80 rd_reg_word(®->nvram); /* PCI Posting. */
82 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 rd_reg_word(®->nvram); /* PCI Posting. */
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
91 * @nv_cmd: NVRAM command
93 * Bit definitions for NVRAM command:
98 * Bit 15-0 = write data
100 * Returns the word read from nvram @addr.
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
110 /* Send command to NVRAM. */
112 for (cnt = 0; cnt < 11; cnt++) {
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 qla2x00_nv_write(ha, 0);
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK);
123 rd_reg_word(®->nvram); /* PCI Posting. */
126 reg_data = rd_reg_word(®->nvram);
127 if (reg_data & NVR_DATA_IN)
129 wrt_reg_word(®->nvram, NVR_SELECT);
130 rd_reg_word(®->nvram); /* PCI Posting. */
135 wrt_reg_word(®->nvram, NVR_DESELECT);
136 rd_reg_word(®->nvram); /* PCI Posting. */
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
147 * @addr: Address in NVRAM to read
149 * Returns the word read from nvram @addr.
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173 wrt_reg_word(®->nvram, NVR_DESELECT);
174 rd_reg_word(®->nvram); /* PCI Posting. */
179 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @addr: Address in NVRAM to write
182 * @data: word to program
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data)
189 uint32_t nv_cmd, wait_cnt;
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
191 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
193 qla2x00_nv_write(ha, NVR_DATA_OUT);
194 qla2x00_nv_write(ha, 0);
195 qla2x00_nv_write(ha, 0);
197 for (word = 0; word < 8; word++)
198 qla2x00_nv_write(ha, NVR_DATA_OUT);
200 qla2x00_nv_deselect(ha);
203 nv_cmd = (addr << 16) | NV_WRITE_OP;
204 nv_cmd |= (__force u16)data;
206 for (count = 0; count < 27; count++) {
208 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 qla2x00_nv_write(ha, 0);
215 qla2x00_nv_deselect(ha);
217 /* Wait for NVRAM to become ready */
218 wrt_reg_word(®->nvram, NVR_SELECT);
219 rd_reg_word(®->nvram); /* PCI Posting. */
220 wait_cnt = NVR_WAIT_CNT;
223 ql_dbg(ql_dbg_user, vha, 0x708d,
224 "NVRAM didn't go ready...\n");
228 word = rd_reg_word(®->nvram);
229 } while ((word & NVR_DATA_IN) == 0);
231 qla2x00_nv_deselect(ha);
234 qla2x00_nv_write(ha, NVR_DATA_OUT);
235 for (count = 0; count < 10; count++)
236 qla2x00_nv_write(ha, 0);
238 qla2x00_nv_deselect(ha);
242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
243 __le16 data, uint32_t tmo)
248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
252 qla2x00_nv_write(ha, NVR_DATA_OUT);
253 qla2x00_nv_write(ha, 0);
254 qla2x00_nv_write(ha, 0);
256 for (word = 0; word < 8; word++)
257 qla2x00_nv_write(ha, NVR_DATA_OUT);
259 qla2x00_nv_deselect(ha);
262 nv_cmd = (addr << 16) | NV_WRITE_OP;
263 nv_cmd |= (__force u16)data;
265 for (count = 0; count < 27; count++) {
267 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 qla2x00_nv_write(ha, 0);
274 qla2x00_nv_deselect(ha);
276 /* Wait for NVRAM to become ready */
277 wrt_reg_word(®->nvram, NVR_SELECT);
278 rd_reg_word(®->nvram); /* PCI Posting. */
281 word = rd_reg_word(®->nvram);
283 ret = QLA_FUNCTION_FAILED;
286 } while ((word & NVR_DATA_IN) == 0);
288 qla2x00_nv_deselect(ha);
291 qla2x00_nv_write(ha, NVR_DATA_OUT);
292 for (count = 0; count < 10; count++)
293 qla2x00_nv_write(ha, 0);
295 qla2x00_nv_deselect(ha);
301 * qla2x00_clear_nvram_protection() -
305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
309 uint32_t word, wait_cnt;
310 __le16 wprot, wprot_old;
311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313 /* Clear NVRAM write protection. */
314 ret = QLA_FUNCTION_FAILED;
316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
318 cpu_to_le16(0x1234), 100000);
319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
320 if (stat != QLA_SUCCESS || wprot != cpu_to_le16(0x1234)) {
322 qla2x00_nv_write(ha, NVR_DATA_OUT);
323 qla2x00_nv_write(ha, 0);
324 qla2x00_nv_write(ha, 0);
325 for (word = 0; word < 8; word++)
326 qla2x00_nv_write(ha, NVR_DATA_OUT);
328 qla2x00_nv_deselect(ha);
330 /* Enable protection register. */
331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 for (word = 0; word < 8; word++)
335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337 qla2x00_nv_deselect(ha);
339 /* Clear protection register (ffff is cleared). */
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 for (word = 0; word < 8; word++)
344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346 qla2x00_nv_deselect(ha);
348 /* Wait for NVRAM to become ready. */
349 wrt_reg_word(®->nvram, NVR_SELECT);
350 rd_reg_word(®->nvram); /* PCI Posting. */
351 wait_cnt = NVR_WAIT_CNT;
354 ql_dbg(ql_dbg_user, vha, 0x708e,
355 "NVRAM didn't go ready...\n");
359 word = rd_reg_word(®->nvram);
360 } while ((word & NVR_DATA_IN) == 0);
365 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
371 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
374 uint32_t word, wait_cnt;
375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
377 if (stat != QLA_SUCCESS)
380 /* Set NVRAM write protection. */
382 qla2x00_nv_write(ha, NVR_DATA_OUT);
383 qla2x00_nv_write(ha, 0);
384 qla2x00_nv_write(ha, 0);
385 for (word = 0; word < 8; word++)
386 qla2x00_nv_write(ha, NVR_DATA_OUT);
388 qla2x00_nv_deselect(ha);
390 /* Enable protection register. */
391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
392 qla2x00_nv_write(ha, NVR_PR_ENABLE);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 for (word = 0; word < 8; word++)
395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397 qla2x00_nv_deselect(ha);
399 /* Enable protection register. */
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
403 for (word = 0; word < 8; word++)
404 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406 qla2x00_nv_deselect(ha);
408 /* Wait for NVRAM to become ready. */
409 wrt_reg_word(®->nvram, NVR_SELECT);
410 rd_reg_word(®->nvram); /* PCI Posting. */
411 wait_cnt = NVR_WAIT_CNT;
414 ql_dbg(ql_dbg_user, vha, 0x708f,
415 "NVRAM didn't go ready...\n");
419 word = rd_reg_word(®->nvram);
420 } while ((word & NVR_DATA_IN) == 0);
424 /*****************************************************************************/
425 /* Flash Manipulation Routines */
426 /*****************************************************************************/
428 static inline uint32_t
429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431 return ha->flash_conf_off + faddr;
434 static inline uint32_t
435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437 return ha->flash_data_off + faddr;
440 static inline uint32_t
441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443 return ha->nvram_conf_off + naddr;
446 static inline uint32_t
447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449 return ha->nvram_data_off + naddr;
453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data)
455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG);
461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) {
462 *data = rd_reg_dword(®->flash_data);
469 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
470 "Flash read dword at %x timeout.\n", addr);
472 return QLA_FUNCTION_TIMEOUT;
476 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
480 int ret = QLA_SUCCESS;
481 struct qla_hw_data *ha = vha->hw;
483 /* Dword reads to flash. */
484 faddr = flash_data_addr(ha, faddr);
485 for (i = 0; i < dwords; i++, faddr++, dwptr++) {
486 ret = qla24xx_read_flash_dword(ha, faddr, dwptr);
487 if (ret != QLA_SUCCESS)
496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
501 wrt_reg_dword(®->flash_data, data);
502 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG);
505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG))
511 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
512 "Flash write dword at %x timeout.\n", addr);
513 return QLA_FUNCTION_TIMEOUT;
517 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
520 uint32_t faddr, ids = 0;
522 *man_id = *flash_id = 0;
524 faddr = flash_conf_addr(ha, 0x03ab);
525 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
527 *flash_id = MSB(ids);
530 /* Check if man_id and flash_id are valid. */
531 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
532 /* Read information using 0x9f opcode
533 * Device ID, Mfg ID would be read in the format:
534 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
535 * Example: ATMEL 0x00 01 45 1F
536 * Extract MFG and Dev ID from last two bytes.
538 faddr = flash_conf_addr(ha, 0x009f);
539 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
541 *flash_id = MSB(ids);
547 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
549 const char *loc, *locations[] = { "DEF", "PCI" };
550 uint32_t pcihdr, pcids;
551 uint16_t cnt, chksum;
553 struct qla_hw_data *ha = vha->hw;
554 struct req_que *req = ha->req_q_map[0];
555 struct qla_flt_location *fltl = (void *)req->ring;
556 uint32_t *dcode = (uint32_t *)req->ring;
557 uint8_t *buf = (void *)req->ring, *bcode, last_image;
560 * FLT-location structure resides after the last PCI region.
563 /* Begin with sane defaults. */
566 if (IS_QLA24XX_TYPE(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_24;
568 else if (IS_QLA25XX(ha))
569 *start = FA_FLASH_LAYOUT_ADDR;
570 else if (IS_QLA81XX(ha))
571 *start = FA_FLASH_LAYOUT_ADDR_81;
572 else if (IS_P3P_TYPE(ha)) {
573 *start = FA_FLASH_LAYOUT_ADDR_82;
575 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
576 *start = FA_FLASH_LAYOUT_ADDR_83;
578 } else if (IS_QLA28XX(ha)) {
579 *start = FA_FLASH_LAYOUT_ADDR_28;
583 /* Begin with first PCI expansion ROM header. */
586 /* Verify PCI expansion ROM header. */
587 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
588 bcode = buf + (pcihdr % 4);
589 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
592 /* Locate PCI data structure. */
593 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
594 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
595 bcode = buf + (pcihdr % 4);
597 /* Validate signature of PCI data structure. */
598 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
599 bcode[0x2] != 'I' || bcode[0x3] != 'R')
602 last_image = bcode[0x15] & BIT_7;
604 /* Locate next PCI expansion ROM. */
605 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
606 } while (!last_image);
608 /* Now verify FLT-location structure. */
609 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2);
610 if (memcmp(fltl->sig, "QFLT", 4))
613 wptr = (__force __le16 *)req->ring;
614 cnt = sizeof(*fltl) / sizeof(*wptr);
615 for (chksum = 0; cnt--; wptr++)
616 chksum += le16_to_cpu(*wptr);
618 ql_log(ql_log_fatal, vha, 0x0045,
619 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
620 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
621 fltl, sizeof(*fltl));
622 return QLA_FUNCTION_FAILED;
625 /* Good data. Use specified location. */
627 *start = (le16_to_cpu(fltl->start_hi) << 16 |
628 le16_to_cpu(fltl->start_lo)) >> 2;
630 ql_dbg(ql_dbg_init, vha, 0x0046,
631 "FLTL[%s] = 0x%x.\n",
637 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
639 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1];
640 const uint32_t def_fw[] =
641 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
642 const uint32_t def_boot[] =
643 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
644 const uint32_t def_vpd_nvram[] =
645 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
646 const uint32_t def_vpd0[] =
647 { 0, 0, FA_VPD0_ADDR_81 };
648 const uint32_t def_vpd1[] =
649 { 0, 0, FA_VPD1_ADDR_81 };
650 const uint32_t def_nvram0[] =
651 { 0, 0, FA_NVRAM0_ADDR_81 };
652 const uint32_t def_nvram1[] =
653 { 0, 0, FA_NVRAM1_ADDR_81 };
654 const uint32_t def_fdt[] =
655 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
656 FA_FLASH_DESCR_ADDR_81 };
657 const uint32_t def_npiv_conf0[] =
658 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
659 FA_NPIV_CONF0_ADDR_81 };
660 const uint32_t def_npiv_conf1[] =
661 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
662 FA_NPIV_CONF1_ADDR_81 };
663 const uint32_t fcp_prio_cfg0[] =
664 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
666 const uint32_t fcp_prio_cfg1[] =
667 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
670 struct qla_hw_data *ha = vha->hw;
671 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0;
672 struct qla_flt_header *flt = ha->flt;
673 struct qla_flt_region *region = &flt->region[0];
675 uint16_t cnt, chksum;
678 /* Assign FCP prio region since older adapters may not have FLT, or
679 FCP prio region in it's FLT.
681 ha->flt_region_fcp_prio = (ha->port_no == 0) ?
682 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
684 ha->flt_region_flt = flt_addr;
685 wptr = (__force __le16 *)ha->flt;
686 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2,
687 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE));
689 if (le16_to_cpu(*wptr) == 0xffff)
691 if (flt->version != cpu_to_le16(1)) {
692 ql_log(ql_log_warn, vha, 0x0047,
693 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
694 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
695 le16_to_cpu(flt->checksum));
699 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr);
700 for (chksum = 0; cnt--; wptr++)
701 chksum += le16_to_cpu(*wptr);
703 ql_log(ql_log_fatal, vha, 0x0048,
704 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
705 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
706 le16_to_cpu(flt->checksum));
710 cnt = le16_to_cpu(flt->length) / sizeof(*region);
711 for ( ; cnt; cnt--, region++) {
712 /* Store addresses as DWORD offsets. */
713 start = le32_to_cpu(region->start) >> 2;
714 ql_dbg(ql_dbg_init, vha, 0x0049,
715 "FLT[%#x]: start=%#x end=%#x size=%#x.\n",
716 le16_to_cpu(region->code), start,
717 le32_to_cpu(region->end) >> 2,
718 le32_to_cpu(region->size) >> 2);
719 if (region->attribute)
720 ql_log(ql_dbg_init, vha, 0xffff,
721 "Region %x is secure\n", region->code);
723 switch (le16_to_cpu(region->code)) {
724 case FLT_REG_FCOE_FW:
727 ha->flt_region_fw = start;
732 ha->flt_region_fw = start;
734 case FLT_REG_BOOT_CODE:
735 ha->flt_region_boot = start;
740 ha->flt_region_vpd_nvram = start;
743 if (ha->port_no == 0)
744 ha->flt_region_vpd = start;
747 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
749 if (ha->port_no == 1)
750 ha->flt_region_vpd = start;
753 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
755 if (ha->port_no == 2)
756 ha->flt_region_vpd = start;
759 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
761 if (ha->port_no == 3)
762 ha->flt_region_vpd = start;
764 case FLT_REG_NVRAM_0:
767 if (ha->port_no == 0)
768 ha->flt_region_nvram = start;
770 case FLT_REG_NVRAM_1:
773 if (ha->port_no == 1)
774 ha->flt_region_nvram = start;
776 case FLT_REG_NVRAM_2:
777 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
779 if (ha->port_no == 2)
780 ha->flt_region_nvram = start;
782 case FLT_REG_NVRAM_3:
783 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
785 if (ha->port_no == 3)
786 ha->flt_region_nvram = start;
789 ha->flt_region_fdt = start;
791 case FLT_REG_NPIV_CONF_0:
792 if (ha->port_no == 0)
793 ha->flt_region_npiv_conf = start;
795 case FLT_REG_NPIV_CONF_1:
796 if (ha->port_no == 1)
797 ha->flt_region_npiv_conf = start;
799 case FLT_REG_GOLD_FW:
800 ha->flt_region_gold_fw = start;
802 case FLT_REG_FCP_PRIO_0:
803 if (ha->port_no == 0)
804 ha->flt_region_fcp_prio = start;
806 case FLT_REG_FCP_PRIO_1:
807 if (ha->port_no == 1)
808 ha->flt_region_fcp_prio = start;
810 case FLT_REG_BOOT_CODE_82XX:
811 ha->flt_region_boot = start;
813 case FLT_REG_BOOT_CODE_8044:
815 ha->flt_region_boot = start;
817 case FLT_REG_FW_82XX:
818 ha->flt_region_fw = start;
821 if (IS_CNA_CAPABLE(ha))
822 ha->flt_region_fw = start;
824 case FLT_REG_GOLD_FW_82XX:
825 ha->flt_region_gold_fw = start;
827 case FLT_REG_BOOTLOAD_82XX:
828 ha->flt_region_bootload = start;
830 case FLT_REG_VPD_8XXX:
831 if (IS_CNA_CAPABLE(ha))
832 ha->flt_region_vpd = start;
834 case FLT_REG_FCOE_NVRAM_0:
835 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
837 if (ha->port_no == 0)
838 ha->flt_region_nvram = start;
840 case FLT_REG_FCOE_NVRAM_1:
841 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
843 if (ha->port_no == 1)
844 ha->flt_region_nvram = start;
846 case FLT_REG_IMG_PRI_27XX:
847 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
848 ha->flt_region_img_status_pri = start;
850 case FLT_REG_IMG_SEC_27XX:
851 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
852 ha->flt_region_img_status_sec = start;
854 case FLT_REG_FW_SEC_27XX:
855 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
856 ha->flt_region_fw_sec = start;
858 case FLT_REG_BOOTLOAD_SEC_27XX:
859 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
860 ha->flt_region_boot_sec = start;
862 case FLT_REG_AUX_IMG_PRI_28XX:
863 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
864 ha->flt_region_aux_img_status_pri = start;
866 case FLT_REG_AUX_IMG_SEC_28XX:
867 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
868 ha->flt_region_aux_img_status_sec = start;
870 case FLT_REG_NVRAM_SEC_28XX_0:
871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
872 if (ha->port_no == 0)
873 ha->flt_region_nvram_sec = start;
875 case FLT_REG_NVRAM_SEC_28XX_1:
876 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
877 if (ha->port_no == 1)
878 ha->flt_region_nvram_sec = start;
880 case FLT_REG_NVRAM_SEC_28XX_2:
881 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
882 if (ha->port_no == 2)
883 ha->flt_region_nvram_sec = start;
885 case FLT_REG_NVRAM_SEC_28XX_3:
886 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
887 if (ha->port_no == 3)
888 ha->flt_region_nvram_sec = start;
890 case FLT_REG_VPD_SEC_27XX_0:
891 case FLT_REG_VPD_SEC_28XX_0:
892 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
893 ha->flt_region_vpd_nvram_sec = start;
894 if (ha->port_no == 0)
895 ha->flt_region_vpd_sec = start;
898 case FLT_REG_VPD_SEC_27XX_1:
899 case FLT_REG_VPD_SEC_28XX_1:
900 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
901 if (ha->port_no == 1)
902 ha->flt_region_vpd_sec = start;
904 case FLT_REG_VPD_SEC_27XX_2:
905 case FLT_REG_VPD_SEC_28XX_2:
906 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
907 if (ha->port_no == 2)
908 ha->flt_region_vpd_sec = start;
910 case FLT_REG_VPD_SEC_27XX_3:
911 case FLT_REG_VPD_SEC_28XX_3:
912 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
913 if (ha->port_no == 3)
914 ha->flt_region_vpd_sec = start;
921 /* Use hardcoded defaults. */
923 ha->flt_region_fw = def_fw[def];
924 ha->flt_region_boot = def_boot[def];
925 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
926 ha->flt_region_vpd = (ha->port_no == 0) ?
927 def_vpd0[def] : def_vpd1[def];
928 ha->flt_region_nvram = (ha->port_no == 0) ?
929 def_nvram0[def] : def_nvram1[def];
930 ha->flt_region_fdt = def_fdt[def];
931 ha->flt_region_npiv_conf = (ha->port_no == 0) ?
932 def_npiv_conf0[def] : def_npiv_conf1[def];
934 ql_dbg(ql_dbg_init, vha, 0x004a,
935 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
936 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
937 loc, ha->flt_region_boot, ha->flt_region_fw,
938 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
939 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
940 ha->flt_region_fcp_prio);
944 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
946 #define FLASH_BLK_SIZE_4K 0x1000
947 #define FLASH_BLK_SIZE_32K 0x8000
948 #define FLASH_BLK_SIZE_64K 0x10000
949 const char *loc, *locations[] = { "MID", "FDT" };
950 struct qla_hw_data *ha = vha->hw;
951 struct req_que *req = ha->req_q_map[0];
952 uint16_t cnt, chksum;
953 __le16 *wptr = (__force __le16 *)req->ring;
954 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring;
955 uint8_t man_id, flash_id;
956 uint16_t mid = 0, fid = 0;
958 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2,
959 OPTROM_BURST_DWORDS);
960 if (le16_to_cpu(*wptr) == 0xffff)
962 if (memcmp(fdt->sig, "QLID", 4))
965 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
966 chksum += le16_to_cpu(*wptr);
968 ql_dbg(ql_dbg_init, vha, 0x004c,
969 "Inconsistent FDT detected:"
970 " checksum=0x%x id=%c version0x%x.\n", chksum,
971 fdt->sig[0], le16_to_cpu(fdt->version));
972 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
978 mid = le16_to_cpu(fdt->man_id);
979 fid = le16_to_cpu(fdt->id);
980 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
981 ha->fdt_wrt_enable = fdt->wrt_enable_bits;
982 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd;
984 ha->fdt_erase_cmd = fdt->erase_cmd;
987 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
988 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
989 if (fdt->unprotect_sec_cmd) {
990 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
991 fdt->unprotect_sec_cmd);
992 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
993 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) :
994 flash_conf_addr(ha, 0x0336);
999 if (IS_P3P_TYPE(ha)) {
1000 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1003 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
1006 ha->fdt_wrt_disable = 0x9c;
1007 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
1009 case 0xbf: /* STT flash. */
1010 if (flash_id == 0x8e)
1011 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1013 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
1015 if (flash_id == 0x80)
1016 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
1018 case 0x13: /* ST M25P80. */
1019 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1021 case 0x1f: /* Atmel 26DF081A. */
1022 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
1023 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
1024 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
1025 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
1028 /* Default to 64 kb sector size. */
1029 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1033 ql_dbg(ql_dbg_init, vha, 0x004d,
1034 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
1035 "pr=%x wrtd=0x%x blk=0x%x.\n",
1037 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
1038 ha->fdt_wrt_disable, ha->fdt_block_size);
1043 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
1045 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
1047 struct qla_hw_data *ha = vha->hw;
1048 struct req_que *req = ha->req_q_map[0];
1050 if (!(IS_P3P_TYPE(ha)))
1053 wptr = (__force __le32 *)req->ring;
1054 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8);
1056 if (*wptr == cpu_to_le32(0xffffffff)) {
1057 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
1058 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
1060 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr);
1062 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
1064 ql_dbg(ql_dbg_init, vha, 0x004e,
1065 "fcoe_dev_init_timeout=%d "
1066 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
1067 ha->fcoe_reset_timeout);
1072 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
1076 struct qla_hw_data *ha = vha->hw;
1078 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1079 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) &&
1080 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1083 ret = qla2xxx_find_flt_start(vha, &flt_addr);
1084 if (ret != QLA_SUCCESS)
1087 qla2xxx_get_flt_info(vha, flt_addr);
1088 qla2xxx_get_fdt_info(vha);
1089 qla2xxx_get_idc_param(vha);
1095 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
1097 #define NPIV_CONFIG_SIZE (16*1024)
1100 uint16_t cnt, chksum;
1102 struct qla_npiv_header hdr;
1103 struct qla_npiv_entry *entry;
1104 struct qla_hw_data *ha = vha->hw;
1106 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1107 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1110 if (ha->flags.nic_core_reset_hdlr_active)
1116 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2,
1117 sizeof(struct qla_npiv_header));
1118 if (hdr.version == cpu_to_le16(0xffff))
1120 if (hdr.version != cpu_to_le16(1)) {
1121 ql_dbg(ql_dbg_user, vha, 0x7090,
1122 "Unsupported NPIV-Config "
1123 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1124 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1125 le16_to_cpu(hdr.checksum));
1129 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1131 ql_log(ql_log_warn, vha, 0x7091,
1132 "Unable to allocate memory for data.\n");
1136 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2,
1139 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
1140 for (wptr = data, chksum = 0; cnt--; wptr++)
1141 chksum += le16_to_cpu(*wptr);
1143 ql_dbg(ql_dbg_user, vha, 0x7092,
1144 "Inconsistent NPIV-Config "
1145 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1146 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1147 le16_to_cpu(hdr.checksum));
1151 entry = data + sizeof(struct qla_npiv_header);
1152 cnt = le16_to_cpu(hdr.entries);
1153 for (i = 0; cnt; cnt--, entry++, i++) {
1155 struct fc_vport_identifiers vid;
1156 struct fc_vport *vport;
1158 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1160 flags = le16_to_cpu(entry->flags);
1161 if (flags == 0xffff)
1163 if ((flags & BIT_0) == 0)
1166 memset(&vid, 0, sizeof(vid));
1167 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1168 vid.vport_type = FC_PORTTYPE_NPIV;
1169 vid.disable = false;
1170 vid.port_name = wwn_to_u64(entry->port_name);
1171 vid.node_name = wwn_to_u64(entry->node_name);
1173 ql_dbg(ql_dbg_user, vha, 0x7093,
1174 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n",
1175 cnt, vid.port_name, vid.node_name,
1176 le16_to_cpu(entry->vf_id),
1177 entry->q_qos, entry->f_qos);
1179 if (i < QLA_PRECONFIG_VPORTS) {
1180 vport = fc_vport_create(vha->host, 0, &vid);
1182 ql_log(ql_log_warn, vha, 0x7094,
1183 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n",
1184 cnt, vid.port_name, vid.node_name);
1192 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1194 struct qla_hw_data *ha = vha->hw;
1195 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1197 if (ha->flags.fac_supported)
1198 return qla81xx_fac_do_write_enable(vha, 1);
1200 /* Enable flash write. */
1201 wrt_reg_dword(®->ctrl_status,
1202 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE);
1203 rd_reg_dword(®->ctrl_status); /* PCI Posting. */
1205 if (!ha->fdt_wrt_disable)
1208 /* Disable flash write-protection, first clear SR protection bit */
1209 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1210 /* Then write zero again to clear remaining SR bits.*/
1211 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1217 qla24xx_protect_flash(scsi_qla_host_t *vha)
1219 struct qla_hw_data *ha = vha->hw;
1220 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1222 uint32_t faddr, dword;
1224 if (ha->flags.fac_supported)
1225 return qla81xx_fac_do_write_enable(vha, 0);
1227 if (!ha->fdt_wrt_disable)
1228 goto skip_wrt_protect;
1230 /* Enable flash write-protection and wait for completion. */
1231 faddr = flash_conf_addr(ha, 0x101);
1232 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable);
1233 faddr = flash_conf_addr(ha, 0x5);
1235 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) {
1236 if (!(dword & BIT_0))
1243 /* Disable flash write. */
1244 wrt_reg_dword(®->ctrl_status,
1245 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1251 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1253 struct qla_hw_data *ha = vha->hw;
1254 uint32_t start, finish;
1256 if (ha->flags.fac_supported) {
1258 finish = start + (ha->fdt_block_size >> 2) - 1;
1259 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1260 start), flash_data_addr(ha, finish));
1263 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1264 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1265 ((fdata >> 16) & 0xff));
1269 qla24xx_write_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
1274 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
1275 uint32_t sec_mask, rest_addr, fdata;
1276 dma_addr_t optrom_dma;
1277 void *optrom = NULL;
1278 struct qla_hw_data *ha = vha->hw;
1280 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1281 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1284 /* Allocate dma buffer for burst write */
1285 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1286 &optrom_dma, GFP_KERNEL);
1288 ql_log(ql_log_warn, vha, 0x7095,
1289 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
1293 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1294 "Unprotect flash...\n");
1295 ret = qla24xx_unprotect_flash(vha);
1297 ql_log(ql_log_warn, vha, 0x7096,
1298 "Failed to unprotect flash.\n");
1302 rest_addr = (ha->fdt_block_size >> 2) - 1;
1303 sec_mask = ~rest_addr;
1304 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1305 fdata = (faddr & sec_mask) << 2;
1307 /* Are we at the beginning of a sector? */
1308 if (!(faddr & rest_addr)) {
1309 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1310 "Erase sector %#x...\n", faddr);
1312 ret = qla24xx_erase_sector(vha, fdata);
1314 ql_dbg(ql_dbg_user, vha, 0x7007,
1315 "Failed to erase sector %x.\n", faddr);
1321 /* If smaller than a burst remaining */
1322 if (dwords - liter < dburst)
1323 dburst = dwords - liter;
1325 /* Copy to dma buffer */
1326 memcpy(optrom, dwptr, dburst << 2);
1329 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1330 "Write burst (%#lx dwords)...\n", dburst);
1331 ret = qla2x00_load_ram(vha, optrom_dma,
1332 flash_data_addr(ha, faddr), dburst);
1334 liter += dburst - 1;
1335 faddr += dburst - 1;
1336 dwptr += dburst - 1;
1340 ql_log(ql_log_warn, vha, 0x7097,
1341 "Failed burst-write at %x (%p/%#llx)....\n",
1342 flash_data_addr(ha, faddr), optrom,
1345 dma_free_coherent(&ha->pdev->dev,
1346 OPTROM_BURST_SIZE, optrom, optrom_dma);
1348 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
1350 ql_log(ql_log_warn, vha, 0x7098,
1351 "Reverting to slow write...\n");
1355 ret = qla24xx_write_flash_dword(ha,
1356 flash_data_addr(ha, faddr), le32_to_cpu(*dwptr));
1358 ql_dbg(ql_dbg_user, vha, 0x7006,
1359 "Failed slow write %x (%x)\n", faddr, *dwptr);
1364 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1365 "Protect flash...\n");
1366 ret = qla24xx_protect_flash(vha);
1368 ql_log(ql_log_warn, vha, 0x7099,
1369 "Failed to protect flash\n");
1372 dma_free_coherent(&ha->pdev->dev,
1373 OPTROM_BURST_SIZE, optrom, optrom_dma);
1379 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1384 struct qla_hw_data *ha = vha->hw;
1386 /* Word reads to NVRAM via registers. */
1388 qla2x00_lock_nvram_access(ha);
1389 for (i = 0; i < bytes >> 1; i++, naddr++)
1390 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1392 qla2x00_unlock_nvram_access(ha);
1398 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1401 struct qla_hw_data *ha = vha->hw;
1402 uint32_t *dwptr = buf;
1405 if (IS_P3P_TYPE(ha))
1408 /* Dword reads to flash. */
1409 naddr = nvram_data_addr(ha, naddr);
1411 for (i = 0; i < bytes; i++, naddr++, dwptr++) {
1412 if (qla24xx_read_flash_dword(ha, naddr, dwptr))
1414 cpu_to_le32s(dwptr);
1421 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1427 unsigned long flags;
1428 struct qla_hw_data *ha = vha->hw;
1432 spin_lock_irqsave(&ha->hardware_lock, flags);
1433 qla2x00_lock_nvram_access(ha);
1435 /* Disable NVRAM write-protection. */
1436 stat = qla2x00_clear_nvram_protection(ha);
1438 wptr = (uint16_t *)buf;
1439 for (i = 0; i < bytes >> 1; i++, naddr++) {
1440 qla2x00_write_nvram_word(ha, naddr,
1441 cpu_to_le16(*wptr));
1445 /* Enable NVRAM write-protection. */
1446 qla2x00_set_nvram_protection(ha, stat);
1448 qla2x00_unlock_nvram_access(ha);
1449 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1455 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1458 struct qla_hw_data *ha = vha->hw;
1459 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1460 __le32 *dwptr = buf;
1466 if (IS_P3P_TYPE(ha))
1469 /* Enable flash write. */
1470 wrt_reg_dword(®->ctrl_status,
1471 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE);
1472 rd_reg_dword(®->ctrl_status); /* PCI Posting. */
1474 /* Disable NVRAM write-protection. */
1475 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1476 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1478 /* Dword writes to flash. */
1479 naddr = nvram_data_addr(ha, naddr);
1481 for (i = 0; i < bytes; i++, naddr++, dwptr++) {
1482 if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) {
1483 ql_dbg(ql_dbg_user, vha, 0x709a,
1484 "Unable to program nvram address=%x data=%x.\n",
1490 /* Enable NVRAM write-protection. */
1491 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1493 /* Disable flash write. */
1494 wrt_reg_dword(®->ctrl_status,
1495 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1496 rd_reg_dword(®->ctrl_status); /* PCI Posting. */
1502 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1505 struct qla_hw_data *ha = vha->hw;
1506 uint32_t *dwptr = buf;
1509 /* Dword reads to flash. */
1510 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr);
1512 for (i = 0; i < bytes; i++, naddr++, dwptr++) {
1513 if (qla24xx_read_flash_dword(ha, naddr, dwptr))
1516 cpu_to_le32s(dwptr);
1522 #define RMW_BUFFER_SIZE (64 * 1024)
1524 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1527 struct qla_hw_data *ha = vha->hw;
1528 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE);
1531 return QLA_MEMORY_ALLOC_FAILED;
1532 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1534 memcpy(dbuf + (naddr << 2), buf, bytes);
1535 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1543 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1545 if (IS_QLA2322(ha)) {
1546 /* Flip all colors. */
1547 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1549 ha->beacon_color_state = 0;
1550 *pflags = GPIO_LED_ALL_OFF;
1553 ha->beacon_color_state = QLA_LED_ALL_ON;
1554 *pflags = GPIO_LED_RGA_ON;
1557 /* Flip green led only. */
1558 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1560 ha->beacon_color_state = 0;
1561 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1564 ha->beacon_color_state = QLA_LED_GRN_ON;
1565 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1570 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1573 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1575 uint16_t gpio_enable;
1577 uint16_t led_color = 0;
1578 unsigned long flags;
1579 struct qla_hw_data *ha = vha->hw;
1580 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1582 if (IS_P3P_TYPE(ha))
1585 spin_lock_irqsave(&ha->hardware_lock, flags);
1587 /* Save the Original GPIOE. */
1588 if (ha->pio_address) {
1589 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1590 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1592 gpio_enable = rd_reg_word(®->gpioe);
1593 gpio_data = rd_reg_word(®->gpiod);
1596 /* Set the modified gpio_enable values */
1597 gpio_enable |= GPIO_LED_MASK;
1599 if (ha->pio_address) {
1600 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1602 wrt_reg_word(®->gpioe, gpio_enable);
1603 rd_reg_word(®->gpioe);
1606 qla2x00_flip_colors(ha, &led_color);
1608 /* Clear out any previously set LED color. */
1609 gpio_data &= ~GPIO_LED_MASK;
1611 /* Set the new input LED color to GPIOD. */
1612 gpio_data |= led_color;
1614 /* Set the modified gpio_data values */
1615 if (ha->pio_address) {
1616 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1618 wrt_reg_word(®->gpiod, gpio_data);
1619 rd_reg_word(®->gpiod);
1622 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1626 qla2x00_beacon_on(struct scsi_qla_host *vha)
1628 uint16_t gpio_enable;
1630 unsigned long flags;
1631 struct qla_hw_data *ha = vha->hw;
1632 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1634 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1635 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1637 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1638 ql_log(ql_log_warn, vha, 0x709b,
1639 "Unable to update fw options (beacon on).\n");
1640 return QLA_FUNCTION_FAILED;
1643 /* Turn off LEDs. */
1644 spin_lock_irqsave(&ha->hardware_lock, flags);
1645 if (ha->pio_address) {
1646 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1647 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1649 gpio_enable = rd_reg_word(®->gpioe);
1650 gpio_data = rd_reg_word(®->gpiod);
1652 gpio_enable |= GPIO_LED_MASK;
1654 /* Set the modified gpio_enable values. */
1655 if (ha->pio_address) {
1656 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1658 wrt_reg_word(®->gpioe, gpio_enable);
1659 rd_reg_word(®->gpioe);
1662 /* Clear out previously set LED colour. */
1663 gpio_data &= ~GPIO_LED_MASK;
1664 if (ha->pio_address) {
1665 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1667 wrt_reg_word(®->gpiod, gpio_data);
1668 rd_reg_word(®->gpiod);
1670 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1673 * Let the per HBA timer kick off the blinking process based on
1674 * the following flags. No need to do anything else now.
1676 ha->beacon_blink_led = 1;
1677 ha->beacon_color_state = 0;
1683 qla2x00_beacon_off(struct scsi_qla_host *vha)
1685 int rval = QLA_SUCCESS;
1686 struct qla_hw_data *ha = vha->hw;
1688 ha->beacon_blink_led = 0;
1690 /* Set the on flag so when it gets flipped it will be off. */
1692 ha->beacon_color_state = QLA_LED_ALL_ON;
1694 ha->beacon_color_state = QLA_LED_GRN_ON;
1696 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1698 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1699 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1701 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1702 if (rval != QLA_SUCCESS)
1703 ql_log(ql_log_warn, vha, 0x709c,
1704 "Unable to update fw options (beacon off).\n");
1710 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1712 /* Flip all colors. */
1713 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1715 ha->beacon_color_state = 0;
1719 ha->beacon_color_state = QLA_LED_ALL_ON;
1720 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1725 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1727 uint16_t led_color = 0;
1729 unsigned long flags;
1730 struct qla_hw_data *ha = vha->hw;
1731 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1733 /* Save the Original GPIOD. */
1734 spin_lock_irqsave(&ha->hardware_lock, flags);
1735 gpio_data = rd_reg_dword(®->gpiod);
1737 /* Enable the gpio_data reg for update. */
1738 gpio_data |= GPDX_LED_UPDATE_MASK;
1740 wrt_reg_dword(®->gpiod, gpio_data);
1741 gpio_data = rd_reg_dword(®->gpiod);
1743 /* Set the color bits. */
1744 qla24xx_flip_colors(ha, &led_color);
1746 /* Clear out any previously set LED color. */
1747 gpio_data &= ~GPDX_LED_COLOR_MASK;
1749 /* Set the new input LED color to GPIOD. */
1750 gpio_data |= led_color;
1752 /* Set the modified gpio_data values. */
1753 wrt_reg_dword(®->gpiod, gpio_data);
1754 gpio_data = rd_reg_dword(®->gpiod);
1755 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1759 qla83xx_select_led_port(struct qla_hw_data *ha)
1761 uint32_t led_select_value = 0;
1763 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1766 if (ha->port_no == 0)
1767 led_select_value = QLA83XX_LED_PORT0;
1769 led_select_value = QLA83XX_LED_PORT1;
1772 return led_select_value;
1776 qla83xx_beacon_blink(struct scsi_qla_host *vha)
1778 uint32_t led_select_value;
1779 struct qla_hw_data *ha = vha->hw;
1780 uint16_t led_cfg[6];
1781 uint16_t orig_led_cfg[6];
1782 uint32_t led_10_value, led_43_value;
1784 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) &&
1788 if (!ha->beacon_blink_led)
1791 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1792 qla2x00_write_ram_word(vha, 0x1003, 0x40000230);
1793 qla2x00_write_ram_word(vha, 0x1004, 0x40000230);
1794 } else if (IS_QLA2031(ha)) {
1795 led_select_value = qla83xx_select_led_port(ha);
1797 qla83xx_wr_reg(vha, led_select_value, 0x40000230);
1798 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230);
1799 } else if (IS_QLA8031(ha)) {
1800 led_select_value = qla83xx_select_led_port(ha);
1802 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1803 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1804 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1806 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1808 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1809 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1810 } else if (IS_QLA81XX(ha)) {
1814 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1816 if (rval == QLA_SUCCESS) {
1817 if (IS_QLA81XX(ha)) {
1818 led_cfg[0] = 0x4000;
1819 led_cfg[1] = 0x2000;
1825 led_cfg[0] = 0x4000;
1826 led_cfg[1] = 0x4000;
1827 led_cfg[2] = 0x4000;
1828 led_cfg[3] = 0x2000;
1830 led_cfg[5] = 0x2000;
1832 rval = qla81xx_set_led_config(vha, led_cfg);
1834 if (IS_QLA81XX(ha)) {
1835 led_cfg[0] = 0x4000;
1836 led_cfg[1] = 0x2000;
1839 led_cfg[0] = 0x4000;
1840 led_cfg[1] = 0x2000;
1841 led_cfg[2] = 0x4000;
1842 led_cfg[3] = 0x4000;
1844 led_cfg[5] = 0x2000;
1846 rval = qla81xx_set_led_config(vha, led_cfg);
1848 /* On exit, restore original (presumes no status change) */
1849 qla81xx_set_led_config(vha, orig_led_cfg);
1854 qla24xx_beacon_on(struct scsi_qla_host *vha)
1857 unsigned long flags;
1858 struct qla_hw_data *ha = vha->hw;
1859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1861 if (IS_P3P_TYPE(ha))
1864 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1865 goto skip_gpio; /* let blink handle it */
1867 if (ha->beacon_blink_led == 0) {
1868 /* Enable firmware for update */
1869 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1871 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1872 return QLA_FUNCTION_FAILED;
1874 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1876 ql_log(ql_log_warn, vha, 0x7009,
1877 "Unable to update fw options (beacon on).\n");
1878 return QLA_FUNCTION_FAILED;
1881 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1884 spin_lock_irqsave(&ha->hardware_lock, flags);
1885 gpio_data = rd_reg_dword(®->gpiod);
1887 /* Enable the gpio_data reg for update. */
1888 gpio_data |= GPDX_LED_UPDATE_MASK;
1889 wrt_reg_dword(®->gpiod, gpio_data);
1890 rd_reg_dword(®->gpiod);
1892 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1895 /* So all colors blink together. */
1896 ha->beacon_color_state = 0;
1899 /* Let the per HBA timer kick off the blinking process. */
1900 ha->beacon_blink_led = 1;
1906 qla24xx_beacon_off(struct scsi_qla_host *vha)
1909 unsigned long flags;
1910 struct qla_hw_data *ha = vha->hw;
1911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1913 if (IS_P3P_TYPE(ha))
1916 if (!ha->flags.fw_started)
1919 ha->beacon_blink_led = 0;
1921 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1922 goto set_fw_options;
1924 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1927 ha->beacon_color_state = QLA_LED_ALL_ON;
1929 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1931 /* Give control back to firmware. */
1932 spin_lock_irqsave(&ha->hardware_lock, flags);
1933 gpio_data = rd_reg_dword(®->gpiod);
1935 /* Disable the gpio_data reg for update. */
1936 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1937 wrt_reg_dword(®->gpiod, gpio_data);
1938 rd_reg_dword(®->gpiod);
1939 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1942 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1944 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1945 ql_log(ql_log_warn, vha, 0x704d,
1946 "Unable to update fw options (beacon on).\n");
1947 return QLA_FUNCTION_FAILED;
1950 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1951 ql_log(ql_log_warn, vha, 0x704e,
1952 "Unable to update fw options (beacon on).\n");
1953 return QLA_FUNCTION_FAILED;
1961 * Flash support routines
1965 * qla2x00_flash_enable() - Setup flash for reading and writing.
1969 qla2x00_flash_enable(struct qla_hw_data *ha)
1972 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1974 data = rd_reg_word(®->ctrl_status);
1975 data |= CSR_FLASH_ENABLE;
1976 wrt_reg_word(®->ctrl_status, data);
1977 rd_reg_word(®->ctrl_status); /* PCI Posting. */
1981 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1985 qla2x00_flash_disable(struct qla_hw_data *ha)
1988 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1990 data = rd_reg_word(®->ctrl_status);
1991 data &= ~(CSR_FLASH_ENABLE);
1992 wrt_reg_word(®->ctrl_status, data);
1993 rd_reg_word(®->ctrl_status); /* PCI Posting. */
1997 * qla2x00_read_flash_byte() - Reads a byte from flash
1999 * @addr: Address in flash to read
2001 * A word is read from the chip, but, only the lower byte is valid.
2003 * Returns the byte read from flash @addr.
2006 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
2009 uint16_t bank_select;
2010 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2012 bank_select = rd_reg_word(®->ctrl_status);
2014 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2015 /* Specify 64K address range: */
2016 /* clear out Module Select and Flash Address bits [19:16]. */
2017 bank_select &= ~0xf8;
2018 bank_select |= addr >> 12 & 0xf0;
2019 bank_select |= CSR_FLASH_64K_BANK;
2020 wrt_reg_word(®->ctrl_status, bank_select);
2021 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2023 wrt_reg_word(®->flash_address, (uint16_t)addr);
2024 data = rd_reg_word(®->flash_data);
2026 return (uint8_t)data;
2029 /* Setup bit 16 of flash address. */
2030 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2031 bank_select |= CSR_FLASH_64K_BANK;
2032 wrt_reg_word(®->ctrl_status, bank_select);
2033 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2034 } else if (((addr & BIT_16) == 0) &&
2035 (bank_select & CSR_FLASH_64K_BANK)) {
2036 bank_select &= ~(CSR_FLASH_64K_BANK);
2037 wrt_reg_word(®->ctrl_status, bank_select);
2038 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2041 /* Always perform IO mapped accesses to the FLASH registers. */
2042 if (ha->pio_address) {
2045 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2047 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2050 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2051 } while (data != data2);
2053 wrt_reg_word(®->flash_address, (uint16_t)addr);
2054 data = qla2x00_debounce_register(®->flash_data);
2057 return (uint8_t)data;
2061 * qla2x00_write_flash_byte() - Write a byte to flash
2063 * @addr: Address in flash to write
2064 * @data: Data to write
2067 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
2069 uint16_t bank_select;
2070 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2072 bank_select = rd_reg_word(®->ctrl_status);
2073 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2074 /* Specify 64K address range: */
2075 /* clear out Module Select and Flash Address bits [19:16]. */
2076 bank_select &= ~0xf8;
2077 bank_select |= addr >> 12 & 0xf0;
2078 bank_select |= CSR_FLASH_64K_BANK;
2079 wrt_reg_word(®->ctrl_status, bank_select);
2080 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2082 wrt_reg_word(®->flash_address, (uint16_t)addr);
2083 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2084 wrt_reg_word(®->flash_data, (uint16_t)data);
2085 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2090 /* Setup bit 16 of flash address. */
2091 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2092 bank_select |= CSR_FLASH_64K_BANK;
2093 wrt_reg_word(®->ctrl_status, bank_select);
2094 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2095 } else if (((addr & BIT_16) == 0) &&
2096 (bank_select & CSR_FLASH_64K_BANK)) {
2097 bank_select &= ~(CSR_FLASH_64K_BANK);
2098 wrt_reg_word(®->ctrl_status, bank_select);
2099 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2102 /* Always perform IO mapped accesses to the FLASH registers. */
2103 if (ha->pio_address) {
2104 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2105 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
2107 wrt_reg_word(®->flash_address, (uint16_t)addr);
2108 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2109 wrt_reg_word(®->flash_data, (uint16_t)data);
2110 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2115 * qla2x00_poll_flash() - Polls flash for completion.
2117 * @addr: Address in flash to poll
2118 * @poll_data: Data to be polled
2119 * @man_id: Flash manufacturer ID
2120 * @flash_id: Flash ID
2122 * This function polls the device until bit 7 of what is read matches data
2123 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
2124 * out (a fatal error). The flash book recommeds reading bit 7 again after
2125 * reading bit 5 as a 1.
2127 * Returns 0 on success, else non-zero.
2130 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2131 uint8_t man_id, uint8_t flash_id)
2139 /* Wait for 30 seconds for command to finish. */
2141 for (cnt = 3000000; cnt; cnt--) {
2142 flash_data = qla2x00_read_flash_byte(ha, addr);
2143 if ((flash_data & BIT_7) == poll_data) {
2148 if (man_id != 0x40 && man_id != 0xda) {
2149 if ((flash_data & BIT_5) && cnt > 2)
2160 * qla2x00_program_flash_address() - Programs a flash address
2162 * @addr: Address in flash to program
2163 * @data: Data to be written in flash
2164 * @man_id: Flash manufacturer ID
2165 * @flash_id: Flash ID
2167 * Returns 0 on success, else non-zero.
2170 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2171 uint8_t data, uint8_t man_id, uint8_t flash_id)
2173 /* Write Program Command Sequence. */
2174 if (IS_OEM_001(ha)) {
2175 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2176 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2177 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2178 qla2x00_write_flash_byte(ha, addr, data);
2180 if (man_id == 0xda && flash_id == 0xc1) {
2181 qla2x00_write_flash_byte(ha, addr, data);
2185 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2186 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2187 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2188 qla2x00_write_flash_byte(ha, addr, data);
2194 /* Wait for write to complete. */
2195 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2199 * qla2x00_erase_flash() - Erase the flash.
2201 * @man_id: Flash manufacturer ID
2202 * @flash_id: Flash ID
2204 * Returns 0 on success, else non-zero.
2207 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2209 /* Individual Sector Erase Command Sequence */
2210 if (IS_OEM_001(ha)) {
2211 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2212 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2213 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2214 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2215 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2216 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2218 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2219 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2220 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2221 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2222 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2223 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2228 /* Wait for erase to complete. */
2229 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2233 * qla2x00_erase_flash_sector() - Erase a flash sector.
2235 * @addr: Flash sector to erase
2236 * @sec_mask: Sector address mask
2237 * @man_id: Flash manufacturer ID
2238 * @flash_id: Flash ID
2240 * Returns 0 on success, else non-zero.
2243 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2244 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2246 /* Individual Sector Erase Command Sequence */
2247 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2248 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2249 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2250 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2251 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2252 if (man_id == 0x1f && flash_id == 0x13)
2253 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2255 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2259 /* Wait for erase to complete. */
2260 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2264 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2266 * @man_id: Flash manufacturer ID
2267 * @flash_id: Flash ID
2270 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2273 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2274 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2275 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2276 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2277 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2278 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2279 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2280 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2284 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2285 uint32_t saddr, uint32_t length)
2287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2288 uint32_t midpoint, ilength;
2291 midpoint = length / 2;
2293 wrt_reg_word(®->nvram, 0);
2294 rd_reg_word(®->nvram);
2295 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2296 if (ilength == midpoint) {
2297 wrt_reg_word(®->nvram, NVR_SELECT);
2298 rd_reg_word(®->nvram);
2300 data = qla2x00_read_flash_byte(ha, saddr);
2309 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2312 unsigned long flags;
2313 struct qla_hw_data *ha = vha->hw;
2314 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2317 scsi_block_requests(vha->host);
2318 ha->isp_ops->disable_intrs(ha);
2319 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2322 spin_lock_irqsave(&ha->hardware_lock, flags);
2323 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2324 rd_reg_word(®->hccr);
2325 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2326 for (cnt = 0; cnt < 30000; cnt++) {
2327 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0)
2334 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2338 qla2x00_resume_hba(struct scsi_qla_host *vha)
2340 struct qla_hw_data *ha = vha->hw;
2343 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2344 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2345 qla2xxx_wake_dpc(vha);
2346 qla2x00_wait_for_chip_reset(vha);
2347 scsi_unblock_requests(vha->host);
2351 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2352 uint32_t offset, uint32_t length)
2354 uint32_t addr, midpoint;
2356 struct qla_hw_data *ha = vha->hw;
2357 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2360 qla2x00_suspend_hba(vha);
2363 midpoint = ha->optrom_size / 2;
2365 qla2x00_flash_enable(ha);
2366 wrt_reg_word(®->nvram, 0);
2367 rd_reg_word(®->nvram); /* PCI Posting. */
2368 for (addr = offset, data = buf; addr < length; addr++, data++) {
2369 if (addr == midpoint) {
2370 wrt_reg_word(®->nvram, NVR_SELECT);
2371 rd_reg_word(®->nvram); /* PCI Posting. */
2374 *data = qla2x00_read_flash_byte(ha, addr);
2376 qla2x00_flash_disable(ha);
2379 qla2x00_resume_hba(vha);
2385 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2386 uint32_t offset, uint32_t length)
2390 uint8_t man_id, flash_id, sec_number, *data;
2392 uint32_t addr, liter, sec_mask, rest_addr;
2393 struct qla_hw_data *ha = vha->hw;
2394 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2397 qla2x00_suspend_hba(vha);
2402 /* Reset ISP chip. */
2403 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
2404 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2406 /* Go with write. */
2407 qla2x00_flash_enable(ha);
2408 do { /* Loop once to provide quick error exit */
2409 /* Structure of flash memory based on manufacturer */
2410 if (IS_OEM_001(ha)) {
2411 /* OEM variant with special flash part. */
2412 man_id = flash_id = 0;
2417 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2419 case 0x20: /* ST flash. */
2420 if (flash_id == 0xd2 || flash_id == 0xe3) {
2422 * ST m29w008at part - 64kb sector size with
2423 * 32kb,8kb,8kb,16kb sectors at memory address
2431 * ST m29w010b part - 16kb sector size
2432 * Default to 16kb sectors
2437 case 0x40: /* Mostel flash. */
2438 /* Mostel v29c51001 part - 512 byte sector size. */
2442 case 0xbf: /* SST flash. */
2443 /* SST39sf10 part - 4kb sector size. */
2447 case 0xda: /* Winbond flash. */
2448 /* Winbond W29EE011 part - 256 byte sector size. */
2452 case 0xc2: /* Macronix flash. */
2453 /* 64k sector size. */
2454 if (flash_id == 0x38 || flash_id == 0x4f) {
2461 case 0x1f: /* Atmel flash. */
2462 /* 512k sector size. */
2463 if (flash_id == 0x13) {
2464 rest_addr = 0x7fffffff;
2465 sec_mask = 0x80000000;
2470 case 0x01: /* AMD flash. */
2471 if (flash_id == 0x38 || flash_id == 0x40 ||
2473 /* Am29LV081 part - 64kb sector size. */
2474 /* Am29LV002BT part - 64kb sector size. */
2478 } else if (flash_id == 0x3e) {
2480 * Am29LV008b part - 64kb sector size with
2481 * 32kb,8kb,8kb,16kb sector at memory address
2487 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2489 * Am29LV010 part or AM29f010 - 16kb sector
2495 } else if (flash_id == 0x6d) {
2496 /* Am29LV001 part - 8kb sector size. */
2503 /* Default to 16 kb sector size. */
2510 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2511 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2512 rval = QLA_FUNCTION_FAILED;
2517 for (addr = offset, liter = 0; liter < length; liter++,
2520 /* Are we at the beginning of a sector? */
2521 if ((addr & rest_addr) == 0) {
2522 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2523 if (addr >= 0x10000UL) {
2524 if (((addr >> 12) & 0xf0) &&
2526 flash_id == 0x3e) ||
2528 flash_id == 0xd2))) {
2530 if (sec_number == 1) {
2551 } else if (addr == ha->optrom_size / 2) {
2552 wrt_reg_word(®->nvram, NVR_SELECT);
2553 rd_reg_word(®->nvram);
2556 if (flash_id == 0xda && man_id == 0xc1) {
2557 qla2x00_write_flash_byte(ha, 0x5555,
2559 qla2x00_write_flash_byte(ha, 0x2aaa,
2561 qla2x00_write_flash_byte(ha, 0x5555,
2563 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2565 if (qla2x00_erase_flash_sector(ha,
2566 addr, sec_mask, man_id,
2568 rval = QLA_FUNCTION_FAILED;
2571 if (man_id == 0x01 && flash_id == 0x6d)
2576 if (man_id == 0x01 && flash_id == 0x6d) {
2577 if (sec_number == 1 &&
2578 addr == (rest_addr - 1)) {
2581 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2587 if (qla2x00_program_flash_address(ha, addr, *data,
2588 man_id, flash_id)) {
2589 rval = QLA_FUNCTION_FAILED;
2595 qla2x00_flash_disable(ha);
2598 qla2x00_resume_hba(vha);
2604 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2605 uint32_t offset, uint32_t length)
2607 struct qla_hw_data *ha = vha->hw;
2610 scsi_block_requests(vha->host);
2611 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2614 qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2);
2617 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2618 scsi_unblock_requests(vha->host);
2624 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, __le32 *buf,
2625 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf)
2627 uint32_t check_sum = 0;
2631 p = buf + buf_size_without_sfub;
2633 /* Extract SFUB from end of file */
2634 memcpy(sfub_buf, (uint8_t *)p,
2635 sizeof(struct secure_flash_update_block));
2637 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++)
2638 check_sum += le32_to_cpu(p[i]);
2640 check_sum = (~check_sum) + 1;
2642 if (check_sum != le32_to_cpu(p[i])) {
2643 ql_log(ql_log_warn, vha, 0x7097,
2644 "SFUB checksum failed, 0x%x, 0x%x\n",
2645 check_sum, le32_to_cpu(p[i]));
2646 return QLA_COMMAND_ERROR;
2653 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start,
2654 struct qla_flt_region *region)
2656 struct qla_hw_data *ha = vha->hw;
2657 struct qla_flt_header *flt = ha->flt;
2658 struct qla_flt_region *flt_reg = &flt->region[0];
2660 int rval = QLA_FUNCTION_FAILED;
2663 return QLA_FUNCTION_FAILED;
2665 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
2666 for (; cnt; cnt--, flt_reg++) {
2667 if (le32_to_cpu(flt_reg->start) == start) {
2668 memcpy((uint8_t *)region, flt_reg,
2669 sizeof(struct qla_flt_region));
2679 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2682 struct qla_hw_data *ha = vha->hw;
2684 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
2685 uint32_t sec_mask, rest_addr, fdata;
2686 void *optrom = NULL;
2687 dma_addr_t optrom_dma;
2689 struct secure_flash_update_block *sfub;
2690 dma_addr_t sfub_dma;
2691 uint32_t offset = faddr << 2;
2692 uint32_t buf_size_without_sfub = 0;
2693 struct qla_flt_region region;
2694 bool reset_to_rom = false;
2695 uint32_t risc_size, risc_attr = 0;
2696 __be32 *fw_array = NULL;
2698 /* Retrieve region info - must be a start address passed in */
2699 rval = qla28xx_get_flash_region(vha, offset, ®ion);
2701 if (rval != QLA_SUCCESS) {
2702 ql_log(ql_log_warn, vha, 0xffff,
2703 "Invalid address %x - not a region start address\n",
2708 /* Allocate dma buffer for burst write */
2709 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2710 &optrom_dma, GFP_KERNEL);
2712 ql_log(ql_log_warn, vha, 0x7095,
2713 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
2714 rval = QLA_COMMAND_ERROR;
2719 * If adapter supports secure flash and region is secure
2720 * extract secure flash update block (SFUB) and verify
2722 if (ha->flags.secure_adapter && region.attribute) {
2724 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2725 "Region %x is secure\n", le16_to_cpu(region.code));
2727 switch (le16_to_cpu(region.code)) {
2729 case FLT_REG_FW_SEC_27XX:
2730 case FLT_REG_MPI_PRI_28XX:
2731 case FLT_REG_MPI_SEC_28XX:
2732 fw_array = (__force __be32 *)dwptr;
2735 risc_size = be32_to_cpu(fw_array[3]);
2736 risc_attr = be32_to_cpu(fw_array[9]);
2738 buf_size_without_sfub = risc_size;
2739 fw_array += risc_size;
2742 risc_size = be32_to_cpu(fw_array[3]);
2744 buf_size_without_sfub += risc_size;
2745 fw_array += risc_size;
2747 /* 1st dump template */
2748 risc_size = be32_to_cpu(fw_array[2]);
2750 /* skip header and ignore checksum */
2751 buf_size_without_sfub += risc_size;
2752 fw_array += risc_size;
2754 if (risc_attr & BIT_9) {
2755 /* 2nd dump template */
2756 risc_size = be32_to_cpu(fw_array[2]);
2758 /* skip header and ignore checksum */
2759 buf_size_without_sfub += risc_size;
2760 fw_array += risc_size;
2764 case FLT_REG_PEP_PRI_28XX:
2765 case FLT_REG_PEP_SEC_28XX:
2766 fw_array = (__force __be32 *)dwptr;
2769 risc_size = be32_to_cpu(fw_array[3]);
2770 risc_attr = be32_to_cpu(fw_array[9]);
2772 buf_size_without_sfub = risc_size;
2773 fw_array += risc_size;
2777 ql_log(ql_log_warn + ql_dbg_verbose, vha,
2778 0xffff, "Secure region %x not supported\n",
2779 le16_to_cpu(region.code));
2780 rval = QLA_COMMAND_ERROR;
2784 sfub = dma_alloc_coherent(&ha->pdev->dev,
2785 sizeof(struct secure_flash_update_block), &sfub_dma,
2788 ql_log(ql_log_warn, vha, 0xffff,
2789 "Unable to allocate memory for SFUB\n");
2790 rval = QLA_COMMAND_ERROR;
2794 rval = qla28xx_extract_sfub_and_verify(vha, (__le32 *)dwptr,
2795 dwords, buf_size_without_sfub, (uint8_t *)sfub);
2797 if (rval != QLA_SUCCESS)
2800 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2801 "SFUB extract and verify successful\n");
2804 rest_addr = (ha->fdt_block_size >> 2) - 1;
2805 sec_mask = ~rest_addr;
2807 /* Lock semaphore */
2808 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK);
2809 if (rval != QLA_SUCCESS) {
2810 ql_log(ql_log_warn, vha, 0xffff,
2811 "Unable to lock flash semaphore.");
2815 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2816 "Unprotect flash...\n");
2817 rval = qla24xx_unprotect_flash(vha);
2819 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK);
2820 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n");
2824 for (liter = 0; liter < dwords; liter++, faddr++) {
2825 fdata = (faddr & sec_mask) << 2;
2827 /* If start of sector */
2828 if (!(faddr & rest_addr)) {
2829 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2830 "Erase sector %#x...\n", faddr);
2831 rval = qla24xx_erase_sector(vha, fdata);
2833 ql_dbg(ql_dbg_user, vha, 0x7007,
2834 "Failed erase sector %#x\n", faddr);
2840 if (ha->flags.secure_adapter) {
2842 * If adapter supports secure flash but FW doesn't,
2843 * disable write protect, release semaphore and reset
2844 * chip to execute ROM code in order to update region securely
2846 if (!ha->flags.secure_fw) {
2847 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2848 "Disable Write and Release Semaphore.");
2849 rval = qla24xx_protect_flash(vha);
2850 if (rval != QLA_SUCCESS) {
2851 qla81xx_fac_semaphore_access(vha,
2852 FAC_SEMAPHORE_UNLOCK);
2853 ql_log(ql_log_warn, vha, 0xffff,
2854 "Unable to protect flash.");
2858 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2859 "Reset chip to ROM.");
2860 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2861 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags);
2862 qla2xxx_wake_dpc(vha);
2863 rval = qla2x00_wait_for_chip_reset(vha);
2864 if (rval != QLA_SUCCESS) {
2865 ql_log(ql_log_warn, vha, 0xffff,
2866 "Unable to reset to ROM code.");
2869 reset_to_rom = true;
2870 ha->flags.fac_supported = 0;
2872 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2874 rval = qla2xxx_write_remote_register(vha,
2875 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002);
2876 if (rval != QLA_SUCCESS) {
2877 ql_log(ql_log_warn, vha, 0xffff,
2878 "Unable to lock flash semaphore.");
2882 /* Unprotect flash */
2883 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2885 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0);
2887 ql_log(ql_log_warn, vha, 0x7096,
2888 "Failed unprotect flash\n");
2893 /* If region is secure, send Secure Flash MB Cmd */
2894 if (region.attribute && buf_size_without_sfub) {
2895 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2896 "Sending Secure Flash MB Cmd\n");
2897 rval = qla28xx_secure_flash_update(vha, 0,
2898 le16_to_cpu(region.code),
2899 buf_size_without_sfub, sfub_dma,
2900 sizeof(struct secure_flash_update_block) >> 2);
2901 if (rval != QLA_SUCCESS) {
2902 ql_log(ql_log_warn, vha, 0xffff,
2903 "Secure Flash MB Cmd failed %x.", rval);
2910 /* re-init flash offset */
2911 faddr = offset >> 2;
2913 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
2914 fdata = (faddr & sec_mask) << 2;
2916 /* If smaller than a burst remaining */
2917 if (dwords - liter < dburst)
2918 dburst = dwords - liter;
2920 /* Copy to dma buffer */
2921 memcpy(optrom, dwptr, dburst << 2);
2924 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2925 "Write burst (%#lx dwords)...\n", dburst);
2926 rval = qla2x00_load_ram(vha, optrom_dma,
2927 flash_data_addr(ha, faddr), dburst);
2928 if (rval != QLA_SUCCESS) {
2929 ql_log(ql_log_warn, vha, 0x7097,
2930 "Failed burst write at %x (%p/%#llx)...\n",
2931 flash_data_addr(ha, faddr), optrom,
2936 liter += dburst - 1;
2937 faddr += dburst - 1;
2938 dwptr += dburst - 1;
2942 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2943 "Protect flash...\n");
2944 ret = qla24xx_protect_flash(vha);
2946 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK);
2947 ql_log(ql_log_warn, vha, 0x7099,
2948 "Failed protect flash\n");
2949 rval = QLA_COMMAND_ERROR;
2952 if (reset_to_rom == true) {
2953 /* Schedule DPC to restart the RISC */
2954 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2955 qla2xxx_wake_dpc(vha);
2957 ret = qla2x00_wait_for_hba_online(vha);
2958 if (ret != QLA_SUCCESS) {
2959 ql_log(ql_log_warn, vha, 0xffff,
2960 "Adapter did not come out of reset\n");
2961 rval = QLA_COMMAND_ERROR;
2967 dma_free_coherent(&ha->pdev->dev,
2968 OPTROM_BURST_SIZE, optrom, optrom_dma);
2974 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2975 uint32_t offset, uint32_t length)
2978 struct qla_hw_data *ha = vha->hw;
2981 scsi_block_requests(vha->host);
2982 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2984 /* Go with write. */
2986 rval = qla28xx_write_flash_data(vha, buf, offset >> 2,
2989 rval = qla24xx_write_flash_data(vha, buf, offset >> 2,
2992 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2993 scsi_unblock_requests(vha->host);
2999 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
3000 uint32_t offset, uint32_t length)
3003 dma_addr_t optrom_dma;
3006 uint32_t faddr, left, burst;
3007 struct qla_hw_data *ha = vha->hw;
3009 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
3010 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3014 if (length < OPTROM_BURST_SIZE)
3020 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3021 &optrom_dma, GFP_KERNEL);
3023 ql_log(ql_log_warn, vha, 0x00cc,
3024 "Unable to allocate memory for optrom burst read (%x KB).\n",
3025 OPTROM_BURST_SIZE / 1024);
3030 faddr = offset >> 2;
3032 burst = OPTROM_BURST_DWORDS;
3037 rval = qla2x00_dump_ram(vha, optrom_dma,
3038 flash_data_addr(ha, faddr), burst);
3040 ql_log(ql_log_warn, vha, 0x00f5,
3041 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
3042 rval, flash_data_addr(ha, faddr),
3043 (unsigned long long)optrom_dma);
3044 ql_log(ql_log_warn, vha, 0x00f6,
3045 "Reverting to slow-read.\n");
3047 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3048 optrom, optrom_dma);
3052 memcpy(pbuf, optrom, burst * 4);
3059 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
3065 return qla24xx_read_optrom_data(vha, buf, offset, length);
3069 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
3071 * @pcids: Pointer to the FCODE PCI data structure
3073 * The process of retrieving the FCODE version information is at best
3074 * described as interesting.
3076 * Within the first 100h bytes of the image an ASCII string is present
3077 * which contains several pieces of information including the FCODE
3078 * version. Unfortunately it seems the only reliable way to retrieve
3079 * the version is by scanning for another sentinel within the string,
3080 * the FCODE build date:
3082 * ... 2.00.02 10/17/02 ...
3084 * Returns QLA_SUCCESS on successful retrieval of version.
3087 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
3089 int ret = QLA_FUNCTION_FAILED;
3090 uint32_t istart, iend, iter, vend;
3091 uint8_t do_next, rbyte, *vbyte;
3093 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3095 /* Skip the PCI data structure. */
3097 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
3098 qla2x00_read_flash_byte(ha, pcids + 0x0A));
3099 iend = istart + 0x100;
3101 /* Scan for the sentinel date string...eeewww. */
3104 while ((iter < iend) && !do_next) {
3106 if (qla2x00_read_flash_byte(ha, iter) == '/') {
3107 if (qla2x00_read_flash_byte(ha, iter + 2) ==
3110 else if (qla2x00_read_flash_byte(ha,
3118 /* Backtrack to previous ' ' (space). */
3120 while ((iter > istart) && !do_next) {
3122 if (qla2x00_read_flash_byte(ha, iter) == ' ')
3129 * Mark end of version tag, and find previous ' ' (space) or
3130 * string length (recent FCODE images -- major hack ahead!!!).
3134 while ((iter > istart) && !do_next) {
3136 rbyte = qla2x00_read_flash_byte(ha, iter);
3137 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
3143 /* Mark beginning of version tag, and copy data. */
3145 if ((vend - iter) &&
3146 ((vend - iter) < sizeof(ha->fcode_revision))) {
3147 vbyte = ha->fcode_revision;
3148 while (iter <= vend) {
3149 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
3156 if (ret != QLA_SUCCESS)
3157 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3161 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3163 int ret = QLA_SUCCESS;
3164 uint8_t code_type, last_image;
3165 uint32_t pcihdr, pcids;
3168 struct qla_hw_data *ha = vha->hw;
3170 if (!ha->pio_address || !mbuf)
3171 return QLA_FUNCTION_FAILED;
3173 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3174 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3175 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3176 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3178 qla2x00_flash_enable(ha);
3180 /* Begin with first PCI expansion ROM header. */
3184 /* Verify PCI expansion ROM header. */
3185 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
3186 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
3188 ql_log(ql_log_fatal, vha, 0x0050,
3189 "No matching ROM signature.\n");
3190 ret = QLA_FUNCTION_FAILED;
3194 /* Locate PCI data structure. */
3196 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
3197 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
3199 /* Validate signature of PCI data structure. */
3200 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
3201 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
3202 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
3203 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
3204 /* Incorrect header. */
3205 ql_log(ql_log_fatal, vha, 0x0051,
3206 "PCI data struct not found pcir_adr=%x.\n", pcids);
3207 ret = QLA_FUNCTION_FAILED;
3212 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
3213 switch (code_type) {
3214 case ROM_CODE_TYPE_BIOS:
3215 /* Intel x86, PC-AT compatible. */
3216 ha->bios_revision[0] =
3217 qla2x00_read_flash_byte(ha, pcids + 0x12);
3218 ha->bios_revision[1] =
3219 qla2x00_read_flash_byte(ha, pcids + 0x13);
3220 ql_dbg(ql_dbg_init, vha, 0x0052,
3221 "Read BIOS %d.%d.\n",
3222 ha->bios_revision[1], ha->bios_revision[0]);
3224 case ROM_CODE_TYPE_FCODE:
3225 /* Open Firmware standard for PCI (FCode). */
3227 qla2x00_get_fcode_version(ha, pcids);
3229 case ROM_CODE_TYPE_EFI:
3230 /* Extensible Firmware Interface (EFI). */
3231 ha->efi_revision[0] =
3232 qla2x00_read_flash_byte(ha, pcids + 0x12);
3233 ha->efi_revision[1] =
3234 qla2x00_read_flash_byte(ha, pcids + 0x13);
3235 ql_dbg(ql_dbg_init, vha, 0x0053,
3236 "Read EFI %d.%d.\n",
3237 ha->efi_revision[1], ha->efi_revision[0]);
3240 ql_log(ql_log_warn, vha, 0x0054,
3241 "Unrecognized code type %x at pcids %x.\n",
3246 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
3248 /* Locate next PCI expansion ROM. */
3249 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
3250 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
3251 } while (!last_image);
3253 if (IS_QLA2322(ha)) {
3254 /* Read firmware image information. */
3255 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3257 memset(dbyte, 0, 8);
3258 dcode = (uint16_t *)dbyte;
3260 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
3262 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
3264 "ver from flash:.\n");
3265 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
3268 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
3269 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
3270 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3272 ql_log(ql_log_warn, vha, 0x0057,
3273 "Unrecognized fw revision at %x.\n",
3274 ha->flt_region_fw * 4);
3276 /* values are in big endian */
3277 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
3278 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
3279 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
3280 ql_dbg(ql_dbg_init, vha, 0x0058,
3282 "%d.%d.%d.\n", ha->fw_revision[0],
3283 ha->fw_revision[1], ha->fw_revision[2]);
3287 qla2x00_flash_disable(ha);
3293 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3295 int ret = QLA_SUCCESS;
3296 uint32_t pcihdr, pcids;
3297 uint32_t *dcode = mbuf;
3298 uint8_t *bcode = mbuf;
3299 uint8_t code_type, last_image;
3300 struct qla_hw_data *ha = vha->hw;
3303 return QLA_FUNCTION_FAILED;
3305 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3306 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3307 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3308 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3310 /* Begin with first PCI expansion ROM header. */
3311 pcihdr = ha->flt_region_boot << 2;
3314 /* Verify PCI expansion ROM header. */
3315 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4);
3316 bcode = mbuf + (pcihdr % 4);
3317 if (memcmp(bcode, "\x55\xaa", 2)) {
3319 ql_log(ql_log_fatal, vha, 0x0154,
3320 "No matching ROM signature.\n");
3321 ret = QLA_FUNCTION_FAILED;
3325 /* Locate PCI data structure. */
3326 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3328 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4);
3329 bcode = mbuf + (pcihdr % 4);
3331 /* Validate signature of PCI data structure. */
3332 if (memcmp(bcode, "PCIR", 4)) {
3333 /* Incorrect header. */
3334 ql_log(ql_log_fatal, vha, 0x0155,
3335 "PCI data struct not found pcir_adr=%x.\n", pcids);
3336 ret = QLA_FUNCTION_FAILED;
3341 code_type = bcode[0x14];
3342 switch (code_type) {
3343 case ROM_CODE_TYPE_BIOS:
3344 /* Intel x86, PC-AT compatible. */
3345 ha->bios_revision[0] = bcode[0x12];
3346 ha->bios_revision[1] = bcode[0x13];
3347 ql_dbg(ql_dbg_init, vha, 0x0156,
3348 "Read BIOS %d.%d.\n",
3349 ha->bios_revision[1], ha->bios_revision[0]);
3351 case ROM_CODE_TYPE_FCODE:
3352 /* Open Firmware standard for PCI (FCode). */
3353 ha->fcode_revision[0] = bcode[0x12];
3354 ha->fcode_revision[1] = bcode[0x13];
3355 ql_dbg(ql_dbg_init, vha, 0x0157,
3356 "Read FCODE %d.%d.\n",
3357 ha->fcode_revision[1], ha->fcode_revision[0]);
3359 case ROM_CODE_TYPE_EFI:
3360 /* Extensible Firmware Interface (EFI). */
3361 ha->efi_revision[0] = bcode[0x12];
3362 ha->efi_revision[1] = bcode[0x13];
3363 ql_dbg(ql_dbg_init, vha, 0x0158,
3364 "Read EFI %d.%d.\n",
3365 ha->efi_revision[1], ha->efi_revision[0]);
3368 ql_log(ql_log_warn, vha, 0x0159,
3369 "Unrecognized code type %x at pcids %x.\n",
3374 last_image = bcode[0x15] & BIT_7;
3376 /* Locate next PCI expansion ROM. */
3377 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3378 } while (!last_image);
3380 /* Read firmware image information. */
3381 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3383 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20);
3384 bcode = mbuf + (pcihdr % 4);
3386 /* Validate signature of PCI data structure. */
3387 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 &&
3388 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) {
3389 ha->fw_revision[0] = bcode[0x4];
3390 ha->fw_revision[1] = bcode[0x5];
3391 ha->fw_revision[2] = bcode[0x6];
3392 ql_dbg(ql_dbg_init, vha, 0x0153,
3393 "Firmware revision %d.%d.%d\n",
3394 ha->fw_revision[0], ha->fw_revision[1],
3395 ha->fw_revision[2]);
3402 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3404 int ret = QLA_SUCCESS;
3405 uint32_t pcihdr = 0, pcids = 0;
3406 uint32_t *dcode = mbuf;
3407 uint8_t *bcode = mbuf;
3408 uint8_t code_type, last_image;
3410 struct qla_hw_data *ha = vha->hw;
3412 struct active_regions active_regions = { };
3414 if (IS_P3P_TYPE(ha))
3418 return QLA_FUNCTION_FAILED;
3420 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3421 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3422 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3423 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3425 pcihdr = ha->flt_region_boot << 2;
3426 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3427 qla27xx_get_active_image(vha, &active_regions);
3428 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) {
3429 pcihdr = ha->flt_region_boot_sec << 2;
3434 /* Verify PCI expansion ROM header. */
3435 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
3436 bcode = mbuf + (pcihdr % 4);
3437 if (memcmp(bcode, "\x55\xaa", 2)) {
3439 ql_log(ql_log_fatal, vha, 0x0059,
3440 "No matching ROM signature.\n");
3441 ret = QLA_FUNCTION_FAILED;
3445 /* Locate PCI data structure. */
3446 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3448 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
3449 bcode = mbuf + (pcihdr % 4);
3451 /* Validate signature of PCI data structure. */
3452 if (memcmp(bcode, "PCIR", 4)) {
3453 /* Incorrect header. */
3454 ql_log(ql_log_fatal, vha, 0x005a,
3455 "PCI data struct not found pcir_adr=%x.\n", pcids);
3456 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32);
3457 ret = QLA_FUNCTION_FAILED;
3462 code_type = bcode[0x14];
3463 switch (code_type) {
3464 case ROM_CODE_TYPE_BIOS:
3465 /* Intel x86, PC-AT compatible. */
3466 ha->bios_revision[0] = bcode[0x12];
3467 ha->bios_revision[1] = bcode[0x13];
3468 ql_dbg(ql_dbg_init, vha, 0x005b,
3469 "Read BIOS %d.%d.\n",
3470 ha->bios_revision[1], ha->bios_revision[0]);
3472 case ROM_CODE_TYPE_FCODE:
3473 /* Open Firmware standard for PCI (FCode). */
3474 ha->fcode_revision[0] = bcode[0x12];
3475 ha->fcode_revision[1] = bcode[0x13];
3476 ql_dbg(ql_dbg_init, vha, 0x005c,
3477 "Read FCODE %d.%d.\n",
3478 ha->fcode_revision[1], ha->fcode_revision[0]);
3480 case ROM_CODE_TYPE_EFI:
3481 /* Extensible Firmware Interface (EFI). */
3482 ha->efi_revision[0] = bcode[0x12];
3483 ha->efi_revision[1] = bcode[0x13];
3484 ql_dbg(ql_dbg_init, vha, 0x005d,
3485 "Read EFI %d.%d.\n",
3486 ha->efi_revision[1], ha->efi_revision[0]);
3489 ql_log(ql_log_warn, vha, 0x005e,
3490 "Unrecognized code type %x at pcids %x.\n",
3495 last_image = bcode[0x15] & BIT_7;
3497 /* Locate next PCI expansion ROM. */
3498 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3499 } while (!last_image);
3501 /* Read firmware image information. */
3502 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3503 faddr = ha->flt_region_fw;
3504 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3505 qla27xx_get_active_image(vha, &active_regions);
3506 if (active_regions.global == QLA27XX_SECONDARY_IMAGE)
3507 faddr = ha->flt_region_fw_sec;
3510 qla24xx_read_flash_data(vha, dcode, faddr, 8);
3511 if (qla24xx_risc_firmware_invalid(dcode)) {
3512 ql_log(ql_log_warn, vha, 0x005f,
3513 "Unrecognized fw revision at %x.\n",
3514 ha->flt_region_fw * 4);
3515 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32);
3517 for (i = 0; i < 4; i++)
3518 ha->fw_revision[i] =
3519 be32_to_cpu((__force __be32)dcode[4+i]);
3520 ql_dbg(ql_dbg_init, vha, 0x0060,
3521 "Firmware revision (flash) %u.%u.%u (%x).\n",
3522 ha->fw_revision[0], ha->fw_revision[1],
3523 ha->fw_revision[2], ha->fw_revision[3]);
3526 /* Check for golden firmware and get version if available */
3527 if (!IS_QLA81XX(ha)) {
3528 /* Golden firmware is not present in non 81XX adapters */
3532 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3533 faddr = ha->flt_region_gold_fw;
3534 qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8);
3535 if (qla24xx_risc_firmware_invalid(dcode)) {
3536 ql_log(ql_log_warn, vha, 0x0056,
3537 "Unrecognized golden fw at %#x.\n", faddr);
3538 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32);
3542 for (i = 0; i < 4; i++)
3543 ha->gold_fw_version[i] =
3544 be32_to_cpu((__force __be32)dcode[4+i]);
3550 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
3552 if (pos >= end || *pos != 0x82)
3556 if (pos >= end || *pos != 0x90)
3560 if (pos >= end || *pos != 0x78)
3567 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
3569 struct qla_hw_data *ha = vha->hw;
3570 uint8_t *pos = ha->vpd;
3571 uint8_t *end = pos + ha->vpd_size;
3574 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
3577 while (pos < end && *pos != 0x78) {
3578 len = (*pos == 0x82) ? pos[1] : pos[2];
3580 if (!strncmp(pos, key, strlen(key)))
3583 if (*pos != 0x90 && *pos != 0x91)
3589 if (pos < end - len && *pos != 0x78)
3590 return scnprintf(str, size, "%.*s", len, pos + 3);
3596 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3599 uint32_t fcp_prio_addr;
3600 struct qla_hw_data *ha = vha->hw;
3602 if (!ha->fcp_prio_cfg) {
3603 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3604 if (!ha->fcp_prio_cfg) {
3605 ql_log(ql_log_warn, vha, 0x00d5,
3606 "Unable to allocate memory for fcp priority data (%x).\n",
3608 return QLA_FUNCTION_FAILED;
3611 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3613 fcp_prio_addr = ha->flt_region_fcp_prio;
3615 /* first read the fcp priority data header from flash */
3616 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg,
3617 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3619 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3622 /* read remaining FCP CMD config data from flash */
3623 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3624 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry);
3625 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3627 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0],
3628 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3630 /* revalidate the entire FCP priority config data, including entries */
3631 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3634 ha->flags.fcp_prio_enabled = 1;
3637 vfree(ha->fcp_prio_cfg);
3638 ha->fcp_prio_cfg = NULL;
3639 return QLA_FUNCTION_FAILED;