1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Marvell Fibre Channel HBA Driver
4 * Copyright (c) 2021 Marvell
10 #define EDIF_APP_ID 0x73730001
12 #define EDIF_MAX_INDEX 2048
14 struct list_head next;
19 #define EDIF_SA_CTL_FLG_REPL BIT_0
20 #define EDIF_SA_CTL_FLG_DEL BIT_1
21 #define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4
22 // Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE
24 #define EDIF_SA_CTL_USED 1 /* Active Sa update */
25 #define EDIF_SA_CTL_PEND 2 /* Waiting for slot */
26 #define EDIF_SA_CTL_REPL 3 /* Active Replace and Delete */
27 #define EDIF_SA_CTL_DEL 4 /* Delete Pending */
28 struct fc_port *fcport;
29 struct bsg_job *bsg_job;
30 struct qla_sa_update_frame sa_frame;
38 enum enode_flags_t enode_flags;
40 struct list_head head;
47 #define DBELL_ACTIVE(_v) (_v->e_dbell.db_flags & EDB_ACTIVE)
48 #define DBELL_INACTIVE(_v) (!(_v->e_dbell.db_flags & EDB_ACTIVE))
51 enum db_flags_t db_flags;
53 struct list_head head;
54 struct completion dbell;
57 #define SA_UPDATE_IOCB_TYPE 0x71 /* Security Association Update IOCB entry */
58 struct sa_update_28xx {
59 uint8_t entry_type; /* Entry type. */
60 uint8_t entry_count; /* Entry count. */
61 uint8_t sys_define; /* System Defined. */
62 uint8_t entry_status; /* Entry Status. */
64 uint32_t handle; /* IOCB System handle. */
67 __le16 nport_handle; /* in: N_PORT handle. */
68 __le16 comp_sts; /* out: completion status */
69 #define CS_PORT_EDIF_UNAVAIL 0x28
70 #define CS_PORT_EDIF_LOGOUT 0x29
71 #define CS_PORT_EDIF_SUPP_NOT_RDY 0x64
72 #define CS_PORT_EDIF_INV_REQ 0x66
78 #define SA_FLAG_INVALIDATE BIT_0
79 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
81 uint8_t sa_key[32]; /* 256 bit key */
85 #define SA_CNTL_ENC_FCSP (1 << 3)
86 #define SA_CNTL_ENC_OPD (2 << 3)
87 #define SA_CNTL_ENC_MSK (3 << 3) // mask bits 4,3
88 #define SA_CNTL_AES_GMAC (1 << 2)
89 #define SA_CNTL_KEY256 (2 << 0)
90 #define SA_CNTL_KEY128 0
93 __le16 sa_index; // reserve: bit 11-15
98 #define NUM_ENTRIES 256
110 short pur_bytes_rcvd;
111 unsigned short pur_nphdl;
112 unsigned int pur_rx_xchg_address;
116 struct pur_ninfo pur_info;
124 struct list_head list;
128 struct purexevent purexinfo;
132 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
134 #define EDIF_SESSION_DOWN(_s) \
135 (qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
136 _s->disc_state == DSC_DELETED || \
137 !_s->edif.app_sess_online))
139 #define EDIF_NEGOTIATION_PENDING(_fcport) \
140 (DBELL_ACTIVE(_fcport->vha) && \
141 (_fcport->disc_state == DSC_LOGIN_AUTH_PEND))
143 #endif /* __QLA_EDIF_H */