2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
28 #include <linux/btree.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport_fc.h>
35 #include <scsi/scsi_bsg_fc.h>
41 #define QLA2XXX_DRIVER_NAME "qla2xxx"
42 #define QLA2XXX_APIDEV "ql2xapidev"
43 #define QLA2XXX_MANUFACTURER "QLogic Corporation"
46 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
47 * but that's fine as we don't look at the last 24 ones for
50 #define MAILBOX_REGISTER_COUNT_2100 8
51 #define MAILBOX_REGISTER_COUNT_2200 24
52 #define MAILBOX_REGISTER_COUNT 32
54 #define QLA2200A_RISC_ROM_VER 4
58 #include "qla_settings.h"
60 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
63 * Data bit definitions
81 #define BIT_16 0x10000
82 #define BIT_17 0x20000
83 #define BIT_18 0x40000
84 #define BIT_19 0x80000
85 #define BIT_20 0x100000
86 #define BIT_21 0x200000
87 #define BIT_22 0x400000
88 #define BIT_23 0x800000
89 #define BIT_24 0x1000000
90 #define BIT_25 0x2000000
91 #define BIT_26 0x4000000
92 #define BIT_27 0x8000000
93 #define BIT_28 0x10000000
94 #define BIT_29 0x20000000
95 #define BIT_30 0x40000000
96 #define BIT_31 0x80000000
98 #define LSB(x) ((uint8_t)(x))
99 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
101 #define LSW(x) ((uint16_t)(x))
102 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
104 #define LSD(x) ((uint32_t)((uint64_t)(x)))
105 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
107 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
113 #define RD_REG_BYTE(addr) readb(addr)
114 #define RD_REG_WORD(addr) readw(addr)
115 #define RD_REG_DWORD(addr) readl(addr)
116 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
117 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
118 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
119 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
120 #define WRT_REG_WORD(addr, data) writew(data,addr)
121 #define WRT_REG_DWORD(addr, data) writel(data,addr)
124 * ISP83XX specific remote register addresses
126 #define QLA83XX_LED_PORT0 0x00201320
127 #define QLA83XX_LED_PORT1 0x00201328
128 #define QLA83XX_IDC_DEV_STATE 0x22102384
129 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
130 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
131 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
132 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
133 #define QLA83XX_IDC_CONTROL 0x22102390
134 #define QLA83XX_IDC_AUDIT 0x22102394
135 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
136 #define QLA83XX_DRIVER_LOCKID 0x22102104
137 #define QLA83XX_DRIVER_LOCK 0x8111c028
138 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
139 #define QLA83XX_FLASH_LOCKID 0x22102100
140 #define QLA83XX_FLASH_LOCK 0x8111c010
141 #define QLA83XX_FLASH_UNLOCK 0x8111c014
142 #define QLA83XX_DEV_PARTINFO1 0x221023e0
143 #define QLA83XX_DEV_PARTINFO2 0x221023e4
144 #define QLA83XX_FW_HEARTBEAT 0x221020b0
145 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
146 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
148 /* 83XX: Macros defining 8200 AEN Reason codes */
149 #define IDC_DEVICE_STATE_CHANGE BIT_0
150 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
151 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
152 #define IDC_HEARTBEAT_FAILURE BIT_3
154 /* 83XX: Macros defining 8200 AEN Error-levels */
155 #define ERR_LEVEL_NON_FATAL 0x1
156 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
157 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
159 /* 83XX: Macros for IDC Version */
160 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
161 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
163 /* 83XX: Macros for scheduling dpc tasks */
164 #define QLA83XX_NIC_CORE_RESET 0x1
165 #define QLA83XX_IDC_STATE_HANDLER 0x2
166 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
168 /* 83XX: Macros for defining IDC-Control bits */
169 #define QLA83XX_IDC_RESET_DISABLED BIT_0
170 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
172 /* 83XX: Macros for different timeouts */
173 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
174 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
175 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
177 /* 83XX: Macros for defining class in DEV-Partition Info register */
178 #define QLA83XX_CLASS_TYPE_NONE 0x0
179 #define QLA83XX_CLASS_TYPE_NIC 0x1
180 #define QLA83XX_CLASS_TYPE_FCOE 0x2
181 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
183 /* 83XX: Macros for IDC Lock-Recovery stages */
184 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
187 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
189 /* 83XX: Macros for IDC Audit type */
190 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
191 * dev-state change to NEED-RESET
194 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
195 * reset-recovery completion is
198 /* ISP2031: Values for laser on/off */
199 #define PORT_0_2031 0x00201340
200 #define PORT_1_2031 0x00201350
201 #define LASER_ON_2031 0x01800100
202 #define LASER_OFF_2031 0x01800180
205 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
208 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
209 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
212 * Fibre Channel device definitions.
214 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
215 #define MAX_FIBRE_DEVICES_2100 512
216 #define MAX_FIBRE_DEVICES_2400 2048
217 #define MAX_FIBRE_DEVICES_LOOP 128
218 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
219 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
220 #define MAX_FIBRE_LUNS 0xFFFF
221 #define MAX_HOST_COUNT 16
224 * Host adapter default definitions.
226 #define MAX_BUSES 1 /* We only have one bus today */
228 #define MAX_LUNS MAX_FIBRE_LUNS
229 #define MAX_CMDS_PER_LUN 255
232 * Fibre Channel device definitions.
234 #define SNS_LAST_LOOP_ID_2100 0xfe
235 #define SNS_LAST_LOOP_ID_2300 0x7ff
237 #define LAST_LOCAL_LOOP_ID 0x7d
238 #define SNS_FL_PORT 0x7e
239 #define FABRIC_CONTROLLER 0x7f
240 #define SIMPLE_NAME_SERVER 0x80
241 #define SNS_FIRST_LOOP_ID 0x81
242 #define MANAGEMENT_SERVER 0xfe
243 #define BROADCAST 0xff
246 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
247 * valid range of an N-PORT id is 0 through 0x7ef.
249 #define NPH_LAST_HANDLE 0x7ef
250 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
251 #define NPH_SNS 0x7fc /* FFFFFC */
252 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
253 #define NPH_F_PORT 0x7fe /* FFFFFE */
254 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
256 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
258 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
261 struct name_list_extended {
262 struct get_name_list_extended *l;
264 struct list_head fcports; /* protect by sess_list */
269 * Timeout timer counts in seconds
271 #define PORT_RETRY_TIME 1
272 #define LOOP_DOWN_TIMEOUT 60
273 #define LOOP_DOWN_TIME 255 /* 240 */
274 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
276 #define DEFAULT_OUTSTANDING_COMMANDS 4096
277 #define MIN_OUTSTANDING_COMMANDS 128
279 /* ISP request and response entry counts (37-65535) */
280 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
281 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
282 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
283 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
284 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
285 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
286 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
287 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
288 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
289 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
290 #define FW_DEF_EXCHANGES_CNT 2048
299 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
300 uint32_t request_sense_length;
301 uint32_t fw_sense_length;
302 uint8_t *request_sense_ptr;
307 * SRB flag definitions
309 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
310 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
311 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
312 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
313 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
315 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
316 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
319 * 24 bit port ID type definition.
329 #elif defined(__LITTLE_ENDIAN)
334 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
339 #define INVALID_PORT_ID 0xFFFFFF
341 struct els_logo_payload {
346 uint8_t wwpn[WWN_SIZE];
368 #define SRB_LOGIN_RETRIED BIT_0
369 #define SRB_LOGIN_COND_PLOGI BIT_1
370 #define SRB_LOGIN_SKIP_PRLI BIT_2
371 #define SRB_LOGIN_NVME_PRLI BIT_3
376 #define ELS_DCMD_TIMEOUT 20
377 #define ELS_DCMD_LOGO 0x5
380 struct completion comp;
381 struct els_logo_payload *els_logo_pyld;
382 dma_addr_t els_logo_pyld_dma;
386 * Values for flags field below are as
387 * defined in tsk_mgmt_entry struct
388 * for control_flags field in qla_fw.h.
393 struct completion comp;
397 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
398 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
399 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
400 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
401 #define FXDISC_TIMEOUT 20
407 dma_addr_t req_dma_handle;
408 dma_addr_t rsp_dma_handle;
410 __le32 adapter_id_hi;
411 __le16 req_func_type;
413 __le32 req_data_extra;
417 struct completion fxiocb_comp;
424 struct completion comp;
427 #define MAX_IOCB_MB_REG 28
428 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
430 __le16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
431 __le16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
433 dma_addr_t out_dma, in_dma;
434 struct completion comp;
438 struct imm_ntfy_from_isp *ntfy;
442 uint16_t rsp_pyld_len;
446 /* These are only used with ls4 requests */
451 enum nvmefc_fcp_datadir dir;
453 uint32_t timeout_sec;
454 struct list_head entry;
458 struct timer_list timer;
459 void (*timeout)(void *);
462 /* Values for srb_ctx type */
463 #define SRB_LOGIN_CMD 1
464 #define SRB_LOGOUT_CMD 2
465 #define SRB_ELS_CMD_RPT 3
466 #define SRB_ELS_CMD_HST 4
468 #define SRB_ADISC_CMD 6
470 #define SRB_SCSI_CMD 8
471 #define SRB_BIDI_CMD 9
472 #define SRB_FXIOCB_DCMD 10
473 #define SRB_FXIOCB_BCMD 11
474 #define SRB_ABT_CMD 12
475 #define SRB_ELS_DCMD 13
476 #define SRB_MB_IOCB 14
477 #define SRB_CT_PTHRU_CMD 15
478 #define SRB_NACK_PLOGI 16
479 #define SRB_NACK_PRLI 17
480 #define SRB_NACK_LOGO 18
481 #define SRB_NVME_CMD 19
482 #define SRB_NVME_LS 20
483 #define SRB_PRLI_CMD 21
492 * Do not move cmd_type field, it needs to
493 * line up with qla_tgt_cmd->cmd_type
498 wait_queue_head_t nvme_ls_waitq;
499 struct fc_port *fcport;
500 struct scsi_qla_host *vha;
506 struct qla_qpair *qpair;
507 struct list_head elem;
508 u32 gen1; /* scratch */
509 u32 gen2; /* scratch */
511 struct srb_iocb iocb_cmd;
512 struct bsg_job *bsg_job;
515 void (*done)(void *, int);
516 void (*free)(void *);
519 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
520 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd)
521 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx)
523 #define GET_CMD_SENSE_LEN(sp) \
524 (sp->u.scmd.request_sense_length)
525 #define SET_CMD_SENSE_LEN(sp, len) \
526 (sp->u.scmd.request_sense_length = len)
527 #define GET_CMD_SENSE_PTR(sp) \
528 (sp->u.scmd.request_sense_ptr)
529 #define SET_CMD_SENSE_PTR(sp, ptr) \
530 (sp->u.scmd.request_sense_ptr = ptr)
531 #define GET_FW_SENSE_LEN(sp) \
532 (sp->u.scmd.fw_sense_length)
533 #define SET_FW_SENSE_LEN(sp, len) \
534 (sp->u.scmd.fw_sense_length = len)
542 uint32_t transfer_size;
543 uint32_t iteration_count;
547 * ISP I/O Register Set structure definitions.
549 struct device_reg_2xxx {
550 uint16_t flash_address; /* Flash BIOS address */
551 uint16_t flash_data; /* Flash BIOS data */
552 uint16_t unused_1[1]; /* Gap */
553 uint16_t ctrl_status; /* Control/Status */
554 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
555 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
556 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
558 uint16_t ictrl; /* Interrupt control */
559 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
560 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
562 uint16_t istatus; /* Interrupt status */
563 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
565 uint16_t semaphore; /* Semaphore */
566 uint16_t nvram; /* NVRAM register. */
567 #define NVR_DESELECT 0
568 #define NVR_BUSY BIT_15
569 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
570 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
571 #define NVR_DATA_IN BIT_3
572 #define NVR_DATA_OUT BIT_2
573 #define NVR_SELECT BIT_1
574 #define NVR_CLOCK BIT_0
576 #define NVR_WAIT_CNT 20000
588 uint16_t unused_2[59]; /* Gap */
589 } __attribute__((packed)) isp2100;
592 uint16_t req_q_in; /* In-Pointer */
593 uint16_t req_q_out; /* Out-Pointer */
595 uint16_t rsp_q_in; /* In-Pointer */
596 uint16_t rsp_q_out; /* Out-Pointer */
598 /* RISC to Host Status */
599 uint32_t host_status;
600 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
601 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
603 /* Host to Host Semaphore */
604 uint16_t host_semaphore;
605 uint16_t unused_3[17]; /* Gap */
639 uint16_t unused_4[10]; /* Gap */
640 } __attribute__((packed)) isp2300;
643 uint16_t fpm_diag_config;
644 uint16_t unused_5[0x4]; /* Gap */
646 uint16_t unused_5_1; /* Gap */
647 uint16_t pcr; /* Processor Control Register. */
648 uint16_t unused_6[0x5]; /* Gap */
649 uint16_t mctr; /* Memory Configuration and Timing. */
650 uint16_t unused_7[0x3]; /* Gap */
651 uint16_t fb_cmd_2100; /* Unused on 23XX */
652 uint16_t unused_8[0x3]; /* Gap */
653 uint16_t hccr; /* Host command & control register. */
654 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
655 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
657 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
658 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
659 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
660 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
661 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
662 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
663 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
664 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
666 uint16_t unused_9[5]; /* Gap */
667 uint16_t gpiod; /* GPIO Data register. */
668 uint16_t gpioe; /* GPIO Enable register. */
669 #define GPIO_LED_MASK 0x00C0
670 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
671 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
672 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
673 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
674 #define GPIO_LED_ALL_OFF 0x0000
675 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
676 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
680 uint16_t unused_10[8]; /* Gap */
696 uint16_t mailbox23; /* Also probe reg. */
697 } __attribute__((packed)) isp2200;
701 struct device_reg_25xxmq {
711 struct device_reg_fx00 {
712 uint32_t mailbox0; /* 00 */
713 uint32_t mailbox1; /* 04 */
714 uint32_t mailbox2; /* 08 */
715 uint32_t mailbox3; /* 0C */
716 uint32_t mailbox4; /* 10 */
717 uint32_t mailbox5; /* 14 */
718 uint32_t mailbox6; /* 18 */
719 uint32_t mailbox7; /* 1C */
720 uint32_t mailbox8; /* 20 */
721 uint32_t mailbox9; /* 24 */
722 uint32_t mailbox10; /* 28 */
744 uint32_t aenmailbox0;
745 uint32_t aenmailbox1;
746 uint32_t aenmailbox2;
747 uint32_t aenmailbox3;
748 uint32_t aenmailbox4;
749 uint32_t aenmailbox5;
750 uint32_t aenmailbox6;
751 uint32_t aenmailbox7;
753 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */
754 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */
755 /* Response Queue. */
756 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */
757 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */
758 /* Init values shadowed on FW Up Event */
759 uint32_t initval0; /* B0 */
760 uint32_t initval1; /* B4 */
761 uint32_t initval2; /* B8 */
762 uint32_t initval3; /* BC */
763 uint32_t initval4; /* C0 */
764 uint32_t initval5; /* C4 */
765 uint32_t initval6; /* C8 */
766 uint32_t initval7; /* CC */
767 uint32_t fwheartbeat; /* D0 */
768 uint32_t pseudoaen; /* D4 */
774 struct device_reg_2xxx isp;
775 struct device_reg_24xx isp24;
776 struct device_reg_25xxmq isp25mq;
777 struct device_reg_82xx isp82;
778 struct device_reg_fx00 ispfx00;
779 } __iomem device_reg_t;
781 #define ISP_REQ_Q_IN(ha, reg) \
782 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
783 &(reg)->u.isp2100.mailbox4 : \
784 &(reg)->u.isp2300.req_q_in)
785 #define ISP_REQ_Q_OUT(ha, reg) \
786 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
787 &(reg)->u.isp2100.mailbox4 : \
788 &(reg)->u.isp2300.req_q_out)
789 #define ISP_RSP_Q_IN(ha, reg) \
790 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
791 &(reg)->u.isp2100.mailbox5 : \
792 &(reg)->u.isp2300.rsp_q_in)
793 #define ISP_RSP_Q_OUT(ha, reg) \
794 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
795 &(reg)->u.isp2100.mailbox5 : \
796 &(reg)->u.isp2300.rsp_q_out)
798 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
799 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
801 #define MAILBOX_REG(ha, reg, num) \
802 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
804 &(reg)->u.isp2100.mailbox0 + (num) : \
805 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
806 &(reg)->u.isp2300.mailbox0 + (num))
807 #define RD_MAILBOX_REG(ha, reg, num) \
808 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
809 #define WRT_MAILBOX_REG(ha, reg, num, data) \
810 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
812 #define FB_CMD_REG(ha, reg) \
813 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
814 &(reg)->fb_cmd_2100 : \
815 &(reg)->u.isp2300.fb_cmd)
816 #define RD_FB_CMD_REG(ha, reg) \
817 RD_REG_WORD(FB_CMD_REG(ha, reg))
818 #define WRT_FB_CMD_REG(ha, reg, data) \
819 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
822 uint32_t out_mb; /* outbound from driver */
823 uint32_t in_mb; /* Incoming from RISC */
824 uint16_t mb[MAILBOX_REGISTER_COUNT];
829 #define MBX_DMA_IN BIT_0
830 #define MBX_DMA_OUT BIT_1
831 #define IOCTL_CMD BIT_2
835 uint32_t out_mb; /* outbound from driver */
836 uint32_t in_mb; /* Incoming from RISC */
837 uint32_t mb[MAILBOX_REGISTER_COUNT];
842 #define MBX_DMA_IN BIT_0
843 #define MBX_DMA_OUT BIT_1
844 #define IOCTL_CMD BIT_2
848 #define MBX_TOV_SECONDS 30
851 * ISP product identification definitions in mailboxes after reset.
853 #define PROD_ID_1 0x4953
854 #define PROD_ID_2 0x0000
855 #define PROD_ID_2a 0x5020
856 #define PROD_ID_3 0x2020
859 * ISP mailbox Self-Test status codes
861 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
862 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
863 #define MBS_BUSY 4 /* Busy. */
866 * ISP mailbox command complete status codes
868 #define MBS_COMMAND_COMPLETE 0x4000
869 #define MBS_INVALID_COMMAND 0x4001
870 #define MBS_HOST_INTERFACE_ERROR 0x4002
871 #define MBS_TEST_FAILED 0x4003
872 #define MBS_COMMAND_ERROR 0x4005
873 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
874 #define MBS_PORT_ID_USED 0x4007
875 #define MBS_LOOP_ID_USED 0x4008
876 #define MBS_ALL_IDS_IN_USE 0x4009
877 #define MBS_NOT_LOGGED_IN 0x400A
878 #define MBS_LINK_DOWN_ERROR 0x400B
879 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
882 * ISP mailbox asynchronous event status codes
884 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
885 #define MBA_RESET 0x8001 /* Reset Detected. */
886 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
887 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
888 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
889 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
890 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
892 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
893 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
894 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
895 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
896 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
897 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
898 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
899 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
900 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
901 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
902 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
903 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
904 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
905 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
906 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
907 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
909 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
910 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
911 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
912 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
913 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
914 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
915 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
916 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
917 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
918 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
919 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
920 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
921 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
922 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
923 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
924 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
925 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
926 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
927 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
928 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
929 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
930 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
931 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
932 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
934 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
935 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
936 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
937 /* 83XX FCoE specific */
938 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
940 /* Interrupt type codes */
941 #define INTR_ROM_MB_SUCCESS 0x1
942 #define INTR_ROM_MB_FAILED 0x2
943 #define INTR_MB_SUCCESS 0x10
944 #define INTR_MB_FAILED 0x11
945 #define INTR_ASYNC_EVENT 0x12
946 #define INTR_RSP_QUE_UPDATE 0x13
947 #define INTR_RSP_QUE_UPDATE_83XX 0x14
948 #define INTR_ATIO_QUE_UPDATE 0x1C
949 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
951 /* ISP mailbox loopback echo diagnostic error code */
952 #define MBS_LB_RESET 0x17
954 * Firmware options 1, 2, 3.
956 #define FO1_AE_ON_LIPF8 BIT_0
957 #define FO1_AE_ALL_LIP_RESET BIT_1
958 #define FO1_CTIO_RETRY BIT_3
959 #define FO1_DISABLE_LIP_F7_SW BIT_4
960 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
961 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
962 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
963 #define FO1_SET_EMPHASIS_SWING BIT_8
964 #define FO1_AE_AUTO_BYPASS BIT_9
965 #define FO1_ENABLE_PURE_IOCB BIT_10
966 #define FO1_AE_PLOGI_RJT BIT_11
967 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
968 #define FO1_AE_QUEUE_FULL BIT_13
970 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
971 #define FO2_REV_LOOPBACK BIT_1
973 #define FO3_ENABLE_EMERG_IOCB BIT_0
974 #define FO3_AE_RND_ERROR BIT_1
976 /* 24XX additional firmware options */
977 #define ADD_FO_COUNT 3
978 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
979 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
981 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
983 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
986 * ISP mailbox commands
988 #define MBC_LOAD_RAM 1 /* Load RAM. */
989 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
990 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
991 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
992 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
993 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
994 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
995 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
996 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
997 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
998 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
999 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1000 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1001 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1002 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1003 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1004 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1005 #define MBC_RESET 0x18 /* Reset. */
1006 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1007 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1008 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1009 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1010 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1011 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1012 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1013 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1014 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1015 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1016 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1017 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1018 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1019 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1020 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1021 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1022 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1023 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1024 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1025 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1026 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1027 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1028 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1029 #define MBC_DATA_RATE 0x5d /* Data Rate */
1030 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1031 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1032 /* Initialization Procedure */
1033 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1034 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1035 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1036 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1037 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1038 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1039 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1040 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1041 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1042 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1043 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1045 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1046 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1047 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1048 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1049 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1050 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1051 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1052 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1053 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1054 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1055 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1058 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1059 * should be defined with MBC_MR_*
1061 #define MBC_MR_DRV_SHUTDOWN 0x6A
1064 * ISP24xx mailbox commands
1066 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1067 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1068 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1069 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1070 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1071 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1072 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1073 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1074 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1075 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1076 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1077 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1078 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1079 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1080 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1081 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1082 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1083 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1084 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1085 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1086 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1087 #define MBC_PORT_RESET 0x120 /* Port Reset */
1088 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1089 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1092 * ISP81xx mailbox commands
1094 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1097 * ISP8044 mailbox commands
1099 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1100 #define HCS_WRITE_SERDES 0x3
1101 #define HCS_READ_SERDES 0x4
1103 /* Firmware return data sizes */
1104 #define FCAL_MAP_SIZE 128
1106 /* Mailbox bit definitions for out_mb and in_mb */
1107 #define MBX_31 BIT_31
1108 #define MBX_30 BIT_30
1109 #define MBX_29 BIT_29
1110 #define MBX_28 BIT_28
1111 #define MBX_27 BIT_27
1112 #define MBX_26 BIT_26
1113 #define MBX_25 BIT_25
1114 #define MBX_24 BIT_24
1115 #define MBX_23 BIT_23
1116 #define MBX_22 BIT_22
1117 #define MBX_21 BIT_21
1118 #define MBX_20 BIT_20
1119 #define MBX_19 BIT_19
1120 #define MBX_18 BIT_18
1121 #define MBX_17 BIT_17
1122 #define MBX_16 BIT_16
1123 #define MBX_15 BIT_15
1124 #define MBX_14 BIT_14
1125 #define MBX_13 BIT_13
1126 #define MBX_12 BIT_12
1127 #define MBX_11 BIT_11
1128 #define MBX_10 BIT_10
1140 #define RNID_TYPE_PORT_LOGIN 0x7
1141 #define RNID_TYPE_SET_VERSION 0x9
1142 #define RNID_TYPE_ASIC_TEMP 0xC
1145 * Firmware state codes from get firmware state mailbox command
1147 #define FSTATE_CONFIG_WAIT 0
1148 #define FSTATE_WAIT_AL_PA 1
1149 #define FSTATE_WAIT_LOGIN 2
1150 #define FSTATE_READY 3
1151 #define FSTATE_LOSS_OF_SYNC 4
1152 #define FSTATE_ERROR 5
1153 #define FSTATE_REINIT 6
1154 #define FSTATE_NON_PART 7
1156 #define FSTATE_CONFIG_CORRECT 0
1157 #define FSTATE_P2P_RCV_LIP 1
1158 #define FSTATE_P2P_CHOOSE_LOOP 2
1159 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1160 #define FSTATE_FATAL_ERROR 4
1161 #define FSTATE_LOOP_BACK_CONN 5
1163 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1164 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1165 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1166 #define QLA27XX_PRIMARY_IMAGE 1
1167 #define QLA27XX_SECONDARY_IMAGE 2
1170 * Port Database structure definition
1171 * Little endian except where noted.
1173 #define PORT_DATABASE_SIZE 128 /* bytes */
1177 uint8_t master_state;
1178 uint8_t slave_state;
1179 uint8_t reserved[2];
1180 uint8_t hard_address;
1183 uint8_t node_name[WWN_SIZE];
1184 uint8_t port_name[WWN_SIZE];
1185 uint16_t execution_throttle;
1186 uint16_t execution_count;
1187 uint8_t reset_count;
1189 uint16_t resource_allocation;
1190 uint16_t current_allocation;
1191 uint16_t queue_head;
1192 uint16_t queue_tail;
1193 uint16_t transmit_execution_list_next;
1194 uint16_t transmit_execution_list_previous;
1195 uint16_t common_features;
1196 uint16_t total_concurrent_sequences;
1197 uint16_t RO_by_information_category;
1200 uint16_t receive_data_size;
1201 uint16_t concurrent_sequences;
1202 uint16_t open_sequences_per_exchange;
1203 uint16_t lun_abort_flags;
1204 uint16_t lun_stop_flags;
1205 uint16_t stop_queue_head;
1206 uint16_t stop_queue_tail;
1207 uint16_t port_retry_timer;
1208 uint16_t next_sequence_id;
1209 uint16_t frame_count;
1210 uint16_t PRLI_payload_length;
1211 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1212 /* Bits 15-0 of word 0 */
1213 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1214 /* Bits 15-0 of word 3 */
1216 uint16_t extended_lun_info_list_pointer;
1217 uint16_t extended_lun_stop_list_pointer;
1221 * Port database slave/master states
1223 #define PD_STATE_DISCOVERY 0
1224 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1225 #define PD_STATE_PORT_LOGIN 2
1226 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1227 #define PD_STATE_PROCESS_LOGIN 4
1228 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1229 #define PD_STATE_PORT_LOGGED_IN 6
1230 #define PD_STATE_PORT_UNAVAILABLE 7
1231 #define PD_STATE_PROCESS_LOGOUT 8
1232 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1233 #define PD_STATE_PORT_LOGOUT 10
1234 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1237 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1238 #define QLA_ZIO_DISABLED 0
1239 #define QLA_ZIO_DEFAULT_TIMER 2
1242 * ISP Initialization Control Block.
1243 * Little endian except where noted.
1245 #define ICB_VERSION 1
1251 * LSB BIT 0 = Enable Hard Loop Id
1252 * LSB BIT 1 = Enable Fairness
1253 * LSB BIT 2 = Enable Full-Duplex
1254 * LSB BIT 3 = Enable Fast Posting
1255 * LSB BIT 4 = Enable Target Mode
1256 * LSB BIT 5 = Disable Initiator Mode
1257 * LSB BIT 6 = Enable ADISC
1258 * LSB BIT 7 = Enable Target Inquiry Data
1260 * MSB BIT 0 = Enable PDBC Notify
1261 * MSB BIT 1 = Non Participating LIP
1262 * MSB BIT 2 = Descending Loop ID Search
1263 * MSB BIT 3 = Acquire Loop ID in LIPA
1264 * MSB BIT 4 = Stop PortQ on Full Status
1265 * MSB BIT 5 = Full Login after LIP
1266 * MSB BIT 6 = Node Name Option
1267 * MSB BIT 7 = Ext IFWCB enable bit
1269 uint8_t firmware_options[2];
1271 uint16_t frame_payload_size;
1272 uint16_t max_iocb_allocation;
1273 uint16_t execution_throttle;
1274 uint8_t retry_count;
1275 uint8_t retry_delay; /* unused */
1276 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1277 uint16_t hard_address;
1278 uint8_t inquiry_data;
1279 uint8_t login_timeout;
1280 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1282 uint16_t request_q_outpointer;
1283 uint16_t response_q_inpointer;
1284 uint16_t request_q_length;
1285 uint16_t response_q_length;
1286 uint32_t request_q_address[2];
1287 uint32_t response_q_address[2];
1289 uint16_t lun_enables;
1290 uint8_t command_resource_count;
1291 uint8_t immediate_notify_resource_count;
1293 uint8_t reserved_2[2];
1296 * LSB BIT 0 = Timer Operation mode bit 0
1297 * LSB BIT 1 = Timer Operation mode bit 1
1298 * LSB BIT 2 = Timer Operation mode bit 2
1299 * LSB BIT 3 = Timer Operation mode bit 3
1300 * LSB BIT 4 = Init Config Mode bit 0
1301 * LSB BIT 5 = Init Config Mode bit 1
1302 * LSB BIT 6 = Init Config Mode bit 2
1303 * LSB BIT 7 = Enable Non part on LIHA failure
1305 * MSB BIT 0 = Enable class 2
1306 * MSB BIT 1 = Enable ACK0
1309 * MSB BIT 4 = FC Tape Enable
1310 * MSB BIT 5 = Enable FC Confirm
1311 * MSB BIT 6 = Enable command queuing in target mode
1312 * MSB BIT 7 = No Logo On Link Down
1314 uint8_t add_firmware_options[2];
1316 uint8_t response_accumulation_timer;
1317 uint8_t interrupt_delay_timer;
1320 * LSB BIT 0 = Enable Read xfr_rdy
1321 * LSB BIT 1 = Soft ID only
1324 * LSB BIT 4 = FCP RSP Payload [0]
1325 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1326 * LSB BIT 6 = Enable Out-of-Order frame handling
1327 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1329 * MSB BIT 0 = Sbus enable - 2300
1333 * MSB BIT 4 = LED mode
1334 * MSB BIT 5 = enable 50 ohm termination
1335 * MSB BIT 6 = Data Rate (2300 only)
1336 * MSB BIT 7 = Data Rate (2300 only)
1338 uint8_t special_options[2];
1340 uint8_t reserved_3[26];
1344 * Get Link Status mailbox command return buffer.
1346 #define GLSO_SEND_RPS BIT_0
1347 #define GLSO_USE_DID BIT_3
1349 struct link_statistics {
1350 uint32_t link_fail_cnt;
1351 uint32_t loss_sync_cnt;
1352 uint32_t loss_sig_cnt;
1353 uint32_t prim_seq_err_cnt;
1354 uint32_t inval_xmit_word_cnt;
1355 uint32_t inval_crc_cnt;
1357 uint32_t link_up_cnt;
1358 uint32_t link_down_loop_init_tmo;
1359 uint32_t link_down_los;
1360 uint32_t link_down_loss_rcv_clk;
1361 uint32_t reserved0[5];
1362 uint32_t port_cfg_chg;
1363 uint32_t reserved1[11];
1364 uint32_t rsp_q_full;
1365 uint32_t atio_q_full;
1367 uint32_t els_proto_err;
1371 uint32_t discarded_frames;
1372 uint32_t dropped_frames;
1375 uint32_t reserved4[4];
1377 uint32_t rcv_exfail;
1379 uint32_t seq_frm_miss;
1382 uint32_t nport_full;
1385 uint32_t fpm_recv_word_cnt_lo;
1386 uint32_t fpm_recv_word_cnt_hi;
1387 uint32_t fpm_disc_word_cnt_lo;
1388 uint32_t fpm_disc_word_cnt_hi;
1389 uint32_t fpm_xmit_word_cnt_lo;
1390 uint32_t fpm_xmit_word_cnt_hi;
1391 uint32_t reserved6[70];
1395 * NVRAM Command values.
1397 #define NV_START_BIT BIT_2
1398 #define NV_WRITE_OP (BIT_26+BIT_24)
1399 #define NV_READ_OP (BIT_26+BIT_25)
1400 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1401 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1402 #define NV_DELAY_COUNT 10
1405 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1412 uint8_t nvram_version;
1416 * NVRAM RISC parameter block
1418 uint8_t parameter_block_version;
1422 * LSB BIT 0 = Enable Hard Loop Id
1423 * LSB BIT 1 = Enable Fairness
1424 * LSB BIT 2 = Enable Full-Duplex
1425 * LSB BIT 3 = Enable Fast Posting
1426 * LSB BIT 4 = Enable Target Mode
1427 * LSB BIT 5 = Disable Initiator Mode
1428 * LSB BIT 6 = Enable ADISC
1429 * LSB BIT 7 = Enable Target Inquiry Data
1431 * MSB BIT 0 = Enable PDBC Notify
1432 * MSB BIT 1 = Non Participating LIP
1433 * MSB BIT 2 = Descending Loop ID Search
1434 * MSB BIT 3 = Acquire Loop ID in LIPA
1435 * MSB BIT 4 = Stop PortQ on Full Status
1436 * MSB BIT 5 = Full Login after LIP
1437 * MSB BIT 6 = Node Name Option
1438 * MSB BIT 7 = Ext IFWCB enable bit
1440 uint8_t firmware_options[2];
1442 uint16_t frame_payload_size;
1443 uint16_t max_iocb_allocation;
1444 uint16_t execution_throttle;
1445 uint8_t retry_count;
1446 uint8_t retry_delay; /* unused */
1447 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1448 uint16_t hard_address;
1449 uint8_t inquiry_data;
1450 uint8_t login_timeout;
1451 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1454 * LSB BIT 0 = Timer Operation mode bit 0
1455 * LSB BIT 1 = Timer Operation mode bit 1
1456 * LSB BIT 2 = Timer Operation mode bit 2
1457 * LSB BIT 3 = Timer Operation mode bit 3
1458 * LSB BIT 4 = Init Config Mode bit 0
1459 * LSB BIT 5 = Init Config Mode bit 1
1460 * LSB BIT 6 = Init Config Mode bit 2
1461 * LSB BIT 7 = Enable Non part on LIHA failure
1463 * MSB BIT 0 = Enable class 2
1464 * MSB BIT 1 = Enable ACK0
1467 * MSB BIT 4 = FC Tape Enable
1468 * MSB BIT 5 = Enable FC Confirm
1469 * MSB BIT 6 = Enable command queuing in target mode
1470 * MSB BIT 7 = No Logo On Link Down
1472 uint8_t add_firmware_options[2];
1474 uint8_t response_accumulation_timer;
1475 uint8_t interrupt_delay_timer;
1478 * LSB BIT 0 = Enable Read xfr_rdy
1479 * LSB BIT 1 = Soft ID only
1482 * LSB BIT 4 = FCP RSP Payload [0]
1483 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1484 * LSB BIT 6 = Enable Out-of-Order frame handling
1485 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1487 * MSB BIT 0 = Sbus enable - 2300
1491 * MSB BIT 4 = LED mode
1492 * MSB BIT 5 = enable 50 ohm termination
1493 * MSB BIT 6 = Data Rate (2300 only)
1494 * MSB BIT 7 = Data Rate (2300 only)
1496 uint8_t special_options[2];
1498 /* Reserved for expanded RISC parameter block */
1499 uint8_t reserved_2[22];
1502 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1503 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1504 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1505 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1506 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1507 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1508 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1509 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1511 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1512 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1513 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1514 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1515 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1516 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1517 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1518 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1520 * LSB BIT 0 = Output Swing 1G bit 0
1521 * LSB BIT 1 = Output Swing 1G bit 1
1522 * LSB BIT 2 = Output Swing 1G bit 2
1523 * LSB BIT 3 = Output Emphasis 1G bit 0
1524 * LSB BIT 4 = Output Emphasis 1G bit 1
1525 * LSB BIT 5 = Output Swing 2G bit 0
1526 * LSB BIT 6 = Output Swing 2G bit 1
1527 * LSB BIT 7 = Output Swing 2G bit 2
1529 * MSB BIT 0 = Output Emphasis 2G bit 0
1530 * MSB BIT 1 = Output Emphasis 2G bit 1
1531 * MSB BIT 2 = Output Enable
1538 uint8_t seriallink_options[4];
1541 * NVRAM host parameter block
1543 * LSB BIT 0 = Enable spinup delay
1544 * LSB BIT 1 = Disable BIOS
1545 * LSB BIT 2 = Enable Memory Map BIOS
1546 * LSB BIT 3 = Enable Selectable Boot
1547 * LSB BIT 4 = Disable RISC code load
1548 * LSB BIT 5 = Set cache line size 1
1549 * LSB BIT 6 = PCI Parity Disable
1550 * LSB BIT 7 = Enable extended logging
1552 * MSB BIT 0 = Enable 64bit addressing
1553 * MSB BIT 1 = Enable lip reset
1554 * MSB BIT 2 = Enable lip full login
1555 * MSB BIT 3 = Enable target reset
1556 * MSB BIT 4 = Enable database storage
1557 * MSB BIT 5 = Enable cache flush read
1558 * MSB BIT 6 = Enable database load
1559 * MSB BIT 7 = Enable alternate WWN
1563 uint8_t boot_node_name[WWN_SIZE];
1564 uint8_t boot_lun_number;
1565 uint8_t reset_delay;
1566 uint8_t port_down_retry_count;
1567 uint8_t boot_id_number;
1568 uint16_t max_luns_per_target;
1569 uint8_t fcode_boot_port_name[WWN_SIZE];
1570 uint8_t alternate_port_name[WWN_SIZE];
1571 uint8_t alternate_node_name[WWN_SIZE];
1574 * BIT 0 = Selective Login
1575 * BIT 1 = Alt-Boot Enable
1577 * BIT 3 = Boot Order List
1579 * BIT 5 = Selective LUN
1583 uint8_t efi_parameters;
1585 uint8_t link_down_timeout;
1587 uint8_t adapter_id[16];
1589 uint8_t alt1_boot_node_name[WWN_SIZE];
1590 uint16_t alt1_boot_lun_number;
1591 uint8_t alt2_boot_node_name[WWN_SIZE];
1592 uint16_t alt2_boot_lun_number;
1593 uint8_t alt3_boot_node_name[WWN_SIZE];
1594 uint16_t alt3_boot_lun_number;
1595 uint8_t alt4_boot_node_name[WWN_SIZE];
1596 uint16_t alt4_boot_lun_number;
1597 uint8_t alt5_boot_node_name[WWN_SIZE];
1598 uint16_t alt5_boot_lun_number;
1599 uint8_t alt6_boot_node_name[WWN_SIZE];
1600 uint16_t alt6_boot_lun_number;
1601 uint8_t alt7_boot_node_name[WWN_SIZE];
1602 uint16_t alt7_boot_lun_number;
1604 uint8_t reserved_3[2];
1606 /* Offset 200-215 : Model Number */
1607 uint8_t model_number[16];
1609 /* OEM related items */
1610 uint8_t oem_specific[16];
1613 * NVRAM Adapter Features offset 232-239
1615 * LSB BIT 0 = External GBIC
1616 * LSB BIT 1 = Risc RAM parity
1617 * LSB BIT 2 = Buffer Plus Module
1618 * LSB BIT 3 = Multi Chip Adapter
1619 * LSB BIT 4 = Internal connector
1633 uint8_t adapter_features[2];
1635 uint8_t reserved_4[16];
1637 /* Subsystem vendor ID for ISP2200 */
1638 uint16_t subsystem_vendor_id_2200;
1640 /* Subsystem device ID for ISP2200 */
1641 uint16_t subsystem_device_id_2200;
1648 * ISP queue - response queue entry definition.
1651 uint8_t entry_type; /* Entry type. */
1652 uint8_t entry_count; /* Entry count. */
1653 uint8_t sys_define; /* System defined. */
1654 uint8_t entry_status; /* Entry Status. */
1655 uint32_t handle; /* System defined handle */
1658 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1662 * ISP queue - ATIO queue entry definition.
1665 uint8_t entry_type; /* Entry type. */
1666 uint8_t entry_count; /* Entry count. */
1667 __le16 attr_n_length;
1670 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1681 #define SET_TARGET_ID(ha, to, from) \
1683 if (HAS_EXTENDED_IDS(ha)) \
1684 to.extended = cpu_to_le16(from); \
1686 to.id.standard = (uint8_t)from; \
1690 * ISP queue - command entry structure definition.
1692 #define COMMAND_TYPE 0x11 /* Command entry */
1694 uint8_t entry_type; /* Entry type. */
1695 uint8_t entry_count; /* Entry count. */
1696 uint8_t sys_define; /* System defined. */
1697 uint8_t entry_status; /* Entry Status. */
1698 uint32_t handle; /* System handle. */
1699 target_id_t target; /* SCSI ID */
1700 uint16_t lun; /* SCSI LUN */
1701 uint16_t control_flags; /* Control flags. */
1702 #define CF_WRITE BIT_6
1703 #define CF_READ BIT_5
1704 #define CF_SIMPLE_TAG BIT_3
1705 #define CF_ORDERED_TAG BIT_2
1706 #define CF_HEAD_TAG BIT_1
1707 uint16_t reserved_1;
1708 uint16_t timeout; /* Command timeout. */
1709 uint16_t dseg_count; /* Data segment count. */
1710 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1711 uint32_t byte_count; /* Total byte count. */
1712 uint32_t dseg_0_address; /* Data segment 0 address. */
1713 uint32_t dseg_0_length; /* Data segment 0 length. */
1714 uint32_t dseg_1_address; /* Data segment 1 address. */
1715 uint32_t dseg_1_length; /* Data segment 1 length. */
1716 uint32_t dseg_2_address; /* Data segment 2 address. */
1717 uint32_t dseg_2_length; /* Data segment 2 length. */
1721 * ISP queue - 64-Bit addressing, command entry structure definition.
1723 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1725 uint8_t entry_type; /* Entry type. */
1726 uint8_t entry_count; /* Entry count. */
1727 uint8_t sys_define; /* System defined. */
1728 uint8_t entry_status; /* Entry Status. */
1729 uint32_t handle; /* System handle. */
1730 target_id_t target; /* SCSI ID */
1731 uint16_t lun; /* SCSI LUN */
1732 uint16_t control_flags; /* Control flags. */
1733 uint16_t reserved_1;
1734 uint16_t timeout; /* Command timeout. */
1735 uint16_t dseg_count; /* Data segment count. */
1736 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1737 uint32_t byte_count; /* Total byte count. */
1738 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1739 uint32_t dseg_0_length; /* Data segment 0 length. */
1740 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1741 uint32_t dseg_1_length; /* Data segment 1 length. */
1742 } cmd_a64_entry_t, request_t;
1745 * ISP queue - continuation entry structure definition.
1747 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1749 uint8_t entry_type; /* Entry type. */
1750 uint8_t entry_count; /* Entry count. */
1751 uint8_t sys_define; /* System defined. */
1752 uint8_t entry_status; /* Entry Status. */
1754 uint32_t dseg_0_address; /* Data segment 0 address. */
1755 uint32_t dseg_0_length; /* Data segment 0 length. */
1756 uint32_t dseg_1_address; /* Data segment 1 address. */
1757 uint32_t dseg_1_length; /* Data segment 1 length. */
1758 uint32_t dseg_2_address; /* Data segment 2 address. */
1759 uint32_t dseg_2_length; /* Data segment 2 length. */
1760 uint32_t dseg_3_address; /* Data segment 3 address. */
1761 uint32_t dseg_3_length; /* Data segment 3 length. */
1762 uint32_t dseg_4_address; /* Data segment 4 address. */
1763 uint32_t dseg_4_length; /* Data segment 4 length. */
1764 uint32_t dseg_5_address; /* Data segment 5 address. */
1765 uint32_t dseg_5_length; /* Data segment 5 length. */
1766 uint32_t dseg_6_address; /* Data segment 6 address. */
1767 uint32_t dseg_6_length; /* Data segment 6 length. */
1771 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1773 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1775 uint8_t entry_type; /* Entry type. */
1776 uint8_t entry_count; /* Entry count. */
1777 uint8_t sys_define; /* System defined. */
1778 uint8_t entry_status; /* Entry Status. */
1779 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1780 uint32_t dseg_0_length; /* Data segment 0 length. */
1781 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1782 uint32_t dseg_1_length; /* Data segment 1 length. */
1783 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1784 uint32_t dseg_2_length; /* Data segment 2 length. */
1785 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1786 uint32_t dseg_3_length; /* Data segment 3 length. */
1787 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1788 uint32_t dseg_4_length; /* Data segment 4 length. */
1791 #define PO_MODE_DIF_INSERT 0
1792 #define PO_MODE_DIF_REMOVE 1
1793 #define PO_MODE_DIF_PASS 2
1794 #define PO_MODE_DIF_REPLACE 3
1795 #define PO_MODE_DIF_TCP_CKSUM 6
1796 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1797 #define PO_DISABLE_GUARD_CHECK BIT_4
1798 #define PO_DISABLE_INCR_REF_TAG BIT_5
1799 #define PO_DIS_HEADER_MODE BIT_7
1800 #define PO_ENABLE_DIF_BUNDLING BIT_8
1801 #define PO_DIS_FRAME_MODE BIT_9
1802 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
1803 #define PO_DIS_VALD_APP_REF_ESC BIT_11
1805 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
1806 #define PO_DIS_REF_TAG_REPL BIT_13
1807 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
1808 #define PO_DIS_REF_TAG_VALD BIT_15
1811 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1813 struct crc_context {
1814 uint32_t handle; /* System handle. */
1817 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1818 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1819 __le16 guard_seed; /* Initial Guard Seed */
1820 __le16 prot_opts; /* Requested Data Protection Mode */
1821 __le16 blk_size; /* Data size in bytes */
1822 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1824 __le32 byte_count; /* Total byte count/ total data
1828 uint32_t reserved_1;
1829 uint16_t reserved_2;
1830 uint16_t reserved_3;
1831 uint32_t reserved_4;
1832 uint32_t data_address[2];
1833 uint32_t data_length;
1834 uint32_t reserved_5[2];
1835 uint32_t reserved_6;
1838 __le32 dif_byte_count; /* Total DIF byte
1840 uint16_t reserved_1;
1841 __le16 dseg_count; /* Data segment count */
1842 uint32_t reserved_2;
1843 uint32_t data_address[2];
1844 uint32_t data_length;
1845 uint32_t dif_address[2];
1846 uint32_t dif_length; /* Data segment 0
1851 struct fcp_cmnd fcp_cmnd;
1852 dma_addr_t crc_ctx_dma;
1853 /* List of DMA context transfers */
1854 struct list_head dsd_list;
1856 /* This structure should not exceed 512 bytes */
1859 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1860 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1863 * ISP queue - status entry structure definition.
1865 #define STATUS_TYPE 0x03 /* Status entry. */
1867 uint8_t entry_type; /* Entry type. */
1868 uint8_t entry_count; /* Entry count. */
1869 uint8_t sys_define; /* System defined. */
1870 uint8_t entry_status; /* Entry Status. */
1871 uint32_t handle; /* System handle. */
1872 uint16_t scsi_status; /* SCSI status. */
1873 uint16_t comp_status; /* Completion status. */
1874 uint16_t state_flags; /* State flags. */
1875 uint16_t status_flags; /* Status flags. */
1876 uint16_t rsp_info_len; /* Response Info Length. */
1877 uint16_t req_sense_length; /* Request sense data length. */
1878 uint32_t residual_length; /* Residual transfer length. */
1879 uint8_t rsp_info[8]; /* FCP response information. */
1880 uint8_t req_sense_data[32]; /* Request sense data. */
1884 * Status entry entry status
1886 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1887 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1888 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1889 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1890 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1891 #define RF_BUSY BIT_1 /* Busy */
1892 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1893 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1894 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1898 * Status entry SCSI status bit definitions.
1900 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1901 #define SS_RESIDUAL_UNDER BIT_11
1902 #define SS_RESIDUAL_OVER BIT_10
1903 #define SS_SENSE_LEN_VALID BIT_9
1904 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1905 #define SS_SCSI_STATUS_BYTE 0xff
1907 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1908 #define SS_BUSY_CONDITION BIT_3
1909 #define SS_CONDITION_MET BIT_2
1910 #define SS_CHECK_CONDITION BIT_1
1913 * Status entry completion status
1915 #define CS_COMPLETE 0x0 /* No errors */
1916 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1917 #define CS_DMA 0x2 /* A DMA direction error. */
1918 #define CS_TRANSPORT 0x3 /* Transport error. */
1919 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1920 #define CS_ABORTED 0x5 /* System aborted command. */
1921 #define CS_TIMEOUT 0x6 /* Timeout error. */
1922 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1923 #define CS_DIF_ERROR 0xC /* DIF error detected */
1925 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1926 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1927 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1928 /* (selection timeout) */
1929 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1930 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1931 #define CS_PORT_BUSY 0x2B /* Port Busy */
1932 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1933 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
1935 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1936 #define CS_UNKNOWN 0x81 /* Driver defined */
1937 #define CS_RETRY 0x82 /* Driver defined */
1938 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1940 #define CS_BIDIR_RD_OVERRUN 0x700
1941 #define CS_BIDIR_RD_WR_OVERRUN 0x707
1942 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
1943 #define CS_BIDIR_RD_UNDERRUN 0x1500
1944 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
1945 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
1946 #define CS_BIDIR_DMA 0x200
1948 * Status entry status flags
1950 #define SF_ABTS_TERMINATED BIT_10
1951 #define SF_LOGOUT_SENT BIT_13
1954 * ISP queue - status continuation entry structure definition.
1956 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1958 uint8_t entry_type; /* Entry type. */
1959 uint8_t entry_count; /* Entry count. */
1960 uint8_t sys_define; /* System defined. */
1961 uint8_t entry_status; /* Entry Status. */
1962 uint8_t data[60]; /* data */
1966 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1967 * structure definition.
1969 #define STATUS_TYPE_21 0x21 /* Status entry. */
1971 uint8_t entry_type; /* Entry type. */
1972 uint8_t entry_count; /* Entry count. */
1973 uint8_t handle_count; /* Handle count. */
1974 uint8_t entry_status; /* Entry Status. */
1975 uint32_t handle[15]; /* System handles. */
1979 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1980 * structure definition.
1982 #define STATUS_TYPE_22 0x22 /* Status entry. */
1984 uint8_t entry_type; /* Entry type. */
1985 uint8_t entry_count; /* Entry count. */
1986 uint8_t handle_count; /* Handle count. */
1987 uint8_t entry_status; /* Entry Status. */
1988 uint16_t handle[30]; /* System handles. */
1992 * ISP queue - marker entry structure definition.
1994 #define MARKER_TYPE 0x04 /* Marker entry. */
1996 uint8_t entry_type; /* Entry type. */
1997 uint8_t entry_count; /* Entry count. */
1998 uint8_t handle_count; /* Handle count. */
1999 uint8_t entry_status; /* Entry Status. */
2000 uint32_t sys_define_2; /* System defined. */
2001 target_id_t target; /* SCSI ID */
2002 uint8_t modifier; /* Modifier (7-0). */
2003 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2004 #define MK_SYNC_ID 1 /* Synchronize ID */
2005 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2006 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2007 /* clear port changed, */
2008 /* use sequence number. */
2010 uint16_t sequence_number; /* Sequence number of event */
2011 uint16_t lun; /* SCSI LUN */
2012 uint8_t reserved_2[48];
2016 * ISP queue - Management Server entry structure definition.
2018 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2020 uint8_t entry_type; /* Entry type. */
2021 uint8_t entry_count; /* Entry count. */
2022 uint8_t handle_count; /* Handle count. */
2023 uint8_t entry_status; /* Entry Status. */
2024 uint32_t handle1; /* System handle. */
2025 target_id_t loop_id;
2027 uint16_t control_flags; /* Control flags. */
2030 uint16_t cmd_dsd_count;
2031 uint16_t total_dsd_count;
2037 uint32_t rsp_bytecount;
2038 uint32_t req_bytecount;
2039 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
2040 uint32_t dseg_req_length; /* Data segment 0 length. */
2041 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
2042 uint32_t dseg_rsp_length; /* Data segment 1 length. */
2047 * ISP queue - Mailbox Command entry structure definition.
2049 #define MBX_IOCB_TYPE 0x39
2052 uint8_t entry_count;
2053 uint8_t sys_define1;
2054 /* Use sys_define1 for source type */
2055 #define SOURCE_SCSI 0x00
2056 #define SOURCE_IP 0x01
2057 #define SOURCE_VI 0x02
2058 #define SOURCE_SCTP 0x03
2059 #define SOURCE_MP 0x04
2060 #define SOURCE_MPIOCTL 0x05
2061 #define SOURCE_ASYNC_IOCB 0x07
2063 uint8_t entry_status;
2066 target_id_t loop_id;
2069 uint16_t state_flags;
2070 uint16_t status_flags;
2072 uint32_t sys_define2[2];
2082 uint32_t reserved_2[2];
2083 uint8_t node_name[WWN_SIZE];
2084 uint8_t port_name[WWN_SIZE];
2087 #ifndef IMMED_NOTIFY_TYPE
2088 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2090 * ISP queue - immediate notify entry structure definition.
2091 * This is sent by the ISP to the Target driver.
2092 * This IOCB would have report of events sent by the
2093 * initiator, that needs to be handled by the target
2094 * driver immediately.
2096 struct imm_ntfy_from_isp {
2097 uint8_t entry_type; /* Entry type. */
2098 uint8_t entry_count; /* Entry count. */
2099 uint8_t sys_define; /* System defined. */
2100 uint8_t entry_status; /* Entry Status. */
2103 uint32_t sys_define_2; /* System defined. */
2108 uint16_t status_modifier;
2110 uint16_t task_flags;
2113 uint32_t srr_rel_offs;
2115 #define SRR_IU_DATA_IN 0x1
2116 #define SRR_IU_DATA_OUT 0x5
2117 #define SRR_IU_STATUS 0x7
2119 uint8_t reserved_2[28];
2123 uint16_t nport_handle;
2124 uint16_t reserved_2;
2126 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2127 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2130 uint8_t status_subcode;
2132 uint32_t exchange_address;
2133 uint32_t srr_rel_offs;
2138 uint8_t node_name[8];
2139 } plogi; /* PLOGI/ADISC/PDISC */
2141 /* PRLI word 3 bit 0-15 */
2148 uint16_t nport_handle;
2152 uint8_t port_name[8];
2155 uint32_t reserved_5;
2160 uint16_t reserved_7;
2166 * ISP request and response queue entry sizes
2168 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2169 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2174 * Switch info gathering structure.
2178 uint8_t node_name[WWN_SIZE];
2179 uint8_t port_name[WWN_SIZE];
2180 uint8_t fabric_port_name[WWN_SIZE];
2183 uint8_t fc4f_nvme; /* nvme fc4 feature bits */
2187 #define FC4_TYPE_FCP_SCSI 0x08
2188 #define FC4_TYPE_OTHER 0x0
2189 #define FC4_TYPE_UNKNOWN 0xff
2191 /* mailbox command 4G & above */
2192 struct mbx_24xx_entry {
2194 uint8_t entry_count;
2195 uint8_t sys_define1;
2196 uint8_t entry_status;
2201 #define IOCB_SIZE 64
2204 * Fibre channel port type.
2216 enum qla_sess_deletion {
2217 QLA_SESS_DELETION_NONE = 0,
2218 QLA_SESS_DELETION_IN_PROGRESS,
2222 enum qlt_plogi_link_t {
2223 QLT_PLOGI_LINK_SAME_WWN,
2224 QLT_PLOGI_LINK_CONFLICT,
2228 struct qlt_plogi_ack_t {
2229 struct list_head list;
2230 struct imm_ntfy_from_isp iocb;
2236 struct ct_sns_desc {
2237 struct ct_sns_pkt *ct_sns;
2238 dma_addr_t ct_sns_dma;
2241 enum discovery_state {
2254 enum login_state { /* FW control Target side */
2255 DSC_LS_LLIOCB_SENT = 2,
2260 DSC_LS_PORT_UNAVAIL,
2261 DSC_LS_PRLO_PEND = 9,
2265 enum fcport_mgt_event {
2269 FCME_PLOGI_DONE, /* Initiator side sent LLIOCB */
2279 enum rscn_addr_format {
2287 * Fibre channel port structure.
2289 typedef struct fc_port {
2290 struct list_head list;
2291 struct scsi_qla_host *vha;
2293 uint8_t node_name[WWN_SIZE];
2294 uint8_t port_name[WWN_SIZE];
2297 uint16_t old_loop_id;
2299 unsigned int conf_compl_supported:1;
2300 unsigned int deleted:2;
2301 unsigned int local:1;
2302 unsigned int logout_on_delete:1;
2303 unsigned int logo_ack_needed:1;
2304 unsigned int keep_nport_handle:1;
2305 unsigned int send_els_logo:1;
2306 unsigned int login_pause:1;
2307 unsigned int login_succ:1;
2309 struct work_struct nvme_del_work;
2310 struct completion nvme_del_done;
2311 uint32_t nvme_prli_service_param;
2312 #define NVME_PRLI_SP_CONF BIT_7
2313 #define NVME_PRLI_SP_INITIATOR BIT_5
2314 #define NVME_PRLI_SP_TARGET BIT_4
2315 #define NVME_PRLI_SP_DISCOVERY BIT_3
2317 #define NVME_FLAG_REGISTERED 4
2319 struct fc_port *conflict;
2320 unsigned char logout_completed;
2323 struct se_session *se_sess;
2324 struct kref sess_kref;
2325 struct qla_tgt *tgt;
2326 unsigned long expires;
2327 struct list_head del_list_entry;
2328 struct work_struct free_work;
2330 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2333 uint16_t old_tgt_id;
2337 uint8_t fabric_port_name[WWN_SIZE];
2340 fc_port_type_t port_type;
2347 struct fc_rport *rport, *drport;
2348 u32 supported_classes;
2354 unsigned long last_queue_full;
2355 unsigned long last_ramp_up;
2359 struct nvme_fc_remote_port *nvme_remote_port;
2361 unsigned long retry_delay_timestamp;
2362 struct qla_tgt_sess *tgt_session;
2363 struct ct_sns_desc ct_desc;
2364 enum discovery_state disc_state;
2365 enum login_state fw_login_state;
2366 unsigned long plogi_nack_done_deadline;
2368 u32 login_gen, last_login_gen;
2369 u32 rscn_gen, last_rscn_gen;
2371 struct list_head gnl_entry;
2372 struct work_struct del_work;
2376 #define QLA_FCPORT_SCAN 1
2377 #define QLA_FCPORT_FOUND 2
2380 enum fcport_mgt_event event;
2385 u8 port_name[WWN_SIZE];
2392 * Fibre channel port/lun states.
2394 #define FCS_UNCONFIGURED 1
2395 #define FCS_DEVICE_DEAD 2
2396 #define FCS_DEVICE_LOST 3
2397 #define FCS_ONLINE 4
2399 static const char * const port_state_str[] = {
2410 #define FCF_FABRIC_DEVICE BIT_0
2411 #define FCF_LOGIN_NEEDED BIT_1
2412 #define FCF_FCP2_DEVICE BIT_2
2413 #define FCF_ASYNC_SENT BIT_3
2414 #define FCF_CONF_COMP_SUPPORTED BIT_4
2416 /* No loop ID flag. */
2417 #define FC_NO_LOOP_ID 0x1000
2422 * NOTE: All structures are big-endian in form.
2425 #define CT_REJECT_RESPONSE 0x8001
2426 #define CT_ACCEPT_RESPONSE 0x8002
2427 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2428 #define CT_REASON_CANNOT_PERFORM 0x09
2429 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2430 #define CT_EXPL_ALREADY_REGISTERED 0x10
2431 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2432 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2433 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2434 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2435 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2436 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2437 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2438 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2439 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2440 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2441 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2443 #define NS_N_PORT_TYPE 0x01
2444 #define NS_NL_PORT_TYPE 0x02
2445 #define NS_NX_PORT_TYPE 0x7F
2447 #define GA_NXT_CMD 0x100
2448 #define GA_NXT_REQ_SIZE (16 + 4)
2449 #define GA_NXT_RSP_SIZE (16 + 620)
2451 #define GID_PT_CMD 0x1A1
2452 #define GID_PT_REQ_SIZE (16 + 4)
2454 #define GPN_ID_CMD 0x112
2455 #define GPN_ID_REQ_SIZE (16 + 4)
2456 #define GPN_ID_RSP_SIZE (16 + 8)
2458 #define GNN_ID_CMD 0x113
2459 #define GNN_ID_REQ_SIZE (16 + 4)
2460 #define GNN_ID_RSP_SIZE (16 + 8)
2462 #define GFT_ID_CMD 0x117
2463 #define GFT_ID_REQ_SIZE (16 + 4)
2464 #define GFT_ID_RSP_SIZE (16 + 32)
2466 #define GID_PN_CMD 0x121
2467 #define GID_PN_REQ_SIZE (16 + 8)
2468 #define GID_PN_RSP_SIZE (16 + 4)
2470 #define RFT_ID_CMD 0x217
2471 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2472 #define RFT_ID_RSP_SIZE 16
2474 #define RFF_ID_CMD 0x21F
2475 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2476 #define RFF_ID_RSP_SIZE 16
2478 #define RNN_ID_CMD 0x213
2479 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2480 #define RNN_ID_RSP_SIZE 16
2482 #define RSNN_NN_CMD 0x239
2483 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2484 #define RSNN_NN_RSP_SIZE 16
2486 #define GFPN_ID_CMD 0x11C
2487 #define GFPN_ID_REQ_SIZE (16 + 4)
2488 #define GFPN_ID_RSP_SIZE (16 + 8)
2490 #define GPSC_CMD 0x127
2491 #define GPSC_REQ_SIZE (16 + 8)
2492 #define GPSC_RSP_SIZE (16 + 2 + 2)
2494 #define GFF_ID_CMD 0x011F
2495 #define GFF_ID_REQ_SIZE (16 + 4)
2496 #define GFF_ID_RSP_SIZE (16 + 128)
2499 * HBA attribute types.
2501 #define FDMI_HBA_ATTR_COUNT 9
2502 #define FDMIV2_HBA_ATTR_COUNT 17
2503 #define FDMI_HBA_NODE_NAME 0x1
2504 #define FDMI_HBA_MANUFACTURER 0x2
2505 #define FDMI_HBA_SERIAL_NUMBER 0x3
2506 #define FDMI_HBA_MODEL 0x4
2507 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2508 #define FDMI_HBA_HARDWARE_VERSION 0x6
2509 #define FDMI_HBA_DRIVER_VERSION 0x7
2510 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2511 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2512 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2513 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2514 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2515 #define FDMI_HBA_VENDOR_ID 0xd
2516 #define FDMI_HBA_NUM_PORTS 0xe
2517 #define FDMI_HBA_FABRIC_NAME 0xf
2518 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2519 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0
2521 struct ct_fdmi_hba_attr {
2525 uint8_t node_name[WWN_SIZE];
2526 uint8_t manufacturer[64];
2527 uint8_t serial_num[32];
2528 uint8_t model[16+1];
2529 uint8_t model_desc[80];
2530 uint8_t hw_version[32];
2531 uint8_t driver_version[32];
2532 uint8_t orom_version[16];
2533 uint8_t fw_version[32];
2534 uint8_t os_version[128];
2535 uint32_t max_ct_len;
2539 struct ct_fdmi_hba_attributes {
2541 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
2544 struct ct_fdmiv2_hba_attr {
2548 uint8_t node_name[WWN_SIZE];
2549 uint8_t manufacturer[64];
2550 uint8_t serial_num[32];
2551 uint8_t model[16+1];
2552 uint8_t model_desc[80];
2553 uint8_t hw_version[16];
2554 uint8_t driver_version[32];
2555 uint8_t orom_version[16];
2556 uint8_t fw_version[32];
2557 uint8_t os_version[128];
2558 uint32_t max_ct_len;
2559 uint8_t sym_name[256];
2562 uint8_t fabric_name[WWN_SIZE];
2563 uint8_t bios_name[32];
2564 uint8_t vendor_identifier[8];
2568 struct ct_fdmiv2_hba_attributes {
2570 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT];
2574 * Port attribute types.
2576 #define FDMI_PORT_ATTR_COUNT 6
2577 #define FDMIV2_PORT_ATTR_COUNT 16
2578 #define FDMI_PORT_FC4_TYPES 0x1
2579 #define FDMI_PORT_SUPPORT_SPEED 0x2
2580 #define FDMI_PORT_CURRENT_SPEED 0x3
2581 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2582 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2583 #define FDMI_PORT_HOST_NAME 0x6
2584 #define FDMI_PORT_NODE_NAME 0x7
2585 #define FDMI_PORT_NAME 0x8
2586 #define FDMI_PORT_SYM_NAME 0x9
2587 #define FDMI_PORT_TYPE 0xa
2588 #define FDMI_PORT_SUPP_COS 0xb
2589 #define FDMI_PORT_FABRIC_NAME 0xc
2590 #define FDMI_PORT_FC4_TYPE 0xd
2591 #define FDMI_PORT_STATE 0x101
2592 #define FDMI_PORT_COUNT 0x102
2593 #define FDMI_PORT_ID 0x103
2595 #define FDMI_PORT_SPEED_1GB 0x1
2596 #define FDMI_PORT_SPEED_2GB 0x2
2597 #define FDMI_PORT_SPEED_10GB 0x4
2598 #define FDMI_PORT_SPEED_4GB 0x8
2599 #define FDMI_PORT_SPEED_8GB 0x10
2600 #define FDMI_PORT_SPEED_16GB 0x20
2601 #define FDMI_PORT_SPEED_32GB 0x40
2602 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2604 #define FC_CLASS_2 0x04
2605 #define FC_CLASS_3 0x08
2606 #define FC_CLASS_2_3 0x0C
2608 struct ct_fdmiv2_port_attr {
2612 uint8_t fc4_types[32];
2615 uint32_t max_frame_size;
2616 uint8_t os_dev_name[32];
2617 uint8_t host_name[256];
2618 uint8_t node_name[WWN_SIZE];
2619 uint8_t port_name[WWN_SIZE];
2620 uint8_t port_sym_name[128];
2622 uint32_t port_supported_cos;
2623 uint8_t fabric_name[WWN_SIZE];
2624 uint8_t port_fc4_type[32];
2625 uint32_t port_state;
2632 * Port Attribute Block.
2634 struct ct_fdmiv2_port_attributes {
2636 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT];
2639 struct ct_fdmi_port_attr {
2643 uint8_t fc4_types[32];
2646 uint32_t max_frame_size;
2647 uint8_t os_dev_name[32];
2648 uint8_t host_name[256];
2652 struct ct_fdmi_port_attributes {
2654 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
2657 /* FDMI definitions. */
2658 #define GRHL_CMD 0x100
2659 #define GHAT_CMD 0x101
2660 #define GRPL_CMD 0x102
2661 #define GPAT_CMD 0x110
2663 #define RHBA_CMD 0x200
2664 #define RHBA_RSP_SIZE 16
2666 #define RHAT_CMD 0x201
2667 #define RPRT_CMD 0x210
2669 #define RPA_CMD 0x211
2670 #define RPA_RSP_SIZE 16
2672 #define DHBA_CMD 0x300
2673 #define DHBA_REQ_SIZE (16 + 8)
2674 #define DHBA_RSP_SIZE 16
2676 #define DHAT_CMD 0x301
2677 #define DPRT_CMD 0x310
2678 #define DPA_CMD 0x311
2680 /* CT command header -- request/response common fields */
2690 /* CT command request */
2692 struct ct_cmd_hdr header;
2694 uint16_t max_rsp_size;
2695 uint8_t fragment_id;
2696 uint8_t reserved[3];
2699 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
2715 uint8_t fc4_types[32];
2722 uint8_t fc4_feature;
2729 uint8_t node_name[8];
2733 uint8_t node_name[8];
2735 uint8_t sym_node_name[255];
2739 uint8_t hba_identifier[8];
2743 uint8_t hba_identifier[8];
2744 uint32_t entry_count;
2745 uint8_t port_name[8];
2746 struct ct_fdmi_hba_attributes attrs;
2750 uint8_t hba_identifier[8];
2751 uint32_t entry_count;
2752 uint8_t port_name[8];
2753 struct ct_fdmiv2_hba_attributes attrs;
2757 uint8_t hba_identifier[8];
2758 struct ct_fdmi_hba_attributes attrs;
2762 uint8_t port_name[8];
2763 struct ct_fdmi_port_attributes attrs;
2767 uint8_t port_name[8];
2768 struct ct_fdmiv2_port_attributes attrs;
2772 uint8_t port_name[8];
2776 uint8_t port_name[8];
2780 uint8_t port_name[8];
2784 uint8_t port_name[8];
2788 uint8_t port_name[8];
2797 uint8_t port_name[8];
2802 /* CT command response header */
2804 struct ct_cmd_hdr header;
2807 uint8_t fragment_id;
2808 uint8_t reason_code;
2809 uint8_t explanation_code;
2810 uint8_t vendor_unique;
2813 struct ct_sns_gid_pt_data {
2814 uint8_t control_byte;
2819 struct ct_rsp_hdr header;
2825 uint8_t port_name[8];
2826 uint8_t sym_port_name_len;
2827 uint8_t sym_port_name[255];
2828 uint8_t node_name[8];
2829 uint8_t sym_node_name_len;
2830 uint8_t sym_node_name[255];
2831 uint8_t init_proc_assoc[8];
2832 uint8_t node_ip_addr[16];
2833 uint8_t class_of_service[4];
2834 uint8_t fc4_types[32];
2835 uint8_t ip_address[16];
2836 uint8_t fabric_port_name[8];
2838 uint8_t hard_address[3];
2842 /* Assume the largest number of targets for the union */
2843 struct ct_sns_gid_pt_data
2844 entries[MAX_FIBRE_DEVICES_MAX];
2848 uint8_t port_name[8];
2852 uint8_t node_name[8];
2856 uint8_t fc4_types[32];
2860 uint32_t entry_count;
2861 uint8_t port_name[8];
2862 struct ct_fdmi_hba_attributes attrs;
2866 uint8_t port_name[8];
2874 #define GFF_FCP_SCSI_OFFSET 7
2875 #define GFF_NVME_OFFSET 23 /* type = 28h */
2877 uint8_t fc4_features[128];
2888 struct ct_sns_req req;
2889 struct ct_sns_rsp rsp;
2894 * SNS command structures -- for 2200 compatibility.
2896 #define RFT_ID_SNS_SCMD_LEN 22
2897 #define RFT_ID_SNS_CMD_SIZE 60
2898 #define RFT_ID_SNS_DATA_SIZE 16
2900 #define RNN_ID_SNS_SCMD_LEN 10
2901 #define RNN_ID_SNS_CMD_SIZE 36
2902 #define RNN_ID_SNS_DATA_SIZE 16
2904 #define GA_NXT_SNS_SCMD_LEN 6
2905 #define GA_NXT_SNS_CMD_SIZE 28
2906 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2908 #define GID_PT_SNS_SCMD_LEN 6
2909 #define GID_PT_SNS_CMD_SIZE 28
2911 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
2914 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
2916 #define GPN_ID_SNS_SCMD_LEN 6
2917 #define GPN_ID_SNS_CMD_SIZE 28
2918 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2920 #define GNN_ID_SNS_SCMD_LEN 6
2921 #define GNN_ID_SNS_CMD_SIZE 28
2922 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2924 struct sns_cmd_pkt {
2927 uint16_t buffer_length;
2928 uint16_t reserved_1;
2929 uint32_t buffer_address[2];
2930 uint16_t subcommand_length;
2931 uint16_t reserved_2;
2932 uint16_t subcommand;
2934 uint32_t reserved_3;
2938 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2939 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2940 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2941 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2942 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2943 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2950 const struct firmware *fw;
2953 /* Return data from MBC_GET_ID_LIST call. */
2954 struct gid_list_info {
2958 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2959 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2960 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2964 typedef struct vport_info {
2965 uint8_t port_name[WWN_SIZE];
2966 uint8_t node_name[WWN_SIZE];
2969 unsigned long host_no;
2974 typedef struct vport_params {
2975 uint8_t port_name[WWN_SIZE];
2976 uint8_t node_name[WWN_SIZE];
2978 #define VP_OPTS_RETRY_ENABLE BIT_0
2979 #define VP_OPTS_VP_DISABLE BIT_1
2982 /* NPIV - return codes of VP create and modify */
2983 #define VP_RET_CODE_OK 0
2984 #define VP_RET_CODE_FATAL 1
2985 #define VP_RET_CODE_WRONG_ID 2
2986 #define VP_RET_CODE_WWPN 3
2987 #define VP_RET_CODE_RESOURCES 4
2988 #define VP_RET_CODE_NO_MEM 5
2989 #define VP_RET_CODE_NOT_FOUND 6
2996 struct isp_operations {
2998 int (*pci_config) (struct scsi_qla_host *);
2999 void (*reset_chip) (struct scsi_qla_host *);
3000 int (*chip_diag) (struct scsi_qla_host *);
3001 void (*config_rings) (struct scsi_qla_host *);
3002 void (*reset_adapter) (struct scsi_qla_host *);
3003 int (*nvram_config) (struct scsi_qla_host *);
3004 void (*update_fw_options) (struct scsi_qla_host *);
3005 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3007 char * (*pci_info_str) (struct scsi_qla_host *, char *);
3008 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3010 irq_handler_t intr_handler;
3011 void (*enable_intrs) (struct qla_hw_data *);
3012 void (*disable_intrs) (struct qla_hw_data *);
3014 int (*abort_command) (srb_t *);
3015 int (*target_reset) (struct fc_port *, uint64_t, int);
3016 int (*lun_reset) (struct fc_port *, uint64_t, int);
3017 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3018 uint8_t, uint8_t, uint16_t *, uint8_t);
3019 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3022 uint16_t (*calc_req_entries) (uint16_t);
3023 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3024 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3025 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3028 uint8_t *(*read_nvram) (struct scsi_qla_host *, uint8_t *,
3029 uint32_t, uint32_t);
3030 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
3033 void (*fw_dump) (struct scsi_qla_host *, int);
3035 int (*beacon_on) (struct scsi_qla_host *);
3036 int (*beacon_off) (struct scsi_qla_host *);
3037 void (*beacon_blink) (struct scsi_qla_host *);
3039 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
3040 uint32_t, uint32_t);
3041 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
3044 int (*get_flash_version) (struct scsi_qla_host *, void *);
3045 int (*start_scsi) (srb_t *);
3046 int (*start_scsi_mq) (srb_t *);
3047 int (*abort_isp) (struct scsi_qla_host *);
3048 int (*iospace_config)(struct qla_hw_data*);
3049 int (*initialize_adapter)(struct scsi_qla_host *);
3052 /* MSI-X Support *************************************************************/
3054 #define QLA_MSIX_CHIP_REV_24XX 3
3055 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3056 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3058 #define QLA_BASE_VECTORS 2 /* default + RSP */
3059 #define QLA_MSIX_RSP_Q 0x01
3060 #define QLA_ATIO_VECTOR 0x02
3061 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3063 #define QLA_MIDX_DEFAULT 0
3064 #define QLA_MIDX_RSP_Q 1
3065 #define QLA_PCI_MSIX_CONTROL 0xa2
3066 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3068 struct scsi_qla_host;
3071 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3073 struct qla_msix_entry {
3083 #define WATCH_INTERVAL 1 /* number of seconds */
3086 enum qla_work_type {
3089 QLA_EVT_ASYNC_LOGIN,
3090 QLA_EVT_ASYNC_LOGOUT,
3091 QLA_EVT_ASYNC_LOGOUT_DONE,
3092 QLA_EVT_ASYNC_ADISC,
3093 QLA_EVT_ASYNC_ADISC_DONE,
3109 struct qla_work_evt {
3110 struct list_head list;
3111 enum qla_work_type type;
3113 #define QLA_EVT_FLAG_FREE 0x1
3117 enum fc_host_event_code code;
3121 #define QLA_IDC_ACK_REGS 7
3122 uint16_t mb[QLA_IDC_ACK_REGS];
3125 struct fc_port *fcport;
3126 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3131 #define QLA_UEVENT_CODE_FW_DUMP 0
3149 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3161 struct qla_chip_state_84xx {
3162 struct list_head list;
3166 spinlock_t access_lock;
3167 struct mutex fw_update_mutex;
3169 uint32_t op_fw_version;
3170 uint32_t op_fw_size;
3171 uint32_t op_fw_seq_size;
3172 uint32_t diag_fw_version;
3173 uint32_t gold_fw_version;
3176 struct qla_dif_statistics {
3177 uint64_t dif_input_bytes;
3178 uint64_t dif_output_bytes;
3179 uint64_t dif_input_requests;
3180 uint64_t dif_output_requests;
3181 uint32_t dif_guard_err;
3182 uint32_t dif_ref_tag_err;
3183 uint32_t dif_app_tag_err;
3186 struct qla_statistics {
3187 uint32_t total_isp_aborts;
3188 uint64_t input_bytes;
3189 uint64_t output_bytes;
3190 uint64_t input_requests;
3191 uint64_t output_requests;
3192 uint32_t control_requests;
3194 uint64_t jiffies_at_last_reset;
3195 uint32_t stat_max_pend_cmds;
3196 uint32_t stat_max_qfull_cmds_alloc;
3197 uint32_t stat_max_qfull_cmds_dropped;
3199 struct qla_dif_statistics qla_dif_stats;
3202 struct bidi_statistics {
3203 unsigned long long io_count;
3204 unsigned long long transfer_bytes;
3207 struct qla_tc_param {
3208 struct scsi_qla_host *vha;
3211 struct scatterlist *sg;
3212 struct scatterlist *prot_sg;
3213 struct crc_context *ctx;
3214 uint8_t *ctx_dsd_alloced;
3217 /* Multi queue support */
3218 #define MBC_INITIALIZE_MULTIQ 0x1f
3219 #define QLA_QUE_PAGE 0X1000
3220 #define QLA_MQ_SIZE 32
3221 #define QLA_MAX_QUEUES 256
3222 #define ISP_QUE_REG(ha, id) \
3223 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \
3224 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3225 ((void __iomem *)ha->iobase))
3226 #define QLA_REQ_QUE_ID(tag) \
3227 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3228 #define QLA_DEFAULT_QUE_QOS 5
3229 #define QLA_PRECONFIG_VPORTS 32
3230 #define QLA_MAX_VPORTS_QLA24XX 128
3231 #define QLA_MAX_VPORTS_QLA25XX 256
3233 struct qla_tgt_counters {
3234 uint64_t qla_core_sbt_cmd;
3235 uint64_t core_qla_que_buf;
3236 uint64_t qla_core_ret_ctio;
3237 uint64_t core_qla_snd_status;
3238 uint64_t qla_core_ret_sta_ctio;
3239 uint64_t core_qla_free_cmd;
3240 uint64_t num_q_full_sent;
3241 uint64_t num_alloc_iocb_failed;
3242 uint64_t num_term_xchg_sent;
3247 /* Response queue data structure */
3251 response_t *ring_ptr;
3252 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
3253 uint32_t __iomem *rsp_q_out;
3254 uint16_t ring_index;
3256 uint16_t *in_ptr; /* queue shadow in index */
3262 struct qla_hw_data *hw;
3263 struct qla_msix_entry *msix;
3264 struct req_que *req;
3265 srb_t *status_srb; /* status continuation entry */
3266 struct qla_qpair *qpair;
3268 dma_addr_t dma_fx00;
3269 response_t *ring_fx00;
3270 uint16_t length_fx00;
3271 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3274 /* Request queue data structure */
3278 request_t *ring_ptr;
3279 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
3280 uint32_t __iomem *req_q_out;
3281 uint16_t ring_index;
3283 uint16_t *out_ptr; /* queue shadow out index */
3291 struct rsp_que *rsp;
3292 srb_t **outstanding_cmds;
3293 uint32_t current_outstanding_cmd;
3294 uint16_t num_outstanding_cmds;
3297 dma_addr_t dma_fx00;
3298 request_t *ring_fx00;
3299 uint16_t length_fx00;
3300 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3303 /*Queue pair data structure */
3309 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3310 * legacy code. For other Qpair(s), it will point at qp_lock.
3312 spinlock_t *qp_lock_ptr;
3313 struct scsi_qla_host *vha;
3316 /* distill these fields down to 'online=0/1'
3317 * ha->flags.eeh_busy
3318 * ha->flags.pci_channel_io_perm_failure
3319 * base_vha->loop_state
3322 /* move vha->flags.difdix_supported here */
3323 uint32_t difdix_supported:1;
3324 uint32_t delete_in_progress:1;
3325 uint32_t fw_started:1;
3326 uint32_t enable_class_2:1;
3327 uint32_t enable_explicit_conf:1;
3328 uint32_t use_shadow_reg:1;
3330 uint16_t id; /* qp number used with FW */
3331 uint16_t vp_idx; /* vport ID */
3332 mempool_t *srb_mempool;
3334 struct pci_dev *pdev;
3335 void (*reqq_start_iocbs)(struct qla_qpair *);
3337 /* to do: New driver: move queues to here instead of pointers */
3338 struct req_que *req;
3339 struct rsp_que *rsp;
3340 struct atio_que *atio;
3341 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3342 struct qla_hw_data *hw;
3343 struct work_struct q_work;
3344 struct list_head qp_list_elem; /* vha->qp_list */
3345 struct list_head hints_list;
3346 struct list_head nvme_done_list;
3348 struct qla_tgt_counters tgt_counters;
3351 /* Place holder for FW buffer parameters */
3358 struct scsi_qlt_host {
3359 void *target_lport_ptr;
3360 struct mutex tgt_mutex;
3361 struct mutex tgt_host_action_mutex;
3362 struct qla_tgt *qla_tgt;
3365 struct qlt_hw_data {
3366 /* Protected by hw lock */
3367 uint32_t node_name_set:1;
3369 dma_addr_t atio_dma; /* Physical address. */
3370 struct atio *atio_ring; /* Base virtual address */
3371 struct atio *atio_ring_ptr; /* Current address. */
3372 uint16_t atio_ring_index; /* Current index. */
3373 uint16_t atio_q_length;
3374 uint32_t __iomem *atio_q_in;
3375 uint32_t __iomem *atio_q_out;
3377 struct qla_tgt_func_tmpl *tgt_ops;
3378 struct qla_tgt_vp_map *tgt_vp_map;
3381 uint16_t saved_exchange_count;
3382 uint32_t saved_firmware_options_1;
3383 uint32_t saved_firmware_options_2;
3384 uint32_t saved_firmware_options_3;
3385 uint8_t saved_firmware_options[2];
3386 uint8_t saved_add_firmware_options[2];
3388 uint8_t tgt_node_name[WWN_SIZE];
3390 struct dentry *dfs_tgt_sess;
3391 struct dentry *dfs_tgt_port_database;
3392 struct dentry *dfs_naqp;
3394 struct list_head q_full_list;
3395 uint32_t num_pend_cmds;
3396 uint32_t num_qfull_cmds_alloc;
3397 uint32_t num_qfull_cmds_dropped;
3398 spinlock_t q_full_lock;
3399 uint32_t leak_exchg_thresh_hold;
3400 spinlock_t sess_lock;
3402 #define DEFAULT_NAQP 2
3403 spinlock_t atio_lock ____cacheline_aligned;
3404 struct btree_head32 host_map;
3407 #define MAX_QFULL_CMDS_ALLOC 8192
3408 #define Q_FULL_THRESH_HOLD_PERCENT 90
3409 #define Q_FULL_THRESH_HOLD(ha) \
3410 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3412 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3414 #define QLA_EARLY_LINKUP(_ha) \
3415 ((_ha->flags.n2n_ae || _ha->flags.lip_ae) && \
3416 _ha->flags.fw_started && !_ha->flags.fw_init_done)
3419 * Qlogic host adapter specific data structure.
3421 struct qla_hw_data {
3422 struct pci_dev *pdev;
3424 #define SRB_MIN_REQ 128
3425 mempool_t *srb_mempool;
3428 uint32_t mbox_int :1;
3429 uint32_t mbox_busy :1;
3430 uint32_t disable_risc_code_load :1;
3431 uint32_t enable_64bit_addressing :1;
3432 uint32_t enable_lip_reset :1;
3433 uint32_t enable_target_reset :1;
3434 uint32_t enable_lip_full_login :1;
3435 uint32_t enable_led_scheme :1;
3437 uint32_t msi_enabled :1;
3438 uint32_t msix_enabled :1;
3439 uint32_t disable_serdes :1;
3440 uint32_t gpsc_supported :1;
3441 uint32_t npiv_supported :1;
3442 uint32_t pci_channel_io_perm_failure :1;
3443 uint32_t fce_enabled :1;
3444 uint32_t fac_supported :1;
3446 uint32_t chip_reset_done :1;
3447 uint32_t running_gold_fw :1;
3448 uint32_t eeh_busy :1;
3449 uint32_t disable_msix_handshake :1;
3450 uint32_t fcp_prio_enabled :1;
3451 uint32_t isp82xx_fw_hung:1;
3452 uint32_t nic_core_hung:1;
3454 uint32_t quiesce_owner:1;
3455 uint32_t nic_core_reset_hdlr_active:1;
3456 uint32_t nic_core_reset_owner:1;
3457 uint32_t isp82xx_no_md_cap:1;
3458 uint32_t host_shutting_down:1;
3459 uint32_t idc_compl_status:1;
3460 uint32_t mr_reset_hdlr_active:1;
3461 uint32_t mr_intr_valid:1;
3463 uint32_t dport_enabled:1;
3464 uint32_t fawwpn_enabled:1;
3465 uint32_t exlogins_enabled:1;
3466 uint32_t exchoffld_enabled:1;
3470 uint32_t fw_started:1;
3471 uint32_t fw_init_done:1;
3473 uint32_t detected_lr_sfp:1;
3474 uint32_t using_lr_setting:1;
3477 uint16_t long_range_distance; /* 32G & above */
3478 #define LR_DISTANCE_5K 1
3479 #define LR_DISTANCE_10K 0
3481 /* This spinlock is used to protect "io transactions", you must
3482 * acquire it before doing any IO to the card, eg with RD_REG*() and
3483 * WRT_REG*() for the duration of your entire commandtransaction.
3485 * This spinlock is of lower priority than the io request lock.
3488 spinlock_t hardware_lock ____cacheline_aligned;
3491 device_reg_t *iobase; /* Base I/O address */
3492 resource_size_t pio_address;
3494 #define MIN_IOBASE_LEN 0x100
3495 dma_addr_t bar0_hdl;
3497 void __iomem *cregbase;
3498 dma_addr_t bar2_hdl;
3499 #define BAR0_LEN_FX00 (1024 * 1024)
3500 #define BAR2_LEN_FX00 (128 * 1024)
3502 uint32_t rqstq_intr_code;
3503 uint32_t mbx_intr_code;
3504 uint32_t req_que_len;
3505 uint32_t rsp_que_len;
3506 uint32_t req_que_off;
3507 uint32_t rsp_que_off;
3509 /* Multi queue data structs */
3510 device_reg_t *mqiobase;
3511 device_reg_t *msixbase;
3512 uint16_t msix_count;
3514 struct req_que **req_q_map;
3515 struct rsp_que **rsp_q_map;
3516 struct qla_qpair **queue_pair_map;
3517 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3518 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
3519 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
3520 / sizeof(unsigned long)];
3521 uint8_t max_req_queues;
3522 uint8_t max_rsp_queues;
3525 struct qla_qpair *base_qpair;
3526 struct qla_npiv_entry *npiv_info;
3527 uint16_t nvram_npiv_size;
3529 uint16_t switch_cap;
3530 #define FLOGI_SEQ_DEL BIT_8
3531 #define FLOGI_MID_SUPPORT BIT_10
3532 #define FLOGI_VSAN_SUPPORT BIT_12
3533 #define FLOGI_SP_SUPPORT BIT_13
3535 uint8_t port_no; /* Physical port of adapter */
3536 uint8_t exch_starvation;
3538 /* Timeout timers. */
3539 uint8_t loop_down_abort_time; /* port down timer */
3540 atomic_t loop_down_timer; /* loop down timer */
3541 uint8_t link_down_timeout; /* link down timeout */
3542 uint16_t max_loop_id;
3543 uint16_t max_fibre_devices; /* Maximum number of targets */
3546 uint16_t min_external_loopid; /* First external loop Id */
3548 #define PORT_SPEED_UNKNOWN 0xFFFF
3549 #define PORT_SPEED_1GB 0x00
3550 #define PORT_SPEED_2GB 0x01
3551 #define PORT_SPEED_4GB 0x03
3552 #define PORT_SPEED_8GB 0x04
3553 #define PORT_SPEED_16GB 0x05
3554 #define PORT_SPEED_32GB 0x06
3555 #define PORT_SPEED_10GB 0x13
3556 uint16_t link_data_rate; /* F/W operating speed */
3558 uint8_t current_topology;
3559 uint8_t prev_topology;
3560 #define ISP_CFG_NL 1
3562 #define ISP_CFG_FL 4
3565 uint8_t operating_mode; /* F/W operating mode */
3570 uint8_t interrupts_on;
3571 uint32_t isp_abort_cnt;
3572 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
3573 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
3574 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
3575 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
3576 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
3577 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
3578 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
3579 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
3582 #define DT_ISP2100 BIT_0
3583 #define DT_ISP2200 BIT_1
3584 #define DT_ISP2300 BIT_2
3585 #define DT_ISP2312 BIT_3
3586 #define DT_ISP2322 BIT_4
3587 #define DT_ISP6312 BIT_5
3588 #define DT_ISP6322 BIT_6
3589 #define DT_ISP2422 BIT_7
3590 #define DT_ISP2432 BIT_8
3591 #define DT_ISP5422 BIT_9
3592 #define DT_ISP5432 BIT_10
3593 #define DT_ISP2532 BIT_11
3594 #define DT_ISP8432 BIT_12
3595 #define DT_ISP8001 BIT_13
3596 #define DT_ISP8021 BIT_14
3597 #define DT_ISP2031 BIT_15
3598 #define DT_ISP8031 BIT_16
3599 #define DT_ISPFX00 BIT_17
3600 #define DT_ISP8044 BIT_18
3601 #define DT_ISP2071 BIT_19
3602 #define DT_ISP2271 BIT_20
3603 #define DT_ISP2261 BIT_21
3604 #define DT_ISP_LAST (DT_ISP2261 << 1)
3606 uint32_t device_type;
3607 #define DT_T10_PI BIT_25
3608 #define DT_IIDMA BIT_26
3609 #define DT_FWI2 BIT_27
3610 #define DT_ZIO_SUPPORTED BIT_28
3611 #define DT_OEM_001 BIT_29
3612 #define DT_ISP2200A BIT_30
3613 #define DT_EXTENDED_IDS BIT_31
3615 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
3616 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
3617 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
3618 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
3619 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
3620 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
3621 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
3622 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
3623 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
3624 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
3625 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
3626 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
3627 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
3628 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
3629 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
3630 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
3631 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
3632 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
3633 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
3634 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
3635 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
3636 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
3637 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
3638 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
3640 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
3641 IS_QLA6312(ha) || IS_QLA6322(ha))
3642 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
3643 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
3644 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
3645 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
3646 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
3647 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
3648 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
3650 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
3651 IS_QLA8031(ha) || IS_QLA8044(ha))
3652 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
3653 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
3654 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
3655 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
3656 IS_QLA8044(ha) || IS_QLA27XX(ha))
3657 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3659 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
3660 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3662 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
3664 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
3666 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
3667 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
3668 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
3669 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
3670 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
3671 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
3672 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
3673 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
3675 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha)))
3676 /* Bit 21 of fw_attributes decides the MCTP capabilities */
3677 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
3678 ((ha)->fw_attributes_ext[0] & BIT_0))
3679 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3680 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3681 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
3682 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3683 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
3684 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
3685 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3686 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
3687 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha))
3688 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3689 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3690 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
3691 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3692 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
3693 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3695 /* HBA serial number */
3700 /* NVRAM configuration data */
3701 #define MAX_NVRAM_SIZE 4096
3702 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
3703 uint16_t nvram_size;
3704 uint16_t nvram_base;
3710 uint16_t loop_reset_delay;
3711 uint8_t retry_count;
3712 uint8_t login_timeout;
3714 int port_down_retry_count;
3716 uint8_t aen_mbx_count;
3718 uint32_t login_retry_count;
3719 /* SNS command interfaces. */
3720 ms_iocb_entry_t *ms_iocb;
3721 dma_addr_t ms_iocb_dma;
3722 struct ct_sns_pkt *ct_sns;
3723 dma_addr_t ct_sns_dma;
3724 /* SNS command interfaces for 2200. */
3725 struct sns_cmd_pkt *sns_cmd;
3726 dma_addr_t sns_cmd_dma;
3728 #define SFP_DEV_SIZE 512
3729 #define SFP_BLOCK_SIZE 64
3731 dma_addr_t sfp_data_dma;
3733 #define XGMAC_DATA_SIZE 4096
3735 dma_addr_t xgmac_data_dma;
3737 #define DCBX_TLV_DATA_SIZE 4096
3739 dma_addr_t dcbx_tlv_dma;
3741 struct task_struct *dpc_thread;
3742 uint8_t dpc_active; /* DPC routine is active */
3744 dma_addr_t gid_list_dma;
3745 struct gid_list_info *gid_list;
3746 int gid_list_info_size;
3748 /* Small DMA pool allocations -- maximum 256 bytes in length. */
3749 #define DMA_POOL_SIZE 256
3750 struct dma_pool *s_dma_pool;
3752 dma_addr_t init_cb_dma;
3755 dma_addr_t ex_init_cb_dma;
3756 struct ex_init_cb_81xx *ex_init_cb;
3759 dma_addr_t async_pd_dma;
3761 #define ENABLE_EXTENDED_LOGIN BIT_7
3763 /* Extended Logins */
3765 dma_addr_t exlogin_buf_dma;
3768 #define ENABLE_EXCHANGE_OFFLD BIT_2
3770 /* Exchange Offload */
3771 void *exchoffld_buf;
3772 dma_addr_t exchoffld_buf_dma;
3774 int exchoffld_count;
3778 /* These are used by mailbox operations. */
3779 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
3780 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
3781 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
3784 struct mbx_cmd_32 *mcp32;
3786 unsigned long mbx_cmd_flags;
3787 #define MBX_INTERRUPT 1
3788 #define MBX_INTR_WAIT 2
3789 #define MBX_UPDATE_FLASH_ACTIVE 3
3791 struct mutex vport_lock; /* Virtual port synchronization */
3792 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
3793 struct mutex mq_lock; /* multi-queue synchronization */
3794 struct completion mbx_cmd_comp; /* Serialize mbx access */
3795 struct completion mbx_intr_comp; /* Used for completion notification */
3796 struct completion dcbx_comp; /* For set port config notification */
3797 struct completion lb_portup_comp; /* Used to wait for link up during
3799 #define DCBX_COMP_TIMEOUT 20
3800 #define LB_PORTUP_COMP_TIMEOUT 10
3802 int notify_dcbx_comp;
3803 int notify_lb_portup_comp;
3804 struct mutex selflogin_lock;
3806 /* Basic firmware related information. */
3807 uint16_t fw_major_version;
3808 uint16_t fw_minor_version;
3809 uint16_t fw_subminor_version;
3810 uint16_t fw_attributes;
3811 uint16_t fw_attributes_h;
3812 uint16_t fw_attributes_ext[2];
3813 uint32_t fw_memory_size;
3814 uint32_t fw_transfer_size;
3815 uint32_t fw_srisc_address;
3816 #define RISC_START_ADDRESS_2100 0x1000
3817 #define RISC_START_ADDRESS_2300 0x800
3818 #define RISC_START_ADDRESS_2400 0x100000
3820 uint16_t orig_fw_tgt_xcb_count;
3821 uint16_t cur_fw_tgt_xcb_count;
3822 uint16_t orig_fw_xcb_count;
3823 uint16_t cur_fw_xcb_count;
3824 uint16_t orig_fw_iocb_count;
3825 uint16_t cur_fw_iocb_count;
3826 uint16_t fw_max_fcf_count;
3828 uint32_t fw_shared_ram_start;
3829 uint32_t fw_shared_ram_end;
3830 uint32_t fw_ddr_ram_start;
3831 uint32_t fw_ddr_ram_end;
3833 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
3834 uint8_t fw_seriallink_options[4];
3835 uint16_t fw_seriallink_options24[4];
3837 uint8_t mpi_version[3];
3838 uint32_t mpi_capabilities;
3839 uint8_t phy_version[3];
3840 uint8_t pep_version[3];
3842 /* Firmware dump template */
3843 void *fw_dump_template;
3844 uint32_t fw_dump_template_len;
3845 /* Firmware dump information. */
3846 struct qla2xxx_fw_dump *fw_dump;
3847 uint32_t fw_dump_len;
3849 unsigned long fw_dump_cap_flags;
3850 #define RISC_PAUSE_CMPL 0
3851 #define DMA_SHUTDOWN_CMPL 1
3852 #define ISP_RESET_CMPL 2
3853 #define RISC_RDY_AFT_RESET 3
3854 #define RISC_SRAM_DUMP_CMPL 4
3855 #define RISC_EXT_MEM_DUMP_CMPL 5
3856 #define ISP_MBX_RDY 6
3857 #define ISP_SOFT_RESET_CMPL 7
3858 int fw_dump_reading;
3859 int prev_minidump_failed;
3862 /* Current size of mctp dump is 0x086064 bytes */
3863 #define MCTP_DUMP_SIZE 0x086064
3864 dma_addr_t mctp_dump_dma;
3867 int mctp_dump_reading;
3868 uint32_t chain_offset;
3869 struct dentry *dfs_dir;
3870 struct dentry *dfs_fce;
3871 struct dentry *dfs_tgt_counters;
3872 struct dentry *dfs_fw_resource_cnt;
3878 uint64_t fce_wr, fce_rd;
3879 struct mutex fce_mutex;
3882 uint16_t chip_revision;
3884 uint16_t product_id[4];
3886 uint8_t model_number[16+1];
3887 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
3888 char model_desc[80];
3889 uint8_t adapter_id[16+1];
3891 /* Option ROM information. */
3892 char *optrom_buffer;
3893 uint32_t optrom_size;
3895 #define QLA_SWAITING 0
3896 #define QLA_SREADING 1
3897 #define QLA_SWRITING 2
3898 uint32_t optrom_region_start;
3899 uint32_t optrom_region_size;
3900 struct mutex optrom_mutex;
3902 /* PCI expansion ROM image information. */
3903 #define ROM_CODE_TYPE_BIOS 0
3904 #define ROM_CODE_TYPE_FCODE 1
3905 #define ROM_CODE_TYPE_EFI 3
3906 uint8_t bios_revision[2];
3907 uint8_t efi_revision[2];
3908 uint8_t fcode_revision[16];
3909 uint32_t fw_revision[4];
3911 uint32_t gold_fw_version[4];
3913 /* Offsets for flash/nvram access (set to ~0 if not used). */
3914 uint32_t flash_conf_off;
3915 uint32_t flash_data_off;
3916 uint32_t nvram_conf_off;
3917 uint32_t nvram_data_off;
3919 uint32_t fdt_wrt_disable;
3920 uint32_t fdt_wrt_enable;
3921 uint32_t fdt_erase_cmd;
3922 uint32_t fdt_block_size;
3923 uint32_t fdt_unprotect_sec_cmd;
3924 uint32_t fdt_protect_sec_cmd;
3925 uint32_t fdt_wrt_sts_reg_cmd;
3927 uint32_t flt_region_flt;
3928 uint32_t flt_region_fdt;
3929 uint32_t flt_region_boot;
3930 uint32_t flt_region_boot_sec;
3931 uint32_t flt_region_fw;
3932 uint32_t flt_region_fw_sec;
3933 uint32_t flt_region_vpd_nvram;
3934 uint32_t flt_region_vpd;
3935 uint32_t flt_region_vpd_sec;
3936 uint32_t flt_region_nvram;
3937 uint32_t flt_region_npiv_conf;
3938 uint32_t flt_region_gold_fw;
3939 uint32_t flt_region_fcp_prio;
3940 uint32_t flt_region_bootload;
3941 uint32_t flt_region_img_status_pri;
3942 uint32_t flt_region_img_status_sec;
3943 uint8_t active_image;
3945 /* Needed for BEACON */
3946 uint16_t beacon_blink_led;
3947 uint8_t beacon_color_state;
3948 #define QLA_LED_GRN_ON 0x01
3949 #define QLA_LED_YLW_ON 0x02
3950 #define QLA_LED_ABR_ON 0x04
3951 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
3952 /* ISP2322: red, green, amber. */
3956 struct qla_msix_entry *msix_entries;
3958 struct list_head vp_list; /* list of VP */
3959 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
3960 sizeof(unsigned long)];
3961 uint16_t num_vhosts; /* number of vports created */
3962 uint16_t num_vsans; /* number of vsan created */
3963 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
3964 int cur_vport_count;
3966 struct qla_chip_state_84xx *cs84xx;
3967 struct isp_operations *isp_ops;
3968 struct workqueue_struct *wq;
3969 struct qlfc_fw fw_buf;
3971 /* FCP_CMND priority support */
3972 struct qla_fcp_prio_cfg *fcp_prio_cfg;
3974 struct dma_pool *dl_dma_pool;
3975 #define DSD_LIST_DMA_POOL_SIZE 512
3977 struct dma_pool *fcp_cmnd_dma_pool;
3978 mempool_t *ctx_mempool;
3979 #define FCP_CMND_DMA_POOL_SIZE 512
3981 void __iomem *nx_pcibase; /* Base I/O address */
3982 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
3983 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
3986 uint32_t curr_window;
3987 uint32_t ddr_mn_window;
3988 unsigned long mn_win_crb;
3989 unsigned long ms_win_crb;
3991 uint32_t fcoe_dev_init_timeout;
3992 uint32_t fcoe_reset_timeout;
3994 uint16_t portnum; /* port number */
3996 struct fw_blob *hablob;
3997 struct qla82xx_legacy_intr_set nx_legacy_intr;
3999 uint16_t gbl_dsd_inuse;
4000 uint16_t gbl_dsd_avail;
4001 struct list_head gbl_dsd_list;
4002 #define NUM_DSD_CHAIN 4096
4005 __le32 file_prd_off; /* File firmware product offset */
4007 uint32_t md_template_size;
4009 dma_addr_t md_tmplt_hdr_dma;
4011 uint32_t md_dump_size;
4015 /* QLA83XX IDC specific fields */
4016 uint32_t idc_audit_ts;
4017 uint32_t idc_extend_tmo;
4019 /* DPC low-priority workqueue */
4020 struct workqueue_struct *dpc_lp_wq;
4021 struct work_struct idc_aen;
4022 /* DPC high-priority workqueue */
4023 struct workqueue_struct *dpc_hp_wq;
4024 struct work_struct nic_core_reset;
4025 struct work_struct idc_state_handler;
4026 struct work_struct nic_core_unrecoverable;
4027 struct work_struct board_disable;
4029 struct mr_data_fx00 mr;
4031 struct qlt_hw_data tgt;
4032 int allow_cna_fw_dump;
4033 uint32_t fw_ability_mask;
4034 uint16_t min_link_speed;
4035 uint16_t max_speed_sup;
4037 atomic_t nvme_active_aen_cnt;
4038 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4041 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4042 #define FW_ABILITY_MAX_SPEED_16G 0x0
4043 #define FW_ABILITY_MAX_SPEED_32G 0x1
4044 #define FW_ABILITY_MAX_SPEED(ha) \
4045 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4048 * Qlogic scsi host structure
4050 typedef struct scsi_qla_host {
4051 struct list_head list;
4052 struct list_head vp_fcports; /* list of fcports */
4053 struct list_head work_list;
4054 spinlock_t work_lock;
4055 struct work_struct iocb_work;
4057 /* Commonly used flags and state information. */
4058 struct Scsi_Host *host;
4059 unsigned long host_no;
4060 uint8_t host_str[16];
4063 uint32_t init_done :1;
4065 uint32_t reset_active :1;
4067 uint32_t management_server_logged_in :1;
4068 uint32_t process_response_queue :1;
4069 uint32_t difdix_supported:1;
4070 uint32_t delete_progress:1;
4072 uint32_t fw_tgt_reported:1;
4073 uint32_t bbcr_enable:1;
4074 uint32_t qpairs_available:1;
4075 uint32_t qpairs_req_created:1;
4076 uint32_t qpairs_rsp_created:1;
4077 uint32_t nvme_enabled:1;
4080 atomic_t loop_state;
4081 #define LOOP_TIMEOUT 1
4084 #define LOOP_UPDATE 4
4085 #define LOOP_READY 5
4088 unsigned long relogin_jif;
4089 unsigned long dpc_flags;
4090 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4091 #define RESET_ACTIVE 1
4092 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4093 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4094 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4095 #define LOOP_RESYNC_ACTIVE 5
4096 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4097 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4098 #define RELOGIN_NEEDED 8
4099 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4100 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4101 #define BEACON_BLINK_NEEDED 11
4102 #define REGISTER_FDMI_NEEDED 12
4103 #define FCPORT_UPDATE_NEEDED 13
4104 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4105 #define UNLOADING 15
4106 #define NPIV_CONFIG_NEEDED 16
4107 #define ISP_UNRECOVERABLE 17
4108 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4109 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4110 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4112 #define PORT_UPDATE_NEEDED 22
4113 #define FX00_RESET_RECOVERY 23
4114 #define FX00_TARGET_SCAN 24
4115 #define FX00_CRITEMP_RECOVERY 25
4116 #define FX00_HOST_INFO_RESEND 26
4117 #define QPAIR_ONLINE_CHECK_NEEDED 27
4118 #define SET_ZIO_THRESHOLD_NEEDED 28
4119 #define DETECT_SFP_CHANGE 29
4121 unsigned long pci_flags;
4122 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4123 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4124 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4126 uint32_t device_flags;
4127 #define SWITCH_FOUND BIT_0
4128 #define DFLG_NO_CABLE BIT_1
4129 #define DFLG_DEV_FAILED BIT_5
4131 /* ISP configuration data. */
4132 uint16_t loop_id; /* Host adapter loop id */
4133 uint16_t self_login_loop_id; /* host adapter loop id
4134 * get it on self login
4136 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4137 * no need of allocating it for
4141 port_id_t d_id; /* Host adapter port id */
4142 uint8_t marker_needed;
4143 uint16_t mgmt_svr_loop_id;
4147 /* Timeout timers. */
4148 uint8_t loop_down_abort_time; /* port down timer */
4149 atomic_t loop_down_timer; /* loop down timer */
4150 uint8_t link_down_timeout; /* link down timeout */
4152 uint32_t timer_active;
4153 struct timer_list timer;
4155 uint8_t node_name[WWN_SIZE];
4156 uint8_t port_name[WWN_SIZE];
4157 uint8_t fabric_node_name[WWN_SIZE];
4159 struct nvme_fc_local_port *nvme_local_port;
4160 struct completion nvme_del_done;
4161 struct list_head nvme_rport_list;
4162 atomic_t nvme_active_aen_cnt;
4163 uint16_t nvme_last_rptd_aen;
4165 uint16_t fcoe_vlan_id;
4166 uint16_t fcoe_fcf_idx;
4167 uint8_t fcoe_vn_port_mac[6];
4169 /* list of commands waiting on workqueue */
4170 struct list_head qla_cmd_list;
4171 struct list_head qla_sess_op_cmd_list;
4172 struct list_head unknown_atio_list;
4173 spinlock_t cmd_list_lock;
4174 struct delayed_work unknown_atio_work;
4176 /* Counter to detect races between ELS and RSCN events */
4177 atomic_t generation_tick;
4178 /* Time when global fcport update has been scheduled */
4179 int total_fcport_update_gen;
4180 /* List of pending LOGOs, protected by tgt_mutex */
4181 struct list_head logo_list;
4182 /* List of pending PLOGI acks, protected by hw lock */
4183 struct list_head plogi_ack_list;
4185 struct list_head qp_list;
4187 uint32_t vp_abort_cnt;
4189 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4190 uint16_t vp_idx; /* vport ID */
4191 struct qla_qpair *qpair; /* base qpair */
4193 unsigned long vp_flags;
4194 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4195 #define VP_CREATE_NEEDED 1
4196 #define VP_BIND_NEEDED 2
4197 #define VP_DELETE_NEEDED 3
4198 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4199 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4201 #define VP_OFFLINE 0
4204 // #define VP_DISABLE 3
4205 uint16_t vp_err_state;
4206 uint16_t vp_prev_err_state;
4207 #define VP_ERR_UNKWN 0
4208 #define VP_ERR_PORTDWN 1
4209 #define VP_ERR_FAB_UNSUPPORTED 2
4210 #define VP_ERR_FAB_NORESOURCES 3
4211 #define VP_ERR_FAB_LOGOUT 4
4212 #define VP_ERR_ADAP_NORESOURCES 5
4213 struct qla_hw_data *hw;
4214 struct scsi_qlt_host vha_tgt;
4215 struct req_que *req;
4216 int fw_heartbeat_counter;
4217 int seconds_since_last_heartbeat;
4218 struct fc_host_statistics fc_host_stat;
4219 struct qla_statistics qla_stats;
4220 struct bidi_statistics bidi_stats;
4221 atomic_t vref_count;
4222 struct qla8044_reset_template reset_tmplt;
4224 struct name_list_extended gnl;
4225 /* Count of active session/fcport */
4227 wait_queue_head_t fcport_waitQ;
4228 wait_queue_head_t vref_waitq;
4229 uint8_t min_link_speed_feat;
4230 struct list_head gpnid_list;
4233 struct qla27xx_image_status {
4234 uint8_t image_status_mask;
4235 uint16_t generation_number;
4236 uint8_t reserved[3];
4243 #define SET_VP_IDX 1
4245 #define RESET_VP_IDX 3
4246 #define RESET_AL_PA 4
4247 struct qla_tgt_vp_map {
4249 scsi_qla_host_t *vha;
4253 dma_addr_t dma_addr; /* OUT */
4254 uint32_t dma_len; /* OUT */
4256 uint32_t tot_bytes; /* IN */
4257 struct scatterlist *cur_sg; /* IN */
4259 /* for book keeping, bzero on initial invocation */
4260 uint32_t bytes_consumed;
4262 uint32_t tot_partial;
4269 #define QLA_FW_STARTED(_ha) { \
4271 _ha->flags.fw_started = 1; \
4272 _ha->base_qpair->fw_started = 1; \
4273 for (i = 0; i < _ha->max_qpairs; i++) { \
4274 if (_ha->queue_pair_map[i]) \
4275 _ha->queue_pair_map[i]->fw_started = 1; \
4279 #define QLA_FW_STOPPED(_ha) { \
4281 _ha->flags.fw_started = 0; \
4282 _ha->base_qpair->fw_started = 0; \
4283 for (i = 0; i < _ha->max_qpairs; i++) { \
4284 if (_ha->queue_pair_map[i]) \
4285 _ha->queue_pair_map[i]->fw_started = 0; \
4290 * Macros to help code, maintain, etc.
4292 #define LOOP_TRANSITION(ha) \
4293 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4294 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
4295 atomic_read(&ha->loop_state) == LOOP_DOWN)
4297 #define STATE_TRANSITION(ha) \
4298 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
4299 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
4301 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
4302 atomic_inc(&__vha->vref_count); \
4304 if (__vha->flags.delete_progress) { \
4305 atomic_dec(&__vha->vref_count); \
4306 wake_up(&__vha->vref_waitq); \
4313 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
4314 atomic_dec(&__vha->vref_count); \
4315 wake_up(&__vha->vref_waitq); \
4318 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
4319 atomic_inc(&__qpair->ref_count); \
4321 if (__qpair->delete_in_progress) { \
4322 atomic_dec(&__qpair->ref_count); \
4329 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
4330 atomic_dec(&__qpair->ref_count); \
4333 #define QLA_ENA_CONF(_ha) {\
4335 _ha->base_qpair->enable_explicit_conf = 1; \
4336 for (i = 0; i < _ha->max_qpairs; i++) { \
4337 if (_ha->queue_pair_map[i]) \
4338 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
4342 #define QLA_DIS_CONF(_ha) {\
4344 _ha->base_qpair->enable_explicit_conf = 0; \
4345 for (i = 0; i < _ha->max_qpairs; i++) { \
4346 if (_ha->queue_pair_map[i]) \
4347 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
4352 * qla2x00 local function return status codes
4354 #define MBS_MASK 0x3fff
4356 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
4357 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
4358 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
4359 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
4360 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
4361 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
4362 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
4363 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
4364 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
4365 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
4367 #define QLA_FUNCTION_TIMEOUT 0x100
4368 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
4369 #define QLA_FUNCTION_FAILED 0x102
4370 #define QLA_MEMORY_ALLOC_FAILED 0x103
4371 #define QLA_LOCK_TIMEOUT 0x104
4372 #define QLA_ABORTED 0x105
4373 #define QLA_SUSPENDED 0x106
4374 #define QLA_BUSY 0x107
4375 #define QLA_ALREADY_REGISTERED 0x109
4377 #define NVRAM_DELAY() udelay(10)
4380 * Flash support definitions
4382 #define OPTROM_SIZE_2300 0x20000
4383 #define OPTROM_SIZE_2322 0x100000
4384 #define OPTROM_SIZE_24XX 0x100000
4385 #define OPTROM_SIZE_25XX 0x200000
4386 #define OPTROM_SIZE_81XX 0x400000
4387 #define OPTROM_SIZE_82XX 0x800000
4388 #define OPTROM_SIZE_83XX 0x1000000
4390 #define OPTROM_BURST_SIZE 0x1000
4391 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
4393 #define QLA_DSDS_PER_IOCB 37
4395 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
4397 #define QLA_SG_ALL 1024
4399 enum nexus_wait_type {
4405 /* Refer to SNIA SFF 8247 */
4406 struct sff_8247_a0 {
4407 u8 txid; /* transceiver id */
4410 /* compliance code */
4411 u8 eth_infi_cc3; /* ethernet, inifiband */
4415 #define FC_LL_VL BIT_7 /* very long */
4416 #define FC_LL_S BIT_6 /* Short */
4417 #define FC_LL_I BIT_5 /* Intermidiate*/
4418 #define FC_LL_L BIT_4 /* Long */
4419 #define FC_LL_M BIT_3 /* Medium */
4420 #define FC_LL_SA BIT_2 /* ShortWave laser */
4421 #define FC_LL_LC BIT_1 /* LongWave laser */
4422 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
4425 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
4426 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
4427 #define FC_TEC_SL BIT_5 /* short wave with OFC */
4428 #define FC_TEC_LL BIT_4 /* Longwave Laser */
4429 #define FC_TEC_ACT BIT_3 /* Active cable */
4430 #define FC_TEC_PAS BIT_2 /* Passive cable */
4432 /* Transmission Media */
4433 #define FC_MED_TW BIT_7 /* Twin Ax */
4434 #define FC_MED_TP BIT_6 /* Twited Pair */
4435 #define FC_MED_MI BIT_5 /* Min Coax */
4436 #define FC_MED_TV BIT_4 /* Video Coax */
4437 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
4438 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
4439 #define FC_MED_SM BIT_0 /* Single Mode */
4441 /* speed FC_SP_12: 12*100M = 1200 MB/s */
4442 #define FC_SP_12 BIT_7
4443 #define FC_SP_8 BIT_6
4444 #define FC_SP_16 BIT_5
4445 #define FC_SP_4 BIT_4
4446 #define FC_SP_32 BIT_3
4447 #define FC_SP_2 BIT_2
4448 #define FC_SP_1 BIT_0
4453 u8 length_km; /* offset 14/eh */
4459 #define SFF_VEN_NAME_LEN 16
4460 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
4463 #define SFF_PART_NAME_LEN 16
4464 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
4469 u8 options[2]; /* offset 64 */
4478 u8 vendor_specific[32];
4482 #define AUTO_DETECT_SFP_SUPPORT(_vha)\
4483 (ql2xautodetectsfp && !_vha->vp_idx && \
4484 (IS_QLA25XX(_vha->hw) || IS_QLA81XX(_vha->hw) ||\
4485 IS_QLA83XX(_vha->hw) || IS_QLA27XX(_vha->hw)))
4487 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
4488 (IS_QLA27XX(_ha) || IS_QLA83XX(_ha)))
4490 #include "qla_target.h"
4491 #include "qla_gbl.h"
4492 #include "qla_dbg.h"
4493 #include "qla_inline.h"