drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 PM8001_FAIL_DBG(pm8001_ha,
  62                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
  63                         " = 0x%x\n", reg_val));
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 const void *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74         u32 *destination1;
  75         destination1 = (u32 *)destination;
  76
  77         for (index = 0; index < dw_count; index += 4, destination1++) {
  78                 offset = (soffset + index / 4);
  79                 if (offset < (64 * 1024)) {
  80                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  81                         *destination1 =  cpu_to_le32(value);
  82                 }
  83         }
  84         return;
  85 }
  86
  87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  88         struct device_attribute *attr, char *buf)
  89 {
  90         struct Scsi_Host *shost = class_to_shost(cdev);
  91         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  92         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  93         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  94         u32 accum_len , reg_val, index, *temp;
  95         unsigned long start;
  96         u8 *direct_data;
  97         char *fatal_error_data = buf;
  98
  99         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 100         if (pm8001_ha->chip_id == chip_8001) {
 101                 pm8001_ha->forensic_info.data_buf.direct_data +=
 102                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 103                         "Not supported for SPC controller");
 104                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 105                         (char *)buf;
 106         }
 107         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 108                 PM8001_IO_DBG(pm8001_ha,
 109                 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
 110                 direct_data = (u8 *)fatal_error_data;
 111                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 112                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 113                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 114
 115                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 116
 117                 /* start to get data */
 118                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 119                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 120                                 pm8001_ha->fatal_forensic_shift_offset);
 121                 pm8001_ha->forensic_last_offset = 0;
 122                 pm8001_ha->forensic_fatal_step = 0;
 123                 pm8001_ha->fatal_bar_loc = 0;
 124         }
 125
 126         /* Read until accum_len is retrived */
 127         accum_len = pm8001_mr32(fatal_table_address,
 128                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 129         PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
 130                                                 accum_len));
 131         if (accum_len == 0xFFFFFFFF) {
 132                 PM8001_IO_DBG(pm8001_ha,
 133                         pm8001_printk("Possible PCI issue 0x%x not expected\n",
 134                                 accum_len));
 135                 return -EIO;
 136         }
 137         if (accum_len == 0 || accum_len >= 0x100000) {
 138                 pm8001_ha->forensic_info.data_buf.direct_data +=
 139                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 140                                 "%08x ", 0xFFFFFFFF);
 141                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 142                         (char *)buf;
 143         }
 144         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 145         if (pm8001_ha->forensic_fatal_step == 0) {
 146 moreData:
 147                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 148                         /* Data is in bar, copy to host memory */
 149                         pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
 150                          pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 151                                 pm8001_ha->forensic_info.data_buf.direct_len ,
 152                                         1);
 153                 }
 154                 pm8001_ha->fatal_bar_loc +=
 155                         pm8001_ha->forensic_info.data_buf.direct_len;
 156                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 157                         pm8001_ha->forensic_info.data_buf.direct_len;
 158                 pm8001_ha->forensic_last_offset +=
 159                         pm8001_ha->forensic_info.data_buf.direct_len;
 160                 pm8001_ha->forensic_info.data_buf.read_len =
 161                         pm8001_ha->forensic_info.data_buf.direct_len;
 162
 163                 if (pm8001_ha->forensic_last_offset  >= accum_len) {
 164                         pm8001_ha->forensic_info.data_buf.direct_data +=
 165                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 166                                 "%08x ", 3);
 167                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 168                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 169                                         sprintf(pm8001_ha->
 170                                          forensic_info.data_buf.direct_data,
 171                                                 "%08x ", *(temp + index));
 172                         }
 173
 174                         pm8001_ha->fatal_bar_loc = 0;
 175                         pm8001_ha->forensic_fatal_step = 1;
 176                         pm8001_ha->fatal_forensic_shift_offset = 0;
 177                         pm8001_ha->forensic_last_offset = 0;
 178                         return (char *)pm8001_ha->
 179                                 forensic_info.data_buf.direct_data -
 180                                 (char *)buf;
 181                 }
 182                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 183                         pm8001_ha->forensic_info.data_buf.direct_data +=
 184                                 sprintf(pm8001_ha->
 185                                         forensic_info.data_buf.direct_data,
 186                                         "%08x ", 2);
 187                         for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
 188                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 189                                         sprintf(pm8001_ha->
 190                                         forensic_info.data_buf.direct_data,
 191                                         "%08x ", *(temp + index));
 192                         }
 193                         return (char *)pm8001_ha->
 194                                 forensic_info.data_buf.direct_data -
 195                                 (char *)buf;
 196                 }
 197
 198                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 199                 pm8001_ha->forensic_info.data_buf.direct_data +=
 200                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 201                                 "%08x ", 2);
 202                 for (index = 0; index < 256; index++) {
 203                         pm8001_ha->forensic_info.data_buf.direct_data +=
 204                                 sprintf(pm8001_ha->
 205                                         forensic_info.data_buf.direct_data,
 206                                                 "%08x ", *(temp + index));
 207                 }
 208                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 209                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 210                         pm8001_ha->fatal_forensic_shift_offset);
 211                 pm8001_ha->fatal_bar_loc = 0;
 212                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 213                         (char *)buf;
 214         }
 215         if (pm8001_ha->forensic_fatal_step == 1) {
 216                 pm8001_ha->fatal_forensic_shift_offset = 0;
 217                 /* Read 64K of the debug data. */
 218                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 219                         pm8001_ha->fatal_forensic_shift_offset);
 220                 pm8001_mw32(fatal_table_address,
 221                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 222                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 223
 224                 /* Poll FDDHSHK  until clear  */
 225                 start = jiffies + (2 * HZ); /* 2 sec */
 226
 227                 do {
 228                         reg_val = pm8001_mr32(fatal_table_address,
 229                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 230                 } while ((reg_val) && time_before(jiffies, start));
 231
 232                 if (reg_val != 0) {
 233                         PM8001_FAIL_DBG(pm8001_ha,
 234                         pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
 235                         " = 0x%x\n", reg_val));
 236                         return -EIO;
 237                 }
 238
 239                 /* Read the next 64K of the debug data. */
 240                 pm8001_ha->forensic_fatal_step = 0;
 241                 if (pm8001_mr32(fatal_table_address,
 242                         MPI_FATAL_EDUMP_TABLE_STATUS) !=
 243                                 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 244                         pm8001_mw32(fatal_table_address,
 245                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
 246                         goto moreData;
 247                 } else {
 248                         pm8001_ha->forensic_info.data_buf.direct_data +=
 249                                 sprintf(pm8001_ha->
 250                                         forensic_info.data_buf.direct_data,
 251                                                 "%08x ", 4);
 252                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 253                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 254                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 255                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 256                 }
 257         }
 258
 259         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 260                 (char *)buf;
 261 }
 262
 263 /**
 264  * read_main_config_table - read the configure table and save it.
 265  * @pm8001_ha: our hba card information
 266  */
 267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 268 {
 269         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 270
 271         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 272                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 273         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 274                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 275         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 276                 pm8001_mr32(address, MAIN_FW_REVISION);
 277         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 278                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 279         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 280                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 281         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 282                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 283         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 284                 pm8001_mr32(address, MAIN_GST_OFFSET);
 285         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 286                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 287         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 288                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 289
 290         /* read Error Dump Offset and Length */
 291         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 292                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 293         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 294                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 295         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 296                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 297         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 298                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 299
 300         /* read GPIO LED settings from the configuration table */
 301         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 302                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 303
 304         /* read analog Setting offset from the configuration table */
 305         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 306                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 307
 308         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 309                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 310         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 311                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 312         /* read port recover and reset timeout */
 313         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 314                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 315 }
 316
 317 /**
 318  * read_general_status_table - read the general status table and save it.
 319  * @pm8001_ha: our hba card information
 320  */
 321 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 322 {
 323         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 324         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 325                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 326         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 327                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 328         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 329                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 330         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 331                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 332         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 333                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 334         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 335                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 336         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 337                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 338         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 339                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 340         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 341                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 342         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 343                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 344         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 345                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 346         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 347                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 348         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 349                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 350         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 351                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 352 }
 353 /**
 354  * read_phy_attr_table - read the phy attribute table and save it.
 355  * @pm8001_ha: our hba card information
 356  */
 357 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 358 {
 359         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 360         pm8001_ha->phy_attr_table.phystart1_16[0] =
 361                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 362         pm8001_ha->phy_attr_table.phystart1_16[1] =
 363                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 364         pm8001_ha->phy_attr_table.phystart1_16[2] =
 365                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 366         pm8001_ha->phy_attr_table.phystart1_16[3] =
 367                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 368         pm8001_ha->phy_attr_table.phystart1_16[4] =
 369                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 370         pm8001_ha->phy_attr_table.phystart1_16[5] =
 371                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 372         pm8001_ha->phy_attr_table.phystart1_16[6] =
 373                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 374         pm8001_ha->phy_attr_table.phystart1_16[7] =
 375                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 376         pm8001_ha->phy_attr_table.phystart1_16[8] =
 377                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 378         pm8001_ha->phy_attr_table.phystart1_16[9] =
 379                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 380         pm8001_ha->phy_attr_table.phystart1_16[10] =
 381                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 382         pm8001_ha->phy_attr_table.phystart1_16[11] =
 383                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 384         pm8001_ha->phy_attr_table.phystart1_16[12] =
 385                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 386         pm8001_ha->phy_attr_table.phystart1_16[13] =
 387                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 388         pm8001_ha->phy_attr_table.phystart1_16[14] =
 389                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 390         pm8001_ha->phy_attr_table.phystart1_16[15] =
 391                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 392
 393         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 394                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 395         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 396                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 397         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 398                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 399         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 400                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 401         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 402                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 403         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 404                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 405         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 406                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 407         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 408                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 409         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 410                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 411         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 412                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 413         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 414                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 415         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 416                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 417         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 418                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 419         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 420                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 421         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 422                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 423         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 424                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 425
 426 }
 427
 428 /**
 429  * read_inbnd_queue_table - read the inbound queue table and save it.
 430  * @pm8001_ha: our hba card information
 431  */
 432 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 433 {
 434         int i;
 435         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 436         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 437                 u32 offset = i * 0x20;
 438                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 439                         get_pci_bar_index(pm8001_mr32(address,
 440                                 (offset + IB_PIPCI_BAR)));
 441                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 442                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 443         }
 444 }
 445
 446 /**
 447  * read_outbnd_queue_table - read the outbound queue table and save it.
 448  * @pm8001_ha: our hba card information
 449  */
 450 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 451 {
 452         int i;
 453         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 454         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 455                 u32 offset = i * 0x24;
 456                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 457                         get_pci_bar_index(pm8001_mr32(address,
 458                                 (offset + OB_CIPCI_BAR)));
 459                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 460                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 461         }
 462 }
 463
 464 /**
 465  * init_default_table_values - init the default table.
 466  * @pm8001_ha: our hba card information
 467  */
 468 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 469 {
 470         int i;
 471         u32 offsetib, offsetob;
 472         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 473         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 474
 475         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 476                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 477         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 478                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 479         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 480                                                         PM8001_EVENT_LOG_SIZE;
 481         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 482         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 483                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 484         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 485                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 486         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 487                                                         PM8001_EVENT_LOG_SIZE;
 488         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 489         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 490
 491         /* Disable end to end CRC checking */
 492         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 493
 494         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 495                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 496                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 497                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 498                         pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
 499                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 500                 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
 501                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 502                         (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
 503                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 504                         pm8001_ha->memoryMap.region[IB + i].total_len;
 505                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 506                         pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
 507                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 508                         pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
 509                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 510                         pm8001_ha->memoryMap.region[CI + i].virt_ptr;
 511                 offsetib = i * 0x20;
 512                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 513                         get_pci_bar_index(pm8001_mr32(addressib,
 514                                 (offsetib + 0x14)));
 515                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 516                         pm8001_mr32(addressib, (offsetib + 0x18));
 517                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 518                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 519         }
 520         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 521                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 522                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 523                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 524                         pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
 525                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 526                         pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
 527                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 528                         (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
 529                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 530                         pm8001_ha->memoryMap.region[OB + i].total_len;
 531                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 532                         pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
 533                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 534                         pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
 535                 /* interrupt vector based on oq */
 536                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 537                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 538                         pm8001_ha->memoryMap.region[PI + i].virt_ptr;
 539                 offsetob = i * 0x24;
 540                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 541                         get_pci_bar_index(pm8001_mr32(addressob,
 542                         offsetob + 0x14));
 543                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 544                         pm8001_mr32(addressob, (offsetob + 0x18));
 545                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 546                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 547         }
 548 }
 549
 550 /**
 551  * update_main_config_table - update the main default table to the HBA.
 552  * @pm8001_ha: our hba card information
 553  */
 554 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 555 {
 556         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 557         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 558                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 559         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 560                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 561         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 562                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 563         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 564                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 565         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 566                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 567         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 568                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 569         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 570                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 571         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 572                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 573         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 574                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 575         /* Update Fatal error interrupt vector */
 576         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 577                                         ((pm8001_ha->number_of_intr - 1) << 8);
 578         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 579                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 580         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 581                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 582
 583         /* SPCv specific */
 584         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 585         /* Set GPIOLED to 0x2 for LED indicator */
 586         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 587         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 588                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 589
 590         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 591                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 592         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 593                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 594
 595         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 596         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 597                                                         PORT_RECOVERY_TIMEOUT;
 598         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 599                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 600 }
 601
 602 /**
 603  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 604  * @pm8001_ha: our hba card information
 605  */
 606 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 607                                          int number)
 608 {
 609         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 610         u16 offset = number * 0x20;
 611         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 612                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 613         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 614                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 615         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 616                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 617         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 618                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 619         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 620                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 621 }
 622
 623 /**
 624  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 625  * @pm8001_ha: our hba card information
 626  */
 627 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 628                                                  int number)
 629 {
 630         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 631         u16 offset = number * 0x24;
 632         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 633                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 634         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 635                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 636         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 637                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 638         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 639                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 640         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 641                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 642         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 643                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 644 }
 645
 646 /**
 647  * mpi_init_check - check firmware initialization status.
 648  * @pm8001_ha: our hba card information
 649  */
 650 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 651 {
 652         u32 max_wait_count;
 653         u32 value;
 654         u32 gst_len_mpistate;
 655
 656         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 657         table is updated */
 658         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 659         /* wait until Inbound DoorBell Clear Register toggled */
 660         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 661                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
 662         } else {
 663                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 664         }
 665         do {
 666                 udelay(1);
 667                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 668                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
 669         } while ((value != 0) && (--max_wait_count));
 670
 671         if (!max_wait_count)
 672                 return -1;
 673         /* check the MPI-State for initialization upto 100ms*/
 674         max_wait_count = 100 * 1000;/* 100 msec */
 675         do {
 676                 udelay(1);
 677                 gst_len_mpistate =
 678                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 679                                         GST_GSTLEN_MPIS_OFFSET);
 680         } while ((GST_MPI_STATE_INIT !=
 681                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
 682         if (!max_wait_count)
 683                 return -1;
 684
 685         /* check MPI Initialization error */
 686         gst_len_mpistate = gst_len_mpistate >> 16;
 687         if (0x0000 != gst_len_mpistate)
 688                 return -1;
 689
 690         return 0;
 691 }
 692
 693 /**
 694  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 695  * @pm8001_ha: our hba card information
 696  */
 697 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 698 {
 699         u32 value;
 700         u32 max_wait_count;
 701         u32 max_wait_time;
 702         int ret = 0;
 703
 704         /* reset / PCIe ready */
 705         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
 706         do {
 707                 udelay(1);
 708                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 709         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
 710
 711         /* check ila status */
 712         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
 713         do {
 714                 udelay(1);
 715                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 716         } while (((value & SCRATCH_PAD_ILA_READY) !=
 717                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
 718         if (!max_wait_count)
 719                 ret = -1;
 720         else {
 721                 PM8001_MSG_DBG(pm8001_ha,
 722                         pm8001_printk(" ila ready status in %d millisec\n",
 723                                 (max_wait_time - max_wait_count)));
 724         }
 725
 726         /* check RAAE status */
 727         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
 728         do {
 729                 udelay(1);
 730                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 731         } while (((value & SCRATCH_PAD_RAAE_READY) !=
 732                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
 733         if (!max_wait_count)
 734                 ret = -1;
 735         else {
 736                 PM8001_MSG_DBG(pm8001_ha,
 737                         pm8001_printk(" raae ready status in %d millisec\n",
 738                                         (max_wait_time - max_wait_count)));
 739         }
 740
 741         /* check iop0 status */
 742         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
 743         do {
 744                 udelay(1);
 745                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 746         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
 747                         (--max_wait_count));
 748         if (!max_wait_count)
 749                 ret = -1;
 750         else {
 751                 PM8001_MSG_DBG(pm8001_ha,
 752                         pm8001_printk(" iop0 ready status in %d millisec\n",
 753                                 (max_wait_time - max_wait_count)));
 754         }
 755
 756         /* check iop1 status only for 16 port controllers */
 757         if ((pm8001_ha->chip_id != chip_8008) &&
 758                         (pm8001_ha->chip_id != chip_8009)) {
 759                 /* 200 milli sec */
 760                 max_wait_time = max_wait_count = 200 * 1000;
 761                 do {
 762                         udelay(1);
 763                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 764                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
 765                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
 766                 if (!max_wait_count)
 767                         ret = -1;
 768                 else {
 769                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
 770                                 "iop1 ready status in %d millisec\n",
 771                                 (max_wait_time - max_wait_count)));
 772                 }
 773         }
 774
 775         return ret;
 776 }
 777
 778 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 779 {
 780         void __iomem *base_addr;
 781         u32     value;
 782         u32     offset;
 783         u32     pcibar;
 784         u32     pcilogic;
 785
 786         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 787         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
 788
 789         PM8001_INIT_DBG(pm8001_ha,
 790                 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
 791                                 offset, value));
 792         pcilogic = (value & 0xFC000000) >> 26;
 793         pcibar = get_pci_bar_index(pcilogic);
 794         PM8001_INIT_DBG(pm8001_ha,
 795                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 796         pm8001_ha->main_cfg_tbl_addr = base_addr =
 797                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 798         pm8001_ha->general_stat_tbl_addr =
 799                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
 800                                         0xFFFFFF);
 801         pm8001_ha->inbnd_q_tbl_addr =
 802                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
 803                                         0xFFFFFF);
 804         pm8001_ha->outbnd_q_tbl_addr =
 805                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
 806                                         0xFFFFFF);
 807         pm8001_ha->ivt_tbl_addr =
 808                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
 809                                         0xFFFFFF);
 810         pm8001_ha->pspa_q_tbl_addr =
 811                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
 812                                         0xFFFFFF);
 813         pm8001_ha->fatal_tbl_addr =
 814                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
 815                                         0xFFFFFF);
 816
 817         PM8001_INIT_DBG(pm8001_ha,
 818                         pm8001_printk("GST OFFSET 0x%x\n",
 819                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
 820         PM8001_INIT_DBG(pm8001_ha,
 821                         pm8001_printk("INBND OFFSET 0x%x\n",
 822                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
 823         PM8001_INIT_DBG(pm8001_ha,
 824                         pm8001_printk("OBND OFFSET 0x%x\n",
 825                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
 826         PM8001_INIT_DBG(pm8001_ha,
 827                         pm8001_printk("IVT OFFSET 0x%x\n",
 828                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
 829         PM8001_INIT_DBG(pm8001_ha,
 830                         pm8001_printk("PSPA OFFSET 0x%x\n",
 831                         pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
 832         PM8001_INIT_DBG(pm8001_ha,
 833                         pm8001_printk("addr - main cfg %p general status %p\n",
 834                         pm8001_ha->main_cfg_tbl_addr,
 835                         pm8001_ha->general_stat_tbl_addr));
 836         PM8001_INIT_DBG(pm8001_ha,
 837                         pm8001_printk("addr - inbnd %p obnd %p\n",
 838                         pm8001_ha->inbnd_q_tbl_addr,
 839                         pm8001_ha->outbnd_q_tbl_addr));
 840         PM8001_INIT_DBG(pm8001_ha,
 841                         pm8001_printk("addr - pspa %p ivt %p\n",
 842                         pm8001_ha->pspa_q_tbl_addr,
 843                         pm8001_ha->ivt_tbl_addr));
 844 }
 845
 846 /**
 847  * pm80xx_set_thermal_config - support the thermal configuration
 848  * @pm8001_ha: our hba card information.
 849  */
 850 int
 851 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
 852 {
 853         struct set_ctrl_cfg_req payload;
 854         struct inbound_queue_table *circularQ;
 855         int rc;
 856         u32 tag;
 857         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 858         u32 page_code;
 859
 860         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 861         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 862         if (rc)
 863                 return -1;
 864
 865         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 866         payload.tag = cpu_to_le32(tag);
 867
 868         if (IS_SPCV_12G(pm8001_ha->pdev))
 869                 page_code = THERMAL_PAGE_CODE_7H;
 870         else
 871                 page_code = THERMAL_PAGE_CODE_8H;
 872
 873         payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
 874                                 (THERMAL_ENABLE << 8) | page_code;
 875         payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
 876
 877         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 878         if (rc)
 879                 pm8001_tag_free(pm8001_ha, tag);
 880         return rc;
 881
 882 }
 883
 884 /**
 885 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
 886 * Timer configuration page
 887 * @pm8001_ha: our hba card information.
 888 */
 889 static int
 890 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
 891 {
 892         struct set_ctrl_cfg_req payload;
 893         struct inbound_queue_table *circularQ;
 894         SASProtocolTimerConfig_t SASConfigPage;
 895         int rc;
 896         u32 tag;
 897         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
 898
 899         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
 900         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
 901
 902         rc = pm8001_tag_alloc(pm8001_ha, &tag);
 903
 904         if (rc)
 905                 return -1;
 906
 907         circularQ = &pm8001_ha->inbnd_q_tbl[0];
 908         payload.tag = cpu_to_le32(tag);
 909
 910         SASConfigPage.pageCode        =  SAS_PROTOCOL_TIMER_CONFIG_PAGE;
 911         SASConfigPage.MST_MSI         =  3 << 15;
 912         SASConfigPage.STP_SSP_MCT_TMO =  (STP_MCT_TMO << 16) | SSP_MCT_TMO;
 913         SASConfigPage.STP_FRM_TMO     = (SAS_MAX_OPEN_TIME << 24) |
 914                                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
 915         SASConfigPage.STP_IDLE_TMO    =  STP_IDLE_TIME;
 916
 917         if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
 918                 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
 919
 920
 921         SASConfigPage.OPNRJT_RTRY_INTVL =         (SAS_MFD << 16) |
 922                                                 SAS_OPNRJT_RTRY_INTVL;
 923         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =  (SAS_DOPNRJT_RTRY_TMO << 16)
 924                                                 | SAS_COPNRJT_RTRY_TMO;
 925         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =  (SAS_DOPNRJT_RTRY_THR << 16)
 926                                                 | SAS_COPNRJT_RTRY_THR;
 927         SASConfigPage.MAX_AIP =  SAS_MAX_AIP;
 928
 929         PM8001_INIT_DBG(pm8001_ha,
 930                         pm8001_printk("SASConfigPage.pageCode "
 931                         "0x%08x\n", SASConfigPage.pageCode));
 932         PM8001_INIT_DBG(pm8001_ha,
 933                         pm8001_printk("SASConfigPage.MST_MSI "
 934                         " 0x%08x\n", SASConfigPage.MST_MSI));
 935         PM8001_INIT_DBG(pm8001_ha,
 936                         pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
 937                         " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
 938         PM8001_INIT_DBG(pm8001_ha,
 939                         pm8001_printk("SASConfigPage.STP_FRM_TMO "
 940                         " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
 941         PM8001_INIT_DBG(pm8001_ha,
 942                         pm8001_printk("SASConfigPage.STP_IDLE_TMO "
 943                         " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
 944         PM8001_INIT_DBG(pm8001_ha,
 945                         pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
 946                         " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
 947         PM8001_INIT_DBG(pm8001_ha,
 948                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
 949                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
 950         PM8001_INIT_DBG(pm8001_ha,
 951                         pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
 952                         " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
 953         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
 954                         " 0x%08x\n", SASConfigPage.MAX_AIP));
 955
 956         memcpy(&payload.cfg_pg, &SASConfigPage,
 957                          sizeof(SASProtocolTimerConfig_t));
 958
 959         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
 960         if (rc)
 961                 pm8001_tag_free(pm8001_ha, tag);
 962
 963         return rc;
 964 }
 965
 966 /**
 967  * pm80xx_get_encrypt_info - Check for encryption
 968  * @pm8001_ha: our hba card information.
 969  */
 970 static int
 971 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
 972 {
 973         u32 scratch3_value;
 974         int ret = -1;
 975
 976         /* Read encryption status from SCRATCH PAD 3 */
 977         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 978
 979         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
 980                                         SCRATCH_PAD3_ENC_READY) {
 981                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
 982                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
 983                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 984                                                 SCRATCH_PAD3_SMF_ENABLED)
 985                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
 986                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 987                                                 SCRATCH_PAD3_SMA_ENABLED)
 988                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
 989                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
 990                                                 SCRATCH_PAD3_SMB_ENABLED)
 991                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
 992                 pm8001_ha->encrypt_info.status = 0;
 993                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 994                         "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
 995                         "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
 996                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
 997                         pm8001_ha->encrypt_info.sec_mode,
 998                         pm8001_ha->encrypt_info.status));
 999                 ret = 0;
1000         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1001                                         SCRATCH_PAD3_ENC_DISABLED) {
1002                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1003                         "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1004                         scratch3_value));
1005                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1006                 pm8001_ha->encrypt_info.cipher_mode = 0;
1007                 pm8001_ha->encrypt_info.sec_mode = 0;
1008                 ret = 0;
1009         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1010                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1011                 pm8001_ha->encrypt_info.status =
1012                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1013                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1014                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1015                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1016                                         SCRATCH_PAD3_SMF_ENABLED)
1017                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1018                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1019                                         SCRATCH_PAD3_SMA_ENABLED)
1020                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1021                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1022                                         SCRATCH_PAD3_SMB_ENABLED)
1023                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1024                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1025                         "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1026                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1027                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1028                         pm8001_ha->encrypt_info.sec_mode,
1029                         pm8001_ha->encrypt_info.status));
1030         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1031                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1032
1033                 pm8001_ha->encrypt_info.status =
1034                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1035                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1036                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1037                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1038                                         SCRATCH_PAD3_SMF_ENABLED)
1039                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1040                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1041                                         SCRATCH_PAD3_SMA_ENABLED)
1042                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1043                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1044                                         SCRATCH_PAD3_SMB_ENABLED)
1045                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1046
1047                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1048                         "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1049                         "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1050                         scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1051                         pm8001_ha->encrypt_info.sec_mode,
1052                         pm8001_ha->encrypt_info.status));
1053         }
1054         return ret;
1055 }
1056
1057 /**
1058  * pm80xx_encrypt_update - update flash with encryption informtion
1059  * @pm8001_ha: our hba card information.
1060  */
1061 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1062 {
1063         struct kek_mgmt_req payload;
1064         struct inbound_queue_table *circularQ;
1065         int rc;
1066         u32 tag;
1067         u32 opc = OPC_INB_KEK_MANAGEMENT;
1068
1069         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1070         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1071         if (rc)
1072                 return -1;
1073
1074         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1075         payload.tag = cpu_to_le32(tag);
1076         /* Currently only one key is used. New KEK index is 1.
1077          * Current KEK index is 1. Store KEK to NVRAM is 1.
1078          */
1079         payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1080                                         KEK_MGMT_SUBOP_KEYCARDUPDATE);
1081
1082         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1083         if (rc)
1084                 pm8001_tag_free(pm8001_ha, tag);
1085
1086         return rc;
1087 }
1088
1089 /**
1090  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1091  * @pm8001_ha: our hba card information
1092  */
1093 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1094 {
1095         int ret;
1096         u8 i = 0;
1097
1098         /* check the firmware status */
1099         if (-1 == check_fw_ready(pm8001_ha)) {
1100                 PM8001_FAIL_DBG(pm8001_ha,
1101                         pm8001_printk("Firmware is not ready!\n"));
1102                 return -EBUSY;
1103         }
1104
1105         /* Initialize the controller fatal error flag */
1106         pm8001_ha->controller_fatal_error = false;
1107
1108         /* Initialize pci space address eg: mpi offset */
1109         init_pci_device_addresses(pm8001_ha);
1110         init_default_table_values(pm8001_ha);
1111         read_main_config_table(pm8001_ha);
1112         read_general_status_table(pm8001_ha);
1113         read_inbnd_queue_table(pm8001_ha);
1114         read_outbnd_queue_table(pm8001_ha);
1115         read_phy_attr_table(pm8001_ha);
1116
1117         /* update main config table ,inbound table and outbound table */
1118         update_main_config_table(pm8001_ha);
1119         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1120                 update_inbnd_queue_table(pm8001_ha, i);
1121         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1122                 update_outbnd_queue_table(pm8001_ha, i);
1123
1124         /* notify firmware update finished and check initialization status */
1125         if (0 == mpi_init_check(pm8001_ha)) {
1126                 PM8001_INIT_DBG(pm8001_ha,
1127                         pm8001_printk("MPI initialize successful!\n"));
1128         } else
1129                 return -EBUSY;
1130
1131         /* send SAS protocol timer configuration page to FW */
1132         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1133
1134         /* Check for encryption */
1135         if (pm8001_ha->chip->encrypt) {
1136                 PM8001_INIT_DBG(pm8001_ha,
1137                         pm8001_printk("Checking for encryption\n"));
1138                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1139                 if (ret == -1) {
1140                         PM8001_INIT_DBG(pm8001_ha,
1141                                 pm8001_printk("Encryption error !!\n"));
1142                         if (pm8001_ha->encrypt_info.status == 0x81) {
1143                                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1144                                         "Encryption enabled with error."
1145                                         "Saving encryption key to flash\n"));
1146                                 pm80xx_encrypt_update(pm8001_ha);
1147                         }
1148                 }
1149         }
1150         return 0;
1151 }
1152
1153 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1154 {
1155         u32 max_wait_count;
1156         u32 value;
1157         u32 gst_len_mpistate;
1158         init_pci_device_addresses(pm8001_ha);
1159         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1160         table is stop */
1161         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1162
1163         /* wait until Inbound DoorBell Clear Register toggled */
1164         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1165                 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1166         } else {
1167                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1168         }
1169         do {
1170                 udelay(1);
1171                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1172                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1173         } while ((value != 0) && (--max_wait_count));
1174
1175         if (!max_wait_count) {
1176                 PM8001_FAIL_DBG(pm8001_ha,
1177                         pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1178                 return -1;
1179         }
1180
1181         /* check the MPI-State for termination in progress */
1182         /* wait until Inbound DoorBell Clear Register toggled */
1183         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1184         do {
1185                 udelay(1);
1186                 gst_len_mpistate =
1187                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1188                         GST_GSTLEN_MPIS_OFFSET);
1189                 if (GST_MPI_STATE_UNINIT ==
1190                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1191                         break;
1192         } while (--max_wait_count);
1193         if (!max_wait_count) {
1194                 PM8001_FAIL_DBG(pm8001_ha,
1195                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1196                                 gst_len_mpistate & GST_MPI_STATE_MASK));
1197                 return -1;
1198         }
1199
1200         return 0;
1201 }
1202
1203 /**
1204  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1205  * the FW register status to the originated status.
1206  * @pm8001_ha: our hba card information
1207  */
1208
1209 static int
1210 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1211 {
1212         u32 regval;
1213         u32 bootloader_state;
1214         u32 ibutton0, ibutton1;
1215
1216         /* Process MPI table uninitialization only if FW is ready */
1217         if (!pm8001_ha->controller_fatal_error) {
1218                 /* Check if MPI is in ready state to reset */
1219                 if (mpi_uninit_check(pm8001_ha) != 0) {
1220                         regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1221                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1222                                 "MPI state is not ready scratch1 :0x%x\n",
1223                                 regval));
1224                         return -1;
1225                 }
1226         }
1227         /* checked for reset register normal state; 0x0 */
1228         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1229         PM8001_INIT_DBG(pm8001_ha,
1230                 pm8001_printk("reset register before write : 0x%x\n", regval));
1231
1232         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1233         mdelay(500);
1234
1235         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1236         PM8001_INIT_DBG(pm8001_ha,
1237         pm8001_printk("reset register after write 0x%x\n", regval));
1238
1239         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1240                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1241                 PM8001_MSG_DBG(pm8001_ha,
1242                         pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1243                                         regval));
1244         } else {
1245                 PM8001_MSG_DBG(pm8001_ha,
1246                         pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1247                                         regval));
1248
1249                 /* check bootloader is successfully executed or in HDA mode */
1250                 bootloader_state =
1251                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1252                         SCRATCH_PAD1_BOOTSTATE_MASK;
1253
1254                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1255                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1256                                 "Bootloader state - HDA mode SEEPROM\n"));
1257                 } else if (bootloader_state ==
1258                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1259                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1260                                 "Bootloader state - HDA mode Bootstrap Pin\n"));
1261                 } else if (bootloader_state ==
1262                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1263                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1264                                 "Bootloader state - HDA mode soft reset\n"));
1265                 } else if (bootloader_state ==
1266                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1267                         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1268                                 "Bootloader state-HDA mode critical error\n"));
1269                 }
1270                 return -EBUSY;
1271         }
1272
1273         /* check the firmware status after reset */
1274         if (-1 == check_fw_ready(pm8001_ha)) {
1275                 PM8001_FAIL_DBG(pm8001_ha,
1276                         pm8001_printk("Firmware is not ready!\n"));
1277                 /* check iButton feature support for motherboard controller */
1278                 if (pm8001_ha->pdev->subsystem_vendor !=
1279                         PCI_VENDOR_ID_ADAPTEC2 &&
1280                         pm8001_ha->pdev->subsystem_vendor !=
1281                         PCI_VENDOR_ID_ATTO &&
1282                         pm8001_ha->pdev->subsystem_vendor != 0) {
1283                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1284                                         MSGU_HOST_SCRATCH_PAD_6);
1285                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1286                                         MSGU_HOST_SCRATCH_PAD_7);
1287                         if (!ibutton0 && !ibutton1) {
1288                                 PM8001_FAIL_DBG(pm8001_ha,
1289                                         pm8001_printk("iButton Feature is"
1290                                         " not Available!!!\n"));
1291                                 return -EBUSY;
1292                         }
1293                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1294                                 PM8001_FAIL_DBG(pm8001_ha,
1295                                         pm8001_printk("CRC Check for iButton"
1296                                         " Feature Failed!!!\n"));
1297                                 return -EBUSY;
1298                         }
1299                 }
1300         }
1301         PM8001_INIT_DBG(pm8001_ha,
1302                 pm8001_printk("SPCv soft reset Complete\n"));
1303         return 0;
1304 }
1305
1306 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1307 {
1308          u32 i;
1309
1310         PM8001_INIT_DBG(pm8001_ha,
1311                 pm8001_printk("chip reset start\n"));
1312
1313         /* do SPCv chip reset. */
1314         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1315         PM8001_INIT_DBG(pm8001_ha,
1316                 pm8001_printk("SPC soft reset Complete\n"));
1317
1318         /* Check this ..whether delay is required or no */
1319         /* delay 10 usec */
1320         udelay(10);
1321
1322         /* wait for 20 msec until the firmware gets reloaded */
1323         i = 20;
1324         do {
1325                 mdelay(1);
1326         } while ((--i) != 0);
1327
1328         PM8001_INIT_DBG(pm8001_ha,
1329                 pm8001_printk("chip reset finished\n"));
1330 }
1331
1332 /**
1333  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1334  * @pm8001_ha: our hba card information
1335  */
1336 static void
1337 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1338 {
1339         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1340         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1341 }
1342
1343 /**
1344  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1345  * @pm8001_ha: our hba card information
1346  */
1347 static void
1348 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1349 {
1350         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1351 }
1352
1353 /**
1354  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1355  * @pm8001_ha: our hba card information
1356  */
1357 static void
1358 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1359 {
1360 #ifdef PM8001_USE_MSIX
1361         u32 mask;
1362         mask = (u32)(1 << vec);
1363
1364         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1365         return;
1366 #endif
1367         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1368
1369 }
1370
1371 /**
1372  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1373  * @pm8001_ha: our hba card information
1374  */
1375 static void
1376 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1377 {
1378 #ifdef PM8001_USE_MSIX
1379         u32 mask;
1380         if (vec == 0xFF)
1381                 mask = 0xFFFFFFFF;
1382         else
1383                 mask = (u32)(1 << vec);
1384         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1385         return;
1386 #endif
1387         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1388 }
1389
1390 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1391                 struct pm8001_device *pm8001_ha_dev)
1392 {
1393         int res;
1394         u32 ccb_tag;
1395         struct pm8001_ccb_info *ccb;
1396         struct sas_task *task = NULL;
1397         struct task_abort_req task_abort;
1398         struct inbound_queue_table *circularQ;
1399         u32 opc = OPC_INB_SATA_ABORT;
1400         int ret;
1401
1402         if (!pm8001_ha_dev) {
1403                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1404                 return;
1405         }
1406
1407         task = sas_alloc_slow_task(GFP_ATOMIC);
1408
1409         if (!task) {
1410                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1411                                                 "allocate task\n"));
1412                 return;
1413         }
1414
1415         task->task_done = pm8001_task_done;
1416
1417         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1418         if (res) {
1419                 sas_free_task(task);
1420                 return;
1421         }
1422
1423         ccb = &pm8001_ha->ccb_info[ccb_tag];
1424         ccb->device = pm8001_ha_dev;
1425         ccb->ccb_tag = ccb_tag;
1426         ccb->task = task;
1427
1428         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1429
1430         memset(&task_abort, 0, sizeof(task_abort));
1431         task_abort.abort_all = cpu_to_le32(1);
1432         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1433         task_abort.tag = cpu_to_le32(ccb_tag);
1434
1435         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1436         if (ret) {
1437                 sas_free_task(task);
1438                 pm8001_tag_free(pm8001_ha, ccb_tag);
1439         }
1440 }
1441
1442 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1443                 struct pm8001_device *pm8001_ha_dev)
1444 {
1445         struct sata_start_req sata_cmd;
1446         int res;
1447         u32 ccb_tag;
1448         struct pm8001_ccb_info *ccb;
1449         struct sas_task *task = NULL;
1450         struct host_to_dev_fis fis;
1451         struct domain_device *dev;
1452         struct inbound_queue_table *circularQ;
1453         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1454
1455         task = sas_alloc_slow_task(GFP_ATOMIC);
1456
1457         if (!task) {
1458                 PM8001_FAIL_DBG(pm8001_ha,
1459                         pm8001_printk("cannot allocate task !!!\n"));
1460                 return;
1461         }
1462         task->task_done = pm8001_task_done;
1463
1464         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1465         if (res) {
1466                 sas_free_task(task);
1467                 PM8001_FAIL_DBG(pm8001_ha,
1468                         pm8001_printk("cannot allocate tag !!!\n"));
1469                 return;
1470         }
1471
1472         /* allocate domain device by ourselves as libsas
1473          * is not going to provide any
1474         */
1475         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1476         if (!dev) {
1477                 sas_free_task(task);
1478                 pm8001_tag_free(pm8001_ha, ccb_tag);
1479                 PM8001_FAIL_DBG(pm8001_ha,
1480                         pm8001_printk("Domain device cannot be allocated\n"));
1481                 return;
1482         }
1483
1484         task->dev = dev;
1485         task->dev->lldd_dev = pm8001_ha_dev;
1486
1487         ccb = &pm8001_ha->ccb_info[ccb_tag];
1488         ccb->device = pm8001_ha_dev;
1489         ccb->ccb_tag = ccb_tag;
1490         ccb->task = task;
1491         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1492         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1493
1494         memset(&sata_cmd, 0, sizeof(sata_cmd));
1495         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1496
1497         /* construct read log FIS */
1498         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1499         fis.fis_type = 0x27;
1500         fis.flags = 0x80;
1501         fis.command = ATA_CMD_READ_LOG_EXT;
1502         fis.lbal = 0x10;
1503         fis.sector_count = 0x1;
1504
1505         sata_cmd.tag = cpu_to_le32(ccb_tag);
1506         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1507         sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1508         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1509
1510         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1511         if (res) {
1512                 sas_free_task(task);
1513                 pm8001_tag_free(pm8001_ha, ccb_tag);
1514                 kfree(dev);
1515         }
1516 }
1517
1518 /**
1519  * mpi_ssp_completion- process the event that FW response to the SSP request.
1520  * @pm8001_ha: our hba card information
1521  * @piomb: the message contents of this outbound message.
1522  *
1523  * When FW has completed a ssp request for example a IO request, after it has
1524  * filled the SG data with the data, it will trigger this event represent
1525  * that he has finished the job,please check the coresponding buffer.
1526  * So we will tell the caller who maybe waiting the result to tell upper layer
1527  * that the task has been finished.
1528  */
1529 static void
1530 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1531 {
1532         struct sas_task *t;
1533         struct pm8001_ccb_info *ccb;
1534         unsigned long flags;
1535         u32 status;
1536         u32 param;
1537         u32 tag;
1538         struct ssp_completion_resp *psspPayload;
1539         struct task_status_struct *ts;
1540         struct ssp_response_iu *iu;
1541         struct pm8001_device *pm8001_dev;
1542         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1543         status = le32_to_cpu(psspPayload->status);
1544         tag = le32_to_cpu(psspPayload->tag);
1545         ccb = &pm8001_ha->ccb_info[tag];
1546         if ((status == IO_ABORTED) && ccb->open_retry) {
1547                 /* Being completed by another */
1548                 ccb->open_retry = 0;
1549                 return;
1550         }
1551         pm8001_dev = ccb->device;
1552         param = le32_to_cpu(psspPayload->param);
1553         t = ccb->task;
1554
1555         if (status && status != IO_UNDERFLOW)
1556                 PM8001_FAIL_DBG(pm8001_ha,
1557                         pm8001_printk("sas IO status 0x%x\n", status));
1558         if (unlikely(!t || !t->lldd_task || !t->dev))
1559                 return;
1560         ts = &t->task_status;
1561         /* Print sas address of IO failed device */
1562         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1563                 (status != IO_UNDERFLOW))
1564                 PM8001_FAIL_DBG(pm8001_ha,
1565                         pm8001_printk("SAS Address of IO Failure Drive"
1566                         ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1567
1568         switch (status) {
1569         case IO_SUCCESS:
1570                 PM8001_IO_DBG(pm8001_ha,
1571                         pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1572                                 param));
1573                 if (param == 0) {
1574                         ts->resp = SAS_TASK_COMPLETE;
1575                         ts->stat = SAM_STAT_GOOD;
1576                 } else {
1577                         ts->resp = SAS_TASK_COMPLETE;
1578                         ts->stat = SAS_PROTO_RESPONSE;
1579                         ts->residual = param;
1580                         iu = &psspPayload->ssp_resp_iu;
1581                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1582                 }
1583                 if (pm8001_dev)
1584                         pm8001_dev->running_req--;
1585                 break;
1586         case IO_ABORTED:
1587                 PM8001_IO_DBG(pm8001_ha,
1588                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1589                 ts->resp = SAS_TASK_COMPLETE;
1590                 ts->stat = SAS_ABORTED_TASK;
1591                 break;
1592         case IO_UNDERFLOW:
1593                 /* SSP Completion with error */
1594                 PM8001_IO_DBG(pm8001_ha,
1595                         pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1596                                 param));
1597                 ts->resp = SAS_TASK_COMPLETE;
1598                 ts->stat = SAS_DATA_UNDERRUN;
1599                 ts->residual = param;
1600                 if (pm8001_dev)
1601                         pm8001_dev->running_req--;
1602                 break;
1603         case IO_NO_DEVICE:
1604                 PM8001_IO_DBG(pm8001_ha,
1605                         pm8001_printk("IO_NO_DEVICE\n"));
1606                 ts->resp = SAS_TASK_UNDELIVERED;
1607                 ts->stat = SAS_PHY_DOWN;
1608                 break;
1609         case IO_XFER_ERROR_BREAK:
1610                 PM8001_IO_DBG(pm8001_ha,
1611                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1612                 ts->resp = SAS_TASK_COMPLETE;
1613                 ts->stat = SAS_OPEN_REJECT;
1614                 /* Force the midlayer to retry */
1615                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1616                 break;
1617         case IO_XFER_ERROR_PHY_NOT_READY:
1618                 PM8001_IO_DBG(pm8001_ha,
1619                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1620                 ts->resp = SAS_TASK_COMPLETE;
1621                 ts->stat = SAS_OPEN_REJECT;
1622                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1623                 break;
1624         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1625                 PM8001_IO_DBG(pm8001_ha,
1626                         pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1627                 ts->resp = SAS_TASK_COMPLETE;
1628                 ts->stat = SAS_OPEN_REJECT;
1629                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1630                 break;
1631         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1632                 PM8001_IO_DBG(pm8001_ha,
1633                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1634                 ts->resp = SAS_TASK_COMPLETE;
1635                 ts->stat = SAS_OPEN_REJECT;
1636                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1637                 break;
1638         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1639                 PM8001_IO_DBG(pm8001_ha,
1640                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1641                 ts->resp = SAS_TASK_COMPLETE;
1642                 ts->stat = SAS_OPEN_REJECT;
1643                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1644                 break;
1645         case IO_OPEN_CNX_ERROR_BREAK:
1646                 PM8001_IO_DBG(pm8001_ha,
1647                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1648                 ts->resp = SAS_TASK_COMPLETE;
1649                 ts->stat = SAS_OPEN_REJECT;
1650                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1651                 break;
1652         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1653         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1654         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1655         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1656         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1657         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1658                 PM8001_IO_DBG(pm8001_ha,
1659                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1660                 ts->resp = SAS_TASK_COMPLETE;
1661                 ts->stat = SAS_OPEN_REJECT;
1662                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1663                 if (!t->uldd_task)
1664                         pm8001_handle_event(pm8001_ha,
1665                                 pm8001_dev,
1666                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1667                 break;
1668         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1669                 PM8001_IO_DBG(pm8001_ha,
1670                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1671                 ts->resp = SAS_TASK_COMPLETE;
1672                 ts->stat = SAS_OPEN_REJECT;
1673                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1674                 break;
1675         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1676                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1677                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1678                 ts->resp = SAS_TASK_COMPLETE;
1679                 ts->stat = SAS_OPEN_REJECT;
1680                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1681                 break;
1682         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1683                 PM8001_IO_DBG(pm8001_ha,
1684                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1685                 ts->resp = SAS_TASK_UNDELIVERED;
1686                 ts->stat = SAS_OPEN_REJECT;
1687                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1688                 break;
1689         case IO_XFER_ERROR_NAK_RECEIVED:
1690                 PM8001_IO_DBG(pm8001_ha,
1691                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1692                 ts->resp = SAS_TASK_COMPLETE;
1693                 ts->stat = SAS_OPEN_REJECT;
1694                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1695                 break;
1696         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1697                 PM8001_IO_DBG(pm8001_ha,
1698                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1699                 ts->resp = SAS_TASK_COMPLETE;
1700                 ts->stat = SAS_NAK_R_ERR;
1701                 break;
1702         case IO_XFER_ERROR_DMA:
1703                 PM8001_IO_DBG(pm8001_ha,
1704                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1705                 ts->resp = SAS_TASK_COMPLETE;
1706                 ts->stat = SAS_OPEN_REJECT;
1707                 break;
1708         case IO_XFER_OPEN_RETRY_TIMEOUT:
1709                 PM8001_IO_DBG(pm8001_ha,
1710                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1711                 ts->resp = SAS_TASK_COMPLETE;
1712                 ts->stat = SAS_OPEN_REJECT;
1713                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1714                 break;
1715         case IO_XFER_ERROR_OFFSET_MISMATCH:
1716                 PM8001_IO_DBG(pm8001_ha,
1717                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1718                 ts->resp = SAS_TASK_COMPLETE;
1719                 ts->stat = SAS_OPEN_REJECT;
1720                 break;
1721         case IO_PORT_IN_RESET:
1722                 PM8001_IO_DBG(pm8001_ha,
1723                         pm8001_printk("IO_PORT_IN_RESET\n"));
1724                 ts->resp = SAS_TASK_COMPLETE;
1725                 ts->stat = SAS_OPEN_REJECT;
1726                 break;
1727         case IO_DS_NON_OPERATIONAL:
1728                 PM8001_IO_DBG(pm8001_ha,
1729                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1730                 ts->resp = SAS_TASK_COMPLETE;
1731                 ts->stat = SAS_OPEN_REJECT;
1732                 if (!t->uldd_task)
1733                         pm8001_handle_event(pm8001_ha,
1734                                 pm8001_dev,
1735                                 IO_DS_NON_OPERATIONAL);
1736                 break;
1737         case IO_DS_IN_RECOVERY:
1738                 PM8001_IO_DBG(pm8001_ha,
1739                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1740                 ts->resp = SAS_TASK_COMPLETE;
1741                 ts->stat = SAS_OPEN_REJECT;
1742                 break;
1743         case IO_TM_TAG_NOT_FOUND:
1744                 PM8001_IO_DBG(pm8001_ha,
1745                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1746                 ts->resp = SAS_TASK_COMPLETE;
1747                 ts->stat = SAS_OPEN_REJECT;
1748                 break;
1749         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1750                 PM8001_IO_DBG(pm8001_ha,
1751                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1752                 ts->resp = SAS_TASK_COMPLETE;
1753                 ts->stat = SAS_OPEN_REJECT;
1754                 break;
1755         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1756                 PM8001_IO_DBG(pm8001_ha,
1757                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1758                 ts->resp = SAS_TASK_COMPLETE;
1759                 ts->stat = SAS_OPEN_REJECT;
1760                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1761                 break;
1762         default:
1763                 PM8001_IO_DBG(pm8001_ha,
1764                         pm8001_printk("Unknown status 0x%x\n", status));
1765                 /* not allowed case. Therefore, return failed status */
1766                 ts->resp = SAS_TASK_COMPLETE;
1767                 ts->stat = SAS_OPEN_REJECT;
1768                 break;
1769         }
1770         PM8001_IO_DBG(pm8001_ha,
1771                 pm8001_printk("scsi_status = 0x%x\n ",
1772                 psspPayload->ssp_resp_iu.status));
1773         spin_lock_irqsave(&t->task_state_lock, flags);
1774         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1775         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1776         t->task_state_flags |= SAS_TASK_STATE_DONE;
1777         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1778                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1779                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1780                         "task 0x%p done with io_status 0x%x resp 0x%x "
1781                         "stat 0x%x but aborted by upper layer!\n",
1782                         t, status, ts->resp, ts->stat));
1783                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1784         } else {
1785                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1786                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1787                 mb();/* in order to force CPU ordering */
1788                 t->task_done(t);
1789         }
1790 }
1791
1792 /*See the comments for mpi_ssp_completion */
1793 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1794 {
1795         struct sas_task *t;
1796         unsigned long flags;
1797         struct task_status_struct *ts;
1798         struct pm8001_ccb_info *ccb;
1799         struct pm8001_device *pm8001_dev;
1800         struct ssp_event_resp *psspPayload =
1801                 (struct ssp_event_resp *)(piomb + 4);
1802         u32 event = le32_to_cpu(psspPayload->event);
1803         u32 tag = le32_to_cpu(psspPayload->tag);
1804         u32 port_id = le32_to_cpu(psspPayload->port_id);
1805
1806         ccb = &pm8001_ha->ccb_info[tag];
1807         t = ccb->task;
1808         pm8001_dev = ccb->device;
1809         if (event)
1810                 PM8001_FAIL_DBG(pm8001_ha,
1811                         pm8001_printk("sas IO status 0x%x\n", event));
1812         if (unlikely(!t || !t->lldd_task || !t->dev))
1813                 return;
1814         ts = &t->task_status;
1815         PM8001_IO_DBG(pm8001_ha,
1816                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1817                                 port_id, tag, event));
1818         switch (event) {
1819         case IO_OVERFLOW:
1820                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1821                 ts->resp = SAS_TASK_COMPLETE;
1822                 ts->stat = SAS_DATA_OVERRUN;
1823                 ts->residual = 0;
1824                 if (pm8001_dev)
1825                         pm8001_dev->running_req--;
1826                 break;
1827         case IO_XFER_ERROR_BREAK:
1828                 PM8001_IO_DBG(pm8001_ha,
1829                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1830                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1831                 return;
1832         case IO_XFER_ERROR_PHY_NOT_READY:
1833                 PM8001_IO_DBG(pm8001_ha,
1834                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1835                 ts->resp = SAS_TASK_COMPLETE;
1836                 ts->stat = SAS_OPEN_REJECT;
1837                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1838                 break;
1839         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1840                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1841                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1842                 ts->resp = SAS_TASK_COMPLETE;
1843                 ts->stat = SAS_OPEN_REJECT;
1844                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1845                 break;
1846         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1847                 PM8001_IO_DBG(pm8001_ha,
1848                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1849                 ts->resp = SAS_TASK_COMPLETE;
1850                 ts->stat = SAS_OPEN_REJECT;
1851                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1852                 break;
1853         case IO_OPEN_CNX_ERROR_BREAK:
1854                 PM8001_IO_DBG(pm8001_ha,
1855                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1856                 ts->resp = SAS_TASK_COMPLETE;
1857                 ts->stat = SAS_OPEN_REJECT;
1858                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1859                 break;
1860         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1861         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1862         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1863         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1864         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1865         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1866                 PM8001_IO_DBG(pm8001_ha,
1867                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1868                 ts->resp = SAS_TASK_COMPLETE;
1869                 ts->stat = SAS_OPEN_REJECT;
1870                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1871                 if (!t->uldd_task)
1872                         pm8001_handle_event(pm8001_ha,
1873                                 pm8001_dev,
1874                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1875                 break;
1876         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1877                 PM8001_IO_DBG(pm8001_ha,
1878                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1879                 ts->resp = SAS_TASK_COMPLETE;
1880                 ts->stat = SAS_OPEN_REJECT;
1881                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1882                 break;
1883         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1884                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1885                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1886                 ts->resp = SAS_TASK_COMPLETE;
1887                 ts->stat = SAS_OPEN_REJECT;
1888                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1889                 break;
1890         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1891                 PM8001_IO_DBG(pm8001_ha,
1892                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1893                 ts->resp = SAS_TASK_COMPLETE;
1894                 ts->stat = SAS_OPEN_REJECT;
1895                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1896                 break;
1897         case IO_XFER_ERROR_NAK_RECEIVED:
1898                 PM8001_IO_DBG(pm8001_ha,
1899                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1900                 ts->resp = SAS_TASK_COMPLETE;
1901                 ts->stat = SAS_OPEN_REJECT;
1902                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1903                 break;
1904         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1905                 PM8001_IO_DBG(pm8001_ha,
1906                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1907                 ts->resp = SAS_TASK_COMPLETE;
1908                 ts->stat = SAS_NAK_R_ERR;
1909                 break;
1910         case IO_XFER_OPEN_RETRY_TIMEOUT:
1911                 PM8001_IO_DBG(pm8001_ha,
1912                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1913                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1914                 return;
1915         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1916                 PM8001_IO_DBG(pm8001_ha,
1917                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1918                 ts->resp = SAS_TASK_COMPLETE;
1919                 ts->stat = SAS_DATA_OVERRUN;
1920                 break;
1921         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1922                 PM8001_IO_DBG(pm8001_ha,
1923                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1924                 ts->resp = SAS_TASK_COMPLETE;
1925                 ts->stat = SAS_DATA_OVERRUN;
1926                 break;
1927         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1928                 PM8001_IO_DBG(pm8001_ha,
1929                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1930                 ts->resp = SAS_TASK_COMPLETE;
1931                 ts->stat = SAS_DATA_OVERRUN;
1932                 break;
1933         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1934                 PM8001_IO_DBG(pm8001_ha,
1935                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1936                 ts->resp = SAS_TASK_COMPLETE;
1937                 ts->stat = SAS_DATA_OVERRUN;
1938                 break;
1939         case IO_XFER_ERROR_OFFSET_MISMATCH:
1940                 PM8001_IO_DBG(pm8001_ha,
1941                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1942                 ts->resp = SAS_TASK_COMPLETE;
1943                 ts->stat = SAS_DATA_OVERRUN;
1944                 break;
1945         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1946                 PM8001_IO_DBG(pm8001_ha,
1947                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1948                 ts->resp = SAS_TASK_COMPLETE;
1949                 ts->stat = SAS_DATA_OVERRUN;
1950                 break;
1951         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1952                 PM8001_IO_DBG(pm8001_ha,
1953                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1954                 /* TBC: used default set values */
1955                 ts->resp = SAS_TASK_COMPLETE;
1956                 ts->stat = SAS_DATA_OVERRUN;
1957                 break;
1958         case IO_XFER_CMD_FRAME_ISSUED:
1959                 PM8001_IO_DBG(pm8001_ha,
1960                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1961                 return;
1962         default:
1963                 PM8001_IO_DBG(pm8001_ha,
1964                         pm8001_printk("Unknown status 0x%x\n", event));
1965                 /* not allowed case. Therefore, return failed status */
1966                 ts->resp = SAS_TASK_COMPLETE;
1967                 ts->stat = SAS_DATA_OVERRUN;
1968                 break;
1969         }
1970         spin_lock_irqsave(&t->task_state_lock, flags);
1971         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1972         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1973         t->task_state_flags |= SAS_TASK_STATE_DONE;
1974         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1975                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1976                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1977                         "task 0x%p done with event 0x%x resp 0x%x "
1978                         "stat 0x%x but aborted by upper layer!\n",
1979                         t, event, ts->resp, ts->stat));
1980                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1981         } else {
1982                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1983                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1984                 mb();/* in order to force CPU ordering */
1985                 t->task_done(t);
1986         }
1987 }
1988
1989 /*See the comments for mpi_ssp_completion */
1990 static void
1991 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1992 {
1993         struct sas_task *t;
1994         struct pm8001_ccb_info *ccb;
1995         u32 param;
1996         u32 status;
1997         u32 tag;
1998         int i, j;
1999         u8 sata_addr_low[4];
2000         u32 temp_sata_addr_low, temp_sata_addr_hi;
2001         u8 sata_addr_hi[4];
2002         struct sata_completion_resp *psataPayload;
2003         struct task_status_struct *ts;
2004         struct ata_task_resp *resp ;
2005         u32 *sata_resp;
2006         struct pm8001_device *pm8001_dev;
2007         unsigned long flags;
2008
2009         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2010         status = le32_to_cpu(psataPayload->status);
2011         tag = le32_to_cpu(psataPayload->tag);
2012
2013         if (!tag) {
2014                 PM8001_FAIL_DBG(pm8001_ha,
2015                         pm8001_printk("tag null\n"));
2016                 return;
2017         }
2018         ccb = &pm8001_ha->ccb_info[tag];
2019         param = le32_to_cpu(psataPayload->param);
2020         if (ccb) {
2021                 t = ccb->task;
2022                 pm8001_dev = ccb->device;
2023         } else {
2024                 PM8001_FAIL_DBG(pm8001_ha,
2025                         pm8001_printk("ccb null\n"));
2026                 return;
2027         }
2028
2029         if (t) {
2030                 if (t->dev && (t->dev->lldd_dev))
2031                         pm8001_dev = t->dev->lldd_dev;
2032         } else {
2033                 PM8001_FAIL_DBG(pm8001_ha,
2034                         pm8001_printk("task null\n"));
2035                 return;
2036         }
2037
2038         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2039                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2040                 PM8001_FAIL_DBG(pm8001_ha,
2041                         pm8001_printk("task or dev null\n"));
2042                 return;
2043         }
2044
2045         ts = &t->task_status;
2046         if (!ts) {
2047                 PM8001_FAIL_DBG(pm8001_ha,
2048                         pm8001_printk("ts null\n"));
2049                 return;
2050         }
2051         /* Print sas address of IO failed device */
2052         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2053                 (status != IO_UNDERFLOW)) {
2054                 if (!((t->dev->parent) &&
2055                         (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2056                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2057                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2058                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2059                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2060                         memcpy(&temp_sata_addr_low, sata_addr_low,
2061                                 sizeof(sata_addr_low));
2062                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2063                                 sizeof(sata_addr_hi));
2064                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2065                                                 |((temp_sata_addr_hi << 8) &
2066                                                 0xff0000) |
2067                                                 ((temp_sata_addr_hi >> 8)
2068                                                 & 0xff00) |
2069                                                 ((temp_sata_addr_hi << 24) &
2070                                                 0xff000000));
2071                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2072                                                 & 0xff) |
2073                                                 ((temp_sata_addr_low << 8)
2074                                                 & 0xff0000) |
2075                                                 ((temp_sata_addr_low >> 8)
2076                                                 & 0xff00) |
2077                                                 ((temp_sata_addr_low << 24)
2078                                                 & 0xff000000)) +
2079                                                 pm8001_dev->attached_phy +
2080                                                 0x10);
2081                         PM8001_FAIL_DBG(pm8001_ha,
2082                                 pm8001_printk("SAS Address of IO Failure Drive:"
2083                                 "%08x%08x", temp_sata_addr_hi,
2084                                         temp_sata_addr_low));
2085
2086                 } else {
2087                         PM8001_FAIL_DBG(pm8001_ha,
2088                                 pm8001_printk("SAS Address of IO Failure Drive:"
2089                                 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2090                 }
2091         }
2092         switch (status) {
2093         case IO_SUCCESS:
2094                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2095                 if (param == 0) {
2096                         ts->resp = SAS_TASK_COMPLETE;
2097                         ts->stat = SAM_STAT_GOOD;
2098                         /* check if response is for SEND READ LOG */
2099                         if (pm8001_dev &&
2100                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2101                                 /* set new bit for abort_all */
2102                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2103                                 /* clear bit for read log */
2104                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2105                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2106                                 /* Free the tag */
2107                                 pm8001_tag_free(pm8001_ha, tag);
2108                                 sas_free_task(t);
2109                                 return;
2110                         }
2111                 } else {
2112                         u8 len;
2113                         ts->resp = SAS_TASK_COMPLETE;
2114                         ts->stat = SAS_PROTO_RESPONSE;
2115                         ts->residual = param;
2116                         PM8001_IO_DBG(pm8001_ha,
2117                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2118                                 param));
2119                         sata_resp = &psataPayload->sata_resp[0];
2120                         resp = (struct ata_task_resp *)ts->buf;
2121                         if (t->ata_task.dma_xfer == 0 &&
2122                         t->data_dir == PCI_DMA_FROMDEVICE) {
2123                                 len = sizeof(struct pio_setup_fis);
2124                                 PM8001_IO_DBG(pm8001_ha,
2125                                 pm8001_printk("PIO read len = %d\n", len));
2126                         } else if (t->ata_task.use_ncq) {
2127                                 len = sizeof(struct set_dev_bits_fis);
2128                                 PM8001_IO_DBG(pm8001_ha,
2129                                         pm8001_printk("FPDMA len = %d\n", len));
2130                         } else {
2131                                 len = sizeof(struct dev_to_host_fis);
2132                                 PM8001_IO_DBG(pm8001_ha,
2133                                 pm8001_printk("other len = %d\n", len));
2134                         }
2135                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2136                                 resp->frame_len = len;
2137                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2138                                 ts->buf_valid_size = sizeof(*resp);
2139                         } else
2140                                 PM8001_IO_DBG(pm8001_ha,
2141                                         pm8001_printk("response to large\n"));
2142                 }
2143                 if (pm8001_dev)
2144                         pm8001_dev->running_req--;
2145                 break;
2146         case IO_ABORTED:
2147                 PM8001_IO_DBG(pm8001_ha,
2148                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2149                 ts->resp = SAS_TASK_COMPLETE;
2150                 ts->stat = SAS_ABORTED_TASK;
2151                 if (pm8001_dev)
2152                         pm8001_dev->running_req--;
2153                 break;
2154                 /* following cases are to do cases */
2155         case IO_UNDERFLOW:
2156                 /* SATA Completion with error */
2157                 PM8001_IO_DBG(pm8001_ha,
2158                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2159                 ts->resp = SAS_TASK_COMPLETE;
2160                 ts->stat = SAS_DATA_UNDERRUN;
2161                 ts->residual = param;
2162                 if (pm8001_dev)
2163                         pm8001_dev->running_req--;
2164                 break;
2165         case IO_NO_DEVICE:
2166                 PM8001_IO_DBG(pm8001_ha,
2167                         pm8001_printk("IO_NO_DEVICE\n"));
2168                 ts->resp = SAS_TASK_UNDELIVERED;
2169                 ts->stat = SAS_PHY_DOWN;
2170                 break;
2171         case IO_XFER_ERROR_BREAK:
2172                 PM8001_IO_DBG(pm8001_ha,
2173                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2174                 ts->resp = SAS_TASK_COMPLETE;
2175                 ts->stat = SAS_INTERRUPTED;
2176                 break;
2177         case IO_XFER_ERROR_PHY_NOT_READY:
2178                 PM8001_IO_DBG(pm8001_ha,
2179                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2180                 ts->resp = SAS_TASK_COMPLETE;
2181                 ts->stat = SAS_OPEN_REJECT;
2182                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2183                 break;
2184         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2185                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2186                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2187                 ts->resp = SAS_TASK_COMPLETE;
2188                 ts->stat = SAS_OPEN_REJECT;
2189                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2190                 break;
2191         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2192                 PM8001_IO_DBG(pm8001_ha,
2193                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2194                 ts->resp = SAS_TASK_COMPLETE;
2195                 ts->stat = SAS_OPEN_REJECT;
2196                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2197                 break;
2198         case IO_OPEN_CNX_ERROR_BREAK:
2199                 PM8001_IO_DBG(pm8001_ha,
2200                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2201                 ts->resp = SAS_TASK_COMPLETE;
2202                 ts->stat = SAS_OPEN_REJECT;
2203                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2204                 break;
2205         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2206         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2207         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2208         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2209         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2210         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2211                 PM8001_IO_DBG(pm8001_ha,
2212                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2213                 ts->resp = SAS_TASK_COMPLETE;
2214                 ts->stat = SAS_DEV_NO_RESPONSE;
2215                 if (!t->uldd_task) {
2216                         pm8001_handle_event(pm8001_ha,
2217                                 pm8001_dev,
2218                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2219                         ts->resp = SAS_TASK_UNDELIVERED;
2220                         ts->stat = SAS_QUEUE_FULL;
2221                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2222                         return;
2223                 }
2224                 break;
2225         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2226                 PM8001_IO_DBG(pm8001_ha,
2227                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2228                 ts->resp = SAS_TASK_UNDELIVERED;
2229                 ts->stat = SAS_OPEN_REJECT;
2230                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2231                 if (!t->uldd_task) {
2232                         pm8001_handle_event(pm8001_ha,
2233                                 pm8001_dev,
2234                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2235                         ts->resp = SAS_TASK_UNDELIVERED;
2236                         ts->stat = SAS_QUEUE_FULL;
2237                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2238                         return;
2239                 }
2240                 break;
2241         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2242                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2243                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2244                 ts->resp = SAS_TASK_COMPLETE;
2245                 ts->stat = SAS_OPEN_REJECT;
2246                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2247                 break;
2248         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2249                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2250                         "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2251                 ts->resp = SAS_TASK_COMPLETE;
2252                 ts->stat = SAS_DEV_NO_RESPONSE;
2253                 if (!t->uldd_task) {
2254                         pm8001_handle_event(pm8001_ha,
2255                                 pm8001_dev,
2256                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2257                         ts->resp = SAS_TASK_UNDELIVERED;
2258                         ts->stat = SAS_QUEUE_FULL;
2259                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2260                         return;
2261                 }
2262                 break;
2263         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2264                 PM8001_IO_DBG(pm8001_ha,
2265                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2266                 ts->resp = SAS_TASK_COMPLETE;
2267                 ts->stat = SAS_OPEN_REJECT;
2268                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2269                 break;
2270         case IO_XFER_ERROR_NAK_RECEIVED:
2271                 PM8001_IO_DBG(pm8001_ha,
2272                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2273                 ts->resp = SAS_TASK_COMPLETE;
2274                 ts->stat = SAS_NAK_R_ERR;
2275                 break;
2276         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2277                 PM8001_IO_DBG(pm8001_ha,
2278                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2279                 ts->resp = SAS_TASK_COMPLETE;
2280                 ts->stat = SAS_NAK_R_ERR;
2281                 break;
2282         case IO_XFER_ERROR_DMA:
2283                 PM8001_IO_DBG(pm8001_ha,
2284                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2285                 ts->resp = SAS_TASK_COMPLETE;
2286                 ts->stat = SAS_ABORTED_TASK;
2287                 break;
2288         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2289                 PM8001_IO_DBG(pm8001_ha,
2290                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2291                 ts->resp = SAS_TASK_UNDELIVERED;
2292                 ts->stat = SAS_DEV_NO_RESPONSE;
2293                 break;
2294         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2295                 PM8001_IO_DBG(pm8001_ha,
2296                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2297                 ts->resp = SAS_TASK_COMPLETE;
2298                 ts->stat = SAS_DATA_UNDERRUN;
2299                 break;
2300         case IO_XFER_OPEN_RETRY_TIMEOUT:
2301                 PM8001_IO_DBG(pm8001_ha,
2302                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2303                 ts->resp = SAS_TASK_COMPLETE;
2304                 ts->stat = SAS_OPEN_TO;
2305                 break;
2306         case IO_PORT_IN_RESET:
2307                 PM8001_IO_DBG(pm8001_ha,
2308                         pm8001_printk("IO_PORT_IN_RESET\n"));
2309                 ts->resp = SAS_TASK_COMPLETE;
2310                 ts->stat = SAS_DEV_NO_RESPONSE;
2311                 break;
2312         case IO_DS_NON_OPERATIONAL:
2313                 PM8001_IO_DBG(pm8001_ha,
2314                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2315                 ts->resp = SAS_TASK_COMPLETE;
2316                 ts->stat = SAS_DEV_NO_RESPONSE;
2317                 if (!t->uldd_task) {
2318                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2319                                         IO_DS_NON_OPERATIONAL);
2320                         ts->resp = SAS_TASK_UNDELIVERED;
2321                         ts->stat = SAS_QUEUE_FULL;
2322                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2323                         return;
2324                 }
2325                 break;
2326         case IO_DS_IN_RECOVERY:
2327                 PM8001_IO_DBG(pm8001_ha,
2328                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2329                 ts->resp = SAS_TASK_COMPLETE;
2330                 ts->stat = SAS_DEV_NO_RESPONSE;
2331                 break;
2332         case IO_DS_IN_ERROR:
2333                 PM8001_IO_DBG(pm8001_ha,
2334                         pm8001_printk("IO_DS_IN_ERROR\n"));
2335                 ts->resp = SAS_TASK_COMPLETE;
2336                 ts->stat = SAS_DEV_NO_RESPONSE;
2337                 if (!t->uldd_task) {
2338                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2339                                         IO_DS_IN_ERROR);
2340                         ts->resp = SAS_TASK_UNDELIVERED;
2341                         ts->stat = SAS_QUEUE_FULL;
2342                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2343                         return;
2344                 }
2345                 break;
2346         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2347                 PM8001_IO_DBG(pm8001_ha,
2348                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2349                 ts->resp = SAS_TASK_COMPLETE;
2350                 ts->stat = SAS_OPEN_REJECT;
2351                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2352                 break;
2353         default:
2354                 PM8001_IO_DBG(pm8001_ha,
2355                         pm8001_printk("Unknown status 0x%x\n", status));
2356                 /* not allowed case. Therefore, return failed status */
2357                 ts->resp = SAS_TASK_COMPLETE;
2358                 ts->stat = SAS_DEV_NO_RESPONSE;
2359                 break;
2360         }
2361         spin_lock_irqsave(&t->task_state_lock, flags);
2362         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2363         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2364         t->task_state_flags |= SAS_TASK_STATE_DONE;
2365         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2366                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2367                 PM8001_FAIL_DBG(pm8001_ha,
2368                         pm8001_printk("task 0x%p done with io_status 0x%x"
2369                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2370                         t, status, ts->resp, ts->stat));
2371                 if (t->slow_task)
2372                         complete(&t->slow_task->completion);
2373                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2374         } else {
2375                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2376                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2377         }
2378 }
2379
2380 /*See the comments for mpi_ssp_completion */
2381 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2382 {
2383         struct sas_task *t;
2384         struct task_status_struct *ts;
2385         struct pm8001_ccb_info *ccb;
2386         struct pm8001_device *pm8001_dev;
2387         struct sata_event_resp *psataPayload =
2388                 (struct sata_event_resp *)(piomb + 4);
2389         u32 event = le32_to_cpu(psataPayload->event);
2390         u32 tag = le32_to_cpu(psataPayload->tag);
2391         u32 port_id = le32_to_cpu(psataPayload->port_id);
2392         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2393         unsigned long flags;
2394
2395         ccb = &pm8001_ha->ccb_info[tag];
2396
2397         if (ccb) {
2398                 t = ccb->task;
2399                 pm8001_dev = ccb->device;
2400         } else {
2401                 PM8001_FAIL_DBG(pm8001_ha,
2402                         pm8001_printk("No CCB !!!. returning\n"));
2403                 return;
2404         }
2405         if (event)
2406                 PM8001_FAIL_DBG(pm8001_ha,
2407                         pm8001_printk("SATA EVENT 0x%x\n", event));
2408
2409         /* Check if this is NCQ error */
2410         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2411                 /* find device using device id */
2412                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2413                 /* send read log extension */
2414                 if (pm8001_dev)
2415                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2416                 return;
2417         }
2418
2419         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2420                 PM8001_FAIL_DBG(pm8001_ha,
2421                         pm8001_printk("task or dev null\n"));
2422                 return;
2423         }
2424
2425         ts = &t->task_status;
2426         PM8001_IO_DBG(pm8001_ha,
2427                 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2428                                 port_id, tag, event));
2429         switch (event) {
2430         case IO_OVERFLOW:
2431                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2432                 ts->resp = SAS_TASK_COMPLETE;
2433                 ts->stat = SAS_DATA_OVERRUN;
2434                 ts->residual = 0;
2435                 if (pm8001_dev)
2436                         pm8001_dev->running_req--;
2437                 break;
2438         case IO_XFER_ERROR_BREAK:
2439                 PM8001_IO_DBG(pm8001_ha,
2440                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2441                 ts->resp = SAS_TASK_COMPLETE;
2442                 ts->stat = SAS_INTERRUPTED;
2443                 break;
2444         case IO_XFER_ERROR_PHY_NOT_READY:
2445                 PM8001_IO_DBG(pm8001_ha,
2446                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2447                 ts->resp = SAS_TASK_COMPLETE;
2448                 ts->stat = SAS_OPEN_REJECT;
2449                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2450                 break;
2451         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2452                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2453                         "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2454                 ts->resp = SAS_TASK_COMPLETE;
2455                 ts->stat = SAS_OPEN_REJECT;
2456                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2457                 break;
2458         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2459                 PM8001_IO_DBG(pm8001_ha,
2460                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2461                 ts->resp = SAS_TASK_COMPLETE;
2462                 ts->stat = SAS_OPEN_REJECT;
2463                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2464                 break;
2465         case IO_OPEN_CNX_ERROR_BREAK:
2466                 PM8001_IO_DBG(pm8001_ha,
2467                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2468                 ts->resp = SAS_TASK_COMPLETE;
2469                 ts->stat = SAS_OPEN_REJECT;
2470                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2471                 break;
2472         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2473         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2474         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2475         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2476         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2477         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2478                 PM8001_FAIL_DBG(pm8001_ha,
2479                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2480                 ts->resp = SAS_TASK_UNDELIVERED;
2481                 ts->stat = SAS_DEV_NO_RESPONSE;
2482                 if (!t->uldd_task) {
2483                         pm8001_handle_event(pm8001_ha,
2484                                 pm8001_dev,
2485                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2486                         ts->resp = SAS_TASK_COMPLETE;
2487                         ts->stat = SAS_QUEUE_FULL;
2488                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2489                         return;
2490                 }
2491                 break;
2492         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2493                 PM8001_IO_DBG(pm8001_ha,
2494                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2495                 ts->resp = SAS_TASK_UNDELIVERED;
2496                 ts->stat = SAS_OPEN_REJECT;
2497                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2498                 break;
2499         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2500                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2501                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2502                 ts->resp = SAS_TASK_COMPLETE;
2503                 ts->stat = SAS_OPEN_REJECT;
2504                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2505                 break;
2506         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2507                 PM8001_IO_DBG(pm8001_ha,
2508                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2509                 ts->resp = SAS_TASK_COMPLETE;
2510                 ts->stat = SAS_OPEN_REJECT;
2511                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2512                 break;
2513         case IO_XFER_ERROR_NAK_RECEIVED:
2514                 PM8001_IO_DBG(pm8001_ha,
2515                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2516                 ts->resp = SAS_TASK_COMPLETE;
2517                 ts->stat = SAS_NAK_R_ERR;
2518                 break;
2519         case IO_XFER_ERROR_PEER_ABORTED:
2520                 PM8001_IO_DBG(pm8001_ha,
2521                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2522                 ts->resp = SAS_TASK_COMPLETE;
2523                 ts->stat = SAS_NAK_R_ERR;
2524                 break;
2525         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2526                 PM8001_IO_DBG(pm8001_ha,
2527                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2528                 ts->resp = SAS_TASK_COMPLETE;
2529                 ts->stat = SAS_DATA_UNDERRUN;
2530                 break;
2531         case IO_XFER_OPEN_RETRY_TIMEOUT:
2532                 PM8001_IO_DBG(pm8001_ha,
2533                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2534                 ts->resp = SAS_TASK_COMPLETE;
2535                 ts->stat = SAS_OPEN_TO;
2536                 break;
2537         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2538                 PM8001_IO_DBG(pm8001_ha,
2539                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2540                 ts->resp = SAS_TASK_COMPLETE;
2541                 ts->stat = SAS_OPEN_TO;
2542                 break;
2543         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2544                 PM8001_IO_DBG(pm8001_ha,
2545                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2546                 ts->resp = SAS_TASK_COMPLETE;
2547                 ts->stat = SAS_OPEN_TO;
2548                 break;
2549         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2550                 PM8001_IO_DBG(pm8001_ha,
2551                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2552                 ts->resp = SAS_TASK_COMPLETE;
2553                 ts->stat = SAS_OPEN_TO;
2554                 break;
2555         case IO_XFER_ERROR_OFFSET_MISMATCH:
2556                 PM8001_IO_DBG(pm8001_ha,
2557                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2558                 ts->resp = SAS_TASK_COMPLETE;
2559                 ts->stat = SAS_OPEN_TO;
2560                 break;
2561         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2562                 PM8001_IO_DBG(pm8001_ha,
2563                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2564                 ts->resp = SAS_TASK_COMPLETE;
2565                 ts->stat = SAS_OPEN_TO;
2566                 break;
2567         case IO_XFER_CMD_FRAME_ISSUED:
2568                 PM8001_IO_DBG(pm8001_ha,
2569                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2570                 break;
2571         case IO_XFER_PIO_SETUP_ERROR:
2572                 PM8001_IO_DBG(pm8001_ha,
2573                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2574                 ts->resp = SAS_TASK_COMPLETE;
2575                 ts->stat = SAS_OPEN_TO;
2576                 break;
2577         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2578                 PM8001_FAIL_DBG(pm8001_ha,
2579                         pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2580                 /* TBC: used default set values */
2581                 ts->resp = SAS_TASK_COMPLETE;
2582                 ts->stat = SAS_OPEN_TO;
2583                 break;
2584         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2585                 PM8001_FAIL_DBG(pm8001_ha,
2586                         pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2587                 /* TBC: used default set values */
2588                 ts->resp = SAS_TASK_COMPLETE;
2589                 ts->stat = SAS_OPEN_TO;
2590                 break;
2591         default:
2592                 PM8001_IO_DBG(pm8001_ha,
2593                         pm8001_printk("Unknown status 0x%x\n", event));
2594                 /* not allowed case. Therefore, return failed status */
2595                 ts->resp = SAS_TASK_COMPLETE;
2596                 ts->stat = SAS_OPEN_TO;
2597                 break;
2598         }
2599         spin_lock_irqsave(&t->task_state_lock, flags);
2600         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2601         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2602         t->task_state_flags |= SAS_TASK_STATE_DONE;
2603         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2604                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2605                 PM8001_FAIL_DBG(pm8001_ha,
2606                         pm8001_printk("task 0x%p done with io_status 0x%x"
2607                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2608                         t, event, ts->resp, ts->stat));
2609                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2610         } else {
2611                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2612                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2613         }
2614 }
2615
2616 /*See the comments for mpi_ssp_completion */
2617 static void
2618 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2619 {
2620         u32 param, i;
2621         struct sas_task *t;
2622         struct pm8001_ccb_info *ccb;
2623         unsigned long flags;
2624         u32 status;
2625         u32 tag;
2626         struct smp_completion_resp *psmpPayload;
2627         struct task_status_struct *ts;
2628         struct pm8001_device *pm8001_dev;
2629         char *pdma_respaddr = NULL;
2630
2631         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2632         status = le32_to_cpu(psmpPayload->status);
2633         tag = le32_to_cpu(psmpPayload->tag);
2634
2635         ccb = &pm8001_ha->ccb_info[tag];
2636         param = le32_to_cpu(psmpPayload->param);
2637         t = ccb->task;
2638         ts = &t->task_status;
2639         pm8001_dev = ccb->device;
2640         if (status)
2641                 PM8001_FAIL_DBG(pm8001_ha,
2642                         pm8001_printk("smp IO status 0x%x\n", status));
2643         if (unlikely(!t || !t->lldd_task || !t->dev))
2644                 return;
2645
2646         switch (status) {
2647
2648         case IO_SUCCESS:
2649                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2650                 ts->resp = SAS_TASK_COMPLETE;
2651                 ts->stat = SAM_STAT_GOOD;
2652                 if (pm8001_dev)
2653                         pm8001_dev->running_req--;
2654                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2655                         PM8001_IO_DBG(pm8001_ha,
2656                                 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2657                                                 param));
2658                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2659                                                 ((u64)sg_dma_address
2660                                                 (&t->smp_task.smp_resp))));
2661                         for (i = 0; i < param; i++) {
2662                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2663                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2664                                         "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2665                                         i, *(pdma_respaddr+i),
2666                                         psmpPayload->_r_a[i]));
2667                         }
2668                 }
2669                 break;
2670         case IO_ABORTED:
2671                 PM8001_IO_DBG(pm8001_ha,
2672                         pm8001_printk("IO_ABORTED IOMB\n"));
2673                 ts->resp = SAS_TASK_COMPLETE;
2674                 ts->stat = SAS_ABORTED_TASK;
2675                 if (pm8001_dev)
2676                         pm8001_dev->running_req--;
2677                 break;
2678         case IO_OVERFLOW:
2679                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2680                 ts->resp = SAS_TASK_COMPLETE;
2681                 ts->stat = SAS_DATA_OVERRUN;
2682                 ts->residual = 0;
2683                 if (pm8001_dev)
2684                         pm8001_dev->running_req--;
2685                 break;
2686         case IO_NO_DEVICE:
2687                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2688                 ts->resp = SAS_TASK_COMPLETE;
2689                 ts->stat = SAS_PHY_DOWN;
2690                 break;
2691         case IO_ERROR_HW_TIMEOUT:
2692                 PM8001_IO_DBG(pm8001_ha,
2693                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2694                 ts->resp = SAS_TASK_COMPLETE;
2695                 ts->stat = SAM_STAT_BUSY;
2696                 break;
2697         case IO_XFER_ERROR_BREAK:
2698                 PM8001_IO_DBG(pm8001_ha,
2699                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2700                 ts->resp = SAS_TASK_COMPLETE;
2701                 ts->stat = SAM_STAT_BUSY;
2702                 break;
2703         case IO_XFER_ERROR_PHY_NOT_READY:
2704                 PM8001_IO_DBG(pm8001_ha,
2705                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2706                 ts->resp = SAS_TASK_COMPLETE;
2707                 ts->stat = SAM_STAT_BUSY;
2708                 break;
2709         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2710                 PM8001_IO_DBG(pm8001_ha,
2711                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2712                 ts->resp = SAS_TASK_COMPLETE;
2713                 ts->stat = SAS_OPEN_REJECT;
2714                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2715                 break;
2716         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2717                 PM8001_IO_DBG(pm8001_ha,
2718                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2719                 ts->resp = SAS_TASK_COMPLETE;
2720                 ts->stat = SAS_OPEN_REJECT;
2721                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2722                 break;
2723         case IO_OPEN_CNX_ERROR_BREAK:
2724                 PM8001_IO_DBG(pm8001_ha,
2725                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2726                 ts->resp = SAS_TASK_COMPLETE;
2727                 ts->stat = SAS_OPEN_REJECT;
2728                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2729                 break;
2730         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2731         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2732         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2733         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2734         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2735         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2736                 PM8001_IO_DBG(pm8001_ha,
2737                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2738                 ts->resp = SAS_TASK_COMPLETE;
2739                 ts->stat = SAS_OPEN_REJECT;
2740                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2741                 pm8001_handle_event(pm8001_ha,
2742                                 pm8001_dev,
2743                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2744                 break;
2745         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2746                 PM8001_IO_DBG(pm8001_ha,
2747                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2748                 ts->resp = SAS_TASK_COMPLETE;
2749                 ts->stat = SAS_OPEN_REJECT;
2750                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2751                 break;
2752         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2753                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2754                         "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2755                 ts->resp = SAS_TASK_COMPLETE;
2756                 ts->stat = SAS_OPEN_REJECT;
2757                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2758                 break;
2759         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2760                 PM8001_IO_DBG(pm8001_ha,
2761                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2762                 ts->resp = SAS_TASK_COMPLETE;
2763                 ts->stat = SAS_OPEN_REJECT;
2764                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2765                 break;
2766         case IO_XFER_ERROR_RX_FRAME:
2767                 PM8001_IO_DBG(pm8001_ha,
2768                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2769                 ts->resp = SAS_TASK_COMPLETE;
2770                 ts->stat = SAS_DEV_NO_RESPONSE;
2771                 break;
2772         case IO_XFER_OPEN_RETRY_TIMEOUT:
2773                 PM8001_IO_DBG(pm8001_ha,
2774                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2775                 ts->resp = SAS_TASK_COMPLETE;
2776                 ts->stat = SAS_OPEN_REJECT;
2777                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2778                 break;
2779         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2780                 PM8001_IO_DBG(pm8001_ha,
2781                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2782                 ts->resp = SAS_TASK_COMPLETE;
2783                 ts->stat = SAS_QUEUE_FULL;
2784                 break;
2785         case IO_PORT_IN_RESET:
2786                 PM8001_IO_DBG(pm8001_ha,
2787                         pm8001_printk("IO_PORT_IN_RESET\n"));
2788                 ts->resp = SAS_TASK_COMPLETE;
2789                 ts->stat = SAS_OPEN_REJECT;
2790                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2791                 break;
2792         case IO_DS_NON_OPERATIONAL:
2793                 PM8001_IO_DBG(pm8001_ha,
2794                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2795                 ts->resp = SAS_TASK_COMPLETE;
2796                 ts->stat = SAS_DEV_NO_RESPONSE;
2797                 break;
2798         case IO_DS_IN_RECOVERY:
2799                 PM8001_IO_DBG(pm8001_ha,
2800                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2801                 ts->resp = SAS_TASK_COMPLETE;
2802                 ts->stat = SAS_OPEN_REJECT;
2803                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2804                 break;
2805         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2806                 PM8001_IO_DBG(pm8001_ha,
2807                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2808                 ts->resp = SAS_TASK_COMPLETE;
2809                 ts->stat = SAS_OPEN_REJECT;
2810                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2811                 break;
2812         default:
2813                 PM8001_IO_DBG(pm8001_ha,
2814                         pm8001_printk("Unknown status 0x%x\n", status));
2815                 ts->resp = SAS_TASK_COMPLETE;
2816                 ts->stat = SAS_DEV_NO_RESPONSE;
2817                 /* not allowed case. Therefore, return failed status */
2818                 break;
2819         }
2820         spin_lock_irqsave(&t->task_state_lock, flags);
2821         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2822         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2823         t->task_state_flags |= SAS_TASK_STATE_DONE;
2824         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2825                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2826                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2827                         "task 0x%p done with io_status 0x%x resp 0x%x"
2828                         "stat 0x%x but aborted by upper layer!\n",
2829                         t, status, ts->resp, ts->stat));
2830                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2831         } else {
2832                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2833                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2834                 mb();/* in order to force CPU ordering */
2835                 t->task_done(t);
2836         }
2837 }
2838
2839 /**
2840  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2841  * @pm8001_ha: our hba card information
2842  * @Qnum: the outbound queue message number.
2843  * @SEA: source of event to ack
2844  * @port_id: port id.
2845  * @phyId: phy id.
2846  * @param0: parameter 0.
2847  * @param1: parameter 1.
2848  */
2849 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2850         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2851 {
2852         struct hw_event_ack_req  payload;
2853         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2854
2855         struct inbound_queue_table *circularQ;
2856
2857         memset((u8 *)&payload, 0, sizeof(payload));
2858         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2859         payload.tag = cpu_to_le32(1);
2860         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2861                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2862         payload.param0 = cpu_to_le32(param0);
2863         payload.param1 = cpu_to_le32(param1);
2864         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2865 }
2866
2867 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2868         u32 phyId, u32 phy_op);
2869
2870 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2871                                         void *piomb)
2872 {
2873         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2874         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2875         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2876         u32 lr_status_evt_portid =
2877                 le32_to_cpu(pPayload->lr_status_evt_portid);
2878         u8 deviceType = pPayload->sas_identify.dev_type;
2879         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2880         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2881         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2882         struct pm8001_port *port = &pm8001_ha->port[port_id];
2883
2884         if (deviceType == SAS_END_DEVICE) {
2885                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2886                                         PHY_NOTIFY_ENABLE_SPINUP);
2887         }
2888
2889         port->wide_port_phymap |= (1U << phy_id);
2890         pm8001_get_lrate_mode(phy, link_rate);
2891         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2892         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2893         phy->phy_attached = 1;
2894 }
2895
2896 /**
2897  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2898  * @pm8001_ha: our hba card information
2899  * @piomb: IO message buffer
2900  */
2901 static void
2902 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2903 {
2904         struct hw_event_resp *pPayload =
2905                 (struct hw_event_resp *)(piomb + 4);
2906         u32 lr_status_evt_portid =
2907                 le32_to_cpu(pPayload->lr_status_evt_portid);
2908         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2909
2910         u8 link_rate =
2911                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2912         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2913         u8 phy_id =
2914                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2915         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2916
2917         struct pm8001_port *port = &pm8001_ha->port[port_id];
2918         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2919         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2920         unsigned long flags;
2921         u8 deviceType = pPayload->sas_identify.dev_type;
2922         port->port_state = portstate;
2923         port->wide_port_phymap |= (1U << phy_id);
2924         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2925         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2926                 "portid:%d; phyid:%d; linkrate:%d; "
2927                 "portstate:%x; devicetype:%x\n",
2928                 port_id, phy_id, link_rate, portstate, deviceType));
2929
2930         switch (deviceType) {
2931         case SAS_PHY_UNUSED:
2932                 PM8001_MSG_DBG(pm8001_ha,
2933                         pm8001_printk("device type no device.\n"));
2934                 break;
2935         case SAS_END_DEVICE:
2936                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2937                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2938                         PHY_NOTIFY_ENABLE_SPINUP);
2939                 port->port_attached = 1;
2940                 pm8001_get_lrate_mode(phy, link_rate);
2941                 break;
2942         case SAS_EDGE_EXPANDER_DEVICE:
2943                 PM8001_MSG_DBG(pm8001_ha,
2944                         pm8001_printk("expander device.\n"));
2945                 port->port_attached = 1;
2946                 pm8001_get_lrate_mode(phy, link_rate);
2947                 break;
2948         case SAS_FANOUT_EXPANDER_DEVICE:
2949                 PM8001_MSG_DBG(pm8001_ha,
2950                         pm8001_printk("fanout expander device.\n"));
2951                 port->port_attached = 1;
2952                 pm8001_get_lrate_mode(phy, link_rate);
2953                 break;
2954         default:
2955                 PM8001_MSG_DBG(pm8001_ha,
2956                         pm8001_printk("unknown device type(%x)\n", deviceType));
2957                 break;
2958         }
2959         phy->phy_type |= PORT_TYPE_SAS;
2960         phy->identify.device_type = deviceType;
2961         phy->phy_attached = 1;
2962         if (phy->identify.device_type == SAS_END_DEVICE)
2963                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2964         else if (phy->identify.device_type != SAS_PHY_UNUSED)
2965                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2966         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2967         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2968         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2969         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2970                 sizeof(struct sas_identify_frame)-4);
2971         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2972         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2973         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2974         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2975                 mdelay(200);/*delay a moment to wait disk to spinup*/
2976         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2977 }
2978
2979 /**
2980  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2981  * @pm8001_ha: our hba card information
2982  * @piomb: IO message buffer
2983  */
2984 static void
2985 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2986 {
2987         struct hw_event_resp *pPayload =
2988                 (struct hw_event_resp *)(piomb + 4);
2989         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2990         u32 lr_status_evt_portid =
2991                 le32_to_cpu(pPayload->lr_status_evt_portid);
2992         u8 link_rate =
2993                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2994         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2995         u8 phy_id =
2996                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2997
2998         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2999
3000         struct pm8001_port *port = &pm8001_ha->port[port_id];
3001         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3002         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3003         unsigned long flags;
3004         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3005                 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3006                                 port_id, phy_id, link_rate, portstate));
3007
3008         port->port_state = portstate;
3009         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3010         port->port_attached = 1;
3011         pm8001_get_lrate_mode(phy, link_rate);
3012         phy->phy_type |= PORT_TYPE_SATA;
3013         phy->phy_attached = 1;
3014         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3015         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3016         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3017         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3018                 sizeof(struct dev_to_host_fis));
3019         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3020         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3021         phy->identify.device_type = SAS_SATA_DEV;
3022         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3023         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3024         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3025 }
3026
3027 /**
3028  * hw_event_phy_down -we should notify the libsas the phy is down.
3029  * @pm8001_ha: our hba card information
3030  * @piomb: IO message buffer
3031  */
3032 static void
3033 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3034 {
3035         struct hw_event_resp *pPayload =
3036                 (struct hw_event_resp *)(piomb + 4);
3037
3038         u32 lr_status_evt_portid =
3039                 le32_to_cpu(pPayload->lr_status_evt_portid);
3040         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3041         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3042         u8 phy_id =
3043                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3044         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3045
3046         struct pm8001_port *port = &pm8001_ha->port[port_id];
3047         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3048         port->port_state = portstate;
3049         phy->identify.device_type = 0;
3050         phy->phy_attached = 0;
3051         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3052         switch (portstate) {
3053         case PORT_VALID:
3054                 break;
3055         case PORT_INVALID:
3056                 PM8001_MSG_DBG(pm8001_ha,
3057                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3058                 PM8001_MSG_DBG(pm8001_ha,
3059                         pm8001_printk(" Last phy Down and port invalid\n"));
3060                 if (phy->phy_type & PORT_TYPE_SATA) {
3061                         phy->phy_type = 0;
3062                         port->port_attached = 0;
3063                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3064                                         port_id, phy_id, 0, 0);
3065                 }
3066                 sas_phy_disconnected(&phy->sas_phy);
3067                 break;
3068         case PORT_IN_RESET:
3069                 PM8001_MSG_DBG(pm8001_ha,
3070                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3071                 break;
3072         case PORT_NOT_ESTABLISHED:
3073                 PM8001_MSG_DBG(pm8001_ha,
3074                         pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3075                 port->port_attached = 0;
3076                 break;
3077         case PORT_LOSTCOMM:
3078                 PM8001_MSG_DBG(pm8001_ha,
3079                         pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3080                 PM8001_MSG_DBG(pm8001_ha,
3081                         pm8001_printk(" Last phy Down and port invalid\n"));
3082                 if (phy->phy_type & PORT_TYPE_SATA) {
3083                         port->port_attached = 0;
3084                         phy->phy_type = 0;
3085                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3086                                         port_id, phy_id, 0, 0);
3087                 }
3088                 sas_phy_disconnected(&phy->sas_phy);
3089                 break;
3090         default:
3091                 port->port_attached = 0;
3092                 PM8001_MSG_DBG(pm8001_ha,
3093                         pm8001_printk(" Phy Down and(default) = 0x%x\n",
3094                         portstate));
3095                 break;
3096
3097         }
3098 }
3099
3100 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3101 {
3102         struct phy_start_resp *pPayload =
3103                 (struct phy_start_resp *)(piomb + 4);
3104         u32 status =
3105                 le32_to_cpu(pPayload->status);
3106         u32 phy_id =
3107                 le32_to_cpu(pPayload->phyid);
3108         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3109
3110         PM8001_INIT_DBG(pm8001_ha,
3111                 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3112                                 status, phy_id));
3113         if (status == 0) {
3114                 phy->phy_state = 1;
3115                 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3116                         complete(phy->enable_completion);
3117         }
3118         return 0;
3119
3120 }
3121
3122 /**
3123  * mpi_thermal_hw_event -The hw event has come.
3124  * @pm8001_ha: our hba card information
3125  * @piomb: IO message buffer
3126  */
3127 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3128 {
3129         struct thermal_hw_event *pPayload =
3130                 (struct thermal_hw_event *)(piomb + 4);
3131
3132         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3133         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3134
3135         if (thermal_event & 0x40) {
3136                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3137                         "Thermal Event: Local high temperature violated!\n"));
3138                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3139                         "Thermal Event: Measured local high temperature %d\n",
3140                                 ((rht_lht & 0xFF00) >> 8)));
3141         }
3142         if (thermal_event & 0x10) {
3143                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3144                         "Thermal Event: Remote high temperature violated!\n"));
3145                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3146                         "Thermal Event: Measured remote high temperature %d\n",
3147                                 ((rht_lht & 0xFF000000) >> 24)));
3148         }
3149         return 0;
3150 }
3151
3152 /**
3153  * mpi_hw_event -The hw event has come.
3154  * @pm8001_ha: our hba card information
3155  * @piomb: IO message buffer
3156  */
3157 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3158 {
3159         unsigned long flags, i;
3160         struct hw_event_resp *pPayload =
3161                 (struct hw_event_resp *)(piomb + 4);
3162         u32 lr_status_evt_portid =
3163                 le32_to_cpu(pPayload->lr_status_evt_portid);
3164         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3165         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3166         u8 phy_id =
3167                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3168         u16 eventType =
3169                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3170         u8 status =
3171                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3172         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3173         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3174         struct pm8001_port *port = &pm8001_ha->port[port_id];
3175         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3176         PM8001_MSG_DBG(pm8001_ha,
3177                 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3178                                 port_id, phy_id, eventType, status));
3179
3180         switch (eventType) {
3181
3182         case HW_EVENT_SAS_PHY_UP:
3183                 PM8001_MSG_DBG(pm8001_ha,
3184                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3185                 hw_event_sas_phy_up(pm8001_ha, piomb);
3186                 break;
3187         case HW_EVENT_SATA_PHY_UP:
3188                 PM8001_MSG_DBG(pm8001_ha,
3189                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3190                 hw_event_sata_phy_up(pm8001_ha, piomb);
3191                 break;
3192         case HW_EVENT_SATA_SPINUP_HOLD:
3193                 PM8001_MSG_DBG(pm8001_ha,
3194                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3195                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3196                 break;
3197         case HW_EVENT_PHY_DOWN:
3198                 PM8001_MSG_DBG(pm8001_ha,
3199                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3200                 if (phy->phy_type & PORT_TYPE_SATA)
3201                         sas_ha->notify_phy_event(&phy->sas_phy,
3202                                 PHYE_LOSS_OF_SIGNAL);
3203                 phy->phy_attached = 0;
3204                 phy->phy_state = 0;
3205                 hw_event_phy_down(pm8001_ha, piomb);
3206                 break;
3207         case HW_EVENT_PORT_INVALID:
3208                 PM8001_MSG_DBG(pm8001_ha,
3209                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3210                 sas_phy_disconnected(sas_phy);
3211                 phy->phy_attached = 0;
3212                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3213                 break;
3214         /* the broadcast change primitive received, tell the LIBSAS this event
3215         to revalidate the sas domain*/
3216         case HW_EVENT_BROADCAST_CHANGE:
3217                 PM8001_MSG_DBG(pm8001_ha,
3218                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3219                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3220                         port_id, phy_id, 1, 0);
3221                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3222                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3223                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3224                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3225                 break;
3226         case HW_EVENT_PHY_ERROR:
3227                 PM8001_MSG_DBG(pm8001_ha,
3228                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3229                 sas_phy_disconnected(&phy->sas_phy);
3230                 phy->phy_attached = 0;
3231                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3232                 break;
3233         case HW_EVENT_BROADCAST_EXP:
3234                 PM8001_MSG_DBG(pm8001_ha,
3235                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3236                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3237                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3238                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3239                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3240                 break;
3241         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3242                 PM8001_MSG_DBG(pm8001_ha,
3243                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3244                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3245                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3246                 break;
3247         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3248                 PM8001_MSG_DBG(pm8001_ha,
3249                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3250                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3251                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3252                         port_id, phy_id, 0, 0);
3253                 break;
3254         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3255                 PM8001_MSG_DBG(pm8001_ha,
3256                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3257                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3258                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3259                         port_id, phy_id, 0, 0);
3260                 break;
3261         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3262                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3263                                 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3264                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3265                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3266                         port_id, phy_id, 0, 0);
3267                 break;
3268         case HW_EVENT_MALFUNCTION:
3269                 PM8001_MSG_DBG(pm8001_ha,
3270                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3271                 break;
3272         case HW_EVENT_BROADCAST_SES:
3273                 PM8001_MSG_DBG(pm8001_ha,
3274                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3275                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3276                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3277                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3278                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3279                 break;
3280         case HW_EVENT_INBOUND_CRC_ERROR:
3281                 PM8001_MSG_DBG(pm8001_ha,
3282                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3283                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3284                         HW_EVENT_INBOUND_CRC_ERROR,
3285                         port_id, phy_id, 0, 0);
3286                 break;
3287         case HW_EVENT_HARD_RESET_RECEIVED:
3288                 PM8001_MSG_DBG(pm8001_ha,
3289                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3290                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3291                 break;
3292         case HW_EVENT_ID_FRAME_TIMEOUT:
3293                 PM8001_MSG_DBG(pm8001_ha,
3294                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3295                 sas_phy_disconnected(sas_phy);
3296                 phy->phy_attached = 0;
3297                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3298                 break;
3299         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3300                 PM8001_MSG_DBG(pm8001_ha,
3301                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3302                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3303                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3304                         port_id, phy_id, 0, 0);
3305                 sas_phy_disconnected(sas_phy);
3306                 phy->phy_attached = 0;
3307                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3308                 break;
3309         case HW_EVENT_PORT_RESET_TIMER_TMO:
3310                 PM8001_MSG_DBG(pm8001_ha,
3311                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3312                 sas_phy_disconnected(sas_phy);
3313                 phy->phy_attached = 0;
3314                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3315                 break;
3316         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3317                 PM8001_MSG_DBG(pm8001_ha,
3318                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3319                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3320                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3321                         port_id, phy_id, 0, 0);
3322                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3323                         if (port->wide_port_phymap & (1 << i)) {
3324                                 phy = &pm8001_ha->phy[i];
3325                                 sas_ha->notify_phy_event(&phy->sas_phy,
3326                                                 PHYE_LOSS_OF_SIGNAL);
3327                                 port->wide_port_phymap &= ~(1 << i);
3328                         }
3329                 }
3330                 break;
3331         case HW_EVENT_PORT_RECOVER:
3332                 PM8001_MSG_DBG(pm8001_ha,
3333                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3334                 hw_event_port_recover(pm8001_ha, piomb);
3335                 break;
3336         case HW_EVENT_PORT_RESET_COMPLETE:
3337                 PM8001_MSG_DBG(pm8001_ha,
3338                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3339                 break;
3340         case EVENT_BROADCAST_ASYNCH_EVENT:
3341                 PM8001_MSG_DBG(pm8001_ha,
3342                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3343                 break;
3344         default:
3345                 PM8001_MSG_DBG(pm8001_ha,
3346                         pm8001_printk("Unknown event type 0x%x\n", eventType));
3347                 break;
3348         }
3349         return 0;
3350 }
3351
3352 /**
3353  * mpi_phy_stop_resp - SPCv specific
3354  * @pm8001_ha: our hba card information
3355  * @piomb: IO message buffer
3356  */
3357 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3358 {
3359         struct phy_stop_resp *pPayload =
3360                 (struct phy_stop_resp *)(piomb + 4);
3361         u32 status =
3362                 le32_to_cpu(pPayload->status);
3363         u32 phyid =
3364                 le32_to_cpu(pPayload->phyid);
3365         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3366         PM8001_MSG_DBG(pm8001_ha,
3367                         pm8001_printk("phy:0x%x status:0x%x\n",
3368                                         phyid, status));
3369         if (status == 0)
3370                 phy->phy_state = 0;
3371         return 0;
3372 }
3373
3374 /**
3375  * mpi_set_controller_config_resp - SPCv specific
3376  * @pm8001_ha: our hba card information
3377  * @piomb: IO message buffer
3378  */
3379 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3380                         void *piomb)
3381 {
3382         struct set_ctrl_cfg_resp *pPayload =
3383                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3384         u32 status = le32_to_cpu(pPayload->status);
3385         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3386
3387         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3388                         "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3389                         status, err_qlfr_pgcd));
3390
3391         return 0;
3392 }
3393
3394 /**
3395  * mpi_get_controller_config_resp - SPCv specific
3396  * @pm8001_ha: our hba card information
3397  * @piomb: IO message buffer
3398  */
3399 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3400                         void *piomb)
3401 {
3402         PM8001_MSG_DBG(pm8001_ha,
3403                         pm8001_printk(" pm80xx_addition_functionality\n"));
3404
3405         return 0;
3406 }
3407
3408 /**
3409  * mpi_get_phy_profile_resp - SPCv specific
3410  * @pm8001_ha: our hba card information
3411  * @piomb: IO message buffer
3412  */
3413 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3414                         void *piomb)
3415 {
3416         PM8001_MSG_DBG(pm8001_ha,
3417                         pm8001_printk(" pm80xx_addition_functionality\n"));
3418
3419         return 0;
3420 }
3421
3422 /**
3423  * mpi_flash_op_ext_resp - SPCv specific
3424  * @pm8001_ha: our hba card information
3425  * @piomb: IO message buffer
3426  */
3427 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3428 {
3429         PM8001_MSG_DBG(pm8001_ha,
3430                         pm8001_printk(" pm80xx_addition_functionality\n"));
3431
3432         return 0;
3433 }
3434
3435 /**
3436  * mpi_set_phy_profile_resp - SPCv specific
3437  * @pm8001_ha: our hba card information
3438  * @piomb: IO message buffer
3439  */
3440 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3441                         void *piomb)
3442 {
3443         u8 page_code;
3444         struct set_phy_profile_resp *pPayload =
3445                 (struct set_phy_profile_resp *)(piomb + 4);
3446         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3447         u32 status = le32_to_cpu(pPayload->status);
3448
3449         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3450         if (status) {
3451                 /* status is FAILED */
3452                 PM8001_FAIL_DBG(pm8001_ha,
3453                         pm8001_printk("PhyProfile command failed  with status "
3454                         "0x%08X \n", status));
3455                 return -1;
3456         } else {
3457                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3458                         PM8001_FAIL_DBG(pm8001_ha,
3459                                 pm8001_printk("Invalid page code 0x%X\n",
3460                                         page_code));
3461                         return -1;
3462                 }
3463         }
3464         return 0;
3465 }
3466
3467 /**
3468  * mpi_kek_management_resp - SPCv specific
3469  * @pm8001_ha: our hba card information
3470  * @piomb: IO message buffer
3471  */
3472 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3473                         void *piomb)
3474 {
3475         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3476
3477         u32 status = le32_to_cpu(pPayload->status);
3478         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3479         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3480
3481         PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3482                 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3483                 status, kidx_new_curr_ksop, err_qlfr));
3484
3485         return 0;
3486 }
3487
3488 /**
3489  * mpi_dek_management_resp - SPCv specific
3490  * @pm8001_ha: our hba card information
3491  * @piomb: IO message buffer
3492  */
3493 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3494                         void *piomb)
3495 {
3496         PM8001_MSG_DBG(pm8001_ha,
3497                         pm8001_printk(" pm80xx_addition_functionality\n"));
3498
3499         return 0;
3500 }
3501
3502 /**
3503  * ssp_coalesced_comp_resp - SPCv specific
3504  * @pm8001_ha: our hba card information
3505  * @piomb: IO message buffer
3506  */
3507 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3508                         void *piomb)
3509 {
3510         PM8001_MSG_DBG(pm8001_ha,
3511                         pm8001_printk(" pm80xx_addition_functionality\n"));
3512
3513         return 0;
3514 }
3515
3516 /**
3517  * process_one_iomb - process one outbound Queue memory block
3518  * @pm8001_ha: our hba card information
3519  * @piomb: IO message buffer
3520  */
3521 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3522 {
3523         __le32 pHeader = *(__le32 *)piomb;
3524         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3525
3526         switch (opc) {
3527         case OPC_OUB_ECHO:
3528                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3529                 break;
3530         case OPC_OUB_HW_EVENT:
3531                 PM8001_MSG_DBG(pm8001_ha,
3532                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3533                 mpi_hw_event(pm8001_ha, piomb);
3534                 break;
3535         case OPC_OUB_THERM_HW_EVENT:
3536                 PM8001_MSG_DBG(pm8001_ha,
3537                         pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3538                 mpi_thermal_hw_event(pm8001_ha, piomb);
3539                 break;
3540         case OPC_OUB_SSP_COMP:
3541                 PM8001_MSG_DBG(pm8001_ha,
3542                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3543                 mpi_ssp_completion(pm8001_ha, piomb);
3544                 break;
3545         case OPC_OUB_SMP_COMP:
3546                 PM8001_MSG_DBG(pm8001_ha,
3547                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3548                 mpi_smp_completion(pm8001_ha, piomb);
3549                 break;
3550         case OPC_OUB_LOCAL_PHY_CNTRL:
3551                 PM8001_MSG_DBG(pm8001_ha,
3552                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3553                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3554                 break;
3555         case OPC_OUB_DEV_REGIST:
3556                 PM8001_MSG_DBG(pm8001_ha,
3557                 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3558                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3559                 break;
3560         case OPC_OUB_DEREG_DEV:
3561                 PM8001_MSG_DBG(pm8001_ha,
3562                         pm8001_printk("unregister the device\n"));
3563                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3564                 break;
3565         case OPC_OUB_GET_DEV_HANDLE:
3566                 PM8001_MSG_DBG(pm8001_ha,
3567                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3568                 break;
3569         case OPC_OUB_SATA_COMP:
3570                 PM8001_MSG_DBG(pm8001_ha,
3571                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3572                 mpi_sata_completion(pm8001_ha, piomb);
3573                 break;
3574         case OPC_OUB_SATA_EVENT:
3575                 PM8001_MSG_DBG(pm8001_ha,
3576                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3577                 mpi_sata_event(pm8001_ha, piomb);
3578                 break;
3579         case OPC_OUB_SSP_EVENT:
3580                 PM8001_MSG_DBG(pm8001_ha,
3581                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3582                 mpi_ssp_event(pm8001_ha, piomb);
3583                 break;
3584         case OPC_OUB_DEV_HANDLE_ARRIV:
3585                 PM8001_MSG_DBG(pm8001_ha,
3586                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3587                 /*This is for target*/
3588                 break;
3589         case OPC_OUB_SSP_RECV_EVENT:
3590                 PM8001_MSG_DBG(pm8001_ha,
3591                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3592                 /*This is for target*/
3593                 break;
3594         case OPC_OUB_FW_FLASH_UPDATE:
3595                 PM8001_MSG_DBG(pm8001_ha,
3596                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3597                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3598                 break;
3599         case OPC_OUB_GPIO_RESPONSE:
3600                 PM8001_MSG_DBG(pm8001_ha,
3601                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3602                 break;
3603         case OPC_OUB_GPIO_EVENT:
3604                 PM8001_MSG_DBG(pm8001_ha,
3605                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3606                 break;
3607         case OPC_OUB_GENERAL_EVENT:
3608                 PM8001_MSG_DBG(pm8001_ha,
3609                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3610                 pm8001_mpi_general_event(pm8001_ha, piomb);
3611                 break;
3612         case OPC_OUB_SSP_ABORT_RSP:
3613                 PM8001_MSG_DBG(pm8001_ha,
3614                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3615                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3616                 break;
3617         case OPC_OUB_SATA_ABORT_RSP:
3618                 PM8001_MSG_DBG(pm8001_ha,
3619                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3620                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3621                 break;
3622         case OPC_OUB_SAS_DIAG_MODE_START_END:
3623                 PM8001_MSG_DBG(pm8001_ha,
3624                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3625                 break;
3626         case OPC_OUB_SAS_DIAG_EXECUTE:
3627                 PM8001_MSG_DBG(pm8001_ha,
3628                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3629                 break;
3630         case OPC_OUB_GET_TIME_STAMP:
3631                 PM8001_MSG_DBG(pm8001_ha,
3632                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3633                 break;
3634         case OPC_OUB_SAS_HW_EVENT_ACK:
3635                 PM8001_MSG_DBG(pm8001_ha,
3636                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3637                 break;
3638         case OPC_OUB_PORT_CONTROL:
3639                 PM8001_MSG_DBG(pm8001_ha,
3640                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3641                 break;
3642         case OPC_OUB_SMP_ABORT_RSP:
3643                 PM8001_MSG_DBG(pm8001_ha,
3644                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3645                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3646                 break;
3647         case OPC_OUB_GET_NVMD_DATA:
3648                 PM8001_MSG_DBG(pm8001_ha,
3649                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3650                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3651                 break;
3652         case OPC_OUB_SET_NVMD_DATA:
3653                 PM8001_MSG_DBG(pm8001_ha,
3654                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3655                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3656                 break;
3657         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3658                 PM8001_MSG_DBG(pm8001_ha,
3659                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3660                 break;
3661         case OPC_OUB_SET_DEVICE_STATE:
3662                 PM8001_MSG_DBG(pm8001_ha,
3663                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3664                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3665                 break;
3666         case OPC_OUB_GET_DEVICE_STATE:
3667                 PM8001_MSG_DBG(pm8001_ha,
3668                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3669                 break;
3670         case OPC_OUB_SET_DEV_INFO:
3671                 PM8001_MSG_DBG(pm8001_ha,
3672                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3673                 break;
3674         /* spcv specifc commands */
3675         case OPC_OUB_PHY_START_RESP:
3676                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3677                         "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3678                 mpi_phy_start_resp(pm8001_ha, piomb);
3679                 break;
3680         case OPC_OUB_PHY_STOP_RESP:
3681                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3682                         "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3683                 mpi_phy_stop_resp(pm8001_ha, piomb);
3684                 break;
3685         case OPC_OUB_SET_CONTROLLER_CONFIG:
3686                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3687                         "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3688                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3689                 break;
3690         case OPC_OUB_GET_CONTROLLER_CONFIG:
3691                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3692                         "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3693                 mpi_get_controller_config_resp(pm8001_ha, piomb);
3694                 break;
3695         case OPC_OUB_GET_PHY_PROFILE:
3696                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3697                         "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3698                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3699                 break;
3700         case OPC_OUB_FLASH_OP_EXT:
3701                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3702                         "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3703                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3704                 break;
3705         case OPC_OUB_SET_PHY_PROFILE:
3706                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3707                         "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3708                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3709                 break;
3710         case OPC_OUB_KEK_MANAGEMENT_RESP:
3711                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3712                         "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3713                 mpi_kek_management_resp(pm8001_ha, piomb);
3714                 break;
3715         case OPC_OUB_DEK_MANAGEMENT_RESP:
3716                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3717                         "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3718                 mpi_dek_management_resp(pm8001_ha, piomb);
3719                 break;
3720         case OPC_OUB_SSP_COALESCED_COMP_RESP:
3721                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3722                         "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3723                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3724                 break;
3725         default:
3726                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3727                         "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3728                 break;
3729         }
3730 }
3731
3732 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
3733 {
3734         PM8001_FAIL_DBG(pm8001_ha,
3735                 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
3736                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
3737         PM8001_FAIL_DBG(pm8001_ha,
3738                 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
3739                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
3740         PM8001_FAIL_DBG(pm8001_ha,
3741                 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
3742                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
3743         PM8001_FAIL_DBG(pm8001_ha,
3744                 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
3745                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
3746         PM8001_FAIL_DBG(pm8001_ha,
3747                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
3748                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
3749         PM8001_FAIL_DBG(pm8001_ha,
3750                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
3751                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
3752         PM8001_FAIL_DBG(pm8001_ha,
3753                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
3754                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
3755         PM8001_FAIL_DBG(pm8001_ha,
3756                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
3757                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
3758         PM8001_FAIL_DBG(pm8001_ha,
3759                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
3760                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
3761         PM8001_FAIL_DBG(pm8001_ha,
3762                 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
3763                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
3764         PM8001_FAIL_DBG(pm8001_ha,
3765                 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
3766                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
3767         PM8001_FAIL_DBG(pm8001_ha,
3768                 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
3769                         pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
3770 }
3771
3772 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3773 {
3774         struct outbound_queue_table *circularQ;
3775         void *pMsg1 = NULL;
3776         u8 uninitialized_var(bc);
3777         u32 ret = MPI_IO_STATUS_FAIL;
3778         unsigned long flags;
3779         u32 regval;
3780
3781         if (vec == (pm8001_ha->number_of_intr - 1)) {
3782                 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
3783                 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
3784                                         SCRATCH_PAD_MIPSALL_READY) {
3785                         pm8001_ha->controller_fatal_error = true;
3786                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3787                                 "Firmware Fatal error! Regval:0x%x\n", regval));
3788                         print_scratchpad_registers(pm8001_ha);
3789                         return ret;
3790                 }
3791         }
3792         spin_lock_irqsave(&pm8001_ha->lock, flags);
3793         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3794         do {
3795                 /* spurious interrupt during setup if kexec-ing and
3796                  * driver doing a doorbell access w/ the pre-kexec oq
3797                  * interrupt setup.
3798                  */
3799                 if (!circularQ->pi_virt)
3800                         break;
3801                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3802                 if (MPI_IO_STATUS_SUCCESS == ret) {
3803                         /* process the outbound message */
3804                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3805                         /* free the message from the outbound circular buffer */
3806                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3807                                                         circularQ, bc);
3808                 }
3809                 if (MPI_IO_STATUS_BUSY == ret) {
3810                         /* Update the producer index from SPC */
3811                         circularQ->producer_index =
3812                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3813                         if (le32_to_cpu(circularQ->producer_index) ==
3814                                 circularQ->consumer_idx)
3815                                 /* OQ is empty */
3816                                 break;
3817                 }
3818         } while (1);
3819         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3820         return ret;
3821 }
3822
3823 /* PCI_DMA_... to our direction translation. */
3824 static const u8 data_dir_flags[] = {
3825         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3826         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3827         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3828         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3829 };
3830
3831 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3832                         struct smp_req *psmp_cmd, int mode, int length)
3833 {
3834         psmp_cmd->tag = hTag;
3835         psmp_cmd->device_id = cpu_to_le32(deviceID);
3836         if (mode == SMP_DIRECT) {
3837                 length = length - 4; /* subtract crc */
3838                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3839         } else {
3840                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3841         }
3842 }
3843
3844 /**
3845  * pm8001_chip_smp_req - send a SMP task to FW
3846  * @pm8001_ha: our hba card information.
3847  * @ccb: the ccb information this request used.
3848  */
3849 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3850         struct pm8001_ccb_info *ccb)
3851 {
3852         int elem, rc;
3853         struct sas_task *task = ccb->task;
3854         struct domain_device *dev = task->dev;
3855         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3856         struct scatterlist *sg_req, *sg_resp;
3857         u32 req_len, resp_len;
3858         struct smp_req smp_cmd;
3859         u32 opc;
3860         struct inbound_queue_table *circularQ;
3861         char *preq_dma_addr = NULL;
3862         __le64 tmp_addr;
3863         u32 i, length;
3864
3865         memset(&smp_cmd, 0, sizeof(smp_cmd));
3866         /*
3867          * DMA-map SMP request, response buffers
3868          */
3869         sg_req = &task->smp_task.smp_req;
3870         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3871         if (!elem)
3872                 return -ENOMEM;
3873         req_len = sg_dma_len(sg_req);
3874
3875         sg_resp = &task->smp_task.smp_resp;
3876         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3877         if (!elem) {
3878                 rc = -ENOMEM;
3879                 goto err_out;
3880         }
3881         resp_len = sg_dma_len(sg_resp);
3882         /* must be in dwords */
3883         if ((req_len & 0x3) || (resp_len & 0x3)) {
3884                 rc = -EINVAL;
3885                 goto err_out_2;
3886         }
3887
3888         opc = OPC_INB_SMP_REQUEST;
3889         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3890         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3891
3892         length = sg_req->length;
3893         PM8001_IO_DBG(pm8001_ha,
3894                 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3895         if (!(length - 8))
3896                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3897         else
3898                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3899
3900
3901         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3902         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3903
3904         /* INDIRECT MODE command settings. Use DMA */
3905         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3906                 PM8001_IO_DBG(pm8001_ha,
3907                         pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3908                 /* for SPCv indirect mode. Place the top 4 bytes of
3909                  * SMP Request header here. */
3910                 for (i = 0; i < 4; i++)
3911                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3912                 /* exclude top 4 bytes for SMP req header */
3913                 smp_cmd.long_smp_req.long_req_addr =
3914                         cpu_to_le64((u64)sg_dma_address
3915                                 (&task->smp_task.smp_req) + 4);
3916                 /* exclude 4 bytes for SMP req header and CRC */
3917                 smp_cmd.long_smp_req.long_req_size =
3918                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3919                 smp_cmd.long_smp_req.long_resp_addr =
3920                                 cpu_to_le64((u64)sg_dma_address
3921                                         (&task->smp_task.smp_resp));
3922                 smp_cmd.long_smp_req.long_resp_size =
3923                                 cpu_to_le32((u32)sg_dma_len
3924                                         (&task->smp_task.smp_resp)-4);
3925         } else { /* DIRECT MODE */
3926                 smp_cmd.long_smp_req.long_req_addr =
3927                         cpu_to_le64((u64)sg_dma_address
3928                                         (&task->smp_task.smp_req));
3929                 smp_cmd.long_smp_req.long_req_size =
3930                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3931                 smp_cmd.long_smp_req.long_resp_addr =
3932                         cpu_to_le64((u64)sg_dma_address
3933                                 (&task->smp_task.smp_resp));
3934                 smp_cmd.long_smp_req.long_resp_size =
3935                         cpu_to_le32
3936                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3937         }
3938         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3939                 PM8001_IO_DBG(pm8001_ha,
3940                         pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3941                 for (i = 0; i < length; i++)
3942                         if (i < 16) {
3943                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3944                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3945                                         "Byte[%d]:%x (DMA data:%x)\n",
3946                                         i, smp_cmd.smp_req16[i],
3947                                         *(preq_dma_addr)));
3948                         } else {
3949                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3950                                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3951                                         "Byte[%d]:%x (DMA data:%x)\n",
3952                                         i, smp_cmd.smp_req[i],
3953                                         *(preq_dma_addr)));
3954                         }
3955         }
3956
3957         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3958                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3959         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3960                                         (u32 *)&smp_cmd, 0);
3961         if (rc)
3962                 goto err_out_2;
3963         return 0;
3964
3965 err_out_2:
3966         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3967                         PCI_DMA_FROMDEVICE);
3968 err_out:
3969         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3970                         PCI_DMA_TODEVICE);
3971         return rc;
3972 }
3973
3974 static int check_enc_sas_cmd(struct sas_task *task)
3975 {
3976         u8 cmd = task->ssp_task.cmd->cmnd[0];
3977
3978         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3979                 return 1;
3980         else
3981                 return 0;
3982 }
3983
3984 static int check_enc_sat_cmd(struct sas_task *task)
3985 {
3986         int ret = 0;
3987         switch (task->ata_task.fis.command) {
3988         case ATA_CMD_FPDMA_READ:
3989         case ATA_CMD_READ_EXT:
3990         case ATA_CMD_READ:
3991         case ATA_CMD_FPDMA_WRITE:
3992         case ATA_CMD_WRITE_EXT:
3993         case ATA_CMD_WRITE:
3994         case ATA_CMD_PIO_READ:
3995         case ATA_CMD_PIO_READ_EXT:
3996         case ATA_CMD_PIO_WRITE:
3997         case ATA_CMD_PIO_WRITE_EXT:
3998                 ret = 1;
3999                 break;
4000         default:
4001                 ret = 0;
4002                 break;
4003         }
4004         return ret;
4005 }
4006
4007 /**
4008  * pm80xx_chip_ssp_io_req - send a SSP task to FW
4009  * @pm8001_ha: our hba card information.
4010  * @ccb: the ccb information this request used.
4011  */
4012 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4013         struct pm8001_ccb_info *ccb)
4014 {
4015         struct sas_task *task = ccb->task;
4016         struct domain_device *dev = task->dev;
4017         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4018         struct ssp_ini_io_start_req ssp_cmd;
4019         u32 tag = ccb->ccb_tag;
4020         int ret;
4021         u64 phys_addr, start_addr, end_addr;
4022         u32 end_addr_high, end_addr_low;
4023         struct inbound_queue_table *circularQ;
4024         u32 q_index;
4025         u32 opc = OPC_INB_SSPINIIOSTART;
4026         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4027         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4028         /* data address domain added for spcv; set to 0 by host,
4029          * used internally by controller
4030          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4031          */
4032         ssp_cmd.dad_dir_m_tlr =
4033                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4034         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4035         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4036         ssp_cmd.tag = cpu_to_le32(tag);
4037         if (task->ssp_task.enable_first_burst)
4038                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4039         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4040         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4041         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4042                        task->ssp_task.cmd->cmd_len);
4043         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4044         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4045
4046         /* Check if encryption is set */
4047         if (pm8001_ha->chip->encrypt &&
4048                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4049                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4050                         "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4051                         task->ssp_task.cmd->cmnd[0]));
4052                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4053                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4054                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4055                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4056
4057                 /* fill in PRD (scatter/gather) table, if any */
4058                 if (task->num_scatter > 1) {
4059                         pm8001_chip_make_sg(task->scatter,
4060                                                 ccb->n_elem, ccb->buf_prd);
4061                         phys_addr = ccb->ccb_dma_handle +
4062                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4063                         ssp_cmd.enc_addr_low =
4064                                 cpu_to_le32(lower_32_bits(phys_addr));
4065                         ssp_cmd.enc_addr_high =
4066                                 cpu_to_le32(upper_32_bits(phys_addr));
4067                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4068                 } else if (task->num_scatter == 1) {
4069                         u64 dma_addr = sg_dma_address(task->scatter);
4070                         ssp_cmd.enc_addr_low =
4071                                 cpu_to_le32(lower_32_bits(dma_addr));
4072                         ssp_cmd.enc_addr_high =
4073                                 cpu_to_le32(upper_32_bits(dma_addr));
4074                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4075                         ssp_cmd.enc_esgl = 0;
4076                         /* Check 4G Boundary */
4077                         start_addr = cpu_to_le64(dma_addr);
4078                         end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4079                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4080                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4081                         if (end_addr_high != ssp_cmd.enc_addr_high) {
4082                                 PM8001_FAIL_DBG(pm8001_ha,
4083                                         pm8001_printk("The sg list address "
4084                                         "start_addr=0x%016llx data_len=0x%x "
4085                                         "end_addr_high=0x%08x end_addr_low="
4086                                         "0x%08x has crossed 4G boundary\n",
4087                                                 start_addr, ssp_cmd.enc_len,
4088                                                 end_addr_high, end_addr_low));
4089                                 pm8001_chip_make_sg(task->scatter, 1,
4090                                         ccb->buf_prd);
4091                                 phys_addr = ccb->ccb_dma_handle +
4092                                         offsetof(struct pm8001_ccb_info,
4093                                                 buf_prd[0]);
4094                                 ssp_cmd.enc_addr_low =
4095                                         cpu_to_le32(lower_32_bits(phys_addr));
4096                                 ssp_cmd.enc_addr_high =
4097                                         cpu_to_le32(upper_32_bits(phys_addr));
4098                                 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4099                         }
4100                 } else if (task->num_scatter == 0) {
4101                         ssp_cmd.enc_addr_low = 0;
4102                         ssp_cmd.enc_addr_high = 0;
4103                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4104                         ssp_cmd.enc_esgl = 0;
4105                 }
4106                 /* XTS mode. All other fields are 0 */
4107                 ssp_cmd.key_cmode = 0x6 << 4;
4108                 /* set tweak values. Should be the start lba */
4109                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4110                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4111                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4112                                                 (task->ssp_task.cmd->cmnd[5]));
4113         } else {
4114                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4115                         "Sending Normal SAS command 0x%x inb q %x\n",
4116                         task->ssp_task.cmd->cmnd[0], q_index));
4117                 /* fill in PRD (scatter/gather) table, if any */
4118                 if (task->num_scatter > 1) {
4119                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4120                                         ccb->buf_prd);
4121                         phys_addr = ccb->ccb_dma_handle +
4122                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4123                         ssp_cmd.addr_low =
4124                                 cpu_to_le32(lower_32_bits(phys_addr));
4125                         ssp_cmd.addr_high =
4126                                 cpu_to_le32(upper_32_bits(phys_addr));
4127                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4128                 } else if (task->num_scatter == 1) {
4129                         u64 dma_addr = sg_dma_address(task->scatter);
4130                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4131                         ssp_cmd.addr_high =
4132                                 cpu_to_le32(upper_32_bits(dma_addr));
4133                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4134                         ssp_cmd.esgl = 0;
4135                         /* Check 4G Boundary */
4136                         start_addr = cpu_to_le64(dma_addr);
4137                         end_addr = (start_addr + ssp_cmd.len) - 1;
4138                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4139                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4140                         if (end_addr_high != ssp_cmd.addr_high) {
4141                                 PM8001_FAIL_DBG(pm8001_ha,
4142                                         pm8001_printk("The sg list address "
4143                                         "start_addr=0x%016llx data_len=0x%x "
4144                                         "end_addr_high=0x%08x end_addr_low="
4145                                         "0x%08x has crossed 4G boundary\n",
4146                                                  start_addr, ssp_cmd.len,
4147                                                  end_addr_high, end_addr_low));
4148                                 pm8001_chip_make_sg(task->scatter, 1,
4149                                         ccb->buf_prd);
4150                                 phys_addr = ccb->ccb_dma_handle +
4151                                         offsetof(struct pm8001_ccb_info,
4152                                                  buf_prd[0]);
4153                                 ssp_cmd.addr_low =
4154                                         cpu_to_le32(lower_32_bits(phys_addr));
4155                                 ssp_cmd.addr_high =
4156                                         cpu_to_le32(upper_32_bits(phys_addr));
4157                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4158                         }
4159                 } else if (task->num_scatter == 0) {
4160                         ssp_cmd.addr_low = 0;
4161                         ssp_cmd.addr_high = 0;
4162                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4163                         ssp_cmd.esgl = 0;
4164                 }
4165         }
4166         q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4167         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4168                                                 &ssp_cmd, q_index);
4169         return ret;
4170 }
4171
4172 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4173         struct pm8001_ccb_info *ccb)
4174 {
4175         struct sas_task *task = ccb->task;
4176         struct domain_device *dev = task->dev;
4177         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4178         u32 tag = ccb->ccb_tag;
4179         int ret;
4180         u32 q_index;
4181         struct sata_start_req sata_cmd;
4182         u32 hdr_tag, ncg_tag = 0;
4183         u64 phys_addr, start_addr, end_addr;
4184         u32 end_addr_high, end_addr_low;
4185         u32 ATAP = 0x0;
4186         u32 dir;
4187         struct inbound_queue_table *circularQ;
4188         unsigned long flags;
4189         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4190         memset(&sata_cmd, 0, sizeof(sata_cmd));
4191         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4192         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4193
4194         if (task->data_dir == PCI_DMA_NONE) {
4195                 ATAP = 0x04; /* no data*/
4196                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4197         } else if (likely(!task->ata_task.device_control_reg_update)) {
4198                 if (task->ata_task.dma_xfer) {
4199                         ATAP = 0x06; /* DMA */
4200                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4201                 } else {
4202                         ATAP = 0x05; /* PIO*/
4203                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4204                 }
4205                 if (task->ata_task.use_ncq &&
4206                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4207                         ATAP = 0x07; /* FPDMA */
4208                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4209                 }
4210         }
4211         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4212                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4213                 ncg_tag = hdr_tag;
4214         }
4215         dir = data_dir_flags[task->data_dir] << 8;
4216         sata_cmd.tag = cpu_to_le32(tag);
4217         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4218         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4219
4220         sata_cmd.sata_fis = task->ata_task.fis;
4221         if (likely(!task->ata_task.device_control_reg_update))
4222                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4223         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4224
4225         /* Check if encryption is set */
4226         if (pm8001_ha->chip->encrypt &&
4227                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4228                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4229                         "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4230                         sata_cmd.sata_fis.command));
4231                 opc = OPC_INB_SATA_DIF_ENC_IO;
4232
4233                 /* set encryption bit */
4234                 sata_cmd.ncqtag_atap_dir_m_dad =
4235                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4236                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4237                                                         /* dad (bit 0-1) is 0 */
4238                 /* fill in PRD (scatter/gather) table, if any */
4239                 if (task->num_scatter > 1) {
4240                         pm8001_chip_make_sg(task->scatter,
4241                                                 ccb->n_elem, ccb->buf_prd);
4242                         phys_addr = ccb->ccb_dma_handle +
4243                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4244                         sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4245                         sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4246                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4247                 } else if (task->num_scatter == 1) {
4248                         u64 dma_addr = sg_dma_address(task->scatter);
4249                         sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4250                         sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4251                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4252                         sata_cmd.enc_esgl = 0;
4253                         /* Check 4G Boundary */
4254                         start_addr = cpu_to_le64(dma_addr);
4255                         end_addr = (start_addr + sata_cmd.enc_len) - 1;
4256                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4257                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4258                         if (end_addr_high != sata_cmd.enc_addr_high) {
4259                                 PM8001_FAIL_DBG(pm8001_ha,
4260                                         pm8001_printk("The sg list address "
4261                                         "start_addr=0x%016llx data_len=0x%x "
4262                                         "end_addr_high=0x%08x end_addr_low"
4263                                         "=0x%08x has crossed 4G boundary\n",
4264                                                 start_addr, sata_cmd.enc_len,
4265                                                 end_addr_high, end_addr_low));
4266                                 pm8001_chip_make_sg(task->scatter, 1,
4267                                         ccb->buf_prd);
4268                                 phys_addr = ccb->ccb_dma_handle +
4269                                                 offsetof(struct pm8001_ccb_info,
4270                                                 buf_prd[0]);
4271                                 sata_cmd.enc_addr_low =
4272                                         lower_32_bits(phys_addr);
4273                                 sata_cmd.enc_addr_high =
4274                                         upper_32_bits(phys_addr);
4275                                 sata_cmd.enc_esgl =
4276                                         cpu_to_le32(1 << 31);
4277                         }
4278                 } else if (task->num_scatter == 0) {
4279                         sata_cmd.enc_addr_low = 0;
4280                         sata_cmd.enc_addr_high = 0;
4281                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4282                         sata_cmd.enc_esgl = 0;
4283                 }
4284                 /* XTS mode. All other fields are 0 */
4285                 sata_cmd.key_index_mode = 0x6 << 4;
4286                 /* set tweak values. Should be the start lba */
4287                 sata_cmd.twk_val0 =
4288                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4289                                         (sata_cmd.sata_fis.lbah << 16) |
4290                                         (sata_cmd.sata_fis.lbam << 8) |
4291                                         (sata_cmd.sata_fis.lbal));
4292                 sata_cmd.twk_val1 =
4293                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4294                                          (sata_cmd.sata_fis.lbam_exp));
4295         } else {
4296                 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4297                         "Sending Normal SATA command 0x%x inb %x\n",
4298                         sata_cmd.sata_fis.command, q_index));
4299                 /* dad (bit 0-1) is 0 */
4300                 sata_cmd.ncqtag_atap_dir_m_dad =
4301                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4302                                         ((ATAP & 0x3f) << 10) | dir);
4303
4304                 /* fill in PRD (scatter/gather) table, if any */
4305                 if (task->num_scatter > 1) {
4306                         pm8001_chip_make_sg(task->scatter,
4307                                         ccb->n_elem, ccb->buf_prd);
4308                         phys_addr = ccb->ccb_dma_handle +
4309                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4310                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4311                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4312                         sata_cmd.esgl = cpu_to_le32(1 << 31);
4313                 } else if (task->num_scatter == 1) {
4314                         u64 dma_addr = sg_dma_address(task->scatter);
4315                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4316                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4317                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4318                         sata_cmd.esgl = 0;
4319                         /* Check 4G Boundary */
4320                         start_addr = cpu_to_le64(dma_addr);
4321                         end_addr = (start_addr + sata_cmd.len) - 1;
4322                         end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4323                         end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4324                         if (end_addr_high != sata_cmd.addr_high) {
4325                                 PM8001_FAIL_DBG(pm8001_ha,
4326                                         pm8001_printk("The sg list address "
4327                                         "start_addr=0x%016llx data_len=0x%x"
4328                                         "end_addr_high=0x%08x end_addr_low="
4329                                         "0x%08x has crossed 4G boundary\n",
4330                                                 start_addr, sata_cmd.len,
4331                                                 end_addr_high, end_addr_low));
4332                                 pm8001_chip_make_sg(task->scatter, 1,
4333                                         ccb->buf_prd);
4334                                 phys_addr = ccb->ccb_dma_handle +
4335                                         offsetof(struct pm8001_ccb_info,
4336                                         buf_prd[0]);
4337                                 sata_cmd.addr_low =
4338                                         lower_32_bits(phys_addr);
4339                                 sata_cmd.addr_high =
4340                                         upper_32_bits(phys_addr);
4341                                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4342                         }
4343                 } else if (task->num_scatter == 0) {
4344                         sata_cmd.addr_low = 0;
4345                         sata_cmd.addr_high = 0;
4346                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4347                         sata_cmd.esgl = 0;
4348                 }
4349                         /* scsi cdb */
4350                         sata_cmd.atapi_scsi_cdb[0] =
4351                                 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4352                                 (task->ata_task.atapi_packet[1] << 8) |
4353                                 (task->ata_task.atapi_packet[2] << 16) |
4354                                 (task->ata_task.atapi_packet[3] << 24)));
4355                         sata_cmd.atapi_scsi_cdb[1] =
4356                                 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4357                                 (task->ata_task.atapi_packet[5] << 8) |
4358                                 (task->ata_task.atapi_packet[6] << 16) |
4359                                 (task->ata_task.atapi_packet[7] << 24)));
4360                         sata_cmd.atapi_scsi_cdb[2] =
4361                                 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4362                                 (task->ata_task.atapi_packet[9] << 8) |
4363                                 (task->ata_task.atapi_packet[10] << 16) |
4364                                 (task->ata_task.atapi_packet[11] << 24)));
4365                         sata_cmd.atapi_scsi_cdb[3] =
4366                                 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4367                                 (task->ata_task.atapi_packet[13] << 8) |
4368                                 (task->ata_task.atapi_packet[14] << 16) |
4369                                 (task->ata_task.atapi_packet[15] << 24)));
4370         }
4371
4372         /* Check for read log for failed drive and return */
4373         if (sata_cmd.sata_fis.command == 0x2f) {
4374                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4375                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4376                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4377                         struct task_status_struct *ts;
4378
4379                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4380                         ts = &task->task_status;
4381
4382                         spin_lock_irqsave(&task->task_state_lock, flags);
4383                         ts->resp = SAS_TASK_COMPLETE;
4384                         ts->stat = SAM_STAT_GOOD;
4385                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4386                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4387                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4388                         if (unlikely((task->task_state_flags &
4389                                         SAS_TASK_STATE_ABORTED))) {
4390                                 spin_unlock_irqrestore(&task->task_state_lock,
4391                                                         flags);
4392                                 PM8001_FAIL_DBG(pm8001_ha,
4393                                         pm8001_printk("task 0x%p resp 0x%x "
4394                                         " stat 0x%x but aborted by upper layer "
4395                                         "\n", task, ts->resp, ts->stat));
4396                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4397                                 return 0;
4398                         } else {
4399                                 spin_unlock_irqrestore(&task->task_state_lock,
4400                                                         flags);
4401                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4402                                                                 ccb, tag);
4403                                 return 0;
4404                         }
4405                 }
4406         }
4407         q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4408         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4409                                                 &sata_cmd, q_index);
4410         return ret;
4411 }
4412
4413 /**
4414  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4415  * @pm8001_ha: our hba card information.
4416  * @num: the inbound queue number
4417  * @phy_id: the phy id which we wanted to start up.
4418  */
4419 static int
4420 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4421 {
4422         struct phy_start_req payload;
4423         struct inbound_queue_table *circularQ;
4424         int ret;
4425         u32 tag = 0x01;
4426         u32 opcode = OPC_INB_PHYSTART;
4427         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4428         memset(&payload, 0, sizeof(payload));
4429         payload.tag = cpu_to_le32(tag);
4430
4431         PM8001_INIT_DBG(pm8001_ha,
4432                 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4433         /*
4434          ** [0:7]       PHY Identifier
4435          ** [8:11]      link rate 1.5G, 3G, 6G
4436          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4437          ** [14]        0b disable spin up hold; 1b enable spin up hold
4438          ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4439          */
4440         if (!IS_SPCV_12G(pm8001_ha->pdev))
4441                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4442                                 LINKMODE_AUTO | LINKRATE_15 |
4443                                 LINKRATE_30 | LINKRATE_60 | phy_id);
4444         else
4445                 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4446                                 LINKMODE_AUTO | LINKRATE_15 |
4447                                 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4448                                 phy_id);
4449
4450         /* SSC Disable and SAS Analog ST configuration */
4451         /**
4452         payload.ase_sh_lm_slr_phyid =
4453                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4454                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4455                 phy_id);
4456         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4457         **/
4458
4459         payload.sas_identify.dev_type = SAS_END_DEVICE;
4460         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4461         memcpy(payload.sas_identify.sas_addr,
4462                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4463         payload.sas_identify.phy_id = phy_id;
4464         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4465         return ret;
4466 }
4467
4468 /**
4469  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4470  * @pm8001_ha: our hba card information.
4471  * @num: the inbound queue number
4472  * @phy_id: the phy id which we wanted to start up.
4473  */
4474 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4475         u8 phy_id)
4476 {
4477         struct phy_stop_req payload;
4478         struct inbound_queue_table *circularQ;
4479         int ret;
4480         u32 tag = 0x01;
4481         u32 opcode = OPC_INB_PHYSTOP;
4482         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4483         memset(&payload, 0, sizeof(payload));
4484         payload.tag = cpu_to_le32(tag);
4485         payload.phy_id = cpu_to_le32(phy_id);
4486         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4487         return ret;
4488 }
4489
4490 /**
4491  * see comments on pm8001_mpi_reg_resp.
4492  */
4493 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4494         struct pm8001_device *pm8001_dev, u32 flag)
4495 {
4496         struct reg_dev_req payload;
4497         u32     opc;
4498         u32 stp_sspsmp_sata = 0x4;
4499         struct inbound_queue_table *circularQ;
4500         u32 linkrate, phy_id;
4501         int rc, tag = 0xdeadbeef;
4502         struct pm8001_ccb_info *ccb;
4503         u8 retryFlag = 0x1;
4504         u16 firstBurstSize = 0;
4505         u16 ITNT = 2000;
4506         struct domain_device *dev = pm8001_dev->sas_device;
4507         struct domain_device *parent_dev = dev->parent;
4508         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4509
4510         memset(&payload, 0, sizeof(payload));
4511         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4512         if (rc)
4513                 return rc;
4514         ccb = &pm8001_ha->ccb_info[tag];
4515         ccb->device = pm8001_dev;
4516         ccb->ccb_tag = tag;
4517         payload.tag = cpu_to_le32(tag);
4518
4519         if (flag == 1) {
4520                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4521         } else {
4522                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4523                         stp_sspsmp_sata = 0x00; /* stp*/
4524                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4525                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4526                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4527                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4528         }
4529         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4530                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4531         else
4532                 phy_id = pm8001_dev->attached_phy;
4533
4534         opc = OPC_INB_REG_DEV;
4535
4536         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4537                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4538
4539         payload.phyid_portid =
4540                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4541                 ((phy_id & 0xFF) << 8));
4542
4543         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4544                 ((linkrate & 0x0F) << 24) |
4545                 ((stp_sspsmp_sata & 0x03) << 28));
4546         payload.firstburstsize_ITNexustimeout =
4547                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4548
4549         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4550                 SAS_ADDR_SIZE);
4551
4552         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4553         if (rc)
4554                 pm8001_tag_free(pm8001_ha, tag);
4555
4556         return rc;
4557 }
4558
4559 /**
4560  * pm80xx_chip_phy_ctl_req - support the local phy operation
4561  * @pm8001_ha: our hba card information.
4562  * @num: the inbound queue number
4563  * @phy_id: the phy id which we wanted to operate
4564  * @phy_op:
4565  */
4566 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4567         u32 phyId, u32 phy_op)
4568 {
4569         struct local_phy_ctl_req payload;
4570         struct inbound_queue_table *circularQ;
4571         int ret;
4572         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4573         memset(&payload, 0, sizeof(payload));
4574         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4575         payload.tag = cpu_to_le32(1);
4576         payload.phyop_phyid =
4577                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4578         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4579         return ret;
4580 }
4581
4582 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4583 {
4584         u32 value;
4585 #ifdef PM8001_USE_MSIX
4586         return 1;
4587 #endif
4588         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4589         if (value)
4590                 return 1;
4591         return 0;
4592
4593 }
4594
4595 /**
4596  * pm8001_chip_isr - PM8001 isr handler.
4597  * @pm8001_ha: our hba card information.
4598  * @irq: irq number.
4599  * @stat: stat.
4600  */
4601 static irqreturn_t
4602 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4603 {
4604         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4605         process_oq(pm8001_ha, vec);
4606         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4607         return IRQ_HANDLED;
4608 }
4609
4610 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4611         u32 operation, u32 phyid, u32 length, u32 *buf)
4612 {
4613         u32 tag , i, j = 0;
4614         int rc;
4615         struct set_phy_profile_req payload;
4616         struct inbound_queue_table *circularQ;
4617         u32 opc = OPC_INB_SET_PHY_PROFILE;
4618
4619         memset(&payload, 0, sizeof(payload));
4620         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4621         if (rc)
4622                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4623         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4624         payload.tag = cpu_to_le32(tag);
4625         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4626         PM8001_INIT_DBG(pm8001_ha,
4627                 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4628                         payload.ppc_phyid, length));
4629         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4630                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4631                 j++;
4632         }
4633         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4634         if (rc)
4635                 pm8001_tag_free(pm8001_ha, tag);
4636 }
4637
4638 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4639         u32 length, u8 *buf)
4640 {
4641         u32 page_code, i;
4642
4643         page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4644         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4645                 mpi_set_phy_profile_req(pm8001_ha,
4646                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4647                 length = length + PHY_DWORD_LENGTH;
4648         }
4649         PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4650 }
4651
4652 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4653                 u32 phy, u32 length, u32 *buf)
4654 {
4655         u32 tag, opc;
4656         int rc, i;
4657         struct set_phy_profile_req payload;
4658         struct inbound_queue_table *circularQ;
4659
4660         memset(&payload, 0, sizeof(payload));
4661
4662         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4663         if (rc)
4664                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4665
4666         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4667         opc = OPC_INB_SET_PHY_PROFILE;
4668
4669         payload.tag = cpu_to_le32(tag);
4670         payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4671                                 | (phy & 0xFF));
4672
4673         for (i = 0; i < length; i++)
4674                 payload.reserved[i] = cpu_to_le32(*(buf + i));
4675
4676         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4677         if (rc)
4678                 pm8001_tag_free(pm8001_ha, tag);
4679
4680         PM8001_INIT_DBG(pm8001_ha,
4681                 pm8001_printk("PHY %d settings applied", phy));
4682 }
4683 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4684         .name                   = "pmc80xx",
4685         .chip_init              = pm80xx_chip_init,
4686         .chip_soft_rst          = pm80xx_chip_soft_rst,
4687         .chip_rst               = pm80xx_hw_chip_rst,
4688         .chip_iounmap           = pm8001_chip_iounmap,
4689         .isr                    = pm80xx_chip_isr,
4690         .is_our_interupt        = pm80xx_chip_is_our_interupt,
4691         .isr_process_oq         = process_oq,
4692         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4693         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4694         .make_prd               = pm8001_chip_make_sg,
4695         .smp_req                = pm80xx_chip_smp_req,
4696         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4697         .sata_req               = pm80xx_chip_sata_req,
4698         .phy_start_req          = pm80xx_chip_phy_start_req,
4699         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4700         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4701         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4702         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
4703         .task_abort             = pm8001_chip_abort_task,
4704         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4705         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4706         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4707         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4708         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4709 };