2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
47 #define SMP_INDIRECT 2
50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
73 u32 index, value, offset;
75 destination1 = (u32 *)destination;
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index / 4);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len , reg_val, index, *temp;
97 char *fatal_error_data = buf;
99 pm8001_ha->forensic_info.data_buf.direct_data = buf;
100 if (pm8001_ha->chip_id == chip_8001) {
101 pm8001_ha->forensic_info.data_buf.direct_data +=
102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
103 "Not supported for SPC controller");
104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
107 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
108 PM8001_IO_DBG(pm8001_ha,
109 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
110 direct_data = (u8 *)fatal_error_data;
111 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
112 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
113 pm8001_ha->forensic_info.data_buf.read_len = 0;
115 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
117 /* start to get data */
118 /* Program the MEMBASE II Shifting Register with 0x00.*/
119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
120 pm8001_ha->fatal_forensic_shift_offset);
121 pm8001_ha->forensic_last_offset = 0;
122 pm8001_ha->forensic_fatal_step = 0;
123 pm8001_ha->fatal_bar_loc = 0;
126 /* Read until accum_len is retrived */
127 accum_len = pm8001_mr32(fatal_table_address,
128 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
129 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
131 if (accum_len == 0xFFFFFFFF) {
132 PM8001_IO_DBG(pm8001_ha,
133 pm8001_printk("Possible PCI issue 0x%x not expected\n",
137 if (accum_len == 0 || accum_len >= 0x100000) {
138 pm8001_ha->forensic_info.data_buf.direct_data +=
139 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
140 "%08x ", 0xFFFFFFFF);
141 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
144 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
145 if (pm8001_ha->forensic_fatal_step == 0) {
147 if (pm8001_ha->forensic_info.data_buf.direct_data) {
148 /* Data is in bar, copy to host memory */
149 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
150 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
151 pm8001_ha->forensic_info.data_buf.direct_len ,
154 pm8001_ha->fatal_bar_loc +=
155 pm8001_ha->forensic_info.data_buf.direct_len;
156 pm8001_ha->forensic_info.data_buf.direct_offset +=
157 pm8001_ha->forensic_info.data_buf.direct_len;
158 pm8001_ha->forensic_last_offset +=
159 pm8001_ha->forensic_info.data_buf.direct_len;
160 pm8001_ha->forensic_info.data_buf.read_len =
161 pm8001_ha->forensic_info.data_buf.direct_len;
163 if (pm8001_ha->forensic_last_offset >= accum_len) {
164 pm8001_ha->forensic_info.data_buf.direct_data +=
165 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
167 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
168 pm8001_ha->forensic_info.data_buf.direct_data +=
170 forensic_info.data_buf.direct_data,
171 "%08x ", *(temp + index));
174 pm8001_ha->fatal_bar_loc = 0;
175 pm8001_ha->forensic_fatal_step = 1;
176 pm8001_ha->fatal_forensic_shift_offset = 0;
177 pm8001_ha->forensic_last_offset = 0;
178 return (char *)pm8001_ha->
179 forensic_info.data_buf.direct_data -
182 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
185 forensic_info.data_buf.direct_data,
187 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
188 pm8001_ha->forensic_info.data_buf.direct_data +=
190 forensic_info.data_buf.direct_data,
191 "%08x ", *(temp + index));
193 return (char *)pm8001_ha->
194 forensic_info.data_buf.direct_data -
198 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
199 pm8001_ha->forensic_info.data_buf.direct_data +=
200 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
202 for (index = 0; index < 256; index++) {
203 pm8001_ha->forensic_info.data_buf.direct_data +=
205 forensic_info.data_buf.direct_data,
206 "%08x ", *(temp + index));
208 pm8001_ha->fatal_forensic_shift_offset += 0x100;
209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
210 pm8001_ha->fatal_forensic_shift_offset);
211 pm8001_ha->fatal_bar_loc = 0;
212 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
215 if (pm8001_ha->forensic_fatal_step == 1) {
216 pm8001_ha->fatal_forensic_shift_offset = 0;
217 /* Read 64K of the debug data. */
218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
219 pm8001_ha->fatal_forensic_shift_offset);
220 pm8001_mw32(fatal_table_address,
221 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
222 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
224 /* Poll FDDHSHK until clear */
225 start = jiffies + (2 * HZ); /* 2 sec */
228 reg_val = pm8001_mr32(fatal_table_address,
229 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
230 } while ((reg_val) && time_before(jiffies, start));
233 PM8001_FAIL_DBG(pm8001_ha,
234 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
235 " = 0x%x\n", reg_val));
239 /* Read the next 64K of the debug data. */
240 pm8001_ha->forensic_fatal_step = 0;
241 if (pm8001_mr32(fatal_table_address,
242 MPI_FATAL_EDUMP_TABLE_STATUS) !=
243 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
244 pm8001_mw32(fatal_table_address,
245 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
248 pm8001_ha->forensic_info.data_buf.direct_data +=
250 forensic_info.data_buf.direct_data,
252 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
253 pm8001_ha->forensic_info.data_buf.direct_len = 0;
254 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
255 pm8001_ha->forensic_info.data_buf.read_len = 0;
259 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
264 * read_main_config_table - read the configure table and save it.
265 * @pm8001_ha: our hba card information
267 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
269 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
272 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
273 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
274 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
275 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
276 pm8001_mr32(address, MAIN_FW_REVISION);
277 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
278 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
279 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
280 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
281 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
282 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
283 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
284 pm8001_mr32(address, MAIN_GST_OFFSET);
285 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
286 pm8001_mr32(address, MAIN_IBQ_OFFSET);
287 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
288 pm8001_mr32(address, MAIN_OBQ_OFFSET);
290 /* read Error Dump Offset and Length */
291 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
292 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
293 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
294 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
295 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
296 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
297 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
298 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
300 /* read GPIO LED settings from the configuration table */
301 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
302 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
304 /* read analog Setting offset from the configuration table */
305 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
306 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
309 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
310 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
311 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
312 /* read port recover and reset timeout */
313 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
314 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
318 * read_general_status_table - read the general status table and save it.
319 * @pm8001_ha: our hba card information
321 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
323 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
324 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
325 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
326 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
327 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
328 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
329 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
330 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
331 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
332 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
333 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
334 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
335 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
336 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
337 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
338 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
339 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
340 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
341 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
342 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
343 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
344 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
345 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
346 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
347 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
348 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
349 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
350 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
351 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
354 * read_phy_attr_table - read the phy attribute table and save it.
355 * @pm8001_ha: our hba card information
357 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
359 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
360 pm8001_ha->phy_attr_table.phystart1_16[0] =
361 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
362 pm8001_ha->phy_attr_table.phystart1_16[1] =
363 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
364 pm8001_ha->phy_attr_table.phystart1_16[2] =
365 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
366 pm8001_ha->phy_attr_table.phystart1_16[3] =
367 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
368 pm8001_ha->phy_attr_table.phystart1_16[4] =
369 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
370 pm8001_ha->phy_attr_table.phystart1_16[5] =
371 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
372 pm8001_ha->phy_attr_table.phystart1_16[6] =
373 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
374 pm8001_ha->phy_attr_table.phystart1_16[7] =
375 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
376 pm8001_ha->phy_attr_table.phystart1_16[8] =
377 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
378 pm8001_ha->phy_attr_table.phystart1_16[9] =
379 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
380 pm8001_ha->phy_attr_table.phystart1_16[10] =
381 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
382 pm8001_ha->phy_attr_table.phystart1_16[11] =
383 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
384 pm8001_ha->phy_attr_table.phystart1_16[12] =
385 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
386 pm8001_ha->phy_attr_table.phystart1_16[13] =
387 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
388 pm8001_ha->phy_attr_table.phystart1_16[14] =
389 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
390 pm8001_ha->phy_attr_table.phystart1_16[15] =
391 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
393 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
394 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
395 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
396 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
397 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
398 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
399 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
400 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
401 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
402 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
403 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
404 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
405 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
406 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
407 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
408 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
409 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
410 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
411 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
412 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
413 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
414 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
415 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
416 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
417 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
418 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
419 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
420 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
421 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
422 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
423 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
424 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
429 * read_inbnd_queue_table - read the inbound queue table and save it.
430 * @pm8001_ha: our hba card information
432 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
435 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
436 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
437 u32 offset = i * 0x20;
438 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
439 get_pci_bar_index(pm8001_mr32(address,
440 (offset + IB_PIPCI_BAR)));
441 pm8001_ha->inbnd_q_tbl[i].pi_offset =
442 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
447 * read_outbnd_queue_table - read the outbound queue table and save it.
448 * @pm8001_ha: our hba card information
450 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
453 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
454 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
455 u32 offset = i * 0x24;
456 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
457 get_pci_bar_index(pm8001_mr32(address,
458 (offset + OB_CIPCI_BAR)));
459 pm8001_ha->outbnd_q_tbl[i].ci_offset =
460 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
465 * init_default_table_values - init the default table.
466 * @pm8001_ha: our hba card information
468 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
471 u32 offsetib, offsetob;
472 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
473 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
475 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
476 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
477 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
478 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
479 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
480 PM8001_EVENT_LOG_SIZE;
481 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
482 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
483 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
484 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
485 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
486 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
487 PM8001_EVENT_LOG_SIZE;
488 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
489 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
491 /* Disable end to end CRC checking */
492 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
494 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
495 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
496 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
497 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
498 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
499 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
500 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
501 pm8001_ha->inbnd_q_tbl[i].base_virt =
502 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
503 pm8001_ha->inbnd_q_tbl[i].total_length =
504 pm8001_ha->memoryMap.region[IB + i].total_len;
505 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
506 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
507 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
508 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
509 pm8001_ha->inbnd_q_tbl[i].ci_virt =
510 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
512 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
513 get_pci_bar_index(pm8001_mr32(addressib,
515 pm8001_ha->inbnd_q_tbl[i].pi_offset =
516 pm8001_mr32(addressib, (offsetib + 0x18));
517 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
518 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
520 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
521 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
522 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
523 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
524 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
525 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
526 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
527 pm8001_ha->outbnd_q_tbl[i].base_virt =
528 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
529 pm8001_ha->outbnd_q_tbl[i].total_length =
530 pm8001_ha->memoryMap.region[OB + i].total_len;
531 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
532 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
533 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
534 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
535 /* interrupt vector based on oq */
536 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
537 pm8001_ha->outbnd_q_tbl[i].pi_virt =
538 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
540 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
541 get_pci_bar_index(pm8001_mr32(addressob,
543 pm8001_ha->outbnd_q_tbl[i].ci_offset =
544 pm8001_mr32(addressob, (offsetob + 0x18));
545 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
546 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
551 * update_main_config_table - update the main default table to the HBA.
552 * @pm8001_ha: our hba card information
554 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
556 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
557 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
559 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
561 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
562 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
563 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
565 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
567 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
569 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
570 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
571 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
572 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
573 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
575 /* Update Fatal error interrupt vector */
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
577 ((pm8001_ha->number_of_intr - 1) << 8);
578 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
580 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
584 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
585 /* Set GPIOLED to 0x2 for LED indicator */
586 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
587 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
590 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
591 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
592 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
595 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
597 PORT_RECOVERY_TIMEOUT;
598 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
599 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
603 * update_inbnd_queue_table - update the inbound queue table to the HBA.
604 * @pm8001_ha: our hba card information
606 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
609 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
610 u16 offset = number * 0x20;
611 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
612 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
613 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
614 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
615 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
616 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
617 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
618 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
619 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
620 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
624 * update_outbnd_queue_table - update the outbound queue table to the HBA.
625 * @pm8001_ha: our hba card information
627 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
630 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
631 u16 offset = number * 0x24;
632 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
633 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
634 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
635 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
636 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
637 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
638 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
639 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
640 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
641 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
642 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
643 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
647 * mpi_init_check - check firmware initialization status.
648 * @pm8001_ha: our hba card information
650 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
654 u32 gst_len_mpistate;
656 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
658 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
659 /* wait until Inbound DoorBell Clear Register toggled */
660 if (IS_SPCV_12G(pm8001_ha->pdev)) {
661 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
663 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
667 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
668 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
669 } while ((value != 0) && (--max_wait_count));
673 /* check the MPI-State for initialization upto 100ms*/
674 max_wait_count = 100 * 1000;/* 100 msec */
678 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
679 GST_GSTLEN_MPIS_OFFSET);
680 } while ((GST_MPI_STATE_INIT !=
681 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
685 /* check MPI Initialization error */
686 gst_len_mpistate = gst_len_mpistate >> 16;
687 if (0x0000 != gst_len_mpistate)
694 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
695 * @pm8001_ha: our hba card information
697 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
704 /* reset / PCIe ready */
705 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
708 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
709 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
711 /* check ila status */
712 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
715 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
716 } while (((value & SCRATCH_PAD_ILA_READY) !=
717 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
721 PM8001_MSG_DBG(pm8001_ha,
722 pm8001_printk(" ila ready status in %d millisec\n",
723 (max_wait_time - max_wait_count)));
726 /* check RAAE status */
727 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
730 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
731 } while (((value & SCRATCH_PAD_RAAE_READY) !=
732 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
736 PM8001_MSG_DBG(pm8001_ha,
737 pm8001_printk(" raae ready status in %d millisec\n",
738 (max_wait_time - max_wait_count)));
741 /* check iop0 status */
742 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
745 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
746 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
751 PM8001_MSG_DBG(pm8001_ha,
752 pm8001_printk(" iop0 ready status in %d millisec\n",
753 (max_wait_time - max_wait_count)));
756 /* check iop1 status only for 16 port controllers */
757 if ((pm8001_ha->chip_id != chip_8008) &&
758 (pm8001_ha->chip_id != chip_8009)) {
760 max_wait_time = max_wait_count = 200 * 1000;
763 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
764 } while (((value & SCRATCH_PAD_IOP1_READY) !=
765 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
769 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
770 "iop1 ready status in %d millisec\n",
771 (max_wait_time - max_wait_count)));
778 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
780 void __iomem *base_addr;
786 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
787 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
789 PM8001_INIT_DBG(pm8001_ha,
790 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
792 pcilogic = (value & 0xFC000000) >> 26;
793 pcibar = get_pci_bar_index(pcilogic);
794 PM8001_INIT_DBG(pm8001_ha,
795 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
796 pm8001_ha->main_cfg_tbl_addr = base_addr =
797 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
798 pm8001_ha->general_stat_tbl_addr =
799 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
801 pm8001_ha->inbnd_q_tbl_addr =
802 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
804 pm8001_ha->outbnd_q_tbl_addr =
805 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
807 pm8001_ha->ivt_tbl_addr =
808 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
810 pm8001_ha->pspa_q_tbl_addr =
811 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
813 pm8001_ha->fatal_tbl_addr =
814 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
817 PM8001_INIT_DBG(pm8001_ha,
818 pm8001_printk("GST OFFSET 0x%x\n",
819 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
820 PM8001_INIT_DBG(pm8001_ha,
821 pm8001_printk("INBND OFFSET 0x%x\n",
822 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
823 PM8001_INIT_DBG(pm8001_ha,
824 pm8001_printk("OBND OFFSET 0x%x\n",
825 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
826 PM8001_INIT_DBG(pm8001_ha,
827 pm8001_printk("IVT OFFSET 0x%x\n",
828 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
829 PM8001_INIT_DBG(pm8001_ha,
830 pm8001_printk("PSPA OFFSET 0x%x\n",
831 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
832 PM8001_INIT_DBG(pm8001_ha,
833 pm8001_printk("addr - main cfg %p general status %p\n",
834 pm8001_ha->main_cfg_tbl_addr,
835 pm8001_ha->general_stat_tbl_addr));
836 PM8001_INIT_DBG(pm8001_ha,
837 pm8001_printk("addr - inbnd %p obnd %p\n",
838 pm8001_ha->inbnd_q_tbl_addr,
839 pm8001_ha->outbnd_q_tbl_addr));
840 PM8001_INIT_DBG(pm8001_ha,
841 pm8001_printk("addr - pspa %p ivt %p\n",
842 pm8001_ha->pspa_q_tbl_addr,
843 pm8001_ha->ivt_tbl_addr));
847 * pm80xx_set_thermal_config - support the thermal configuration
848 * @pm8001_ha: our hba card information.
851 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
853 struct set_ctrl_cfg_req payload;
854 struct inbound_queue_table *circularQ;
857 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
860 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
861 rc = pm8001_tag_alloc(pm8001_ha, &tag);
865 circularQ = &pm8001_ha->inbnd_q_tbl[0];
866 payload.tag = cpu_to_le32(tag);
868 if (IS_SPCV_12G(pm8001_ha->pdev))
869 page_code = THERMAL_PAGE_CODE_7H;
871 page_code = THERMAL_PAGE_CODE_8H;
874 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
875 (THERMAL_ENABLE << 8) | page_code);
877 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
879 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
881 pm8001_tag_free(pm8001_ha, tag);
887 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
888 * Timer configuration page
889 * @pm8001_ha: our hba card information.
892 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
894 struct set_ctrl_cfg_req payload;
895 struct inbound_queue_table *circularQ;
896 SASProtocolTimerConfig_t SASConfigPage;
899 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
901 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
902 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
904 rc = pm8001_tag_alloc(pm8001_ha, &tag);
909 circularQ = &pm8001_ha->inbnd_q_tbl[0];
910 payload.tag = cpu_to_le32(tag);
912 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
913 SASConfigPage.MST_MSI = 3 << 15;
914 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
915 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
916 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
917 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
919 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
920 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
923 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
924 SAS_OPNRJT_RTRY_INTVL;
925 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
926 | SAS_COPNRJT_RTRY_TMO;
927 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
928 | SAS_COPNRJT_RTRY_THR;
929 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
931 PM8001_INIT_DBG(pm8001_ha,
932 pm8001_printk("SASConfigPage.pageCode "
933 "0x%08x\n", SASConfigPage.pageCode));
934 PM8001_INIT_DBG(pm8001_ha,
935 pm8001_printk("SASConfigPage.MST_MSI "
936 " 0x%08x\n", SASConfigPage.MST_MSI));
937 PM8001_INIT_DBG(pm8001_ha,
938 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
939 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
940 PM8001_INIT_DBG(pm8001_ha,
941 pm8001_printk("SASConfigPage.STP_FRM_TMO "
942 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
943 PM8001_INIT_DBG(pm8001_ha,
944 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
945 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
946 PM8001_INIT_DBG(pm8001_ha,
947 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
948 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
949 PM8001_INIT_DBG(pm8001_ha,
950 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
951 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
952 PM8001_INIT_DBG(pm8001_ha,
953 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
954 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
955 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
956 " 0x%08x\n", SASConfigPage.MAX_AIP));
958 memcpy(&payload.cfg_pg, &SASConfigPage,
959 sizeof(SASProtocolTimerConfig_t));
961 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
963 pm8001_tag_free(pm8001_ha, tag);
969 * pm80xx_get_encrypt_info - Check for encryption
970 * @pm8001_ha: our hba card information.
973 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
978 /* Read encryption status from SCRATCH PAD 3 */
979 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
981 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
982 SCRATCH_PAD3_ENC_READY) {
983 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
984 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
985 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
986 SCRATCH_PAD3_SMF_ENABLED)
987 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
988 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
989 SCRATCH_PAD3_SMA_ENABLED)
990 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
991 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
992 SCRATCH_PAD3_SMB_ENABLED)
993 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
994 pm8001_ha->encrypt_info.status = 0;
995 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
996 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
997 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
998 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
999 pm8001_ha->encrypt_info.sec_mode,
1000 pm8001_ha->encrypt_info.status));
1002 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1003 SCRATCH_PAD3_ENC_DISABLED) {
1004 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1005 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1007 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1008 pm8001_ha->encrypt_info.cipher_mode = 0;
1009 pm8001_ha->encrypt_info.sec_mode = 0;
1011 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1012 SCRATCH_PAD3_ENC_DIS_ERR) {
1013 pm8001_ha->encrypt_info.status =
1014 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1015 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1016 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1017 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1018 SCRATCH_PAD3_SMF_ENABLED)
1019 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1020 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1021 SCRATCH_PAD3_SMA_ENABLED)
1022 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1023 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1024 SCRATCH_PAD3_SMB_ENABLED)
1025 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1026 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1027 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1028 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1029 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1030 pm8001_ha->encrypt_info.sec_mode,
1031 pm8001_ha->encrypt_info.status));
1032 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1033 SCRATCH_PAD3_ENC_ENA_ERR) {
1035 pm8001_ha->encrypt_info.status =
1036 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1037 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1038 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1039 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1040 SCRATCH_PAD3_SMF_ENABLED)
1041 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1042 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1043 SCRATCH_PAD3_SMA_ENABLED)
1044 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1045 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1046 SCRATCH_PAD3_SMB_ENABLED)
1047 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1049 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1050 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1051 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1052 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1053 pm8001_ha->encrypt_info.sec_mode,
1054 pm8001_ha->encrypt_info.status));
1060 * pm80xx_encrypt_update - update flash with encryption informtion
1061 * @pm8001_ha: our hba card information.
1063 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1065 struct kek_mgmt_req payload;
1066 struct inbound_queue_table *circularQ;
1069 u32 opc = OPC_INB_KEK_MANAGEMENT;
1071 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1072 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1076 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1077 payload.tag = cpu_to_le32(tag);
1078 /* Currently only one key is used. New KEK index is 1.
1079 * Current KEK index is 1. Store KEK to NVRAM is 1.
1081 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1082 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1084 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1086 pm8001_tag_free(pm8001_ha, tag);
1092 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1093 * @pm8001_ha: our hba card information
1095 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1100 /* check the firmware status */
1101 if (-1 == check_fw_ready(pm8001_ha)) {
1102 PM8001_FAIL_DBG(pm8001_ha,
1103 pm8001_printk("Firmware is not ready!\n"));
1107 /* Initialize the controller fatal error flag */
1108 pm8001_ha->controller_fatal_error = false;
1110 /* Initialize pci space address eg: mpi offset */
1111 init_pci_device_addresses(pm8001_ha);
1112 init_default_table_values(pm8001_ha);
1113 read_main_config_table(pm8001_ha);
1114 read_general_status_table(pm8001_ha);
1115 read_inbnd_queue_table(pm8001_ha);
1116 read_outbnd_queue_table(pm8001_ha);
1117 read_phy_attr_table(pm8001_ha);
1119 /* update main config table ,inbound table and outbound table */
1120 update_main_config_table(pm8001_ha);
1121 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1122 update_inbnd_queue_table(pm8001_ha, i);
1123 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1124 update_outbnd_queue_table(pm8001_ha, i);
1126 /* notify firmware update finished and check initialization status */
1127 if (0 == mpi_init_check(pm8001_ha)) {
1128 PM8001_INIT_DBG(pm8001_ha,
1129 pm8001_printk("MPI initialize successful!\n"));
1133 /* send SAS protocol timer configuration page to FW */
1134 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1136 /* Check for encryption */
1137 if (pm8001_ha->chip->encrypt) {
1138 PM8001_INIT_DBG(pm8001_ha,
1139 pm8001_printk("Checking for encryption\n"));
1140 ret = pm80xx_get_encrypt_info(pm8001_ha);
1142 PM8001_INIT_DBG(pm8001_ha,
1143 pm8001_printk("Encryption error !!\n"));
1144 if (pm8001_ha->encrypt_info.status == 0x81) {
1145 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1146 "Encryption enabled with error."
1147 "Saving encryption key to flash\n"));
1148 pm80xx_encrypt_update(pm8001_ha);
1155 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1159 u32 gst_len_mpistate;
1160 init_pci_device_addresses(pm8001_ha);
1161 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1163 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1165 /* wait until Inbound DoorBell Clear Register toggled */
1166 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1167 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1169 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1173 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1174 value &= SPCv_MSGU_CFG_TABLE_RESET;
1175 } while ((value != 0) && (--max_wait_count));
1177 if (!max_wait_count) {
1178 PM8001_FAIL_DBG(pm8001_ha,
1179 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1183 /* check the MPI-State for termination in progress */
1184 /* wait until Inbound DoorBell Clear Register toggled */
1185 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1189 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1190 GST_GSTLEN_MPIS_OFFSET);
1191 if (GST_MPI_STATE_UNINIT ==
1192 (gst_len_mpistate & GST_MPI_STATE_MASK))
1194 } while (--max_wait_count);
1195 if (!max_wait_count) {
1196 PM8001_FAIL_DBG(pm8001_ha,
1197 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1198 gst_len_mpistate & GST_MPI_STATE_MASK));
1206 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1207 * the FW register status to the originated status.
1208 * @pm8001_ha: our hba card information
1212 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1215 u32 bootloader_state;
1216 u32 ibutton0, ibutton1;
1218 /* Process MPI table uninitialization only if FW is ready */
1219 if (!pm8001_ha->controller_fatal_error) {
1220 /* Check if MPI is in ready state to reset */
1221 if (mpi_uninit_check(pm8001_ha) != 0) {
1222 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1223 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1224 "MPI state is not ready scratch1 :0x%x\n",
1229 /* checked for reset register normal state; 0x0 */
1230 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1231 PM8001_INIT_DBG(pm8001_ha,
1232 pm8001_printk("reset register before write : 0x%x\n", regval));
1234 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1237 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1238 PM8001_INIT_DBG(pm8001_ha,
1239 pm8001_printk("reset register after write 0x%x\n", regval));
1241 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1242 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1243 PM8001_MSG_DBG(pm8001_ha,
1244 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1247 PM8001_MSG_DBG(pm8001_ha,
1248 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1251 /* check bootloader is successfully executed or in HDA mode */
1253 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1254 SCRATCH_PAD1_BOOTSTATE_MASK;
1256 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1257 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1258 "Bootloader state - HDA mode SEEPROM\n"));
1259 } else if (bootloader_state ==
1260 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1261 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1262 "Bootloader state - HDA mode Bootstrap Pin\n"));
1263 } else if (bootloader_state ==
1264 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1265 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1266 "Bootloader state - HDA mode soft reset\n"));
1267 } else if (bootloader_state ==
1268 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1269 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1270 "Bootloader state-HDA mode critical error\n"));
1275 /* check the firmware status after reset */
1276 if (-1 == check_fw_ready(pm8001_ha)) {
1277 PM8001_FAIL_DBG(pm8001_ha,
1278 pm8001_printk("Firmware is not ready!\n"));
1279 /* check iButton feature support for motherboard controller */
1280 if (pm8001_ha->pdev->subsystem_vendor !=
1281 PCI_VENDOR_ID_ADAPTEC2 &&
1282 pm8001_ha->pdev->subsystem_vendor !=
1283 PCI_VENDOR_ID_ATTO &&
1284 pm8001_ha->pdev->subsystem_vendor != 0) {
1285 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1286 MSGU_HOST_SCRATCH_PAD_6);
1287 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1288 MSGU_HOST_SCRATCH_PAD_7);
1289 if (!ibutton0 && !ibutton1) {
1290 PM8001_FAIL_DBG(pm8001_ha,
1291 pm8001_printk("iButton Feature is"
1292 " not Available!!!\n"));
1295 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1296 PM8001_FAIL_DBG(pm8001_ha,
1297 pm8001_printk("CRC Check for iButton"
1298 " Feature Failed!!!\n"));
1303 PM8001_INIT_DBG(pm8001_ha,
1304 pm8001_printk("SPCv soft reset Complete\n"));
1308 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1312 PM8001_INIT_DBG(pm8001_ha,
1313 pm8001_printk("chip reset start\n"));
1315 /* do SPCv chip reset. */
1316 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1317 PM8001_INIT_DBG(pm8001_ha,
1318 pm8001_printk("SPC soft reset Complete\n"));
1320 /* Check this ..whether delay is required or no */
1324 /* wait for 20 msec until the firmware gets reloaded */
1328 } while ((--i) != 0);
1330 PM8001_INIT_DBG(pm8001_ha,
1331 pm8001_printk("chip reset finished\n"));
1335 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1336 * @pm8001_ha: our hba card information
1339 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1341 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1342 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1346 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1347 * @pm8001_ha: our hba card information
1350 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1352 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1356 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1357 * @pm8001_ha: our hba card information
1360 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1362 #ifdef PM8001_USE_MSIX
1364 mask = (u32)(1 << vec);
1366 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1369 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1374 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1375 * @pm8001_ha: our hba card information
1378 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1380 #ifdef PM8001_USE_MSIX
1385 mask = (u32)(1 << vec);
1386 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1389 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1392 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1393 struct pm8001_device *pm8001_ha_dev)
1397 struct pm8001_ccb_info *ccb;
1398 struct sas_task *task = NULL;
1399 struct task_abort_req task_abort;
1400 struct inbound_queue_table *circularQ;
1401 u32 opc = OPC_INB_SATA_ABORT;
1404 if (!pm8001_ha_dev) {
1405 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1409 task = sas_alloc_slow_task(GFP_ATOMIC);
1412 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1413 "allocate task\n"));
1417 task->task_done = pm8001_task_done;
1419 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1421 sas_free_task(task);
1425 ccb = &pm8001_ha->ccb_info[ccb_tag];
1426 ccb->device = pm8001_ha_dev;
1427 ccb->ccb_tag = ccb_tag;
1431 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1433 memset(&task_abort, 0, sizeof(task_abort));
1434 task_abort.abort_all = cpu_to_le32(1);
1435 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1436 task_abort.tag = cpu_to_le32(ccb_tag);
1438 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1440 sas_free_task(task);
1441 pm8001_tag_free(pm8001_ha, ccb_tag);
1445 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1446 struct pm8001_device *pm8001_ha_dev)
1448 struct sata_start_req sata_cmd;
1451 struct pm8001_ccb_info *ccb;
1452 struct sas_task *task = NULL;
1453 struct host_to_dev_fis fis;
1454 struct domain_device *dev;
1455 struct inbound_queue_table *circularQ;
1456 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1458 task = sas_alloc_slow_task(GFP_ATOMIC);
1461 PM8001_FAIL_DBG(pm8001_ha,
1462 pm8001_printk("cannot allocate task !!!\n"));
1465 task->task_done = pm8001_task_done;
1467 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1469 sas_free_task(task);
1470 PM8001_FAIL_DBG(pm8001_ha,
1471 pm8001_printk("cannot allocate tag !!!\n"));
1475 /* allocate domain device by ourselves as libsas
1476 * is not going to provide any
1478 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1480 sas_free_task(task);
1481 pm8001_tag_free(pm8001_ha, ccb_tag);
1482 PM8001_FAIL_DBG(pm8001_ha,
1483 pm8001_printk("Domain device cannot be allocated\n"));
1488 task->dev->lldd_dev = pm8001_ha_dev;
1490 ccb = &pm8001_ha->ccb_info[ccb_tag];
1491 ccb->device = pm8001_ha_dev;
1492 ccb->ccb_tag = ccb_tag;
1494 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1495 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1497 memset(&sata_cmd, 0, sizeof(sata_cmd));
1498 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1500 /* construct read log FIS */
1501 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1502 fis.fis_type = 0x27;
1504 fis.command = ATA_CMD_READ_LOG_EXT;
1506 fis.sector_count = 0x1;
1508 sata_cmd.tag = cpu_to_le32(ccb_tag);
1509 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1510 sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1511 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1513 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1515 sas_free_task(task);
1516 pm8001_tag_free(pm8001_ha, ccb_tag);
1522 * mpi_ssp_completion- process the event that FW response to the SSP request.
1523 * @pm8001_ha: our hba card information
1524 * @piomb: the message contents of this outbound message.
1526 * When FW has completed a ssp request for example a IO request, after it has
1527 * filled the SG data with the data, it will trigger this event represent
1528 * that he has finished the job,please check the coresponding buffer.
1529 * So we will tell the caller who maybe waiting the result to tell upper layer
1530 * that the task has been finished.
1533 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1536 struct pm8001_ccb_info *ccb;
1537 unsigned long flags;
1541 struct ssp_completion_resp *psspPayload;
1542 struct task_status_struct *ts;
1543 struct ssp_response_iu *iu;
1544 struct pm8001_device *pm8001_dev;
1545 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1546 status = le32_to_cpu(psspPayload->status);
1547 tag = le32_to_cpu(psspPayload->tag);
1548 ccb = &pm8001_ha->ccb_info[tag];
1549 if ((status == IO_ABORTED) && ccb->open_retry) {
1550 /* Being completed by another */
1551 ccb->open_retry = 0;
1554 pm8001_dev = ccb->device;
1555 param = le32_to_cpu(psspPayload->param);
1558 if (status && status != IO_UNDERFLOW)
1559 PM8001_FAIL_DBG(pm8001_ha,
1560 pm8001_printk("sas IO status 0x%x\n", status));
1561 if (unlikely(!t || !t->lldd_task || !t->dev))
1563 ts = &t->task_status;
1564 /* Print sas address of IO failed device */
1565 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1566 (status != IO_UNDERFLOW))
1567 PM8001_FAIL_DBG(pm8001_ha,
1568 pm8001_printk("SAS Address of IO Failure Drive"
1569 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1573 PM8001_IO_DBG(pm8001_ha,
1574 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1577 ts->resp = SAS_TASK_COMPLETE;
1578 ts->stat = SAM_STAT_GOOD;
1580 ts->resp = SAS_TASK_COMPLETE;
1581 ts->stat = SAS_PROTO_RESPONSE;
1582 ts->residual = param;
1583 iu = &psspPayload->ssp_resp_iu;
1584 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1587 pm8001_dev->running_req--;
1590 PM8001_IO_DBG(pm8001_ha,
1591 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1592 ts->resp = SAS_TASK_COMPLETE;
1593 ts->stat = SAS_ABORTED_TASK;
1596 /* SSP Completion with error */
1597 PM8001_IO_DBG(pm8001_ha,
1598 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1600 ts->resp = SAS_TASK_COMPLETE;
1601 ts->stat = SAS_DATA_UNDERRUN;
1602 ts->residual = param;
1604 pm8001_dev->running_req--;
1607 PM8001_IO_DBG(pm8001_ha,
1608 pm8001_printk("IO_NO_DEVICE\n"));
1609 ts->resp = SAS_TASK_UNDELIVERED;
1610 ts->stat = SAS_PHY_DOWN;
1612 case IO_XFER_ERROR_BREAK:
1613 PM8001_IO_DBG(pm8001_ha,
1614 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1615 ts->resp = SAS_TASK_COMPLETE;
1616 ts->stat = SAS_OPEN_REJECT;
1617 /* Force the midlayer to retry */
1618 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1620 case IO_XFER_ERROR_PHY_NOT_READY:
1621 PM8001_IO_DBG(pm8001_ha,
1622 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1623 ts->resp = SAS_TASK_COMPLETE;
1624 ts->stat = SAS_OPEN_REJECT;
1625 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1627 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1628 PM8001_IO_DBG(pm8001_ha,
1629 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1630 ts->resp = SAS_TASK_COMPLETE;
1631 ts->stat = SAS_OPEN_REJECT;
1632 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1634 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1635 PM8001_IO_DBG(pm8001_ha,
1636 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1637 ts->resp = SAS_TASK_COMPLETE;
1638 ts->stat = SAS_OPEN_REJECT;
1639 ts->open_rej_reason = SAS_OREJ_EPROTO;
1641 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1642 PM8001_IO_DBG(pm8001_ha,
1643 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1644 ts->resp = SAS_TASK_COMPLETE;
1645 ts->stat = SAS_OPEN_REJECT;
1646 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1648 case IO_OPEN_CNX_ERROR_BREAK:
1649 PM8001_IO_DBG(pm8001_ha,
1650 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1651 ts->resp = SAS_TASK_COMPLETE;
1652 ts->stat = SAS_OPEN_REJECT;
1653 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1655 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1656 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1657 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1658 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1659 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1660 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1661 PM8001_IO_DBG(pm8001_ha,
1662 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1663 ts->resp = SAS_TASK_COMPLETE;
1664 ts->stat = SAS_OPEN_REJECT;
1665 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1667 pm8001_handle_event(pm8001_ha,
1669 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1671 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1672 PM8001_IO_DBG(pm8001_ha,
1673 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1674 ts->resp = SAS_TASK_COMPLETE;
1675 ts->stat = SAS_OPEN_REJECT;
1676 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1678 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1679 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1680 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1681 ts->resp = SAS_TASK_COMPLETE;
1682 ts->stat = SAS_OPEN_REJECT;
1683 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1685 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1686 PM8001_IO_DBG(pm8001_ha,
1687 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1688 ts->resp = SAS_TASK_UNDELIVERED;
1689 ts->stat = SAS_OPEN_REJECT;
1690 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1692 case IO_XFER_ERROR_NAK_RECEIVED:
1693 PM8001_IO_DBG(pm8001_ha,
1694 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1695 ts->resp = SAS_TASK_COMPLETE;
1696 ts->stat = SAS_OPEN_REJECT;
1697 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1699 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1700 PM8001_IO_DBG(pm8001_ha,
1701 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1702 ts->resp = SAS_TASK_COMPLETE;
1703 ts->stat = SAS_NAK_R_ERR;
1705 case IO_XFER_ERROR_DMA:
1706 PM8001_IO_DBG(pm8001_ha,
1707 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1708 ts->resp = SAS_TASK_COMPLETE;
1709 ts->stat = SAS_OPEN_REJECT;
1711 case IO_XFER_OPEN_RETRY_TIMEOUT:
1712 PM8001_IO_DBG(pm8001_ha,
1713 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1714 ts->resp = SAS_TASK_COMPLETE;
1715 ts->stat = SAS_OPEN_REJECT;
1716 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1718 case IO_XFER_ERROR_OFFSET_MISMATCH:
1719 PM8001_IO_DBG(pm8001_ha,
1720 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1721 ts->resp = SAS_TASK_COMPLETE;
1722 ts->stat = SAS_OPEN_REJECT;
1724 case IO_PORT_IN_RESET:
1725 PM8001_IO_DBG(pm8001_ha,
1726 pm8001_printk("IO_PORT_IN_RESET\n"));
1727 ts->resp = SAS_TASK_COMPLETE;
1728 ts->stat = SAS_OPEN_REJECT;
1730 case IO_DS_NON_OPERATIONAL:
1731 PM8001_IO_DBG(pm8001_ha,
1732 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1733 ts->resp = SAS_TASK_COMPLETE;
1734 ts->stat = SAS_OPEN_REJECT;
1736 pm8001_handle_event(pm8001_ha,
1738 IO_DS_NON_OPERATIONAL);
1740 case IO_DS_IN_RECOVERY:
1741 PM8001_IO_DBG(pm8001_ha,
1742 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1743 ts->resp = SAS_TASK_COMPLETE;
1744 ts->stat = SAS_OPEN_REJECT;
1746 case IO_TM_TAG_NOT_FOUND:
1747 PM8001_IO_DBG(pm8001_ha,
1748 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1749 ts->resp = SAS_TASK_COMPLETE;
1750 ts->stat = SAS_OPEN_REJECT;
1752 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1753 PM8001_IO_DBG(pm8001_ha,
1754 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1755 ts->resp = SAS_TASK_COMPLETE;
1756 ts->stat = SAS_OPEN_REJECT;
1758 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1759 PM8001_IO_DBG(pm8001_ha,
1760 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1761 ts->resp = SAS_TASK_COMPLETE;
1762 ts->stat = SAS_OPEN_REJECT;
1763 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1766 PM8001_IO_DBG(pm8001_ha,
1767 pm8001_printk("Unknown status 0x%x\n", status));
1768 /* not allowed case. Therefore, return failed status */
1769 ts->resp = SAS_TASK_COMPLETE;
1770 ts->stat = SAS_OPEN_REJECT;
1773 PM8001_IO_DBG(pm8001_ha,
1774 pm8001_printk("scsi_status = 0x%x\n ",
1775 psspPayload->ssp_resp_iu.status));
1776 spin_lock_irqsave(&t->task_state_lock, flags);
1777 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1778 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1779 t->task_state_flags |= SAS_TASK_STATE_DONE;
1780 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1781 spin_unlock_irqrestore(&t->task_state_lock, flags);
1782 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1783 "task 0x%p done with io_status 0x%x resp 0x%x "
1784 "stat 0x%x but aborted by upper layer!\n",
1785 t, status, ts->resp, ts->stat));
1786 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1788 spin_unlock_irqrestore(&t->task_state_lock, flags);
1789 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1790 mb();/* in order to force CPU ordering */
1795 /*See the comments for mpi_ssp_completion */
1796 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1799 unsigned long flags;
1800 struct task_status_struct *ts;
1801 struct pm8001_ccb_info *ccb;
1802 struct pm8001_device *pm8001_dev;
1803 struct ssp_event_resp *psspPayload =
1804 (struct ssp_event_resp *)(piomb + 4);
1805 u32 event = le32_to_cpu(psspPayload->event);
1806 u32 tag = le32_to_cpu(psspPayload->tag);
1807 u32 port_id = le32_to_cpu(psspPayload->port_id);
1809 ccb = &pm8001_ha->ccb_info[tag];
1811 pm8001_dev = ccb->device;
1813 PM8001_FAIL_DBG(pm8001_ha,
1814 pm8001_printk("sas IO status 0x%x\n", event));
1815 if (unlikely(!t || !t->lldd_task || !t->dev))
1817 ts = &t->task_status;
1818 PM8001_IO_DBG(pm8001_ha,
1819 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1820 port_id, tag, event));
1823 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1824 ts->resp = SAS_TASK_COMPLETE;
1825 ts->stat = SAS_DATA_OVERRUN;
1828 pm8001_dev->running_req--;
1830 case IO_XFER_ERROR_BREAK:
1831 PM8001_IO_DBG(pm8001_ha,
1832 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1833 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1835 case IO_XFER_ERROR_PHY_NOT_READY:
1836 PM8001_IO_DBG(pm8001_ha,
1837 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1838 ts->resp = SAS_TASK_COMPLETE;
1839 ts->stat = SAS_OPEN_REJECT;
1840 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1842 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1843 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1844 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1845 ts->resp = SAS_TASK_COMPLETE;
1846 ts->stat = SAS_OPEN_REJECT;
1847 ts->open_rej_reason = SAS_OREJ_EPROTO;
1849 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1850 PM8001_IO_DBG(pm8001_ha,
1851 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1852 ts->resp = SAS_TASK_COMPLETE;
1853 ts->stat = SAS_OPEN_REJECT;
1854 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1856 case IO_OPEN_CNX_ERROR_BREAK:
1857 PM8001_IO_DBG(pm8001_ha,
1858 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1859 ts->resp = SAS_TASK_COMPLETE;
1860 ts->stat = SAS_OPEN_REJECT;
1861 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1863 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1864 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1865 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1866 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1867 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1868 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1869 PM8001_IO_DBG(pm8001_ha,
1870 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1871 ts->resp = SAS_TASK_COMPLETE;
1872 ts->stat = SAS_OPEN_REJECT;
1873 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1875 pm8001_handle_event(pm8001_ha,
1877 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1879 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1880 PM8001_IO_DBG(pm8001_ha,
1881 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1882 ts->resp = SAS_TASK_COMPLETE;
1883 ts->stat = SAS_OPEN_REJECT;
1884 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1886 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1887 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1888 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1889 ts->resp = SAS_TASK_COMPLETE;
1890 ts->stat = SAS_OPEN_REJECT;
1891 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1893 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1894 PM8001_IO_DBG(pm8001_ha,
1895 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1896 ts->resp = SAS_TASK_COMPLETE;
1897 ts->stat = SAS_OPEN_REJECT;
1898 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1900 case IO_XFER_ERROR_NAK_RECEIVED:
1901 PM8001_IO_DBG(pm8001_ha,
1902 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1903 ts->resp = SAS_TASK_COMPLETE;
1904 ts->stat = SAS_OPEN_REJECT;
1905 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1907 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1908 PM8001_IO_DBG(pm8001_ha,
1909 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1910 ts->resp = SAS_TASK_COMPLETE;
1911 ts->stat = SAS_NAK_R_ERR;
1913 case IO_XFER_OPEN_RETRY_TIMEOUT:
1914 PM8001_IO_DBG(pm8001_ha,
1915 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1916 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1918 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1919 PM8001_IO_DBG(pm8001_ha,
1920 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1921 ts->resp = SAS_TASK_COMPLETE;
1922 ts->stat = SAS_DATA_OVERRUN;
1924 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1925 PM8001_IO_DBG(pm8001_ha,
1926 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1927 ts->resp = SAS_TASK_COMPLETE;
1928 ts->stat = SAS_DATA_OVERRUN;
1930 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1931 PM8001_IO_DBG(pm8001_ha,
1932 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1933 ts->resp = SAS_TASK_COMPLETE;
1934 ts->stat = SAS_DATA_OVERRUN;
1936 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1937 PM8001_IO_DBG(pm8001_ha,
1938 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1939 ts->resp = SAS_TASK_COMPLETE;
1940 ts->stat = SAS_DATA_OVERRUN;
1942 case IO_XFER_ERROR_OFFSET_MISMATCH:
1943 PM8001_IO_DBG(pm8001_ha,
1944 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1945 ts->resp = SAS_TASK_COMPLETE;
1946 ts->stat = SAS_DATA_OVERRUN;
1948 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1949 PM8001_IO_DBG(pm8001_ha,
1950 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1951 ts->resp = SAS_TASK_COMPLETE;
1952 ts->stat = SAS_DATA_OVERRUN;
1954 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1955 PM8001_IO_DBG(pm8001_ha,
1956 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1957 /* TBC: used default set values */
1958 ts->resp = SAS_TASK_COMPLETE;
1959 ts->stat = SAS_DATA_OVERRUN;
1961 case IO_XFER_CMD_FRAME_ISSUED:
1962 PM8001_IO_DBG(pm8001_ha,
1963 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1966 PM8001_IO_DBG(pm8001_ha,
1967 pm8001_printk("Unknown status 0x%x\n", event));
1968 /* not allowed case. Therefore, return failed status */
1969 ts->resp = SAS_TASK_COMPLETE;
1970 ts->stat = SAS_DATA_OVERRUN;
1973 spin_lock_irqsave(&t->task_state_lock, flags);
1974 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1975 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1976 t->task_state_flags |= SAS_TASK_STATE_DONE;
1977 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1978 spin_unlock_irqrestore(&t->task_state_lock, flags);
1979 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1980 "task 0x%p done with event 0x%x resp 0x%x "
1981 "stat 0x%x but aborted by upper layer!\n",
1982 t, event, ts->resp, ts->stat));
1983 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1985 spin_unlock_irqrestore(&t->task_state_lock, flags);
1986 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1987 mb();/* in order to force CPU ordering */
1992 /*See the comments for mpi_ssp_completion */
1994 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1997 struct pm8001_ccb_info *ccb;
2002 u8 sata_addr_low[4];
2003 u32 temp_sata_addr_low, temp_sata_addr_hi;
2005 struct sata_completion_resp *psataPayload;
2006 struct task_status_struct *ts;
2007 struct ata_task_resp *resp ;
2009 struct pm8001_device *pm8001_dev;
2010 unsigned long flags;
2012 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2013 status = le32_to_cpu(psataPayload->status);
2014 tag = le32_to_cpu(psataPayload->tag);
2017 PM8001_FAIL_DBG(pm8001_ha,
2018 pm8001_printk("tag null\n"));
2021 ccb = &pm8001_ha->ccb_info[tag];
2022 param = le32_to_cpu(psataPayload->param);
2025 pm8001_dev = ccb->device;
2027 PM8001_FAIL_DBG(pm8001_ha,
2028 pm8001_printk("ccb null\n"));
2033 if (t->dev && (t->dev->lldd_dev))
2034 pm8001_dev = t->dev->lldd_dev;
2036 PM8001_FAIL_DBG(pm8001_ha,
2037 pm8001_printk("task null\n"));
2041 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2042 && unlikely(!t || !t->lldd_task || !t->dev)) {
2043 PM8001_FAIL_DBG(pm8001_ha,
2044 pm8001_printk("task or dev null\n"));
2048 ts = &t->task_status;
2050 PM8001_FAIL_DBG(pm8001_ha,
2051 pm8001_printk("ts null\n"));
2054 /* Print sas address of IO failed device */
2055 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2056 (status != IO_UNDERFLOW)) {
2057 if (!((t->dev->parent) &&
2058 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2059 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2060 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2061 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2062 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2063 memcpy(&temp_sata_addr_low, sata_addr_low,
2064 sizeof(sata_addr_low));
2065 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2066 sizeof(sata_addr_hi));
2067 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2068 |((temp_sata_addr_hi << 8) &
2070 ((temp_sata_addr_hi >> 8)
2072 ((temp_sata_addr_hi << 24) &
2074 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2076 ((temp_sata_addr_low << 8)
2078 ((temp_sata_addr_low >> 8)
2080 ((temp_sata_addr_low << 24)
2082 pm8001_dev->attached_phy +
2084 PM8001_FAIL_DBG(pm8001_ha,
2085 pm8001_printk("SAS Address of IO Failure Drive:"
2086 "%08x%08x", temp_sata_addr_hi,
2087 temp_sata_addr_low));
2090 PM8001_FAIL_DBG(pm8001_ha,
2091 pm8001_printk("SAS Address of IO Failure Drive:"
2092 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2097 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2099 ts->resp = SAS_TASK_COMPLETE;
2100 ts->stat = SAM_STAT_GOOD;
2101 /* check if response is for SEND READ LOG */
2103 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2104 /* set new bit for abort_all */
2105 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2106 /* clear bit for read log */
2107 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2108 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2110 pm8001_tag_free(pm8001_ha, tag);
2116 ts->resp = SAS_TASK_COMPLETE;
2117 ts->stat = SAS_PROTO_RESPONSE;
2118 ts->residual = param;
2119 PM8001_IO_DBG(pm8001_ha,
2120 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2122 sata_resp = &psataPayload->sata_resp[0];
2123 resp = (struct ata_task_resp *)ts->buf;
2124 if (t->ata_task.dma_xfer == 0 &&
2125 t->data_dir == PCI_DMA_FROMDEVICE) {
2126 len = sizeof(struct pio_setup_fis);
2127 PM8001_IO_DBG(pm8001_ha,
2128 pm8001_printk("PIO read len = %d\n", len));
2129 } else if (t->ata_task.use_ncq) {
2130 len = sizeof(struct set_dev_bits_fis);
2131 PM8001_IO_DBG(pm8001_ha,
2132 pm8001_printk("FPDMA len = %d\n", len));
2134 len = sizeof(struct dev_to_host_fis);
2135 PM8001_IO_DBG(pm8001_ha,
2136 pm8001_printk("other len = %d\n", len));
2138 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2139 resp->frame_len = len;
2140 memcpy(&resp->ending_fis[0], sata_resp, len);
2141 ts->buf_valid_size = sizeof(*resp);
2143 PM8001_IO_DBG(pm8001_ha,
2144 pm8001_printk("response to large\n"));
2147 pm8001_dev->running_req--;
2150 PM8001_IO_DBG(pm8001_ha,
2151 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2152 ts->resp = SAS_TASK_COMPLETE;
2153 ts->stat = SAS_ABORTED_TASK;
2155 pm8001_dev->running_req--;
2157 /* following cases are to do cases */
2159 /* SATA Completion with error */
2160 PM8001_IO_DBG(pm8001_ha,
2161 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2162 ts->resp = SAS_TASK_COMPLETE;
2163 ts->stat = SAS_DATA_UNDERRUN;
2164 ts->residual = param;
2166 pm8001_dev->running_req--;
2169 PM8001_IO_DBG(pm8001_ha,
2170 pm8001_printk("IO_NO_DEVICE\n"));
2171 ts->resp = SAS_TASK_UNDELIVERED;
2172 ts->stat = SAS_PHY_DOWN;
2174 case IO_XFER_ERROR_BREAK:
2175 PM8001_IO_DBG(pm8001_ha,
2176 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2177 ts->resp = SAS_TASK_COMPLETE;
2178 ts->stat = SAS_INTERRUPTED;
2180 case IO_XFER_ERROR_PHY_NOT_READY:
2181 PM8001_IO_DBG(pm8001_ha,
2182 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2183 ts->resp = SAS_TASK_COMPLETE;
2184 ts->stat = SAS_OPEN_REJECT;
2185 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2187 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2188 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2189 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2190 ts->resp = SAS_TASK_COMPLETE;
2191 ts->stat = SAS_OPEN_REJECT;
2192 ts->open_rej_reason = SAS_OREJ_EPROTO;
2194 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2195 PM8001_IO_DBG(pm8001_ha,
2196 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2197 ts->resp = SAS_TASK_COMPLETE;
2198 ts->stat = SAS_OPEN_REJECT;
2199 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2201 case IO_OPEN_CNX_ERROR_BREAK:
2202 PM8001_IO_DBG(pm8001_ha,
2203 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2204 ts->resp = SAS_TASK_COMPLETE;
2205 ts->stat = SAS_OPEN_REJECT;
2206 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2208 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2209 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2210 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2211 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2212 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2213 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2214 PM8001_IO_DBG(pm8001_ha,
2215 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2216 ts->resp = SAS_TASK_COMPLETE;
2217 ts->stat = SAS_DEV_NO_RESPONSE;
2218 if (!t->uldd_task) {
2219 pm8001_handle_event(pm8001_ha,
2221 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2222 ts->resp = SAS_TASK_UNDELIVERED;
2223 ts->stat = SAS_QUEUE_FULL;
2224 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2228 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2229 PM8001_IO_DBG(pm8001_ha,
2230 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2231 ts->resp = SAS_TASK_UNDELIVERED;
2232 ts->stat = SAS_OPEN_REJECT;
2233 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2234 if (!t->uldd_task) {
2235 pm8001_handle_event(pm8001_ha,
2237 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2238 ts->resp = SAS_TASK_UNDELIVERED;
2239 ts->stat = SAS_QUEUE_FULL;
2240 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2244 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2245 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2246 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2247 ts->resp = SAS_TASK_COMPLETE;
2248 ts->stat = SAS_OPEN_REJECT;
2249 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2251 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2252 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2253 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2254 ts->resp = SAS_TASK_COMPLETE;
2255 ts->stat = SAS_DEV_NO_RESPONSE;
2256 if (!t->uldd_task) {
2257 pm8001_handle_event(pm8001_ha,
2259 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2260 ts->resp = SAS_TASK_UNDELIVERED;
2261 ts->stat = SAS_QUEUE_FULL;
2262 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2266 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2267 PM8001_IO_DBG(pm8001_ha,
2268 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2269 ts->resp = SAS_TASK_COMPLETE;
2270 ts->stat = SAS_OPEN_REJECT;
2271 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2273 case IO_XFER_ERROR_NAK_RECEIVED:
2274 PM8001_IO_DBG(pm8001_ha,
2275 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2276 ts->resp = SAS_TASK_COMPLETE;
2277 ts->stat = SAS_NAK_R_ERR;
2279 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2280 PM8001_IO_DBG(pm8001_ha,
2281 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2282 ts->resp = SAS_TASK_COMPLETE;
2283 ts->stat = SAS_NAK_R_ERR;
2285 case IO_XFER_ERROR_DMA:
2286 PM8001_IO_DBG(pm8001_ha,
2287 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2288 ts->resp = SAS_TASK_COMPLETE;
2289 ts->stat = SAS_ABORTED_TASK;
2291 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2292 PM8001_IO_DBG(pm8001_ha,
2293 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2294 ts->resp = SAS_TASK_UNDELIVERED;
2295 ts->stat = SAS_DEV_NO_RESPONSE;
2297 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2298 PM8001_IO_DBG(pm8001_ha,
2299 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2300 ts->resp = SAS_TASK_COMPLETE;
2301 ts->stat = SAS_DATA_UNDERRUN;
2303 case IO_XFER_OPEN_RETRY_TIMEOUT:
2304 PM8001_IO_DBG(pm8001_ha,
2305 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2306 ts->resp = SAS_TASK_COMPLETE;
2307 ts->stat = SAS_OPEN_TO;
2309 case IO_PORT_IN_RESET:
2310 PM8001_IO_DBG(pm8001_ha,
2311 pm8001_printk("IO_PORT_IN_RESET\n"));
2312 ts->resp = SAS_TASK_COMPLETE;
2313 ts->stat = SAS_DEV_NO_RESPONSE;
2315 case IO_DS_NON_OPERATIONAL:
2316 PM8001_IO_DBG(pm8001_ha,
2317 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2318 ts->resp = SAS_TASK_COMPLETE;
2319 ts->stat = SAS_DEV_NO_RESPONSE;
2320 if (!t->uldd_task) {
2321 pm8001_handle_event(pm8001_ha, pm8001_dev,
2322 IO_DS_NON_OPERATIONAL);
2323 ts->resp = SAS_TASK_UNDELIVERED;
2324 ts->stat = SAS_QUEUE_FULL;
2325 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2329 case IO_DS_IN_RECOVERY:
2330 PM8001_IO_DBG(pm8001_ha,
2331 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2332 ts->resp = SAS_TASK_COMPLETE;
2333 ts->stat = SAS_DEV_NO_RESPONSE;
2335 case IO_DS_IN_ERROR:
2336 PM8001_IO_DBG(pm8001_ha,
2337 pm8001_printk("IO_DS_IN_ERROR\n"));
2338 ts->resp = SAS_TASK_COMPLETE;
2339 ts->stat = SAS_DEV_NO_RESPONSE;
2340 if (!t->uldd_task) {
2341 pm8001_handle_event(pm8001_ha, pm8001_dev,
2343 ts->resp = SAS_TASK_UNDELIVERED;
2344 ts->stat = SAS_QUEUE_FULL;
2345 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2349 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2350 PM8001_IO_DBG(pm8001_ha,
2351 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2352 ts->resp = SAS_TASK_COMPLETE;
2353 ts->stat = SAS_OPEN_REJECT;
2354 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2357 PM8001_IO_DBG(pm8001_ha,
2358 pm8001_printk("Unknown status 0x%x\n", status));
2359 /* not allowed case. Therefore, return failed status */
2360 ts->resp = SAS_TASK_COMPLETE;
2361 ts->stat = SAS_DEV_NO_RESPONSE;
2364 spin_lock_irqsave(&t->task_state_lock, flags);
2365 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2366 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2367 t->task_state_flags |= SAS_TASK_STATE_DONE;
2368 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2369 spin_unlock_irqrestore(&t->task_state_lock, flags);
2370 PM8001_FAIL_DBG(pm8001_ha,
2371 pm8001_printk("task 0x%p done with io_status 0x%x"
2372 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2373 t, status, ts->resp, ts->stat));
2375 complete(&t->slow_task->completion);
2376 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2378 spin_unlock_irqrestore(&t->task_state_lock, flags);
2379 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2383 /*See the comments for mpi_ssp_completion */
2384 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2387 struct task_status_struct *ts;
2388 struct pm8001_ccb_info *ccb;
2389 struct pm8001_device *pm8001_dev;
2390 struct sata_event_resp *psataPayload =
2391 (struct sata_event_resp *)(piomb + 4);
2392 u32 event = le32_to_cpu(psataPayload->event);
2393 u32 tag = le32_to_cpu(psataPayload->tag);
2394 u32 port_id = le32_to_cpu(psataPayload->port_id);
2395 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2396 unsigned long flags;
2398 ccb = &pm8001_ha->ccb_info[tag];
2402 pm8001_dev = ccb->device;
2404 PM8001_FAIL_DBG(pm8001_ha,
2405 pm8001_printk("No CCB !!!. returning\n"));
2409 PM8001_FAIL_DBG(pm8001_ha,
2410 pm8001_printk("SATA EVENT 0x%x\n", event));
2412 /* Check if this is NCQ error */
2413 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2414 /* find device using device id */
2415 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2416 /* send read log extension */
2418 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2422 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2423 PM8001_FAIL_DBG(pm8001_ha,
2424 pm8001_printk("task or dev null\n"));
2428 ts = &t->task_status;
2429 PM8001_IO_DBG(pm8001_ha,
2430 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2431 port_id, tag, event));
2434 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2435 ts->resp = SAS_TASK_COMPLETE;
2436 ts->stat = SAS_DATA_OVERRUN;
2439 pm8001_dev->running_req--;
2441 case IO_XFER_ERROR_BREAK:
2442 PM8001_IO_DBG(pm8001_ha,
2443 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2444 ts->resp = SAS_TASK_COMPLETE;
2445 ts->stat = SAS_INTERRUPTED;
2447 case IO_XFER_ERROR_PHY_NOT_READY:
2448 PM8001_IO_DBG(pm8001_ha,
2449 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2450 ts->resp = SAS_TASK_COMPLETE;
2451 ts->stat = SAS_OPEN_REJECT;
2452 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2454 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2455 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2456 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2457 ts->resp = SAS_TASK_COMPLETE;
2458 ts->stat = SAS_OPEN_REJECT;
2459 ts->open_rej_reason = SAS_OREJ_EPROTO;
2461 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2462 PM8001_IO_DBG(pm8001_ha,
2463 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2464 ts->resp = SAS_TASK_COMPLETE;
2465 ts->stat = SAS_OPEN_REJECT;
2466 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2468 case IO_OPEN_CNX_ERROR_BREAK:
2469 PM8001_IO_DBG(pm8001_ha,
2470 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2471 ts->resp = SAS_TASK_COMPLETE;
2472 ts->stat = SAS_OPEN_REJECT;
2473 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2475 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2476 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2477 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2478 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2479 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2480 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2481 PM8001_FAIL_DBG(pm8001_ha,
2482 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2483 ts->resp = SAS_TASK_UNDELIVERED;
2484 ts->stat = SAS_DEV_NO_RESPONSE;
2485 if (!t->uldd_task) {
2486 pm8001_handle_event(pm8001_ha,
2488 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2489 ts->resp = SAS_TASK_COMPLETE;
2490 ts->stat = SAS_QUEUE_FULL;
2491 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2495 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2496 PM8001_IO_DBG(pm8001_ha,
2497 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2498 ts->resp = SAS_TASK_UNDELIVERED;
2499 ts->stat = SAS_OPEN_REJECT;
2500 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2502 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2503 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2504 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2505 ts->resp = SAS_TASK_COMPLETE;
2506 ts->stat = SAS_OPEN_REJECT;
2507 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2509 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2510 PM8001_IO_DBG(pm8001_ha,
2511 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2512 ts->resp = SAS_TASK_COMPLETE;
2513 ts->stat = SAS_OPEN_REJECT;
2514 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2516 case IO_XFER_ERROR_NAK_RECEIVED:
2517 PM8001_IO_DBG(pm8001_ha,
2518 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2519 ts->resp = SAS_TASK_COMPLETE;
2520 ts->stat = SAS_NAK_R_ERR;
2522 case IO_XFER_ERROR_PEER_ABORTED:
2523 PM8001_IO_DBG(pm8001_ha,
2524 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2525 ts->resp = SAS_TASK_COMPLETE;
2526 ts->stat = SAS_NAK_R_ERR;
2528 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2529 PM8001_IO_DBG(pm8001_ha,
2530 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2531 ts->resp = SAS_TASK_COMPLETE;
2532 ts->stat = SAS_DATA_UNDERRUN;
2534 case IO_XFER_OPEN_RETRY_TIMEOUT:
2535 PM8001_IO_DBG(pm8001_ha,
2536 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2537 ts->resp = SAS_TASK_COMPLETE;
2538 ts->stat = SAS_OPEN_TO;
2540 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2541 PM8001_IO_DBG(pm8001_ha,
2542 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2543 ts->resp = SAS_TASK_COMPLETE;
2544 ts->stat = SAS_OPEN_TO;
2546 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2547 PM8001_IO_DBG(pm8001_ha,
2548 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2549 ts->resp = SAS_TASK_COMPLETE;
2550 ts->stat = SAS_OPEN_TO;
2552 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2553 PM8001_IO_DBG(pm8001_ha,
2554 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2555 ts->resp = SAS_TASK_COMPLETE;
2556 ts->stat = SAS_OPEN_TO;
2558 case IO_XFER_ERROR_OFFSET_MISMATCH:
2559 PM8001_IO_DBG(pm8001_ha,
2560 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2561 ts->resp = SAS_TASK_COMPLETE;
2562 ts->stat = SAS_OPEN_TO;
2564 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2565 PM8001_IO_DBG(pm8001_ha,
2566 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2567 ts->resp = SAS_TASK_COMPLETE;
2568 ts->stat = SAS_OPEN_TO;
2570 case IO_XFER_CMD_FRAME_ISSUED:
2571 PM8001_IO_DBG(pm8001_ha,
2572 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2574 case IO_XFER_PIO_SETUP_ERROR:
2575 PM8001_IO_DBG(pm8001_ha,
2576 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2577 ts->resp = SAS_TASK_COMPLETE;
2578 ts->stat = SAS_OPEN_TO;
2580 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2581 PM8001_FAIL_DBG(pm8001_ha,
2582 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2583 /* TBC: used default set values */
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_OPEN_TO;
2587 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2588 PM8001_FAIL_DBG(pm8001_ha,
2589 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2590 /* TBC: used default set values */
2591 ts->resp = SAS_TASK_COMPLETE;
2592 ts->stat = SAS_OPEN_TO;
2595 PM8001_IO_DBG(pm8001_ha,
2596 pm8001_printk("Unknown status 0x%x\n", event));
2597 /* not allowed case. Therefore, return failed status */
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_OPEN_TO;
2602 spin_lock_irqsave(&t->task_state_lock, flags);
2603 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2604 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2605 t->task_state_flags |= SAS_TASK_STATE_DONE;
2606 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2607 spin_unlock_irqrestore(&t->task_state_lock, flags);
2608 PM8001_FAIL_DBG(pm8001_ha,
2609 pm8001_printk("task 0x%p done with io_status 0x%x"
2610 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2611 t, event, ts->resp, ts->stat));
2612 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2614 spin_unlock_irqrestore(&t->task_state_lock, flags);
2615 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2619 /*See the comments for mpi_ssp_completion */
2621 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2625 struct pm8001_ccb_info *ccb;
2626 unsigned long flags;
2629 struct smp_completion_resp *psmpPayload;
2630 struct task_status_struct *ts;
2631 struct pm8001_device *pm8001_dev;
2632 char *pdma_respaddr = NULL;
2634 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2635 status = le32_to_cpu(psmpPayload->status);
2636 tag = le32_to_cpu(psmpPayload->tag);
2638 ccb = &pm8001_ha->ccb_info[tag];
2639 param = le32_to_cpu(psmpPayload->param);
2641 ts = &t->task_status;
2642 pm8001_dev = ccb->device;
2644 PM8001_FAIL_DBG(pm8001_ha,
2645 pm8001_printk("smp IO status 0x%x\n", status));
2646 if (unlikely(!t || !t->lldd_task || !t->dev))
2652 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2653 ts->resp = SAS_TASK_COMPLETE;
2654 ts->stat = SAM_STAT_GOOD;
2656 pm8001_dev->running_req--;
2657 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2658 PM8001_IO_DBG(pm8001_ha,
2659 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2661 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2662 ((u64)sg_dma_address
2663 (&t->smp_task.smp_resp))));
2664 for (i = 0; i < param; i++) {
2665 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2666 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2667 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2668 i, *(pdma_respaddr+i),
2669 psmpPayload->_r_a[i]));
2674 PM8001_IO_DBG(pm8001_ha,
2675 pm8001_printk("IO_ABORTED IOMB\n"));
2676 ts->resp = SAS_TASK_COMPLETE;
2677 ts->stat = SAS_ABORTED_TASK;
2679 pm8001_dev->running_req--;
2682 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2683 ts->resp = SAS_TASK_COMPLETE;
2684 ts->stat = SAS_DATA_OVERRUN;
2687 pm8001_dev->running_req--;
2690 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2691 ts->resp = SAS_TASK_COMPLETE;
2692 ts->stat = SAS_PHY_DOWN;
2694 case IO_ERROR_HW_TIMEOUT:
2695 PM8001_IO_DBG(pm8001_ha,
2696 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2697 ts->resp = SAS_TASK_COMPLETE;
2698 ts->stat = SAM_STAT_BUSY;
2700 case IO_XFER_ERROR_BREAK:
2701 PM8001_IO_DBG(pm8001_ha,
2702 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2703 ts->resp = SAS_TASK_COMPLETE;
2704 ts->stat = SAM_STAT_BUSY;
2706 case IO_XFER_ERROR_PHY_NOT_READY:
2707 PM8001_IO_DBG(pm8001_ha,
2708 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2709 ts->resp = SAS_TASK_COMPLETE;
2710 ts->stat = SAM_STAT_BUSY;
2712 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2713 PM8001_IO_DBG(pm8001_ha,
2714 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2715 ts->resp = SAS_TASK_COMPLETE;
2716 ts->stat = SAS_OPEN_REJECT;
2717 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2719 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2720 PM8001_IO_DBG(pm8001_ha,
2721 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2722 ts->resp = SAS_TASK_COMPLETE;
2723 ts->stat = SAS_OPEN_REJECT;
2724 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2726 case IO_OPEN_CNX_ERROR_BREAK:
2727 PM8001_IO_DBG(pm8001_ha,
2728 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2729 ts->resp = SAS_TASK_COMPLETE;
2730 ts->stat = SAS_OPEN_REJECT;
2731 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2733 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2734 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2735 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2736 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2737 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2738 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2739 PM8001_IO_DBG(pm8001_ha,
2740 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2741 ts->resp = SAS_TASK_COMPLETE;
2742 ts->stat = SAS_OPEN_REJECT;
2743 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2744 pm8001_handle_event(pm8001_ha,
2746 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2748 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2749 PM8001_IO_DBG(pm8001_ha,
2750 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2751 ts->resp = SAS_TASK_COMPLETE;
2752 ts->stat = SAS_OPEN_REJECT;
2753 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2755 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2756 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2757 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2758 ts->resp = SAS_TASK_COMPLETE;
2759 ts->stat = SAS_OPEN_REJECT;
2760 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2762 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2763 PM8001_IO_DBG(pm8001_ha,
2764 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2765 ts->resp = SAS_TASK_COMPLETE;
2766 ts->stat = SAS_OPEN_REJECT;
2767 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2769 case IO_XFER_ERROR_RX_FRAME:
2770 PM8001_IO_DBG(pm8001_ha,
2771 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2772 ts->resp = SAS_TASK_COMPLETE;
2773 ts->stat = SAS_DEV_NO_RESPONSE;
2775 case IO_XFER_OPEN_RETRY_TIMEOUT:
2776 PM8001_IO_DBG(pm8001_ha,
2777 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2778 ts->resp = SAS_TASK_COMPLETE;
2779 ts->stat = SAS_OPEN_REJECT;
2780 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2782 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2783 PM8001_IO_DBG(pm8001_ha,
2784 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2785 ts->resp = SAS_TASK_COMPLETE;
2786 ts->stat = SAS_QUEUE_FULL;
2788 case IO_PORT_IN_RESET:
2789 PM8001_IO_DBG(pm8001_ha,
2790 pm8001_printk("IO_PORT_IN_RESET\n"));
2791 ts->resp = SAS_TASK_COMPLETE;
2792 ts->stat = SAS_OPEN_REJECT;
2793 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2795 case IO_DS_NON_OPERATIONAL:
2796 PM8001_IO_DBG(pm8001_ha,
2797 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2798 ts->resp = SAS_TASK_COMPLETE;
2799 ts->stat = SAS_DEV_NO_RESPONSE;
2801 case IO_DS_IN_RECOVERY:
2802 PM8001_IO_DBG(pm8001_ha,
2803 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2804 ts->resp = SAS_TASK_COMPLETE;
2805 ts->stat = SAS_OPEN_REJECT;
2806 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2808 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2809 PM8001_IO_DBG(pm8001_ha,
2810 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2811 ts->resp = SAS_TASK_COMPLETE;
2812 ts->stat = SAS_OPEN_REJECT;
2813 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2816 PM8001_IO_DBG(pm8001_ha,
2817 pm8001_printk("Unknown status 0x%x\n", status));
2818 ts->resp = SAS_TASK_COMPLETE;
2819 ts->stat = SAS_DEV_NO_RESPONSE;
2820 /* not allowed case. Therefore, return failed status */
2823 spin_lock_irqsave(&t->task_state_lock, flags);
2824 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2825 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2826 t->task_state_flags |= SAS_TASK_STATE_DONE;
2827 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2828 spin_unlock_irqrestore(&t->task_state_lock, flags);
2829 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2830 "task 0x%p done with io_status 0x%x resp 0x%x"
2831 "stat 0x%x but aborted by upper layer!\n",
2832 t, status, ts->resp, ts->stat));
2833 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2835 spin_unlock_irqrestore(&t->task_state_lock, flags);
2836 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2837 mb();/* in order to force CPU ordering */
2843 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2844 * @pm8001_ha: our hba card information
2845 * @Qnum: the outbound queue message number.
2846 * @SEA: source of event to ack
2847 * @port_id: port id.
2849 * @param0: parameter 0.
2850 * @param1: parameter 1.
2852 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2853 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2855 struct hw_event_ack_req payload;
2856 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2858 struct inbound_queue_table *circularQ;
2860 memset((u8 *)&payload, 0, sizeof(payload));
2861 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2862 payload.tag = cpu_to_le32(1);
2863 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2864 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2865 payload.param0 = cpu_to_le32(param0);
2866 payload.param1 = cpu_to_le32(param1);
2867 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2870 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2871 u32 phyId, u32 phy_op);
2873 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2876 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2877 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2878 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2879 u32 lr_status_evt_portid =
2880 le32_to_cpu(pPayload->lr_status_evt_portid);
2881 u8 deviceType = pPayload->sas_identify.dev_type;
2882 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2883 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2884 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2885 struct pm8001_port *port = &pm8001_ha->port[port_id];
2887 if (deviceType == SAS_END_DEVICE) {
2888 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2889 PHY_NOTIFY_ENABLE_SPINUP);
2892 port->wide_port_phymap |= (1U << phy_id);
2893 pm8001_get_lrate_mode(phy, link_rate);
2894 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2895 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2896 phy->phy_attached = 1;
2900 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2901 * @pm8001_ha: our hba card information
2902 * @piomb: IO message buffer
2905 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2907 struct hw_event_resp *pPayload =
2908 (struct hw_event_resp *)(piomb + 4);
2909 u32 lr_status_evt_portid =
2910 le32_to_cpu(pPayload->lr_status_evt_portid);
2911 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2914 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2915 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2917 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2918 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2920 struct pm8001_port *port = &pm8001_ha->port[port_id];
2921 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2922 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2923 unsigned long flags;
2924 u8 deviceType = pPayload->sas_identify.dev_type;
2925 port->port_state = portstate;
2926 port->wide_port_phymap |= (1U << phy_id);
2927 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2928 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2929 "portid:%d; phyid:%d; linkrate:%d; "
2930 "portstate:%x; devicetype:%x\n",
2931 port_id, phy_id, link_rate, portstate, deviceType));
2933 switch (deviceType) {
2934 case SAS_PHY_UNUSED:
2935 PM8001_MSG_DBG(pm8001_ha,
2936 pm8001_printk("device type no device.\n"));
2938 case SAS_END_DEVICE:
2939 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2940 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2941 PHY_NOTIFY_ENABLE_SPINUP);
2942 port->port_attached = 1;
2943 pm8001_get_lrate_mode(phy, link_rate);
2945 case SAS_EDGE_EXPANDER_DEVICE:
2946 PM8001_MSG_DBG(pm8001_ha,
2947 pm8001_printk("expander device.\n"));
2948 port->port_attached = 1;
2949 pm8001_get_lrate_mode(phy, link_rate);
2951 case SAS_FANOUT_EXPANDER_DEVICE:
2952 PM8001_MSG_DBG(pm8001_ha,
2953 pm8001_printk("fanout expander device.\n"));
2954 port->port_attached = 1;
2955 pm8001_get_lrate_mode(phy, link_rate);
2958 PM8001_MSG_DBG(pm8001_ha,
2959 pm8001_printk("unknown device type(%x)\n", deviceType));
2962 phy->phy_type |= PORT_TYPE_SAS;
2963 phy->identify.device_type = deviceType;
2964 phy->phy_attached = 1;
2965 if (phy->identify.device_type == SAS_END_DEVICE)
2966 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2967 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2968 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2969 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2970 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2971 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2972 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2973 sizeof(struct sas_identify_frame)-4);
2974 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2975 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2976 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2977 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2978 mdelay(200);/*delay a moment to wait disk to spinup*/
2979 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2983 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2984 * @pm8001_ha: our hba card information
2985 * @piomb: IO message buffer
2988 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2990 struct hw_event_resp *pPayload =
2991 (struct hw_event_resp *)(piomb + 4);
2992 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2993 u32 lr_status_evt_portid =
2994 le32_to_cpu(pPayload->lr_status_evt_portid);
2996 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2997 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2999 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3001 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3003 struct pm8001_port *port = &pm8001_ha->port[port_id];
3004 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3005 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3006 unsigned long flags;
3007 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3008 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3009 port_id, phy_id, link_rate, portstate));
3011 port->port_state = portstate;
3012 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3013 port->port_attached = 1;
3014 pm8001_get_lrate_mode(phy, link_rate);
3015 phy->phy_type |= PORT_TYPE_SATA;
3016 phy->phy_attached = 1;
3017 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3018 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3019 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3020 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3021 sizeof(struct dev_to_host_fis));
3022 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3023 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3024 phy->identify.device_type = SAS_SATA_DEV;
3025 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3026 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3027 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3031 * hw_event_phy_down -we should notify the libsas the phy is down.
3032 * @pm8001_ha: our hba card information
3033 * @piomb: IO message buffer
3036 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3038 struct hw_event_resp *pPayload =
3039 (struct hw_event_resp *)(piomb + 4);
3041 u32 lr_status_evt_portid =
3042 le32_to_cpu(pPayload->lr_status_evt_portid);
3043 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3044 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3046 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3047 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3049 struct pm8001_port *port = &pm8001_ha->port[port_id];
3050 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3051 port->port_state = portstate;
3052 phy->identify.device_type = 0;
3053 phy->phy_attached = 0;
3054 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3055 switch (portstate) {
3059 PM8001_MSG_DBG(pm8001_ha,
3060 pm8001_printk(" PortInvalid portID %d\n", port_id));
3061 PM8001_MSG_DBG(pm8001_ha,
3062 pm8001_printk(" Last phy Down and port invalid\n"));
3063 if (phy->phy_type & PORT_TYPE_SATA) {
3065 port->port_attached = 0;
3066 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3067 port_id, phy_id, 0, 0);
3069 sas_phy_disconnected(&phy->sas_phy);
3072 PM8001_MSG_DBG(pm8001_ha,
3073 pm8001_printk(" Port In Reset portID %d\n", port_id));
3075 case PORT_NOT_ESTABLISHED:
3076 PM8001_MSG_DBG(pm8001_ha,
3077 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3078 port->port_attached = 0;
3081 PM8001_MSG_DBG(pm8001_ha,
3082 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3083 PM8001_MSG_DBG(pm8001_ha,
3084 pm8001_printk(" Last phy Down and port invalid\n"));
3085 if (phy->phy_type & PORT_TYPE_SATA) {
3086 port->port_attached = 0;
3088 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3089 port_id, phy_id, 0, 0);
3091 sas_phy_disconnected(&phy->sas_phy);
3094 port->port_attached = 0;
3095 PM8001_MSG_DBG(pm8001_ha,
3096 pm8001_printk(" Phy Down and(default) = 0x%x\n",
3103 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3105 struct phy_start_resp *pPayload =
3106 (struct phy_start_resp *)(piomb + 4);
3108 le32_to_cpu(pPayload->status);
3110 le32_to_cpu(pPayload->phyid);
3111 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3113 PM8001_INIT_DBG(pm8001_ha,
3114 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3118 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3119 complete(phy->enable_completion);
3126 * mpi_thermal_hw_event -The hw event has come.
3127 * @pm8001_ha: our hba card information
3128 * @piomb: IO message buffer
3130 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3132 struct thermal_hw_event *pPayload =
3133 (struct thermal_hw_event *)(piomb + 4);
3135 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3136 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3138 if (thermal_event & 0x40) {
3139 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3140 "Thermal Event: Local high temperature violated!\n"));
3141 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3142 "Thermal Event: Measured local high temperature %d\n",
3143 ((rht_lht & 0xFF00) >> 8)));
3145 if (thermal_event & 0x10) {
3146 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3147 "Thermal Event: Remote high temperature violated!\n"));
3148 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3149 "Thermal Event: Measured remote high temperature %d\n",
3150 ((rht_lht & 0xFF000000) >> 24)));
3156 * mpi_hw_event -The hw event has come.
3157 * @pm8001_ha: our hba card information
3158 * @piomb: IO message buffer
3160 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3162 unsigned long flags, i;
3163 struct hw_event_resp *pPayload =
3164 (struct hw_event_resp *)(piomb + 4);
3165 u32 lr_status_evt_portid =
3166 le32_to_cpu(pPayload->lr_status_evt_portid);
3167 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3168 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3170 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3172 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3174 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3175 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3176 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3177 struct pm8001_port *port = &pm8001_ha->port[port_id];
3178 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3179 PM8001_MSG_DBG(pm8001_ha,
3180 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3181 port_id, phy_id, eventType, status));
3183 switch (eventType) {
3185 case HW_EVENT_SAS_PHY_UP:
3186 PM8001_MSG_DBG(pm8001_ha,
3187 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3188 hw_event_sas_phy_up(pm8001_ha, piomb);
3190 case HW_EVENT_SATA_PHY_UP:
3191 PM8001_MSG_DBG(pm8001_ha,
3192 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3193 hw_event_sata_phy_up(pm8001_ha, piomb);
3195 case HW_EVENT_SATA_SPINUP_HOLD:
3196 PM8001_MSG_DBG(pm8001_ha,
3197 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3198 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3200 case HW_EVENT_PHY_DOWN:
3201 PM8001_MSG_DBG(pm8001_ha,
3202 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3203 if (phy->phy_type & PORT_TYPE_SATA)
3204 sas_ha->notify_phy_event(&phy->sas_phy,
3205 PHYE_LOSS_OF_SIGNAL);
3206 phy->phy_attached = 0;
3208 hw_event_phy_down(pm8001_ha, piomb);
3210 case HW_EVENT_PORT_INVALID:
3211 PM8001_MSG_DBG(pm8001_ha,
3212 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3213 sas_phy_disconnected(sas_phy);
3214 phy->phy_attached = 0;
3215 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3217 /* the broadcast change primitive received, tell the LIBSAS this event
3218 to revalidate the sas domain*/
3219 case HW_EVENT_BROADCAST_CHANGE:
3220 PM8001_MSG_DBG(pm8001_ha,
3221 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3222 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3223 port_id, phy_id, 1, 0);
3224 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3225 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3226 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3227 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3229 case HW_EVENT_PHY_ERROR:
3230 PM8001_MSG_DBG(pm8001_ha,
3231 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3232 sas_phy_disconnected(&phy->sas_phy);
3233 phy->phy_attached = 0;
3234 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3236 case HW_EVENT_BROADCAST_EXP:
3237 PM8001_MSG_DBG(pm8001_ha,
3238 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3239 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3240 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3241 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3242 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3244 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3245 PM8001_MSG_DBG(pm8001_ha,
3246 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3247 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3248 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3250 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3251 PM8001_MSG_DBG(pm8001_ha,
3252 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3253 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3254 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3255 port_id, phy_id, 0, 0);
3257 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3258 PM8001_MSG_DBG(pm8001_ha,
3259 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3260 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3261 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3262 port_id, phy_id, 0, 0);
3264 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3265 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3266 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3267 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3268 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3269 port_id, phy_id, 0, 0);
3271 case HW_EVENT_MALFUNCTION:
3272 PM8001_MSG_DBG(pm8001_ha,
3273 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3275 case HW_EVENT_BROADCAST_SES:
3276 PM8001_MSG_DBG(pm8001_ha,
3277 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3278 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3279 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3280 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3281 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3283 case HW_EVENT_INBOUND_CRC_ERROR:
3284 PM8001_MSG_DBG(pm8001_ha,
3285 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3286 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3287 HW_EVENT_INBOUND_CRC_ERROR,
3288 port_id, phy_id, 0, 0);
3290 case HW_EVENT_HARD_RESET_RECEIVED:
3291 PM8001_MSG_DBG(pm8001_ha,
3292 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3293 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3295 case HW_EVENT_ID_FRAME_TIMEOUT:
3296 PM8001_MSG_DBG(pm8001_ha,
3297 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3298 sas_phy_disconnected(sas_phy);
3299 phy->phy_attached = 0;
3300 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3302 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3303 PM8001_MSG_DBG(pm8001_ha,
3304 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3305 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3306 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3307 port_id, phy_id, 0, 0);
3308 sas_phy_disconnected(sas_phy);
3309 phy->phy_attached = 0;
3310 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3312 case HW_EVENT_PORT_RESET_TIMER_TMO:
3313 PM8001_MSG_DBG(pm8001_ha,
3314 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3315 sas_phy_disconnected(sas_phy);
3316 phy->phy_attached = 0;
3317 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3319 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3320 PM8001_MSG_DBG(pm8001_ha,
3321 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3322 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3323 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3324 port_id, phy_id, 0, 0);
3325 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3326 if (port->wide_port_phymap & (1 << i)) {
3327 phy = &pm8001_ha->phy[i];
3328 sas_ha->notify_phy_event(&phy->sas_phy,
3329 PHYE_LOSS_OF_SIGNAL);
3330 port->wide_port_phymap &= ~(1 << i);
3334 case HW_EVENT_PORT_RECOVER:
3335 PM8001_MSG_DBG(pm8001_ha,
3336 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3337 hw_event_port_recover(pm8001_ha, piomb);
3339 case HW_EVENT_PORT_RESET_COMPLETE:
3340 PM8001_MSG_DBG(pm8001_ha,
3341 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3343 case EVENT_BROADCAST_ASYNCH_EVENT:
3344 PM8001_MSG_DBG(pm8001_ha,
3345 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3348 PM8001_MSG_DBG(pm8001_ha,
3349 pm8001_printk("Unknown event type 0x%x\n", eventType));
3356 * mpi_phy_stop_resp - SPCv specific
3357 * @pm8001_ha: our hba card information
3358 * @piomb: IO message buffer
3360 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3362 struct phy_stop_resp *pPayload =
3363 (struct phy_stop_resp *)(piomb + 4);
3365 le32_to_cpu(pPayload->status);
3367 le32_to_cpu(pPayload->phyid);
3368 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3369 PM8001_MSG_DBG(pm8001_ha,
3370 pm8001_printk("phy:0x%x status:0x%x\n",
3378 * mpi_set_controller_config_resp - SPCv specific
3379 * @pm8001_ha: our hba card information
3380 * @piomb: IO message buffer
3382 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3385 struct set_ctrl_cfg_resp *pPayload =
3386 (struct set_ctrl_cfg_resp *)(piomb + 4);
3387 u32 status = le32_to_cpu(pPayload->status);
3388 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3390 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3391 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3392 status, err_qlfr_pgcd));
3398 * mpi_get_controller_config_resp - SPCv specific
3399 * @pm8001_ha: our hba card information
3400 * @piomb: IO message buffer
3402 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3405 PM8001_MSG_DBG(pm8001_ha,
3406 pm8001_printk(" pm80xx_addition_functionality\n"));
3412 * mpi_get_phy_profile_resp - SPCv specific
3413 * @pm8001_ha: our hba card information
3414 * @piomb: IO message buffer
3416 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3419 PM8001_MSG_DBG(pm8001_ha,
3420 pm8001_printk(" pm80xx_addition_functionality\n"));
3426 * mpi_flash_op_ext_resp - SPCv specific
3427 * @pm8001_ha: our hba card information
3428 * @piomb: IO message buffer
3430 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3432 PM8001_MSG_DBG(pm8001_ha,
3433 pm8001_printk(" pm80xx_addition_functionality\n"));
3439 * mpi_set_phy_profile_resp - SPCv specific
3440 * @pm8001_ha: our hba card information
3441 * @piomb: IO message buffer
3443 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3447 struct set_phy_profile_resp *pPayload =
3448 (struct set_phy_profile_resp *)(piomb + 4);
3449 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3450 u32 status = le32_to_cpu(pPayload->status);
3452 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3454 /* status is FAILED */
3455 PM8001_FAIL_DBG(pm8001_ha,
3456 pm8001_printk("PhyProfile command failed with status "
3457 "0x%08X \n", status));
3460 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3461 PM8001_FAIL_DBG(pm8001_ha,
3462 pm8001_printk("Invalid page code 0x%X\n",
3471 * mpi_kek_management_resp - SPCv specific
3472 * @pm8001_ha: our hba card information
3473 * @piomb: IO message buffer
3475 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3478 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3480 u32 status = le32_to_cpu(pPayload->status);
3481 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3482 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3484 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3485 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3486 status, kidx_new_curr_ksop, err_qlfr));
3492 * mpi_dek_management_resp - SPCv specific
3493 * @pm8001_ha: our hba card information
3494 * @piomb: IO message buffer
3496 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3499 PM8001_MSG_DBG(pm8001_ha,
3500 pm8001_printk(" pm80xx_addition_functionality\n"));
3506 * ssp_coalesced_comp_resp - SPCv specific
3507 * @pm8001_ha: our hba card information
3508 * @piomb: IO message buffer
3510 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3513 PM8001_MSG_DBG(pm8001_ha,
3514 pm8001_printk(" pm80xx_addition_functionality\n"));
3520 * process_one_iomb - process one outbound Queue memory block
3521 * @pm8001_ha: our hba card information
3522 * @piomb: IO message buffer
3524 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3526 __le32 pHeader = *(__le32 *)piomb;
3527 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3531 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3533 case OPC_OUB_HW_EVENT:
3534 PM8001_MSG_DBG(pm8001_ha,
3535 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3536 mpi_hw_event(pm8001_ha, piomb);
3538 case OPC_OUB_THERM_HW_EVENT:
3539 PM8001_MSG_DBG(pm8001_ha,
3540 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3541 mpi_thermal_hw_event(pm8001_ha, piomb);
3543 case OPC_OUB_SSP_COMP:
3544 PM8001_MSG_DBG(pm8001_ha,
3545 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3546 mpi_ssp_completion(pm8001_ha, piomb);
3548 case OPC_OUB_SMP_COMP:
3549 PM8001_MSG_DBG(pm8001_ha,
3550 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3551 mpi_smp_completion(pm8001_ha, piomb);
3553 case OPC_OUB_LOCAL_PHY_CNTRL:
3554 PM8001_MSG_DBG(pm8001_ha,
3555 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3556 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3558 case OPC_OUB_DEV_REGIST:
3559 PM8001_MSG_DBG(pm8001_ha,
3560 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3561 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3563 case OPC_OUB_DEREG_DEV:
3564 PM8001_MSG_DBG(pm8001_ha,
3565 pm8001_printk("unregister the device\n"));
3566 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3568 case OPC_OUB_GET_DEV_HANDLE:
3569 PM8001_MSG_DBG(pm8001_ha,
3570 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3572 case OPC_OUB_SATA_COMP:
3573 PM8001_MSG_DBG(pm8001_ha,
3574 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3575 mpi_sata_completion(pm8001_ha, piomb);
3577 case OPC_OUB_SATA_EVENT:
3578 PM8001_MSG_DBG(pm8001_ha,
3579 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3580 mpi_sata_event(pm8001_ha, piomb);
3582 case OPC_OUB_SSP_EVENT:
3583 PM8001_MSG_DBG(pm8001_ha,
3584 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3585 mpi_ssp_event(pm8001_ha, piomb);
3587 case OPC_OUB_DEV_HANDLE_ARRIV:
3588 PM8001_MSG_DBG(pm8001_ha,
3589 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3590 /*This is for target*/
3592 case OPC_OUB_SSP_RECV_EVENT:
3593 PM8001_MSG_DBG(pm8001_ha,
3594 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3595 /*This is for target*/
3597 case OPC_OUB_FW_FLASH_UPDATE:
3598 PM8001_MSG_DBG(pm8001_ha,
3599 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3600 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3602 case OPC_OUB_GPIO_RESPONSE:
3603 PM8001_MSG_DBG(pm8001_ha,
3604 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3606 case OPC_OUB_GPIO_EVENT:
3607 PM8001_MSG_DBG(pm8001_ha,
3608 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3610 case OPC_OUB_GENERAL_EVENT:
3611 PM8001_MSG_DBG(pm8001_ha,
3612 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3613 pm8001_mpi_general_event(pm8001_ha, piomb);
3615 case OPC_OUB_SSP_ABORT_RSP:
3616 PM8001_MSG_DBG(pm8001_ha,
3617 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3618 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3620 case OPC_OUB_SATA_ABORT_RSP:
3621 PM8001_MSG_DBG(pm8001_ha,
3622 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3623 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3625 case OPC_OUB_SAS_DIAG_MODE_START_END:
3626 PM8001_MSG_DBG(pm8001_ha,
3627 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3629 case OPC_OUB_SAS_DIAG_EXECUTE:
3630 PM8001_MSG_DBG(pm8001_ha,
3631 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3633 case OPC_OUB_GET_TIME_STAMP:
3634 PM8001_MSG_DBG(pm8001_ha,
3635 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3637 case OPC_OUB_SAS_HW_EVENT_ACK:
3638 PM8001_MSG_DBG(pm8001_ha,
3639 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3641 case OPC_OUB_PORT_CONTROL:
3642 PM8001_MSG_DBG(pm8001_ha,
3643 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3645 case OPC_OUB_SMP_ABORT_RSP:
3646 PM8001_MSG_DBG(pm8001_ha,
3647 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3648 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3650 case OPC_OUB_GET_NVMD_DATA:
3651 PM8001_MSG_DBG(pm8001_ha,
3652 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3653 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3655 case OPC_OUB_SET_NVMD_DATA:
3656 PM8001_MSG_DBG(pm8001_ha,
3657 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3658 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3660 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3661 PM8001_MSG_DBG(pm8001_ha,
3662 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3664 case OPC_OUB_SET_DEVICE_STATE:
3665 PM8001_MSG_DBG(pm8001_ha,
3666 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3667 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3669 case OPC_OUB_GET_DEVICE_STATE:
3670 PM8001_MSG_DBG(pm8001_ha,
3671 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3673 case OPC_OUB_SET_DEV_INFO:
3674 PM8001_MSG_DBG(pm8001_ha,
3675 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3677 /* spcv specifc commands */
3678 case OPC_OUB_PHY_START_RESP:
3679 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3680 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3681 mpi_phy_start_resp(pm8001_ha, piomb);
3683 case OPC_OUB_PHY_STOP_RESP:
3684 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3685 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3686 mpi_phy_stop_resp(pm8001_ha, piomb);
3688 case OPC_OUB_SET_CONTROLLER_CONFIG:
3689 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3690 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3691 mpi_set_controller_config_resp(pm8001_ha, piomb);
3693 case OPC_OUB_GET_CONTROLLER_CONFIG:
3694 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3695 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3696 mpi_get_controller_config_resp(pm8001_ha, piomb);
3698 case OPC_OUB_GET_PHY_PROFILE:
3699 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3700 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3701 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3703 case OPC_OUB_FLASH_OP_EXT:
3704 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3705 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3706 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3708 case OPC_OUB_SET_PHY_PROFILE:
3709 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3710 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3711 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3713 case OPC_OUB_KEK_MANAGEMENT_RESP:
3714 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3715 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3716 mpi_kek_management_resp(pm8001_ha, piomb);
3718 case OPC_OUB_DEK_MANAGEMENT_RESP:
3719 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3720 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3721 mpi_dek_management_resp(pm8001_ha, piomb);
3723 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3724 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3725 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3726 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3729 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3730 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3735 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
3737 PM8001_FAIL_DBG(pm8001_ha,
3738 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
3739 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
3740 PM8001_FAIL_DBG(pm8001_ha,
3741 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
3742 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
3743 PM8001_FAIL_DBG(pm8001_ha,
3744 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
3745 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
3746 PM8001_FAIL_DBG(pm8001_ha,
3747 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
3748 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
3749 PM8001_FAIL_DBG(pm8001_ha,
3750 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
3751 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
3752 PM8001_FAIL_DBG(pm8001_ha,
3753 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
3754 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
3755 PM8001_FAIL_DBG(pm8001_ha,
3756 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
3757 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
3758 PM8001_FAIL_DBG(pm8001_ha,
3759 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
3760 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
3761 PM8001_FAIL_DBG(pm8001_ha,
3762 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
3763 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
3764 PM8001_FAIL_DBG(pm8001_ha,
3765 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
3766 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
3767 PM8001_FAIL_DBG(pm8001_ha,
3768 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
3769 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
3770 PM8001_FAIL_DBG(pm8001_ha,
3771 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
3772 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
3775 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3777 struct outbound_queue_table *circularQ;
3780 u32 ret = MPI_IO_STATUS_FAIL;
3781 unsigned long flags;
3784 if (vec == (pm8001_ha->number_of_intr - 1)) {
3785 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
3786 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
3787 SCRATCH_PAD_MIPSALL_READY) {
3788 pm8001_ha->controller_fatal_error = true;
3789 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3790 "Firmware Fatal error! Regval:0x%x\n", regval));
3791 print_scratchpad_registers(pm8001_ha);
3795 spin_lock_irqsave(&pm8001_ha->lock, flags);
3796 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3798 /* spurious interrupt during setup if kexec-ing and
3799 * driver doing a doorbell access w/ the pre-kexec oq
3802 if (!circularQ->pi_virt)
3804 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3805 if (MPI_IO_STATUS_SUCCESS == ret) {
3806 /* process the outbound message */
3807 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3808 /* free the message from the outbound circular buffer */
3809 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3812 if (MPI_IO_STATUS_BUSY == ret) {
3813 /* Update the producer index from SPC */
3814 circularQ->producer_index =
3815 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3816 if (le32_to_cpu(circularQ->producer_index) ==
3817 circularQ->consumer_idx)
3822 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3826 /* PCI_DMA_... to our direction translation. */
3827 static const u8 data_dir_flags[] = {
3828 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3829 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3830 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3831 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3834 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3835 struct smp_req *psmp_cmd, int mode, int length)
3837 psmp_cmd->tag = hTag;
3838 psmp_cmd->device_id = cpu_to_le32(deviceID);
3839 if (mode == SMP_DIRECT) {
3840 length = length - 4; /* subtract crc */
3841 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3843 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3848 * pm8001_chip_smp_req - send a SMP task to FW
3849 * @pm8001_ha: our hba card information.
3850 * @ccb: the ccb information this request used.
3852 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3853 struct pm8001_ccb_info *ccb)
3856 struct sas_task *task = ccb->task;
3857 struct domain_device *dev = task->dev;
3858 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3859 struct scatterlist *sg_req, *sg_resp;
3860 u32 req_len, resp_len;
3861 struct smp_req smp_cmd;
3863 struct inbound_queue_table *circularQ;
3864 char *preq_dma_addr = NULL;
3868 memset(&smp_cmd, 0, sizeof(smp_cmd));
3870 * DMA-map SMP request, response buffers
3872 sg_req = &task->smp_task.smp_req;
3873 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3876 req_len = sg_dma_len(sg_req);
3878 sg_resp = &task->smp_task.smp_resp;
3879 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3884 resp_len = sg_dma_len(sg_resp);
3885 /* must be in dwords */
3886 if ((req_len & 0x3) || (resp_len & 0x3)) {
3891 opc = OPC_INB_SMP_REQUEST;
3892 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3893 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3895 length = sg_req->length;
3896 PM8001_IO_DBG(pm8001_ha,
3897 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3899 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3901 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3904 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3905 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3907 /* INDIRECT MODE command settings. Use DMA */
3908 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3909 PM8001_IO_DBG(pm8001_ha,
3910 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3911 /* for SPCv indirect mode. Place the top 4 bytes of
3912 * SMP Request header here. */
3913 for (i = 0; i < 4; i++)
3914 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3915 /* exclude top 4 bytes for SMP req header */
3916 smp_cmd.long_smp_req.long_req_addr =
3917 cpu_to_le64((u64)sg_dma_address
3918 (&task->smp_task.smp_req) + 4);
3919 /* exclude 4 bytes for SMP req header and CRC */
3920 smp_cmd.long_smp_req.long_req_size =
3921 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3922 smp_cmd.long_smp_req.long_resp_addr =
3923 cpu_to_le64((u64)sg_dma_address
3924 (&task->smp_task.smp_resp));
3925 smp_cmd.long_smp_req.long_resp_size =
3926 cpu_to_le32((u32)sg_dma_len
3927 (&task->smp_task.smp_resp)-4);
3928 } else { /* DIRECT MODE */
3929 smp_cmd.long_smp_req.long_req_addr =
3930 cpu_to_le64((u64)sg_dma_address
3931 (&task->smp_task.smp_req));
3932 smp_cmd.long_smp_req.long_req_size =
3933 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3934 smp_cmd.long_smp_req.long_resp_addr =
3935 cpu_to_le64((u64)sg_dma_address
3936 (&task->smp_task.smp_resp));
3937 smp_cmd.long_smp_req.long_resp_size =
3939 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3941 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3942 PM8001_IO_DBG(pm8001_ha,
3943 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3944 for (i = 0; i < length; i++)
3946 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3947 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3948 "Byte[%d]:%x (DMA data:%x)\n",
3949 i, smp_cmd.smp_req16[i],
3952 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3953 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3954 "Byte[%d]:%x (DMA data:%x)\n",
3955 i, smp_cmd.smp_req[i],
3960 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3961 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3962 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3963 (u32 *)&smp_cmd, 0);
3969 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3970 PCI_DMA_FROMDEVICE);
3972 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3977 static int check_enc_sas_cmd(struct sas_task *task)
3979 u8 cmd = task->ssp_task.cmd->cmnd[0];
3981 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3987 static int check_enc_sat_cmd(struct sas_task *task)
3990 switch (task->ata_task.fis.command) {
3991 case ATA_CMD_FPDMA_READ:
3992 case ATA_CMD_READ_EXT:
3994 case ATA_CMD_FPDMA_WRITE:
3995 case ATA_CMD_WRITE_EXT:
3997 case ATA_CMD_PIO_READ:
3998 case ATA_CMD_PIO_READ_EXT:
3999 case ATA_CMD_PIO_WRITE:
4000 case ATA_CMD_PIO_WRITE_EXT:
4011 * pm80xx_chip_ssp_io_req - send a SSP task to FW
4012 * @pm8001_ha: our hba card information.
4013 * @ccb: the ccb information this request used.
4015 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4016 struct pm8001_ccb_info *ccb)
4018 struct sas_task *task = ccb->task;
4019 struct domain_device *dev = task->dev;
4020 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4021 struct ssp_ini_io_start_req ssp_cmd;
4022 u32 tag = ccb->ccb_tag;
4024 u64 phys_addr, start_addr, end_addr;
4025 u32 end_addr_high, end_addr_low;
4026 struct inbound_queue_table *circularQ;
4028 u32 opc = OPC_INB_SSPINIIOSTART;
4029 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4030 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4031 /* data address domain added for spcv; set to 0 by host,
4032 * used internally by controller
4033 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4035 ssp_cmd.dad_dir_m_tlr =
4036 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4037 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4038 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4039 ssp_cmd.tag = cpu_to_le32(tag);
4040 if (task->ssp_task.enable_first_burst)
4041 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4042 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4043 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4044 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4045 task->ssp_task.cmd->cmd_len);
4046 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4047 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4049 /* Check if encryption is set */
4050 if (pm8001_ha->chip->encrypt &&
4051 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4052 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4053 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4054 task->ssp_task.cmd->cmnd[0]));
4055 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4056 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4057 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4058 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4060 /* fill in PRD (scatter/gather) table, if any */
4061 if (task->num_scatter > 1) {
4062 pm8001_chip_make_sg(task->scatter,
4063 ccb->n_elem, ccb->buf_prd);
4064 phys_addr = ccb->ccb_dma_handle +
4065 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4066 ssp_cmd.enc_addr_low =
4067 cpu_to_le32(lower_32_bits(phys_addr));
4068 ssp_cmd.enc_addr_high =
4069 cpu_to_le32(upper_32_bits(phys_addr));
4070 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4071 } else if (task->num_scatter == 1) {
4072 u64 dma_addr = sg_dma_address(task->scatter);
4073 ssp_cmd.enc_addr_low =
4074 cpu_to_le32(lower_32_bits(dma_addr));
4075 ssp_cmd.enc_addr_high =
4076 cpu_to_le32(upper_32_bits(dma_addr));
4077 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4078 ssp_cmd.enc_esgl = 0;
4079 /* Check 4G Boundary */
4080 start_addr = cpu_to_le64(dma_addr);
4081 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4082 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4083 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4084 if (end_addr_high != ssp_cmd.enc_addr_high) {
4085 PM8001_FAIL_DBG(pm8001_ha,
4086 pm8001_printk("The sg list address "
4087 "start_addr=0x%016llx data_len=0x%x "
4088 "end_addr_high=0x%08x end_addr_low="
4089 "0x%08x has crossed 4G boundary\n",
4090 start_addr, ssp_cmd.enc_len,
4091 end_addr_high, end_addr_low));
4092 pm8001_chip_make_sg(task->scatter, 1,
4094 phys_addr = ccb->ccb_dma_handle +
4095 offsetof(struct pm8001_ccb_info,
4097 ssp_cmd.enc_addr_low =
4098 cpu_to_le32(lower_32_bits(phys_addr));
4099 ssp_cmd.enc_addr_high =
4100 cpu_to_le32(upper_32_bits(phys_addr));
4101 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4103 } else if (task->num_scatter == 0) {
4104 ssp_cmd.enc_addr_low = 0;
4105 ssp_cmd.enc_addr_high = 0;
4106 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4107 ssp_cmd.enc_esgl = 0;
4109 /* XTS mode. All other fields are 0 */
4110 ssp_cmd.key_cmode = 0x6 << 4;
4111 /* set tweak values. Should be the start lba */
4112 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4113 (task->ssp_task.cmd->cmnd[3] << 16) |
4114 (task->ssp_task.cmd->cmnd[4] << 8) |
4115 (task->ssp_task.cmd->cmnd[5]));
4117 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4118 "Sending Normal SAS command 0x%x inb q %x\n",
4119 task->ssp_task.cmd->cmnd[0], q_index));
4120 /* fill in PRD (scatter/gather) table, if any */
4121 if (task->num_scatter > 1) {
4122 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4124 phys_addr = ccb->ccb_dma_handle +
4125 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4127 cpu_to_le32(lower_32_bits(phys_addr));
4129 cpu_to_le32(upper_32_bits(phys_addr));
4130 ssp_cmd.esgl = cpu_to_le32(1<<31);
4131 } else if (task->num_scatter == 1) {
4132 u64 dma_addr = sg_dma_address(task->scatter);
4133 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4135 cpu_to_le32(upper_32_bits(dma_addr));
4136 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4138 /* Check 4G Boundary */
4139 start_addr = cpu_to_le64(dma_addr);
4140 end_addr = (start_addr + ssp_cmd.len) - 1;
4141 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4142 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4143 if (end_addr_high != ssp_cmd.addr_high) {
4144 PM8001_FAIL_DBG(pm8001_ha,
4145 pm8001_printk("The sg list address "
4146 "start_addr=0x%016llx data_len=0x%x "
4147 "end_addr_high=0x%08x end_addr_low="
4148 "0x%08x has crossed 4G boundary\n",
4149 start_addr, ssp_cmd.len,
4150 end_addr_high, end_addr_low));
4151 pm8001_chip_make_sg(task->scatter, 1,
4153 phys_addr = ccb->ccb_dma_handle +
4154 offsetof(struct pm8001_ccb_info,
4157 cpu_to_le32(lower_32_bits(phys_addr));
4159 cpu_to_le32(upper_32_bits(phys_addr));
4160 ssp_cmd.esgl = cpu_to_le32(1<<31);
4162 } else if (task->num_scatter == 0) {
4163 ssp_cmd.addr_low = 0;
4164 ssp_cmd.addr_high = 0;
4165 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4169 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4170 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4175 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4176 struct pm8001_ccb_info *ccb)
4178 struct sas_task *task = ccb->task;
4179 struct domain_device *dev = task->dev;
4180 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4181 u32 tag = ccb->ccb_tag;
4184 struct sata_start_req sata_cmd;
4185 u32 hdr_tag, ncg_tag = 0;
4186 u64 phys_addr, start_addr, end_addr;
4187 u32 end_addr_high, end_addr_low;
4190 struct inbound_queue_table *circularQ;
4191 unsigned long flags;
4192 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4193 memset(&sata_cmd, 0, sizeof(sata_cmd));
4194 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4195 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4197 if (task->data_dir == PCI_DMA_NONE) {
4198 ATAP = 0x04; /* no data*/
4199 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4200 } else if (likely(!task->ata_task.device_control_reg_update)) {
4201 if (task->ata_task.dma_xfer) {
4202 ATAP = 0x06; /* DMA */
4203 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4205 ATAP = 0x05; /* PIO*/
4206 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4208 if (task->ata_task.use_ncq &&
4209 dev->sata_dev.class != ATA_DEV_ATAPI) {
4210 ATAP = 0x07; /* FPDMA */
4211 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4214 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4215 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4218 dir = data_dir_flags[task->data_dir] << 8;
4219 sata_cmd.tag = cpu_to_le32(tag);
4220 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4221 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4223 sata_cmd.sata_fis = task->ata_task.fis;
4224 if (likely(!task->ata_task.device_control_reg_update))
4225 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4226 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4228 /* Check if encryption is set */
4229 if (pm8001_ha->chip->encrypt &&
4230 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4231 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4232 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4233 sata_cmd.sata_fis.command));
4234 opc = OPC_INB_SATA_DIF_ENC_IO;
4236 /* set encryption bit */
4237 sata_cmd.ncqtag_atap_dir_m_dad =
4238 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4239 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4240 /* dad (bit 0-1) is 0 */
4241 /* fill in PRD (scatter/gather) table, if any */
4242 if (task->num_scatter > 1) {
4243 pm8001_chip_make_sg(task->scatter,
4244 ccb->n_elem, ccb->buf_prd);
4245 phys_addr = ccb->ccb_dma_handle +
4246 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4247 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4248 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4249 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4250 } else if (task->num_scatter == 1) {
4251 u64 dma_addr = sg_dma_address(task->scatter);
4252 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4253 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4254 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4255 sata_cmd.enc_esgl = 0;
4256 /* Check 4G Boundary */
4257 start_addr = cpu_to_le64(dma_addr);
4258 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4259 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4260 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4261 if (end_addr_high != sata_cmd.enc_addr_high) {
4262 PM8001_FAIL_DBG(pm8001_ha,
4263 pm8001_printk("The sg list address "
4264 "start_addr=0x%016llx data_len=0x%x "
4265 "end_addr_high=0x%08x end_addr_low"
4266 "=0x%08x has crossed 4G boundary\n",
4267 start_addr, sata_cmd.enc_len,
4268 end_addr_high, end_addr_low));
4269 pm8001_chip_make_sg(task->scatter, 1,
4271 phys_addr = ccb->ccb_dma_handle +
4272 offsetof(struct pm8001_ccb_info,
4274 sata_cmd.enc_addr_low =
4275 lower_32_bits(phys_addr);
4276 sata_cmd.enc_addr_high =
4277 upper_32_bits(phys_addr);
4279 cpu_to_le32(1 << 31);
4281 } else if (task->num_scatter == 0) {
4282 sata_cmd.enc_addr_low = 0;
4283 sata_cmd.enc_addr_high = 0;
4284 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4285 sata_cmd.enc_esgl = 0;
4287 /* XTS mode. All other fields are 0 */
4288 sata_cmd.key_index_mode = 0x6 << 4;
4289 /* set tweak values. Should be the start lba */
4291 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4292 (sata_cmd.sata_fis.lbah << 16) |
4293 (sata_cmd.sata_fis.lbam << 8) |
4294 (sata_cmd.sata_fis.lbal));
4296 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4297 (sata_cmd.sata_fis.lbam_exp));
4299 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4300 "Sending Normal SATA command 0x%x inb %x\n",
4301 sata_cmd.sata_fis.command, q_index));
4302 /* dad (bit 0-1) is 0 */
4303 sata_cmd.ncqtag_atap_dir_m_dad =
4304 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4305 ((ATAP & 0x3f) << 10) | dir);
4307 /* fill in PRD (scatter/gather) table, if any */
4308 if (task->num_scatter > 1) {
4309 pm8001_chip_make_sg(task->scatter,
4310 ccb->n_elem, ccb->buf_prd);
4311 phys_addr = ccb->ccb_dma_handle +
4312 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4313 sata_cmd.addr_low = lower_32_bits(phys_addr);
4314 sata_cmd.addr_high = upper_32_bits(phys_addr);
4315 sata_cmd.esgl = cpu_to_le32(1 << 31);
4316 } else if (task->num_scatter == 1) {
4317 u64 dma_addr = sg_dma_address(task->scatter);
4318 sata_cmd.addr_low = lower_32_bits(dma_addr);
4319 sata_cmd.addr_high = upper_32_bits(dma_addr);
4320 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4322 /* Check 4G Boundary */
4323 start_addr = cpu_to_le64(dma_addr);
4324 end_addr = (start_addr + sata_cmd.len) - 1;
4325 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4326 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4327 if (end_addr_high != sata_cmd.addr_high) {
4328 PM8001_FAIL_DBG(pm8001_ha,
4329 pm8001_printk("The sg list address "
4330 "start_addr=0x%016llx data_len=0x%x"
4331 "end_addr_high=0x%08x end_addr_low="
4332 "0x%08x has crossed 4G boundary\n",
4333 start_addr, sata_cmd.len,
4334 end_addr_high, end_addr_low));
4335 pm8001_chip_make_sg(task->scatter, 1,
4337 phys_addr = ccb->ccb_dma_handle +
4338 offsetof(struct pm8001_ccb_info,
4341 lower_32_bits(phys_addr);
4342 sata_cmd.addr_high =
4343 upper_32_bits(phys_addr);
4344 sata_cmd.esgl = cpu_to_le32(1 << 31);
4346 } else if (task->num_scatter == 0) {
4347 sata_cmd.addr_low = 0;
4348 sata_cmd.addr_high = 0;
4349 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4353 sata_cmd.atapi_scsi_cdb[0] =
4354 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4355 (task->ata_task.atapi_packet[1] << 8) |
4356 (task->ata_task.atapi_packet[2] << 16) |
4357 (task->ata_task.atapi_packet[3] << 24)));
4358 sata_cmd.atapi_scsi_cdb[1] =
4359 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4360 (task->ata_task.atapi_packet[5] << 8) |
4361 (task->ata_task.atapi_packet[6] << 16) |
4362 (task->ata_task.atapi_packet[7] << 24)));
4363 sata_cmd.atapi_scsi_cdb[2] =
4364 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4365 (task->ata_task.atapi_packet[9] << 8) |
4366 (task->ata_task.atapi_packet[10] << 16) |
4367 (task->ata_task.atapi_packet[11] << 24)));
4368 sata_cmd.atapi_scsi_cdb[3] =
4369 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4370 (task->ata_task.atapi_packet[13] << 8) |
4371 (task->ata_task.atapi_packet[14] << 16) |
4372 (task->ata_task.atapi_packet[15] << 24)));
4375 /* Check for read log for failed drive and return */
4376 if (sata_cmd.sata_fis.command == 0x2f) {
4377 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4378 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4379 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4380 struct task_status_struct *ts;
4382 pm8001_ha_dev->id &= 0xDFFFFFFF;
4383 ts = &task->task_status;
4385 spin_lock_irqsave(&task->task_state_lock, flags);
4386 ts->resp = SAS_TASK_COMPLETE;
4387 ts->stat = SAM_STAT_GOOD;
4388 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4389 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4390 task->task_state_flags |= SAS_TASK_STATE_DONE;
4391 if (unlikely((task->task_state_flags &
4392 SAS_TASK_STATE_ABORTED))) {
4393 spin_unlock_irqrestore(&task->task_state_lock,
4395 PM8001_FAIL_DBG(pm8001_ha,
4396 pm8001_printk("task 0x%p resp 0x%x "
4397 " stat 0x%x but aborted by upper layer "
4398 "\n", task, ts->resp, ts->stat));
4399 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4402 spin_unlock_irqrestore(&task->task_state_lock,
4404 pm8001_ccb_task_free_done(pm8001_ha, task,
4410 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4411 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4412 &sata_cmd, q_index);
4417 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4418 * @pm8001_ha: our hba card information.
4419 * @num: the inbound queue number
4420 * @phy_id: the phy id which we wanted to start up.
4423 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4425 struct phy_start_req payload;
4426 struct inbound_queue_table *circularQ;
4429 u32 opcode = OPC_INB_PHYSTART;
4430 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4431 memset(&payload, 0, sizeof(payload));
4432 payload.tag = cpu_to_le32(tag);
4434 PM8001_INIT_DBG(pm8001_ha,
4435 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4437 ** [0:7] PHY Identifier
4438 ** [8:11] link rate 1.5G, 3G, 6G
4439 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4440 ** [14] 0b disable spin up hold; 1b enable spin up hold
4441 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4443 if (!IS_SPCV_12G(pm8001_ha->pdev))
4444 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4445 LINKMODE_AUTO | LINKRATE_15 |
4446 LINKRATE_30 | LINKRATE_60 | phy_id);
4448 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4449 LINKMODE_AUTO | LINKRATE_15 |
4450 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4453 /* SSC Disable and SAS Analog ST configuration */
4455 payload.ase_sh_lm_slr_phyid =
4456 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4457 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4459 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4462 payload.sas_identify.dev_type = SAS_END_DEVICE;
4463 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4464 memcpy(payload.sas_identify.sas_addr,
4465 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4466 payload.sas_identify.phy_id = phy_id;
4467 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4472 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4473 * @pm8001_ha: our hba card information.
4474 * @num: the inbound queue number
4475 * @phy_id: the phy id which we wanted to start up.
4477 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4480 struct phy_stop_req payload;
4481 struct inbound_queue_table *circularQ;
4484 u32 opcode = OPC_INB_PHYSTOP;
4485 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4486 memset(&payload, 0, sizeof(payload));
4487 payload.tag = cpu_to_le32(tag);
4488 payload.phy_id = cpu_to_le32(phy_id);
4489 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4494 * see comments on pm8001_mpi_reg_resp.
4496 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4497 struct pm8001_device *pm8001_dev, u32 flag)
4499 struct reg_dev_req payload;
4501 u32 stp_sspsmp_sata = 0x4;
4502 struct inbound_queue_table *circularQ;
4503 u32 linkrate, phy_id;
4504 int rc, tag = 0xdeadbeef;
4505 struct pm8001_ccb_info *ccb;
4507 u16 firstBurstSize = 0;
4509 struct domain_device *dev = pm8001_dev->sas_device;
4510 struct domain_device *parent_dev = dev->parent;
4511 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4513 memset(&payload, 0, sizeof(payload));
4514 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4517 ccb = &pm8001_ha->ccb_info[tag];
4518 ccb->device = pm8001_dev;
4520 payload.tag = cpu_to_le32(tag);
4523 stp_sspsmp_sata = 0x02; /*direct attached sata */
4525 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4526 stp_sspsmp_sata = 0x00; /* stp*/
4527 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4528 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4529 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4530 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4532 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4533 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4535 phy_id = pm8001_dev->attached_phy;
4537 opc = OPC_INB_REG_DEV;
4539 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4540 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4542 payload.phyid_portid =
4543 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4544 ((phy_id & 0xFF) << 8));
4546 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4547 ((linkrate & 0x0F) << 24) |
4548 ((stp_sspsmp_sata & 0x03) << 28));
4549 payload.firstburstsize_ITNexustimeout =
4550 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4552 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4555 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4557 pm8001_tag_free(pm8001_ha, tag);
4563 * pm80xx_chip_phy_ctl_req - support the local phy operation
4564 * @pm8001_ha: our hba card information.
4565 * @num: the inbound queue number
4566 * @phy_id: the phy id which we wanted to operate
4569 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4570 u32 phyId, u32 phy_op)
4572 struct local_phy_ctl_req payload;
4573 struct inbound_queue_table *circularQ;
4575 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4576 memset(&payload, 0, sizeof(payload));
4577 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4578 payload.tag = cpu_to_le32(1);
4579 payload.phyop_phyid =
4580 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4581 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4585 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4588 #ifdef PM8001_USE_MSIX
4591 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4599 * pm8001_chip_isr - PM8001 isr handler.
4600 * @pm8001_ha: our hba card information.
4605 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4607 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4608 process_oq(pm8001_ha, vec);
4609 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4613 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4614 u32 operation, u32 phyid, u32 length, u32 *buf)
4618 struct set_phy_profile_req payload;
4619 struct inbound_queue_table *circularQ;
4620 u32 opc = OPC_INB_SET_PHY_PROFILE;
4622 memset(&payload, 0, sizeof(payload));
4623 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4625 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4626 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4627 payload.tag = cpu_to_le32(tag);
4628 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4629 PM8001_INIT_DBG(pm8001_ha,
4630 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4631 payload.ppc_phyid, length));
4632 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4633 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4636 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4638 pm8001_tag_free(pm8001_ha, tag);
4641 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4642 u32 length, u8 *buf)
4646 page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4647 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4648 mpi_set_phy_profile_req(pm8001_ha,
4649 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4650 length = length + PHY_DWORD_LENGTH;
4652 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4655 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4656 u32 phy, u32 length, u32 *buf)
4660 struct set_phy_profile_req payload;
4661 struct inbound_queue_table *circularQ;
4663 memset(&payload, 0, sizeof(payload));
4665 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4667 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4669 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4670 opc = OPC_INB_SET_PHY_PROFILE;
4672 payload.tag = cpu_to_le32(tag);
4673 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4676 for (i = 0; i < length; i++)
4677 payload.reserved[i] = cpu_to_le32(*(buf + i));
4679 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4681 pm8001_tag_free(pm8001_ha, tag);
4683 PM8001_INIT_DBG(pm8001_ha,
4684 pm8001_printk("PHY %d settings applied", phy));
4686 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4688 .chip_init = pm80xx_chip_init,
4689 .chip_soft_rst = pm80xx_chip_soft_rst,
4690 .chip_rst = pm80xx_hw_chip_rst,
4691 .chip_iounmap = pm8001_chip_iounmap,
4692 .isr = pm80xx_chip_isr,
4693 .is_our_interupt = pm80xx_chip_is_our_interupt,
4694 .isr_process_oq = process_oq,
4695 .interrupt_enable = pm80xx_chip_interrupt_enable,
4696 .interrupt_disable = pm80xx_chip_interrupt_disable,
4697 .make_prd = pm8001_chip_make_sg,
4698 .smp_req = pm80xx_chip_smp_req,
4699 .ssp_io_req = pm80xx_chip_ssp_io_req,
4700 .sata_req = pm80xx_chip_sata_req,
4701 .phy_start_req = pm80xx_chip_phy_start_req,
4702 .phy_stop_req = pm80xx_chip_phy_stop_req,
4703 .reg_dev_req = pm80xx_chip_reg_dev_req,
4704 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4705 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4706 .task_abort = pm8001_chip_abort_task,
4707 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4708 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4709 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4710 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4711 .set_dev_state_req = pm8001_chip_set_dev_state_req,