drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 #define SMP_DIRECT 1
  47 #define SMP_INDIRECT 2
  48
  49
  50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  51 {
  52         u32 reg_val;
  53         unsigned long start;
  54         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  55         /* confirm the setting is written */
  56         start = jiffies + HZ; /* 1 sec */
  57         do {
  58                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  59         } while ((reg_val != shift_value) && time_before(jiffies, start));
  60         if (reg_val != shift_value) {
  61                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
  62                            reg_val);
  63                 return -1;
  64         }
  65         return 0;
  66 }
  67
  68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  69                                 __le32 *destination,
  70                                 u32 dw_count, u32 bus_base_number)
  71 {
  72         u32 index, value, offset;
  73
  74         for (index = 0; index < dw_count; index += 4, destination++) {
  75                 offset = (soffset + index);
  76                 if (offset < (64 * 1024)) {
  77                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  78                         *destination = cpu_to_le32(value);
  79                 }
  80         }
  81         return;
  82 }
  83
  84 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  85         struct device_attribute *attr, char *buf)
  86 {
  87         struct Scsi_Host *shost = class_to_shost(cdev);
  88         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  89         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  90         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  91         u32 accum_len , reg_val, index, *temp;
  92         u32 status = 1;
  93         unsigned long start;
  94         u8 *direct_data;
  95         char *fatal_error_data = buf;
  96         u32 length_to_read;
  97         u32 offset;
  98
  99         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 100         if (pm8001_ha->chip_id == chip_8001) {
 101                 pm8001_ha->forensic_info.data_buf.direct_data +=
 102                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 103                         "Not supported for SPC controller");
 104                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 105                         (char *)buf;
 106         }
 107         /* initialize variables for very first call from host application */
 108         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 109                 pm8001_dbg(pm8001_ha, IO,
 110                            "forensic_info TYPE_NON_FATAL..............\n");
 111                 direct_data = (u8 *)fatal_error_data;
 112                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 113                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 114                 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 115                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 116                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 117
 118                 /* Write signature to fatal dump table */
 119                 pm8001_mw32(fatal_table_address,
 120                                 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
 121
 122                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 123                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
 124                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
 125                            pm8001_ha->forensic_info.data_buf.read_len);
 126                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
 127                            pm8001_ha->forensic_info.data_buf.direct_len);
 128                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
 129                            pm8001_ha->forensic_info.data_buf.direct_offset);
 130         }
 131         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 132                 /* start to get data */
 133                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 134                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 135                                 pm8001_ha->fatal_forensic_shift_offset);
 136                 pm8001_ha->forensic_last_offset = 0;
 137                 pm8001_ha->forensic_fatal_step = 0;
 138                 pm8001_ha->fatal_bar_loc = 0;
 139         }
 140
 141         /* Read until accum_len is retrived */
 142         accum_len = pm8001_mr32(fatal_table_address,
 143                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 144         /* Determine length of data between previously stored transfer length
 145          * and current accumulated transfer length
 146          */
 147         length_to_read =
 148                 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
 149         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
 150                    accum_len);
 151         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
 152                    length_to_read);
 153         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
 154                    pm8001_ha->forensic_last_offset);
 155         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
 156                    pm8001_ha->forensic_info.data_buf.read_len);
 157         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
 158                    pm8001_ha->forensic_info.data_buf.direct_len);
 159         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
 160                    pm8001_ha->forensic_info.data_buf.direct_offset);
 161
 162         /* If accumulated length failed to read correctly fail the attempt.*/
 163         if (accum_len == 0xFFFFFFFF) {
 164                 pm8001_dbg(pm8001_ha, IO,
 165                            "Possible PCI issue 0x%x not expected\n",
 166                            accum_len);
 167                 return status;
 168         }
 169         /* If accumulated length is zero fail the attempt */
 170         if (accum_len == 0) {
 171                 pm8001_ha->forensic_info.data_buf.direct_data +=
 172                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 173                         "%08x ", 0xFFFFFFFF);
 174                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 175                         (char *)buf;
 176         }
 177         /* Accumulated length is good so start capturing the first data */
 178         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 179         if (pm8001_ha->forensic_fatal_step == 0) {
 180 moreData:
 181                 /* If data to read is less than SYSFS_OFFSET then reduce the
 182                  * length of dataLen
 183                  */
 184                 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
 185                                 > length_to_read) {
 186                         pm8001_ha->forensic_info.data_buf.direct_len =
 187                                 length_to_read -
 188                                 pm8001_ha->forensic_last_offset;
 189                 } else {
 190                         pm8001_ha->forensic_info.data_buf.direct_len =
 191                                 SYSFS_OFFSET;
 192                 }
 193                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 194                         /* Data is in bar, copy to host memory */
 195                         pm80xx_pci_mem_copy(pm8001_ha,
 196                         pm8001_ha->fatal_bar_loc,
 197                         pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 198                         pm8001_ha->forensic_info.data_buf.direct_len, 1);
 199                 }
 200                 pm8001_ha->fatal_bar_loc +=
 201                         pm8001_ha->forensic_info.data_buf.direct_len;
 202                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 203                         pm8001_ha->forensic_info.data_buf.direct_len;
 204                 pm8001_ha->forensic_last_offset +=
 205                         pm8001_ha->forensic_info.data_buf.direct_len;
 206                 pm8001_ha->forensic_info.data_buf.read_len =
 207                         pm8001_ha->forensic_info.data_buf.direct_len;
 208
 209                 if (pm8001_ha->forensic_last_offset  >= length_to_read) {
 210                         pm8001_ha->forensic_info.data_buf.direct_data +=
 211                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 212                                 "%08x ", 3);
 213                         for (index = 0; index <
 214                                 (pm8001_ha->forensic_info.data_buf.direct_len
 215                                  / 4); index++) {
 216                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 217                                 sprintf(
 218                                 pm8001_ha->forensic_info.data_buf.direct_data,
 219                                 "%08x ", *(temp + index));
 220                         }
 221
 222                         pm8001_ha->fatal_bar_loc = 0;
 223                         pm8001_ha->forensic_fatal_step = 1;
 224                         pm8001_ha->fatal_forensic_shift_offset = 0;
 225                         pm8001_ha->forensic_last_offset = 0;
 226                         status = 0;
 227                         offset = (int)
 228                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 229                         - (char *)buf);
 230                         pm8001_dbg(pm8001_ha, IO,
 231                                    "get_fatal_spcv:return1 0x%x\n", offset);
 232                         return (char *)pm8001_ha->
 233                                 forensic_info.data_buf.direct_data -
 234                                 (char *)buf;
 235                 }
 236                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 237                         pm8001_ha->forensic_info.data_buf.direct_data +=
 238                                 sprintf(pm8001_ha->
 239                                         forensic_info.data_buf.direct_data,
 240                                         "%08x ", 2);
 241                         for (index = 0; index <
 242                                 (pm8001_ha->forensic_info.data_buf.direct_len
 243                                  / 4); index++) {
 244                                 pm8001_ha->forensic_info.data_buf.direct_data
 245                                         += sprintf(pm8001_ha->
 246                                         forensic_info.data_buf.direct_data,
 247                                         "%08x ", *(temp + index));
 248                         }
 249                         status = 0;
 250                         offset = (int)
 251                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 252                         - (char *)buf);
 253                         pm8001_dbg(pm8001_ha, IO,
 254                                    "get_fatal_spcv:return2 0x%x\n", offset);
 255                         return (char *)pm8001_ha->
 256                                 forensic_info.data_buf.direct_data -
 257                                 (char *)buf;
 258                 }
 259
 260                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 261                 pm8001_ha->forensic_info.data_buf.direct_data +=
 262                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 263                                 "%08x ", 2);
 264                 for (index = 0; index <
 265                         (pm8001_ha->forensic_info.data_buf.direct_len
 266                          / 4) ; index++) {
 267                         pm8001_ha->forensic_info.data_buf.direct_data +=
 268                                 sprintf(pm8001_ha->
 269                                 forensic_info.data_buf.direct_data,
 270                                 "%08x ", *(temp + index));
 271                 }
 272                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 273                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 274                         pm8001_ha->fatal_forensic_shift_offset);
 275                 pm8001_ha->fatal_bar_loc = 0;
 276                 status = 0;
 277                 offset = (int)
 278                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 279                         - (char *)buf);
 280                 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
 281                            offset);
 282                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 283                         (char *)buf;
 284         }
 285         if (pm8001_ha->forensic_fatal_step == 1) {
 286                 /* store previous accumulated length before triggering next
 287                  * accumulated length update
 288                  */
 289                 pm8001_ha->forensic_preserved_accumulated_transfer =
 290                         pm8001_mr32(fatal_table_address,
 291                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 292
 293                 /* continue capturing the fatal log until Dump status is 0x3 */
 294                 if (pm8001_mr32(fatal_table_address,
 295                         MPI_FATAL_EDUMP_TABLE_STATUS) <
 296                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 297
 298                         /* reset fddstat bit by writing to zero*/
 299                         pm8001_mw32(fatal_table_address,
 300                                         MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
 301
 302                         /* set dump control value to '1' so that new data will
 303                          * be transferred to shared memory
 304                          */
 305                         pm8001_mw32(fatal_table_address,
 306                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 307                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 308
 309                         /*Poll FDDHSHK  until clear */
 310                         start = jiffies + (2 * HZ); /* 2 sec */
 311
 312                         do {
 313                                 reg_val = pm8001_mr32(fatal_table_address,
 314                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 315                         } while ((reg_val) && time_before(jiffies, start));
 316
 317                         if (reg_val != 0) {
 318                                 pm8001_dbg(pm8001_ha, FAIL,
 319                                            "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
 320                                            reg_val);
 321                                /* Fail the dump if a timeout occurs */
 322                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 323                                 sprintf(
 324                                 pm8001_ha->forensic_info.data_buf.direct_data,
 325                                 "%08x ", 0xFFFFFFFF);
 326                                 return((char *)
 327                                 pm8001_ha->forensic_info.data_buf.direct_data
 328                                 - (char *)buf);
 329                         }
 330                         /* Poll status register until set to 2 or
 331                          * 3 for up to 2 seconds
 332                          */
 333                         start = jiffies + (2 * HZ); /* 2 sec */
 334
 335                         do {
 336                                 reg_val = pm8001_mr32(fatal_table_address,
 337                                         MPI_FATAL_EDUMP_TABLE_STATUS);
 338                         } while (((reg_val != 2) && (reg_val != 3)) &&
 339                                         time_before(jiffies, start));
 340
 341                         if (reg_val < 2) {
 342                                 pm8001_dbg(pm8001_ha, FAIL,
 343                                            "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
 344                                            reg_val);
 345                                 /* Fail the dump if a timeout occurs */
 346                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 347                                 sprintf(
 348                                 pm8001_ha->forensic_info.data_buf.direct_data,
 349                                 "%08x ", 0xFFFFFFFF);
 350                                 pm8001_cw32(pm8001_ha, 0,
 351                                         MEMBASE_II_SHIFT_REGISTER,
 352                                         pm8001_ha->fatal_forensic_shift_offset);
 353                         }
 354                         /* Read the next block of the debug data.*/
 355                         length_to_read = pm8001_mr32(fatal_table_address,
 356                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
 357                         pm8001_ha->forensic_preserved_accumulated_transfer;
 358                         if (length_to_read != 0x0) {
 359                                 pm8001_ha->forensic_fatal_step = 0;
 360                                 goto moreData;
 361                         } else {
 362                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 363                                 sprintf(
 364                                 pm8001_ha->forensic_info.data_buf.direct_data,
 365                                 "%08x ", 4);
 366                                 pm8001_ha->forensic_info.data_buf.read_len
 367                                                                 = 0xFFFFFFFF;
 368                                 pm8001_ha->forensic_info.data_buf.direct_len
 369                                                                 =  0;
 370                                 pm8001_ha->forensic_info.data_buf.direct_offset
 371                                                                 = 0;
 372                                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 373                         }
 374                 }
 375         }
 376         offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
 377                         - (char *)buf);
 378         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
 379         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 380                 (char *)buf;
 381 }
 382
 383 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
 384  * location by the firmware.
 385  */
 386 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
 387         struct device_attribute *attr, char *buf)
 388 {
 389         struct Scsi_Host *shost = class_to_shost(cdev);
 390         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 391         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
 392         void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
 393         u32 accum_len = 0;
 394         u32 total_len = 0;
 395         u32 reg_val = 0;
 396         u32 *temp = NULL;
 397         u32 index = 0;
 398         u32 output_length;
 399         unsigned long start = 0;
 400         char *buf_copy = buf;
 401
 402         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 403         if (++pm8001_ha->non_fatal_count == 1) {
 404                 if (pm8001_ha->chip_id == chip_8001) {
 405                         snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 406                                 PAGE_SIZE, "Not supported for SPC controller");
 407                         return 0;
 408                 }
 409                 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
 410                 /*
 411                  * Step 1: Write the host buffer parameters in the MPI Fatal and
 412                  * Non-Fatal Error Dump Capture Table.This is the buffer
 413                  * where debug data will be DMAed to.
 414                  */
 415                 pm8001_mw32(nonfatal_table_address,
 416                 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
 417                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
 418
 419                 pm8001_mw32(nonfatal_table_address,
 420                 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
 421                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
 422
 423                 pm8001_mw32(nonfatal_table_address,
 424                 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
 425
 426                 /* Optionally, set the DUMPCTRL bit to 1 if the host
 427                  * keeps sending active I/Os while capturing the non-fatal
 428                  * debug data. Otherwise, leave this bit set to zero
 429                  */
 430                 pm8001_mw32(nonfatal_table_address,
 431                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 432
 433                 /*
 434                  * Step 2: Clear Accumulative Length of Debug Data Transferred
 435                  * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
 436                  * Capture Table to zero.
 437                  */
 438                 pm8001_mw32(nonfatal_table_address,
 439                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
 440
 441                 /* initiallize previous accumulated length to 0 */
 442                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 443                 pm8001_ha->non_fatal_read_length = 0;
 444         }
 445
 446         total_len = pm8001_mr32(nonfatal_table_address,
 447                         MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
 448         /*
 449          * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
 450          * field and then request that the SPCv controller transfer the debug
 451          * data by setting bit 7 of the Inbound Doorbell Set Register.
 452          */
 453         pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
 454         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
 455                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
 456
 457         /*
 458          * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
 459          * 2 seconds) until register bit 7 is cleared.
 460          * This step only indicates the request is accepted by the controller.
 461          */
 462         start = jiffies + (2 * HZ); /* 2 sec */
 463         do {
 464                 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
 465                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
 466         } while ((reg_val != 0) && time_before(jiffies, start));
 467
 468         /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
 469          * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
 470          * the MPI Fatal and Non-Fatal Error Dump Capture Table.
 471          */
 472         start = jiffies + (2 * HZ); /* 2 sec */
 473         do {
 474                 reg_val = pm8001_mr32(nonfatal_table_address,
 475                                 MPI_FATAL_EDUMP_TABLE_STATUS);
 476         } while ((!reg_val) && time_before(jiffies, start));
 477
 478         if ((reg_val == 0x00) ||
 479                 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
 480                 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
 481                 pm8001_ha->non_fatal_read_length = 0;
 482                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
 483                 pm8001_ha->non_fatal_count = 0;
 484                 return (buf_copy - buf);
 485         } else if (reg_val ==
 486                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
 487                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
 488         } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
 489                 (pm8001_ha->non_fatal_read_length >= total_len)) {
 490                 pm8001_ha->non_fatal_read_length = 0;
 491                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
 492                 pm8001_ha->non_fatal_count = 0;
 493         }
 494         accum_len = pm8001_mr32(nonfatal_table_address,
 495                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 496         output_length = accum_len -
 497                 pm8001_ha->forensic_preserved_accumulated_transfer;
 498
 499         for (index = 0; index < output_length/4; index++)
 500                 buf_copy += snprintf(buf_copy, PAGE_SIZE,
 501                                 "%08x ", *(temp+index));
 502
 503         pm8001_ha->non_fatal_read_length += output_length;
 504
 505         /* store current accumulated length to use in next iteration as
 506          * the previous accumulated length
 507          */
 508         pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
 509         return (buf_copy - buf);
 510 }
 511
 512 /**
 513  * read_main_config_table - read the configure table and save it.
 514  * @pm8001_ha: our hba card information
 515  */
 516 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 517 {
 518         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 519
 520         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 521                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 522         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 523                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 524         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 525                 pm8001_mr32(address, MAIN_FW_REVISION);
 526         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 527                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 528         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 529                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 530         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 531                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 532         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 533                 pm8001_mr32(address, MAIN_GST_OFFSET);
 534         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 535                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 536         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 537                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 538
 539         /* read Error Dump Offset and Length */
 540         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 541                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 542         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 543                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 544         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 545                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 546         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 547                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 548
 549         /* read GPIO LED settings from the configuration table */
 550         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 551                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 552
 553         /* read analog Setting offset from the configuration table */
 554         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 555                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 556
 557         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 558                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 559         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 560                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 561         /* read port recover and reset timeout */
 562         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 563                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 564         /* read ILA and inactive firmware version */
 565         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
 566                 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
 567         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
 568                 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
 569
 570         pm8001_dbg(pm8001_ha, DEV,
 571                    "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
 572                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
 573                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
 574                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
 575
 576         pm8001_dbg(pm8001_ha, DEV,
 577                    "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
 578                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
 579                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
 580                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
 581                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
 582                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
 583
 584         pm8001_dbg(pm8001_ha, DEV,
 585                    "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
 586                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
 587                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
 588 }
 589
 590 /**
 591  * read_general_status_table - read the general status table and save it.
 592  * @pm8001_ha: our hba card information
 593  */
 594 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 595 {
 596         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 597         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 598                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 599         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 600                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 601         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 602                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 603         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 604                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 605         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 606                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 607         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 608                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 609         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 610                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 611         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 612                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 613         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 614                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 615         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 616                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 617         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 618                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 619         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 620                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 621         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 622                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 623         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 624                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 625 }
 626 /**
 627  * read_phy_attr_table - read the phy attribute table and save it.
 628  * @pm8001_ha: our hba card information
 629  */
 630 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 631 {
 632         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 633         pm8001_ha->phy_attr_table.phystart1_16[0] =
 634                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 635         pm8001_ha->phy_attr_table.phystart1_16[1] =
 636                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 637         pm8001_ha->phy_attr_table.phystart1_16[2] =
 638                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 639         pm8001_ha->phy_attr_table.phystart1_16[3] =
 640                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 641         pm8001_ha->phy_attr_table.phystart1_16[4] =
 642                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 643         pm8001_ha->phy_attr_table.phystart1_16[5] =
 644                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 645         pm8001_ha->phy_attr_table.phystart1_16[6] =
 646                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 647         pm8001_ha->phy_attr_table.phystart1_16[7] =
 648                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 649         pm8001_ha->phy_attr_table.phystart1_16[8] =
 650                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 651         pm8001_ha->phy_attr_table.phystart1_16[9] =
 652                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 653         pm8001_ha->phy_attr_table.phystart1_16[10] =
 654                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 655         pm8001_ha->phy_attr_table.phystart1_16[11] =
 656                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 657         pm8001_ha->phy_attr_table.phystart1_16[12] =
 658                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 659         pm8001_ha->phy_attr_table.phystart1_16[13] =
 660                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 661         pm8001_ha->phy_attr_table.phystart1_16[14] =
 662                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 663         pm8001_ha->phy_attr_table.phystart1_16[15] =
 664                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 665
 666         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 667                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 668         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 669                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 670         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 671                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 672         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 673                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 674         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 675                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 676         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 677                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 678         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 679                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 680         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 681                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 682         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 683                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 684         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 685                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 686         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 687                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 688         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 689                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 690         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 691                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 692         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 693                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 694         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 695                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 696         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 697                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 698
 699 }
 700
 701 /**
 702  * read_inbnd_queue_table - read the inbound queue table and save it.
 703  * @pm8001_ha: our hba card information
 704  */
 705 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 706 {
 707         int i;
 708         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 709         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 710                 u32 offset = i * 0x20;
 711                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 712                         get_pci_bar_index(pm8001_mr32(address,
 713                                 (offset + IB_PIPCI_BAR)));
 714                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 715                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 716         }
 717 }
 718
 719 /**
 720  * read_outbnd_queue_table - read the outbound queue table and save it.
 721  * @pm8001_ha: our hba card information
 722  */
 723 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 724 {
 725         int i;
 726         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 727         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 728                 u32 offset = i * 0x24;
 729                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 730                         get_pci_bar_index(pm8001_mr32(address,
 731                                 (offset + OB_CIPCI_BAR)));
 732                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 733                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 734         }
 735 }
 736
 737 /**
 738  * init_default_table_values - init the default table.
 739  * @pm8001_ha: our hba card information
 740  */
 741 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 742 {
 743         int i;
 744         u32 offsetib, offsetob;
 745         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 746         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 747         u32 ib_offset = pm8001_ha->ib_offset;
 748         u32 ob_offset = pm8001_ha->ob_offset;
 749         u32 ci_offset = pm8001_ha->ci_offset;
 750         u32 pi_offset = pm8001_ha->pi_offset;
 751
 752         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 753                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 754         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 755                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 756         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 757                                                         PM8001_EVENT_LOG_SIZE;
 758         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 759         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 760                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 761         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 762                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 763         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 764                                                         PM8001_EVENT_LOG_SIZE;
 765         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 766         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 767
 768         /* Enable higher IQs and OQs, 32 to 63, bit 16 */
 769         if (pm8001_ha->max_q_num > 32)
 770                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 771                                                         1 << 16;
 772         /* Disable end to end CRC checking */
 773         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 774
 775         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 776                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 777                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 778                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 779                         pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
 780                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 781                 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
 782                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 783                   (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
 784                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 785                         pm8001_ha->memoryMap.region[ib_offset + i].total_len;
 786                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 787                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
 788                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 789                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
 790                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 791                         pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
 792                 offsetib = i * 0x20;
 793                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 794                         get_pci_bar_index(pm8001_mr32(addressib,
 795                                 (offsetib + 0x14)));
 796                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 797                         pm8001_mr32(addressib, (offsetib + 0x18));
 798                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 799                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 800
 801                 pm8001_dbg(pm8001_ha, DEV,
 802                            "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
 803                            pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
 804                            pm8001_ha->inbnd_q_tbl[i].pi_offset);
 805         }
 806         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 807                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 808                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 809                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 810                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
 811                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 812                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
 813                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 814                   (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
 815                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 816                         pm8001_ha->memoryMap.region[ob_offset + i].total_len;
 817                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 818                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
 819                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 820                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
 821                 /* interrupt vector based on oq */
 822                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 823                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 824                         pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
 825                 offsetob = i * 0x24;
 826                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 827                         get_pci_bar_index(pm8001_mr32(addressob,
 828                         offsetob + 0x14));
 829                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 830                         pm8001_mr32(addressob, (offsetob + 0x18));
 831                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 832                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 833
 834                 pm8001_dbg(pm8001_ha, DEV,
 835                            "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
 836                            pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
 837                            pm8001_ha->outbnd_q_tbl[i].ci_offset);
 838         }
 839 }
 840
 841 /**
 842  * update_main_config_table - update the main default table to the HBA.
 843  * @pm8001_ha: our hba card information
 844  */
 845 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 846 {
 847         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 848         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 849                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 850         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 851                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 852         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 853                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 854         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 855                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 856         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 857                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 858         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 859                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 860         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 861                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 862         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 863                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 864         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 865                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 866         /* Update Fatal error interrupt vector */
 867         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 868                                         ((pm8001_ha->max_q_num - 1) << 8);
 869         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 870                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 871         pm8001_dbg(pm8001_ha, DEV,
 872                    "Updated Fatal error interrupt vector 0x%x\n",
 873                    pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
 874
 875         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 876                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 877
 878         /* SPCv specific */
 879         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 880         /* Set GPIOLED to 0x2 for LED indicator */
 881         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 882         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 883                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 884         pm8001_dbg(pm8001_ha, DEV,
 885                    "Programming DW 0x21 in main cfg table with 0x%x\n",
 886                    pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
 887
 888         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 889                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 890         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 891                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 892
 893         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 894         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 895                                                         PORT_RECOVERY_TIMEOUT;
 896         if (pm8001_ha->chip_id == chip_8006) {
 897                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
 898                                         0x0000ffff;
 899                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 900                                         CHIP_8006_PORT_RECOVERY_TIMEOUT;
 901         }
 902         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 903                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 904 }
 905
 906 /**
 907  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 908  * @pm8001_ha: our hba card information
 909  * @number: entry in the queue
 910  */
 911 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 912                                          int number)
 913 {
 914         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 915         u16 offset = number * 0x20;
 916         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 917                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 918         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 919                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 920         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 921                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 922         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 923                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 924         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 925                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 926
 927         pm8001_dbg(pm8001_ha, DEV,
 928                    "IQ %d: Element pri size 0x%x\n",
 929                    number,
 930                    pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 931
 932         pm8001_dbg(pm8001_ha, DEV,
 933                    "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
 934                    pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
 935                    pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 936
 937         pm8001_dbg(pm8001_ha, DEV,
 938                    "CI upper base addr 0x%x CI lower base addr 0x%x\n",
 939                    pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
 940                    pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 941 }
 942
 943 /**
 944  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 945  * @pm8001_ha: our hba card information
 946  * @number: entry in the queue
 947  */
 948 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 949                                                  int number)
 950 {
 951         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 952         u16 offset = number * 0x24;
 953         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 954                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 955         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 956                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 957         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 958                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 959         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 960                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 961         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 962                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 963         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 964                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 965
 966         pm8001_dbg(pm8001_ha, DEV,
 967                    "OQ %d: Element pri size 0x%x\n",
 968                    number,
 969                    pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 970
 971         pm8001_dbg(pm8001_ha, DEV,
 972                    "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
 973                    pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
 974                    pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 975
 976         pm8001_dbg(pm8001_ha, DEV,
 977                    "PI upper base addr 0x%x PI lower base addr 0x%x\n",
 978                    pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
 979                    pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 980 }
 981
 982 /**
 983  * mpi_init_check - check firmware initialization status.
 984  * @pm8001_ha: our hba card information
 985  */
 986 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 987 {
 988         u32 max_wait_count;
 989         u32 value;
 990         u32 gst_len_mpistate;
 991
 992         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 993         table is updated */
 994         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 995         /* wait until Inbound DoorBell Clear Register toggled */
 996         if (IS_SPCV_12G(pm8001_ha->pdev)) {
 997                 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
 998         } else {
 999                 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1000         }
1001         do {
1002                 udelay(1);
1003                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1004                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1005         } while ((value != 0) && (--max_wait_count));
1006
1007         if (!max_wait_count) {
1008                 /* additional check */
1009                 pm8001_dbg(pm8001_ha, FAIL,
1010                            "Inb doorbell clear not toggled[value:%x]\n",
1011                            value);
1012                 return -EBUSY;
1013         }
1014         /* check the MPI-State for initialization upto 100ms*/
1015         max_wait_count = 100 * 1000;/* 100 msec */
1016         do {
1017                 udelay(1);
1018                 gst_len_mpistate =
1019                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1020                                         GST_GSTLEN_MPIS_OFFSET);
1021         } while ((GST_MPI_STATE_INIT !=
1022                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1023         if (!max_wait_count)
1024                 return -EBUSY;
1025
1026         /* check MPI Initialization error */
1027         gst_len_mpistate = gst_len_mpistate >> 16;
1028         if (0x0000 != gst_len_mpistate)
1029                 return -EBUSY;
1030
1031         /*
1032          *  As per controller datasheet, after successful MPI
1033          *  initialization minimum 500ms delay is required before
1034          *  issuing commands.
1035          */
1036         msleep(500);
1037
1038         return 0;
1039 }
1040
1041 /**
1042  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1043  * @pm8001_ha: our hba card information
1044  */
1045 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1046 {
1047         u32 value;
1048         u32 max_wait_count;
1049         u32 max_wait_time;
1050         int ret = 0;
1051
1052         /* reset / PCIe ready */
1053         max_wait_time = max_wait_count = 100 * 1000;    /* 100 milli sec */
1054         do {
1055                 udelay(1);
1056                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1057         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1058
1059         /* check ila status */
1060         max_wait_time = max_wait_count = 1000 * 1000;   /* 1000 milli sec */
1061         do {
1062                 udelay(1);
1063                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1064         } while (((value & SCRATCH_PAD_ILA_READY) !=
1065                         SCRATCH_PAD_ILA_READY) && (--max_wait_count));
1066         if (!max_wait_count)
1067                 ret = -1;
1068         else {
1069                 pm8001_dbg(pm8001_ha, MSG,
1070                            " ila ready status in %d millisec\n",
1071                            (max_wait_time - max_wait_count));
1072         }
1073
1074         /* check RAAE status */
1075         max_wait_time = max_wait_count = 1800 * 1000;   /* 1800 milli sec */
1076         do {
1077                 udelay(1);
1078                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1079         } while (((value & SCRATCH_PAD_RAAE_READY) !=
1080                                 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
1081         if (!max_wait_count)
1082                 ret = -1;
1083         else {
1084                 pm8001_dbg(pm8001_ha, MSG,
1085                            " raae ready status in %d millisec\n",
1086                            (max_wait_time - max_wait_count));
1087         }
1088
1089         /* check iop0 status */
1090         max_wait_time = max_wait_count = 600 * 1000;    /* 600 milli sec */
1091         do {
1092                 udelay(1);
1093                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1094         } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
1095                         (--max_wait_count));
1096         if (!max_wait_count)
1097                 ret = -1;
1098         else {
1099                 pm8001_dbg(pm8001_ha, MSG,
1100                            " iop0 ready status in %d millisec\n",
1101                            (max_wait_time - max_wait_count));
1102         }
1103
1104         /* check iop1 status only for 16 port controllers */
1105         if ((pm8001_ha->chip_id != chip_8008) &&
1106                         (pm8001_ha->chip_id != chip_8009)) {
1107                 /* 200 milli sec */
1108                 max_wait_time = max_wait_count = 200 * 1000;
1109                 do {
1110                         udelay(1);
1111                         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1112                 } while (((value & SCRATCH_PAD_IOP1_READY) !=
1113                                 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
1114                 if (!max_wait_count)
1115                         ret = -1;
1116                 else {
1117                         pm8001_dbg(pm8001_ha, MSG,
1118                                    "iop1 ready status in %d millisec\n",
1119                                    (max_wait_time - max_wait_count));
1120                 }
1121         }
1122
1123         return ret;
1124 }
1125
1126 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1127 {
1128         void __iomem *base_addr;
1129         u32     value;
1130         u32     offset;
1131         u32     pcibar;
1132         u32     pcilogic;
1133
1134         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1135         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1136
1137         pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1138                    offset, value);
1139         pcilogic = (value & 0xFC000000) >> 26;
1140         pcibar = get_pci_bar_index(pcilogic);
1141         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1142         pm8001_ha->main_cfg_tbl_addr = base_addr =
1143                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1144         pm8001_ha->general_stat_tbl_addr =
1145                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1146                                         0xFFFFFF);
1147         pm8001_ha->inbnd_q_tbl_addr =
1148                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1149                                         0xFFFFFF);
1150         pm8001_ha->outbnd_q_tbl_addr =
1151                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1152                                         0xFFFFFF);
1153         pm8001_ha->ivt_tbl_addr =
1154                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1155                                         0xFFFFFF);
1156         pm8001_ha->pspa_q_tbl_addr =
1157                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1158                                         0xFFFFFF);
1159         pm8001_ha->fatal_tbl_addr =
1160                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1161                                         0xFFFFFF);
1162
1163         pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1164                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1165         pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1166                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1167         pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1168                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1169         pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1170                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1171         pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1172                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1173         pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1174                    pm8001_ha->main_cfg_tbl_addr,
1175                    pm8001_ha->general_stat_tbl_addr);
1176         pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1177                    pm8001_ha->inbnd_q_tbl_addr,
1178                    pm8001_ha->outbnd_q_tbl_addr);
1179         pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1180                    pm8001_ha->pspa_q_tbl_addr,
1181                    pm8001_ha->ivt_tbl_addr);
1182 }
1183
1184 /**
1185  * pm80xx_set_thermal_config - support the thermal configuration
1186  * @pm8001_ha: our hba card information.
1187  */
1188 int
1189 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1190 {
1191         struct set_ctrl_cfg_req payload;
1192         struct inbound_queue_table *circularQ;
1193         int rc;
1194         u32 tag;
1195         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1196         u32 page_code;
1197
1198         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1199         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1200         if (rc)
1201                 return -1;
1202
1203         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1204         payload.tag = cpu_to_le32(tag);
1205
1206         if (IS_SPCV_12G(pm8001_ha->pdev))
1207                 page_code = THERMAL_PAGE_CODE_7H;
1208         else
1209                 page_code = THERMAL_PAGE_CODE_8H;
1210
1211         payload.cfg_pg[0] =
1212                 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1213                             (THERMAL_ENABLE << 8) | page_code);
1214         payload.cfg_pg[1] =
1215                 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1216
1217         pm8001_dbg(pm8001_ha, DEV,
1218                    "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1219                    payload.cfg_pg[0], payload.cfg_pg[1]);
1220
1221         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1222                         sizeof(payload), 0);
1223         if (rc)
1224                 pm8001_tag_free(pm8001_ha, tag);
1225         return rc;
1226
1227 }
1228
1229 /**
1230 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1231 * Timer configuration page
1232 * @pm8001_ha: our hba card information.
1233 */
1234 static int
1235 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1236 {
1237         struct set_ctrl_cfg_req payload;
1238         struct inbound_queue_table *circularQ;
1239         SASProtocolTimerConfig_t SASConfigPage;
1240         int rc;
1241         u32 tag;
1242         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1243
1244         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1245         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1246
1247         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1248
1249         if (rc)
1250                 return -1;
1251
1252         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1253         payload.tag = cpu_to_le32(tag);
1254
1255         SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1256         SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1257         SASConfigPage.STP_SSP_MCT_TMO =
1258                 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1259         SASConfigPage.STP_FRM_TMO =
1260                 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1261                             (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1262         SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1263
1264         SASConfigPage.OPNRJT_RTRY_INTVL =
1265                 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1266         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1267                 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1268         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1269                 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1270         SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1271
1272         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1273                    le32_to_cpu(SASConfigPage.pageCode));
1274         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI  0x%08x\n",
1275                    le32_to_cpu(SASConfigPage.MST_MSI));
1276         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO  0x%08x\n",
1277                    le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1278         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO  0x%08x\n",
1279                    le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1280         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO  0x%08x\n",
1281                    le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1282         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL  0x%08x\n",
1283                    le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1284         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO  0x%08x\n",
1285                    le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1286         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR  0x%08x\n",
1287                    le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1288         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP  0x%08x\n",
1289                    le32_to_cpu(SASConfigPage.MAX_AIP));
1290
1291         memcpy(&payload.cfg_pg, &SASConfigPage,
1292                          sizeof(SASProtocolTimerConfig_t));
1293
1294         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1295                         sizeof(payload), 0);
1296         if (rc)
1297                 pm8001_tag_free(pm8001_ha, tag);
1298
1299         return rc;
1300 }
1301
1302 /**
1303  * pm80xx_get_encrypt_info - Check for encryption
1304  * @pm8001_ha: our hba card information.
1305  */
1306 static int
1307 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1308 {
1309         u32 scratch3_value;
1310         int ret = -1;
1311
1312         /* Read encryption status from SCRATCH PAD 3 */
1313         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1314
1315         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1316                                         SCRATCH_PAD3_ENC_READY) {
1317                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1318                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1319                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1320                                                 SCRATCH_PAD3_SMF_ENABLED)
1321                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1322                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1323                                                 SCRATCH_PAD3_SMA_ENABLED)
1324                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1325                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1326                                                 SCRATCH_PAD3_SMB_ENABLED)
1327                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1328                 pm8001_ha->encrypt_info.status = 0;
1329                 pm8001_dbg(pm8001_ha, INIT,
1330                            "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1331                            scratch3_value,
1332                            pm8001_ha->encrypt_info.cipher_mode,
1333                            pm8001_ha->encrypt_info.sec_mode,
1334                            pm8001_ha->encrypt_info.status);
1335                 ret = 0;
1336         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1337                                         SCRATCH_PAD3_ENC_DISABLED) {
1338                 pm8001_dbg(pm8001_ha, INIT,
1339                            "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1340                            scratch3_value);
1341                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1342                 pm8001_ha->encrypt_info.cipher_mode = 0;
1343                 pm8001_ha->encrypt_info.sec_mode = 0;
1344                 ret = 0;
1345         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1346                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1347                 pm8001_ha->encrypt_info.status =
1348                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1349                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1350                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1351                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1352                                         SCRATCH_PAD3_SMF_ENABLED)
1353                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1354                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1355                                         SCRATCH_PAD3_SMA_ENABLED)
1356                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1357                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1358                                         SCRATCH_PAD3_SMB_ENABLED)
1359                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1360                 pm8001_dbg(pm8001_ha, INIT,
1361                            "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1362                            scratch3_value,
1363                            pm8001_ha->encrypt_info.cipher_mode,
1364                            pm8001_ha->encrypt_info.sec_mode,
1365                            pm8001_ha->encrypt_info.status);
1366         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1367                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1368
1369                 pm8001_ha->encrypt_info.status =
1370                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1371                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1372                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1373                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1374                                         SCRATCH_PAD3_SMF_ENABLED)
1375                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1376                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1377                                         SCRATCH_PAD3_SMA_ENABLED)
1378                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1379                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1380                                         SCRATCH_PAD3_SMB_ENABLED)
1381                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1382
1383                 pm8001_dbg(pm8001_ha, INIT,
1384                            "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1385                            scratch3_value,
1386                            pm8001_ha->encrypt_info.cipher_mode,
1387                            pm8001_ha->encrypt_info.sec_mode,
1388                            pm8001_ha->encrypt_info.status);
1389         }
1390         return ret;
1391 }
1392
1393 /**
1394  * pm80xx_encrypt_update - update flash with encryption informtion
1395  * @pm8001_ha: our hba card information.
1396  */
1397 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1398 {
1399         struct kek_mgmt_req payload;
1400         struct inbound_queue_table *circularQ;
1401         int rc;
1402         u32 tag;
1403         u32 opc = OPC_INB_KEK_MANAGEMENT;
1404
1405         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1406         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1407         if (rc)
1408                 return -1;
1409
1410         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1411         payload.tag = cpu_to_le32(tag);
1412         /* Currently only one key is used. New KEK index is 1.
1413          * Current KEK index is 1. Store KEK to NVRAM is 1.
1414          */
1415         payload.new_curidx_ksop =
1416                 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1417                              KEK_MGMT_SUBOP_KEYCARDUPDATE));
1418
1419         pm8001_dbg(pm8001_ha, DEV,
1420                    "Saving Encryption info to flash. payload 0x%x\n",
1421                    le32_to_cpu(payload.new_curidx_ksop));
1422
1423         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1424                         sizeof(payload), 0);
1425         if (rc)
1426                 pm8001_tag_free(pm8001_ha, tag);
1427
1428         return rc;
1429 }
1430
1431 /**
1432  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1433  * @pm8001_ha: our hba card information
1434  */
1435 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1436 {
1437         int ret;
1438         u8 i = 0;
1439
1440         /* check the firmware status */
1441         if (-1 == check_fw_ready(pm8001_ha)) {
1442                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1443                 return -EBUSY;
1444         }
1445
1446         /* Initialize the controller fatal error flag */
1447         pm8001_ha->controller_fatal_error = false;
1448
1449         /* Initialize pci space address eg: mpi offset */
1450         init_pci_device_addresses(pm8001_ha);
1451         init_default_table_values(pm8001_ha);
1452         read_main_config_table(pm8001_ha);
1453         read_general_status_table(pm8001_ha);
1454         read_inbnd_queue_table(pm8001_ha);
1455         read_outbnd_queue_table(pm8001_ha);
1456         read_phy_attr_table(pm8001_ha);
1457
1458         /* update main config table ,inbound table and outbound table */
1459         update_main_config_table(pm8001_ha);
1460         for (i = 0; i < pm8001_ha->max_q_num; i++) {
1461                 update_inbnd_queue_table(pm8001_ha, i);
1462                 update_outbnd_queue_table(pm8001_ha, i);
1463         }
1464         /* notify firmware update finished and check initialization status */
1465         if (0 == mpi_init_check(pm8001_ha)) {
1466                 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1467         } else
1468                 return -EBUSY;
1469
1470         /* send SAS protocol timer configuration page to FW */
1471         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1472
1473         /* Check for encryption */
1474         if (pm8001_ha->chip->encrypt) {
1475                 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1476                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1477                 if (ret == -1) {
1478                         pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1479                         if (pm8001_ha->encrypt_info.status == 0x81) {
1480                                 pm8001_dbg(pm8001_ha, INIT,
1481                                            "Encryption enabled with error.Saving encryption key to flash\n");
1482                                 pm80xx_encrypt_update(pm8001_ha);
1483                         }
1484                 }
1485         }
1486         return 0;
1487 }
1488
1489 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1490 {
1491         u32 max_wait_count;
1492         u32 value;
1493         u32 gst_len_mpistate;
1494         init_pci_device_addresses(pm8001_ha);
1495         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1496         table is stop */
1497         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1498
1499         /* wait until Inbound DoorBell Clear Register toggled */
1500         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1501                 max_wait_count = 30 * 1000 * 1000; /* 30 sec */
1502         } else {
1503                 max_wait_count = 15 * 1000 * 1000; /* 15 sec */
1504         }
1505         do {
1506                 udelay(1);
1507                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1508                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1509         } while ((value != 0) && (--max_wait_count));
1510
1511         if (!max_wait_count) {
1512                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1513                 return -1;
1514         }
1515
1516         /* check the MPI-State for termination in progress */
1517         /* wait until Inbound DoorBell Clear Register toggled */
1518         max_wait_count = 2 * 1000 * 1000;       /* 2 sec for spcv/ve */
1519         do {
1520                 udelay(1);
1521                 gst_len_mpistate =
1522                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1523                         GST_GSTLEN_MPIS_OFFSET);
1524                 if (GST_MPI_STATE_UNINIT ==
1525                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1526                         break;
1527         } while (--max_wait_count);
1528         if (!max_wait_count) {
1529                 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1530                            gst_len_mpistate & GST_MPI_STATE_MASK);
1531                 return -1;
1532         }
1533
1534         return 0;
1535 }
1536
1537 /**
1538  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1539  * the FW register status to the originated status.
1540  * @pm8001_ha: our hba card information
1541  */
1542
1543 static int
1544 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1545 {
1546         u32 regval;
1547         u32 bootloader_state;
1548         u32 ibutton0, ibutton1;
1549
1550         /* Process MPI table uninitialization only if FW is ready */
1551         if (!pm8001_ha->controller_fatal_error) {
1552                 /* Check if MPI is in ready state to reset */
1553                 if (mpi_uninit_check(pm8001_ha) != 0) {
1554                         u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1555                         u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1556                         u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1557                         u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1558                         pm8001_dbg(pm8001_ha, FAIL,
1559                                    "MPI state is not ready scratch: %x:%x:%x:%x\n",
1560                                    r0, r1, r2, r3);
1561                         /* if things aren't ready but the bootloader is ok then
1562                          * try the reset anyway.
1563                          */
1564                         if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1565                                 return -1;
1566                 }
1567         }
1568         /* checked for reset register normal state; 0x0 */
1569         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1570         pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1571                    regval);
1572
1573         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1574         msleep(500);
1575
1576         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1577         pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1578                    regval);
1579
1580         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1581                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1582                 pm8001_dbg(pm8001_ha, MSG,
1583                            " soft reset successful [regval: 0x%x]\n",
1584                            regval);
1585         } else {
1586                 pm8001_dbg(pm8001_ha, MSG,
1587                            " soft reset failed [regval: 0x%x]\n",
1588                            regval);
1589
1590                 /* check bootloader is successfully executed or in HDA mode */
1591                 bootloader_state =
1592                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1593                         SCRATCH_PAD1_BOOTSTATE_MASK;
1594
1595                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1596                         pm8001_dbg(pm8001_ha, MSG,
1597                                    "Bootloader state - HDA mode SEEPROM\n");
1598                 } else if (bootloader_state ==
1599                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1600                         pm8001_dbg(pm8001_ha, MSG,
1601                                    "Bootloader state - HDA mode Bootstrap Pin\n");
1602                 } else if (bootloader_state ==
1603                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1604                         pm8001_dbg(pm8001_ha, MSG,
1605                                    "Bootloader state - HDA mode soft reset\n");
1606                 } else if (bootloader_state ==
1607                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1608                         pm8001_dbg(pm8001_ha, MSG,
1609                                    "Bootloader state-HDA mode critical error\n");
1610                 }
1611                 return -EBUSY;
1612         }
1613
1614         /* check the firmware status after reset */
1615         if (-1 == check_fw_ready(pm8001_ha)) {
1616                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1617                 /* check iButton feature support for motherboard controller */
1618                 if (pm8001_ha->pdev->subsystem_vendor !=
1619                         PCI_VENDOR_ID_ADAPTEC2 &&
1620                         pm8001_ha->pdev->subsystem_vendor !=
1621                         PCI_VENDOR_ID_ATTO &&
1622                         pm8001_ha->pdev->subsystem_vendor != 0) {
1623                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1624                                         MSGU_HOST_SCRATCH_PAD_6);
1625                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1626                                         MSGU_HOST_SCRATCH_PAD_7);
1627                         if (!ibutton0 && !ibutton1) {
1628                                 pm8001_dbg(pm8001_ha, FAIL,
1629                                            "iButton Feature is not Available!!!\n");
1630                                 return -EBUSY;
1631                         }
1632                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1633                                 pm8001_dbg(pm8001_ha, FAIL,
1634                                            "CRC Check for iButton Feature Failed!!!\n");
1635                                 return -EBUSY;
1636                         }
1637                 }
1638         }
1639         pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1640         return 0;
1641 }
1642
1643 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1644 {
1645         u32 i;
1646
1647         pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1648
1649         /* do SPCv chip reset. */
1650         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1651         pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1652
1653         /* Check this ..whether delay is required or no */
1654         /* delay 10 usec */
1655         udelay(10);
1656
1657         /* wait for 20 msec until the firmware gets reloaded */
1658         i = 20;
1659         do {
1660                 mdelay(1);
1661         } while ((--i) != 0);
1662
1663         pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1664 }
1665
1666 /**
1667  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1668  * @pm8001_ha: our hba card information
1669  */
1670 static void
1671 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1672 {
1673         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1674         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1675 }
1676
1677 /**
1678  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1679  * @pm8001_ha: our hba card information
1680  */
1681 static void
1682 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1683 {
1684         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1685 }
1686
1687 /**
1688  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1689  * @pm8001_ha: our hba card information
1690  * @vec: interrupt number to enable
1691  */
1692 static void
1693 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1694 {
1695 #ifdef PM8001_USE_MSIX
1696         if (vec < 32)
1697                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
1698         else
1699                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
1700                             1U << (vec - 32));
1701         return;
1702 #endif
1703         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1704
1705 }
1706
1707 /**
1708  * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1709  * @pm8001_ha: our hba card information
1710  * @vec: interrupt number to disable
1711  */
1712 static void
1713 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1714 {
1715 #ifdef PM8001_USE_MSIX
1716         if (vec == 0xFF) {
1717                 /* disable all vectors 0-31, 32-63 */
1718                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
1719                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
1720         } else if (vec < 32)
1721                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
1722         else
1723                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
1724                             1U << (vec - 32));
1725         return;
1726 #endif
1727         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1728 }
1729
1730 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1731                 struct pm8001_device *pm8001_ha_dev)
1732 {
1733         int res;
1734         u32 ccb_tag;
1735         struct pm8001_ccb_info *ccb;
1736         struct sas_task *task = NULL;
1737         struct task_abort_req task_abort;
1738         struct inbound_queue_table *circularQ;
1739         u32 opc = OPC_INB_SATA_ABORT;
1740         int ret;
1741
1742         if (!pm8001_ha_dev) {
1743                 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1744                 return;
1745         }
1746
1747         task = sas_alloc_slow_task(GFP_ATOMIC);
1748
1749         if (!task) {
1750                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1751                 return;
1752         }
1753
1754         task->task_done = pm8001_task_done;
1755
1756         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1757         if (res) {
1758                 sas_free_task(task);
1759                 return;
1760         }
1761
1762         ccb = &pm8001_ha->ccb_info[ccb_tag];
1763         ccb->device = pm8001_ha_dev;
1764         ccb->ccb_tag = ccb_tag;
1765         ccb->task = task;
1766         ccb->n_elem = 0;
1767
1768         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1769
1770         memset(&task_abort, 0, sizeof(task_abort));
1771         task_abort.abort_all = cpu_to_le32(1);
1772         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1773         task_abort.tag = cpu_to_le32(ccb_tag);
1774
1775         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1776                         sizeof(task_abort), 0);
1777         pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1778         if (ret) {
1779                 sas_free_task(task);
1780                 pm8001_tag_free(pm8001_ha, ccb_tag);
1781         }
1782 }
1783
1784 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1785                 struct pm8001_device *pm8001_ha_dev)
1786 {
1787         struct sata_start_req sata_cmd;
1788         int res;
1789         u32 ccb_tag;
1790         struct pm8001_ccb_info *ccb;
1791         struct sas_task *task = NULL;
1792         struct host_to_dev_fis fis;
1793         struct domain_device *dev;
1794         struct inbound_queue_table *circularQ;
1795         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1796
1797         task = sas_alloc_slow_task(GFP_ATOMIC);
1798
1799         if (!task) {
1800                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1801                 return;
1802         }
1803         task->task_done = pm8001_task_done;
1804
1805         res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1806         if (res) {
1807                 sas_free_task(task);
1808                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1809                 return;
1810         }
1811
1812         /* allocate domain device by ourselves as libsas
1813          * is not going to provide any
1814         */
1815         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1816         if (!dev) {
1817                 sas_free_task(task);
1818                 pm8001_tag_free(pm8001_ha, ccb_tag);
1819                 pm8001_dbg(pm8001_ha, FAIL,
1820                            "Domain device cannot be allocated\n");
1821                 return;
1822         }
1823
1824         task->dev = dev;
1825         task->dev->lldd_dev = pm8001_ha_dev;
1826
1827         ccb = &pm8001_ha->ccb_info[ccb_tag];
1828         ccb->device = pm8001_ha_dev;
1829         ccb->ccb_tag = ccb_tag;
1830         ccb->task = task;
1831         ccb->n_elem = 0;
1832         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1833         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1834
1835         memset(&sata_cmd, 0, sizeof(sata_cmd));
1836         circularQ = &pm8001_ha->inbnd_q_tbl[0];
1837
1838         /* construct read log FIS */
1839         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1840         fis.fis_type = 0x27;
1841         fis.flags = 0x80;
1842         fis.command = ATA_CMD_READ_LOG_EXT;
1843         fis.lbal = 0x10;
1844         fis.sector_count = 0x1;
1845
1846         sata_cmd.tag = cpu_to_le32(ccb_tag);
1847         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1848         sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1849         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1850
1851         res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1852                         sizeof(sata_cmd), 0);
1853         pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1854         if (res) {
1855                 sas_free_task(task);
1856                 pm8001_tag_free(pm8001_ha, ccb_tag);
1857                 kfree(dev);
1858         }
1859 }
1860
1861 /**
1862  * mpi_ssp_completion- process the event that FW response to the SSP request.
1863  * @pm8001_ha: our hba card information
1864  * @piomb: the message contents of this outbound message.
1865  *
1866  * When FW has completed a ssp request for example a IO request, after it has
1867  * filled the SG data with the data, it will trigger this event represent
1868  * that he has finished the job,please check the coresponding buffer.
1869  * So we will tell the caller who maybe waiting the result to tell upper layer
1870  * that the task has been finished.
1871  */
1872 static void
1873 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1874 {
1875         struct sas_task *t;
1876         struct pm8001_ccb_info *ccb;
1877         unsigned long flags;
1878         u32 status;
1879         u32 param;
1880         u32 tag;
1881         struct ssp_completion_resp *psspPayload;
1882         struct task_status_struct *ts;
1883         struct ssp_response_iu *iu;
1884         struct pm8001_device *pm8001_dev;
1885         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1886         status = le32_to_cpu(psspPayload->status);
1887         tag = le32_to_cpu(psspPayload->tag);
1888         ccb = &pm8001_ha->ccb_info[tag];
1889         if ((status == IO_ABORTED) && ccb->open_retry) {
1890                 /* Being completed by another */
1891                 ccb->open_retry = 0;
1892                 return;
1893         }
1894         pm8001_dev = ccb->device;
1895         param = le32_to_cpu(psspPayload->param);
1896         t = ccb->task;
1897
1898         if (status && status != IO_UNDERFLOW)
1899                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1900         if (unlikely(!t || !t->lldd_task || !t->dev))
1901                 return;
1902         ts = &t->task_status;
1903
1904         pm8001_dbg(pm8001_ha, DEV,
1905                    "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1906
1907         /* Print sas address of IO failed device */
1908         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1909                 (status != IO_UNDERFLOW))
1910                 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1911                            SAS_ADDR(t->dev->sas_addr));
1912
1913         switch (status) {
1914         case IO_SUCCESS:
1915                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1916                            param);
1917                 if (param == 0) {
1918                         ts->resp = SAS_TASK_COMPLETE;
1919                         ts->stat = SAS_SAM_STAT_GOOD;
1920                 } else {
1921                         ts->resp = SAS_TASK_COMPLETE;
1922                         ts->stat = SAS_PROTO_RESPONSE;
1923                         ts->residual = param;
1924                         iu = &psspPayload->ssp_resp_iu;
1925                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1926                 }
1927                 if (pm8001_dev)
1928                         atomic_dec(&pm8001_dev->running_req);
1929                 break;
1930         case IO_ABORTED:
1931                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1932                 ts->resp = SAS_TASK_COMPLETE;
1933                 ts->stat = SAS_ABORTED_TASK;
1934                 if (pm8001_dev)
1935                         atomic_dec(&pm8001_dev->running_req);
1936                 break;
1937         case IO_UNDERFLOW:
1938                 /* SSP Completion with error */
1939                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1940                            param);
1941                 ts->resp = SAS_TASK_COMPLETE;
1942                 ts->stat = SAS_DATA_UNDERRUN;
1943                 ts->residual = param;
1944                 if (pm8001_dev)
1945                         atomic_dec(&pm8001_dev->running_req);
1946                 break;
1947         case IO_NO_DEVICE:
1948                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1949                 ts->resp = SAS_TASK_UNDELIVERED;
1950                 ts->stat = SAS_PHY_DOWN;
1951                 if (pm8001_dev)
1952                         atomic_dec(&pm8001_dev->running_req);
1953                 break;
1954         case IO_XFER_ERROR_BREAK:
1955                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1956                 ts->resp = SAS_TASK_COMPLETE;
1957                 ts->stat = SAS_OPEN_REJECT;
1958                 /* Force the midlayer to retry */
1959                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1960                 if (pm8001_dev)
1961                         atomic_dec(&pm8001_dev->running_req);
1962                 break;
1963         case IO_XFER_ERROR_PHY_NOT_READY:
1964                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1965                 ts->resp = SAS_TASK_COMPLETE;
1966                 ts->stat = SAS_OPEN_REJECT;
1967                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1968                 if (pm8001_dev)
1969                         atomic_dec(&pm8001_dev->running_req);
1970                 break;
1971         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1972                 pm8001_dbg(pm8001_ha, IO,
1973                            "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
1974                 ts->resp = SAS_TASK_COMPLETE;
1975                 ts->stat = SAS_OPEN_REJECT;
1976                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1977                 if (pm8001_dev)
1978                         atomic_dec(&pm8001_dev->running_req);
1979                 break;
1980         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1981                 pm8001_dbg(pm8001_ha, IO,
1982                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1983                 ts->resp = SAS_TASK_COMPLETE;
1984                 ts->stat = SAS_OPEN_REJECT;
1985                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1986                 if (pm8001_dev)
1987                         atomic_dec(&pm8001_dev->running_req);
1988                 break;
1989         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1990                 pm8001_dbg(pm8001_ha, IO,
1991                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1992                 ts->resp = SAS_TASK_COMPLETE;
1993                 ts->stat = SAS_OPEN_REJECT;
1994                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1995                 if (pm8001_dev)
1996                         atomic_dec(&pm8001_dev->running_req);
1997                 break;
1998         case IO_OPEN_CNX_ERROR_BREAK:
1999                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2000                 ts->resp = SAS_TASK_COMPLETE;
2001                 ts->stat = SAS_OPEN_REJECT;
2002                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2003                 if (pm8001_dev)
2004                         atomic_dec(&pm8001_dev->running_req);
2005                 break;
2006         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2007         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2008         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2009         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2010         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2011         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2012                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2013                 ts->resp = SAS_TASK_COMPLETE;
2014                 ts->stat = SAS_OPEN_REJECT;
2015                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2016                 if (!t->uldd_task)
2017                         pm8001_handle_event(pm8001_ha,
2018                                 pm8001_dev,
2019                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2020                 break;
2021         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2022                 pm8001_dbg(pm8001_ha, IO,
2023                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2024                 ts->resp = SAS_TASK_COMPLETE;
2025                 ts->stat = SAS_OPEN_REJECT;
2026                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2027                 if (pm8001_dev)
2028                         atomic_dec(&pm8001_dev->running_req);
2029                 break;
2030         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2031                 pm8001_dbg(pm8001_ha, IO,
2032                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2033                 ts->resp = SAS_TASK_COMPLETE;
2034                 ts->stat = SAS_OPEN_REJECT;
2035                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2036                 if (pm8001_dev)
2037                         atomic_dec(&pm8001_dev->running_req);
2038                 break;
2039         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2040                 pm8001_dbg(pm8001_ha, IO,
2041                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2042                 ts->resp = SAS_TASK_UNDELIVERED;
2043                 ts->stat = SAS_OPEN_REJECT;
2044                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2045                 if (pm8001_dev)
2046                         atomic_dec(&pm8001_dev->running_req);
2047                 break;
2048         case IO_XFER_ERROR_NAK_RECEIVED:
2049                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2050                 ts->resp = SAS_TASK_COMPLETE;
2051                 ts->stat = SAS_OPEN_REJECT;
2052                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2053                 if (pm8001_dev)
2054                         atomic_dec(&pm8001_dev->running_req);
2055                 break;
2056         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2057                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2058                 ts->resp = SAS_TASK_COMPLETE;
2059                 ts->stat = SAS_NAK_R_ERR;
2060                 if (pm8001_dev)
2061                         atomic_dec(&pm8001_dev->running_req);
2062                 break;
2063         case IO_XFER_ERROR_DMA:
2064                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2065                 ts->resp = SAS_TASK_COMPLETE;
2066                 ts->stat = SAS_OPEN_REJECT;
2067                 if (pm8001_dev)
2068                         atomic_dec(&pm8001_dev->running_req);
2069                 break;
2070         case IO_XFER_OPEN_RETRY_TIMEOUT:
2071                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2072                 ts->resp = SAS_TASK_COMPLETE;
2073                 ts->stat = SAS_OPEN_REJECT;
2074                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2075                 if (pm8001_dev)
2076                         atomic_dec(&pm8001_dev->running_req);
2077                 break;
2078         case IO_XFER_ERROR_OFFSET_MISMATCH:
2079                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2080                 ts->resp = SAS_TASK_COMPLETE;
2081                 ts->stat = SAS_OPEN_REJECT;
2082                 if (pm8001_dev)
2083                         atomic_dec(&pm8001_dev->running_req);
2084                 break;
2085         case IO_PORT_IN_RESET:
2086                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2087                 ts->resp = SAS_TASK_COMPLETE;
2088                 ts->stat = SAS_OPEN_REJECT;
2089                 if (pm8001_dev)
2090                         atomic_dec(&pm8001_dev->running_req);
2091                 break;
2092         case IO_DS_NON_OPERATIONAL:
2093                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2094                 ts->resp = SAS_TASK_COMPLETE;
2095                 ts->stat = SAS_OPEN_REJECT;
2096                 if (!t->uldd_task)
2097                         pm8001_handle_event(pm8001_ha,
2098                                 pm8001_dev,
2099                                 IO_DS_NON_OPERATIONAL);
2100                 break;
2101         case IO_DS_IN_RECOVERY:
2102                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2103                 ts->resp = SAS_TASK_COMPLETE;
2104                 ts->stat = SAS_OPEN_REJECT;
2105                 if (pm8001_dev)
2106                         atomic_dec(&pm8001_dev->running_req);
2107                 break;
2108         case IO_TM_TAG_NOT_FOUND:
2109                 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2110                 ts->resp = SAS_TASK_COMPLETE;
2111                 ts->stat = SAS_OPEN_REJECT;
2112                 if (pm8001_dev)
2113                         atomic_dec(&pm8001_dev->running_req);
2114                 break;
2115         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2116                 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2117                 ts->resp = SAS_TASK_COMPLETE;
2118                 ts->stat = SAS_OPEN_REJECT;
2119                 if (pm8001_dev)
2120                         atomic_dec(&pm8001_dev->running_req);
2121                 break;
2122         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2123                 pm8001_dbg(pm8001_ha, IO,
2124                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2125                 ts->resp = SAS_TASK_COMPLETE;
2126                 ts->stat = SAS_OPEN_REJECT;
2127                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2128                 if (pm8001_dev)
2129                         atomic_dec(&pm8001_dev->running_req);
2130                 break;
2131         default:
2132                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2133                 /* not allowed case. Therefore, return failed status */
2134                 ts->resp = SAS_TASK_COMPLETE;
2135                 ts->stat = SAS_OPEN_REJECT;
2136                 if (pm8001_dev)
2137                         atomic_dec(&pm8001_dev->running_req);
2138                 break;
2139         }
2140         pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2141                    psspPayload->ssp_resp_iu.status);
2142         spin_lock_irqsave(&t->task_state_lock, flags);
2143         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2144         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2145         t->task_state_flags |= SAS_TASK_STATE_DONE;
2146         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2147                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2148                 pm8001_dbg(pm8001_ha, FAIL,
2149                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2150                            t, status, ts->resp, ts->stat);
2151                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2152                 if (t->slow_task)
2153                         complete(&t->slow_task->completion);
2154         } else {
2155                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2156                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2157                 mb();/* in order to force CPU ordering */
2158                 t->task_done(t);
2159         }
2160 }
2161
2162 /*See the comments for mpi_ssp_completion */
2163 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2164 {
2165         struct sas_task *t;
2166         unsigned long flags;
2167         struct task_status_struct *ts;
2168         struct pm8001_ccb_info *ccb;
2169         struct pm8001_device *pm8001_dev;
2170         struct ssp_event_resp *psspPayload =
2171                 (struct ssp_event_resp *)(piomb + 4);
2172         u32 event = le32_to_cpu(psspPayload->event);
2173         u32 tag = le32_to_cpu(psspPayload->tag);
2174         u32 port_id = le32_to_cpu(psspPayload->port_id);
2175
2176         ccb = &pm8001_ha->ccb_info[tag];
2177         t = ccb->task;
2178         pm8001_dev = ccb->device;
2179         if (event)
2180                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2181         if (unlikely(!t || !t->lldd_task || !t->dev))
2182                 return;
2183         ts = &t->task_status;
2184         pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2185                    port_id, tag, event);
2186         switch (event) {
2187         case IO_OVERFLOW:
2188                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2189                 ts->resp = SAS_TASK_COMPLETE;
2190                 ts->stat = SAS_DATA_OVERRUN;
2191                 ts->residual = 0;
2192                 if (pm8001_dev)
2193                         atomic_dec(&pm8001_dev->running_req);
2194                 break;
2195         case IO_XFER_ERROR_BREAK:
2196                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2197                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2198                 return;
2199         case IO_XFER_ERROR_PHY_NOT_READY:
2200                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2201                 ts->resp = SAS_TASK_COMPLETE;
2202                 ts->stat = SAS_OPEN_REJECT;
2203                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2204                 break;
2205         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2206                 pm8001_dbg(pm8001_ha, IO,
2207                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2208                 ts->resp = SAS_TASK_COMPLETE;
2209                 ts->stat = SAS_OPEN_REJECT;
2210                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2211                 break;
2212         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2213                 pm8001_dbg(pm8001_ha, IO,
2214                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2215                 ts->resp = SAS_TASK_COMPLETE;
2216                 ts->stat = SAS_OPEN_REJECT;
2217                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2218                 break;
2219         case IO_OPEN_CNX_ERROR_BREAK:
2220                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2221                 ts->resp = SAS_TASK_COMPLETE;
2222                 ts->stat = SAS_OPEN_REJECT;
2223                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2224                 break;
2225         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2226         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2227         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2228         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2229         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2230         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2231                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2232                 ts->resp = SAS_TASK_COMPLETE;
2233                 ts->stat = SAS_OPEN_REJECT;
2234                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2235                 if (!t->uldd_task)
2236                         pm8001_handle_event(pm8001_ha,
2237                                 pm8001_dev,
2238                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2239                 break;
2240         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2241                 pm8001_dbg(pm8001_ha, IO,
2242                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2243                 ts->resp = SAS_TASK_COMPLETE;
2244                 ts->stat = SAS_OPEN_REJECT;
2245                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2246                 break;
2247         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2248                 pm8001_dbg(pm8001_ha, IO,
2249                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2250                 ts->resp = SAS_TASK_COMPLETE;
2251                 ts->stat = SAS_OPEN_REJECT;
2252                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2253                 break;
2254         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2255                 pm8001_dbg(pm8001_ha, IO,
2256                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2257                 ts->resp = SAS_TASK_COMPLETE;
2258                 ts->stat = SAS_OPEN_REJECT;
2259                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2260                 break;
2261         case IO_XFER_ERROR_NAK_RECEIVED:
2262                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2263                 ts->resp = SAS_TASK_COMPLETE;
2264                 ts->stat = SAS_OPEN_REJECT;
2265                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2266                 break;
2267         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2268                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2269                 ts->resp = SAS_TASK_COMPLETE;
2270                 ts->stat = SAS_NAK_R_ERR;
2271                 break;
2272         case IO_XFER_OPEN_RETRY_TIMEOUT:
2273                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2274                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2275                 return;
2276         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2277                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2278                 ts->resp = SAS_TASK_COMPLETE;
2279                 ts->stat = SAS_DATA_OVERRUN;
2280                 break;
2281         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2282                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2283                 ts->resp = SAS_TASK_COMPLETE;
2284                 ts->stat = SAS_DATA_OVERRUN;
2285                 break;
2286         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2287                 pm8001_dbg(pm8001_ha, IO,
2288                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2289                 ts->resp = SAS_TASK_COMPLETE;
2290                 ts->stat = SAS_DATA_OVERRUN;
2291                 break;
2292         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2293                 pm8001_dbg(pm8001_ha, IO,
2294                            "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2295                 ts->resp = SAS_TASK_COMPLETE;
2296                 ts->stat = SAS_DATA_OVERRUN;
2297                 break;
2298         case IO_XFER_ERROR_OFFSET_MISMATCH:
2299                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2300                 ts->resp = SAS_TASK_COMPLETE;
2301                 ts->stat = SAS_DATA_OVERRUN;
2302                 break;
2303         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2304                 pm8001_dbg(pm8001_ha, IO,
2305                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2306                 ts->resp = SAS_TASK_COMPLETE;
2307                 ts->stat = SAS_DATA_OVERRUN;
2308                 break;
2309         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2310                 pm8001_dbg(pm8001_ha, IOERR,
2311                            "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2312                 /* TBC: used default set values */
2313                 ts->resp = SAS_TASK_COMPLETE;
2314                 ts->stat = SAS_DATA_OVERRUN;
2315                 break;
2316         case IO_XFER_CMD_FRAME_ISSUED:
2317                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2318                 return;
2319         default:
2320                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2321                 /* not allowed case. Therefore, return failed status */
2322                 ts->resp = SAS_TASK_COMPLETE;
2323                 ts->stat = SAS_DATA_OVERRUN;
2324                 break;
2325         }
2326         spin_lock_irqsave(&t->task_state_lock, flags);
2327         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2328         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2329         t->task_state_flags |= SAS_TASK_STATE_DONE;
2330         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2331                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2332                 pm8001_dbg(pm8001_ha, FAIL,
2333                            "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2334                            t, event, ts->resp, ts->stat);
2335                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2336         } else {
2337                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2338                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2339                 mb();/* in order to force CPU ordering */
2340                 t->task_done(t);
2341         }
2342 }
2343
2344 /*See the comments for mpi_ssp_completion */
2345 static void
2346 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2347 {
2348         struct sas_task *t;
2349         struct pm8001_ccb_info *ccb;
2350         u32 param;
2351         u32 status;
2352         u32 tag;
2353         int i, j;
2354         u8 sata_addr_low[4];
2355         u32 temp_sata_addr_low, temp_sata_addr_hi;
2356         u8 sata_addr_hi[4];
2357         struct sata_completion_resp *psataPayload;
2358         struct task_status_struct *ts;
2359         struct ata_task_resp *resp ;
2360         u32 *sata_resp;
2361         struct pm8001_device *pm8001_dev;
2362         unsigned long flags;
2363
2364         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2365         status = le32_to_cpu(psataPayload->status);
2366         tag = le32_to_cpu(psataPayload->tag);
2367
2368         if (!tag) {
2369                 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2370                 return;
2371         }
2372         ccb = &pm8001_ha->ccb_info[tag];
2373         param = le32_to_cpu(psataPayload->param);
2374         if (ccb) {
2375                 t = ccb->task;
2376                 pm8001_dev = ccb->device;
2377         } else {
2378                 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2379                 return;
2380         }
2381
2382         if (t) {
2383                 if (t->dev && (t->dev->lldd_dev))
2384                         pm8001_dev = t->dev->lldd_dev;
2385         } else {
2386                 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2387                 return;
2388         }
2389
2390         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2391                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2392                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2393                 return;
2394         }
2395
2396         ts = &t->task_status;
2397         if (!ts) {
2398                 pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2399                 return;
2400         }
2401
2402         if (unlikely(status))
2403                 pm8001_dbg(pm8001_ha, IOERR,
2404                            "status:0x%x, tag:0x%x, task::0x%p\n",
2405                            status, tag, t);
2406
2407         /* Print sas address of IO failed device */
2408         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2409                 (status != IO_UNDERFLOW)) {
2410                 if (!((t->dev->parent) &&
2411                         (dev_is_expander(t->dev->parent->dev_type)))) {
2412                         for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2413                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2414                         for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2415                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2416                         memcpy(&temp_sata_addr_low, sata_addr_low,
2417                                 sizeof(sata_addr_low));
2418                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2419                                 sizeof(sata_addr_hi));
2420                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2421                                                 |((temp_sata_addr_hi << 8) &
2422                                                 0xff0000) |
2423                                                 ((temp_sata_addr_hi >> 8)
2424                                                 & 0xff00) |
2425                                                 ((temp_sata_addr_hi << 24) &
2426                                                 0xff000000));
2427                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2428                                                 & 0xff) |
2429                                                 ((temp_sata_addr_low << 8)
2430                                                 & 0xff0000) |
2431                                                 ((temp_sata_addr_low >> 8)
2432                                                 & 0xff00) |
2433                                                 ((temp_sata_addr_low << 24)
2434                                                 & 0xff000000)) +
2435                                                 pm8001_dev->attached_phy +
2436                                                 0x10);
2437                         pm8001_dbg(pm8001_ha, FAIL,
2438                                    "SAS Address of IO Failure Drive:%08x%08x\n",
2439                                    temp_sata_addr_hi,
2440                                    temp_sata_addr_low);
2441
2442                 } else {
2443                         pm8001_dbg(pm8001_ha, FAIL,
2444                                    "SAS Address of IO Failure Drive:%016llx\n",
2445                                    SAS_ADDR(t->dev->sas_addr));
2446                 }
2447         }
2448         switch (status) {
2449         case IO_SUCCESS:
2450                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2451                 if (param == 0) {
2452                         ts->resp = SAS_TASK_COMPLETE;
2453                         ts->stat = SAS_SAM_STAT_GOOD;
2454                         /* check if response is for SEND READ LOG */
2455                         if (pm8001_dev &&
2456                                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2457                                 /* set new bit for abort_all */
2458                                 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2459                                 /* clear bit for read log */
2460                                 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2461                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2462                                 /* Free the tag */
2463                                 pm8001_tag_free(pm8001_ha, tag);
2464                                 sas_free_task(t);
2465                                 return;
2466                         }
2467                 } else {
2468                         u8 len;
2469                         ts->resp = SAS_TASK_COMPLETE;
2470                         ts->stat = SAS_PROTO_RESPONSE;
2471                         ts->residual = param;
2472                         pm8001_dbg(pm8001_ha, IO,
2473                                    "SAS_PROTO_RESPONSE len = %d\n",
2474                                    param);
2475                         sata_resp = &psataPayload->sata_resp[0];
2476                         resp = (struct ata_task_resp *)ts->buf;
2477                         if (t->ata_task.dma_xfer == 0 &&
2478                             t->data_dir == DMA_FROM_DEVICE) {
2479                                 len = sizeof(struct pio_setup_fis);
2480                                 pm8001_dbg(pm8001_ha, IO,
2481                                            "PIO read len = %d\n", len);
2482                         } else if (t->ata_task.use_ncq &&
2483                                    t->data_dir != DMA_NONE) {
2484                                 len = sizeof(struct set_dev_bits_fis);
2485                                 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2486                                            len);
2487                         } else {
2488                                 len = sizeof(struct dev_to_host_fis);
2489                                 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2490                                            len);
2491                         }
2492                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2493                                 resp->frame_len = len;
2494                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2495                                 ts->buf_valid_size = sizeof(*resp);
2496                         } else
2497                                 pm8001_dbg(pm8001_ha, IO,
2498                                            "response too large\n");
2499                 }
2500                 if (pm8001_dev)
2501                         atomic_dec(&pm8001_dev->running_req);
2502                 break;
2503         case IO_ABORTED:
2504                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2505                 ts->resp = SAS_TASK_COMPLETE;
2506                 ts->stat = SAS_ABORTED_TASK;
2507                 if (pm8001_dev)
2508                         atomic_dec(&pm8001_dev->running_req);
2509                 break;
2510                 /* following cases are to do cases */
2511         case IO_UNDERFLOW:
2512                 /* SATA Completion with error */
2513                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2514                 ts->resp = SAS_TASK_COMPLETE;
2515                 ts->stat = SAS_DATA_UNDERRUN;
2516                 ts->residual = param;
2517                 if (pm8001_dev)
2518                         atomic_dec(&pm8001_dev->running_req);
2519                 break;
2520         case IO_NO_DEVICE:
2521                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2522                 ts->resp = SAS_TASK_UNDELIVERED;
2523                 ts->stat = SAS_PHY_DOWN;
2524                 if (pm8001_dev)
2525                         atomic_dec(&pm8001_dev->running_req);
2526                 break;
2527         case IO_XFER_ERROR_BREAK:
2528                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2529                 ts->resp = SAS_TASK_COMPLETE;
2530                 ts->stat = SAS_INTERRUPTED;
2531                 if (pm8001_dev)
2532                         atomic_dec(&pm8001_dev->running_req);
2533                 break;
2534         case IO_XFER_ERROR_PHY_NOT_READY:
2535                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2536                 ts->resp = SAS_TASK_COMPLETE;
2537                 ts->stat = SAS_OPEN_REJECT;
2538                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2539                 if (pm8001_dev)
2540                         atomic_dec(&pm8001_dev->running_req);
2541                 break;
2542         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2543                 pm8001_dbg(pm8001_ha, IO,
2544                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2545                 ts->resp = SAS_TASK_COMPLETE;
2546                 ts->stat = SAS_OPEN_REJECT;
2547                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2548                 if (pm8001_dev)
2549                         atomic_dec(&pm8001_dev->running_req);
2550                 break;
2551         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2552                 pm8001_dbg(pm8001_ha, IO,
2553                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2554                 ts->resp = SAS_TASK_COMPLETE;
2555                 ts->stat = SAS_OPEN_REJECT;
2556                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2557                 if (pm8001_dev)
2558                         atomic_dec(&pm8001_dev->running_req);
2559                 break;
2560         case IO_OPEN_CNX_ERROR_BREAK:
2561                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2562                 ts->resp = SAS_TASK_COMPLETE;
2563                 ts->stat = SAS_OPEN_REJECT;
2564                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2565                 if (pm8001_dev)
2566                         atomic_dec(&pm8001_dev->running_req);
2567                 break;
2568         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2569         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2570         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2571         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2572         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2573         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2574                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2575                 ts->resp = SAS_TASK_COMPLETE;
2576                 ts->stat = SAS_DEV_NO_RESPONSE;
2577                 if (!t->uldd_task) {
2578                         pm8001_handle_event(pm8001_ha,
2579                                 pm8001_dev,
2580                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2581                         ts->resp = SAS_TASK_UNDELIVERED;
2582                         ts->stat = SAS_QUEUE_FULL;
2583                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2584                         return;
2585                 }
2586                 break;
2587         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2588                 pm8001_dbg(pm8001_ha, IO,
2589                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2590                 ts->resp = SAS_TASK_UNDELIVERED;
2591                 ts->stat = SAS_OPEN_REJECT;
2592                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2593                 if (!t->uldd_task) {
2594                         pm8001_handle_event(pm8001_ha,
2595                                 pm8001_dev,
2596                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2597                         ts->resp = SAS_TASK_UNDELIVERED;
2598                         ts->stat = SAS_QUEUE_FULL;
2599                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2600                         return;
2601                 }
2602                 break;
2603         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2604                 pm8001_dbg(pm8001_ha, IO,
2605                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2606                 ts->resp = SAS_TASK_COMPLETE;
2607                 ts->stat = SAS_OPEN_REJECT;
2608                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2609                 if (pm8001_dev)
2610                         atomic_dec(&pm8001_dev->running_req);
2611                 break;
2612         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2613                 pm8001_dbg(pm8001_ha, IO,
2614                            "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2615                 ts->resp = SAS_TASK_COMPLETE;
2616                 ts->stat = SAS_DEV_NO_RESPONSE;
2617                 if (!t->uldd_task) {
2618                         pm8001_handle_event(pm8001_ha,
2619                                 pm8001_dev,
2620                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2621                         ts->resp = SAS_TASK_UNDELIVERED;
2622                         ts->stat = SAS_QUEUE_FULL;
2623                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2624                         return;
2625                 }
2626                 break;
2627         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2628                 pm8001_dbg(pm8001_ha, IO,
2629                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2630                 ts->resp = SAS_TASK_COMPLETE;
2631                 ts->stat = SAS_OPEN_REJECT;
2632                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2633                 if (pm8001_dev)
2634                         atomic_dec(&pm8001_dev->running_req);
2635                 break;
2636         case IO_XFER_ERROR_NAK_RECEIVED:
2637                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2638                 ts->resp = SAS_TASK_COMPLETE;
2639                 ts->stat = SAS_NAK_R_ERR;
2640                 if (pm8001_dev)
2641                         atomic_dec(&pm8001_dev->running_req);
2642                 break;
2643         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2644                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2645                 ts->resp = SAS_TASK_COMPLETE;
2646                 ts->stat = SAS_NAK_R_ERR;
2647                 if (pm8001_dev)
2648                         atomic_dec(&pm8001_dev->running_req);
2649                 break;
2650         case IO_XFER_ERROR_DMA:
2651                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2652                 ts->resp = SAS_TASK_COMPLETE;
2653                 ts->stat = SAS_ABORTED_TASK;
2654                 if (pm8001_dev)
2655                         atomic_dec(&pm8001_dev->running_req);
2656                 break;
2657         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2658                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2659                 ts->resp = SAS_TASK_UNDELIVERED;
2660                 ts->stat = SAS_DEV_NO_RESPONSE;
2661                 if (pm8001_dev)
2662                         atomic_dec(&pm8001_dev->running_req);
2663                 break;
2664         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2665                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2666                 ts->resp = SAS_TASK_COMPLETE;
2667                 ts->stat = SAS_DATA_UNDERRUN;
2668                 if (pm8001_dev)
2669                         atomic_dec(&pm8001_dev->running_req);
2670                 break;
2671         case IO_XFER_OPEN_RETRY_TIMEOUT:
2672                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2673                 ts->resp = SAS_TASK_COMPLETE;
2674                 ts->stat = SAS_OPEN_TO;
2675                 if (pm8001_dev)
2676                         atomic_dec(&pm8001_dev->running_req);
2677                 break;
2678         case IO_PORT_IN_RESET:
2679                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2680                 ts->resp = SAS_TASK_COMPLETE;
2681                 ts->stat = SAS_DEV_NO_RESPONSE;
2682                 if (pm8001_dev)
2683                         atomic_dec(&pm8001_dev->running_req);
2684                 break;
2685         case IO_DS_NON_OPERATIONAL:
2686                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2687                 ts->resp = SAS_TASK_COMPLETE;
2688                 ts->stat = SAS_DEV_NO_RESPONSE;
2689                 if (!t->uldd_task) {
2690                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2691                                         IO_DS_NON_OPERATIONAL);
2692                         ts->resp = SAS_TASK_UNDELIVERED;
2693                         ts->stat = SAS_QUEUE_FULL;
2694                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2695                         return;
2696                 }
2697                 break;
2698         case IO_DS_IN_RECOVERY:
2699                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2700                 ts->resp = SAS_TASK_COMPLETE;
2701                 ts->stat = SAS_DEV_NO_RESPONSE;
2702                 if (pm8001_dev)
2703                         atomic_dec(&pm8001_dev->running_req);
2704                 break;
2705         case IO_DS_IN_ERROR:
2706                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2707                 ts->resp = SAS_TASK_COMPLETE;
2708                 ts->stat = SAS_DEV_NO_RESPONSE;
2709                 if (!t->uldd_task) {
2710                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2711                                         IO_DS_IN_ERROR);
2712                         ts->resp = SAS_TASK_UNDELIVERED;
2713                         ts->stat = SAS_QUEUE_FULL;
2714                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2715                         return;
2716                 }
2717                 break;
2718         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2719                 pm8001_dbg(pm8001_ha, IO,
2720                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2721                 ts->resp = SAS_TASK_COMPLETE;
2722                 ts->stat = SAS_OPEN_REJECT;
2723                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2724                 if (pm8001_dev)
2725                         atomic_dec(&pm8001_dev->running_req);
2726                 break;
2727         default:
2728                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2729                 /* not allowed case. Therefore, return failed status */
2730                 ts->resp = SAS_TASK_COMPLETE;
2731                 ts->stat = SAS_DEV_NO_RESPONSE;
2732                 if (pm8001_dev)
2733                         atomic_dec(&pm8001_dev->running_req);
2734                 break;
2735         }
2736         spin_lock_irqsave(&t->task_state_lock, flags);
2737         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2738         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2739         t->task_state_flags |= SAS_TASK_STATE_DONE;
2740         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2741                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2742                 pm8001_dbg(pm8001_ha, FAIL,
2743                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2744                            t, status, ts->resp, ts->stat);
2745                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2746                 if (t->slow_task)
2747                         complete(&t->slow_task->completion);
2748         } else {
2749                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2750                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2751         }
2752 }
2753
2754 /*See the comments for mpi_ssp_completion */
2755 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2756 {
2757         struct sas_task *t;
2758         struct task_status_struct *ts;
2759         struct pm8001_ccb_info *ccb;
2760         struct pm8001_device *pm8001_dev;
2761         struct sata_event_resp *psataPayload =
2762                 (struct sata_event_resp *)(piomb + 4);
2763         u32 event = le32_to_cpu(psataPayload->event);
2764         u32 tag = le32_to_cpu(psataPayload->tag);
2765         u32 port_id = le32_to_cpu(psataPayload->port_id);
2766         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2767         unsigned long flags;
2768
2769         ccb = &pm8001_ha->ccb_info[tag];
2770
2771         if (ccb) {
2772                 t = ccb->task;
2773                 pm8001_dev = ccb->device;
2774         } else {
2775                 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2776                 return;
2777         }
2778         if (event)
2779                 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2780
2781         /* Check if this is NCQ error */
2782         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2783                 /* find device using device id */
2784                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2785                 /* send read log extension */
2786                 if (pm8001_dev)
2787                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2788                 return;
2789         }
2790
2791         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2792                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2793                 return;
2794         }
2795
2796         ts = &t->task_status;
2797         pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2798                    port_id, tag, event);
2799         switch (event) {
2800         case IO_OVERFLOW:
2801                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2802                 ts->resp = SAS_TASK_COMPLETE;
2803                 ts->stat = SAS_DATA_OVERRUN;
2804                 ts->residual = 0;
2805                 if (pm8001_dev)
2806                         atomic_dec(&pm8001_dev->running_req);
2807                 break;
2808         case IO_XFER_ERROR_BREAK:
2809                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2810                 ts->resp = SAS_TASK_COMPLETE;
2811                 ts->stat = SAS_INTERRUPTED;
2812                 break;
2813         case IO_XFER_ERROR_PHY_NOT_READY:
2814                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2815                 ts->resp = SAS_TASK_COMPLETE;
2816                 ts->stat = SAS_OPEN_REJECT;
2817                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2818                 break;
2819         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2820                 pm8001_dbg(pm8001_ha, IO,
2821                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2822                 ts->resp = SAS_TASK_COMPLETE;
2823                 ts->stat = SAS_OPEN_REJECT;
2824                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2825                 break;
2826         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2827                 pm8001_dbg(pm8001_ha, IO,
2828                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2829                 ts->resp = SAS_TASK_COMPLETE;
2830                 ts->stat = SAS_OPEN_REJECT;
2831                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2832                 break;
2833         case IO_OPEN_CNX_ERROR_BREAK:
2834                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2835                 ts->resp = SAS_TASK_COMPLETE;
2836                 ts->stat = SAS_OPEN_REJECT;
2837                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2838                 break;
2839         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2840         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2841         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2842         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2843         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2844         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2845                 pm8001_dbg(pm8001_ha, FAIL,
2846                            "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2847                 ts->resp = SAS_TASK_UNDELIVERED;
2848                 ts->stat = SAS_DEV_NO_RESPONSE;
2849                 if (!t->uldd_task) {
2850                         pm8001_handle_event(pm8001_ha,
2851                                 pm8001_dev,
2852                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2853                         ts->resp = SAS_TASK_COMPLETE;
2854                         ts->stat = SAS_QUEUE_FULL;
2855                         pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2856                         return;
2857                 }
2858                 break;
2859         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2860                 pm8001_dbg(pm8001_ha, IO,
2861                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2862                 ts->resp = SAS_TASK_UNDELIVERED;
2863                 ts->stat = SAS_OPEN_REJECT;
2864                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2865                 break;
2866         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2867                 pm8001_dbg(pm8001_ha, IO,
2868                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2869                 ts->resp = SAS_TASK_COMPLETE;
2870                 ts->stat = SAS_OPEN_REJECT;
2871                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2872                 break;
2873         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2874                 pm8001_dbg(pm8001_ha, IO,
2875                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2876                 ts->resp = SAS_TASK_COMPLETE;
2877                 ts->stat = SAS_OPEN_REJECT;
2878                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2879                 break;
2880         case IO_XFER_ERROR_NAK_RECEIVED:
2881                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2882                 ts->resp = SAS_TASK_COMPLETE;
2883                 ts->stat = SAS_NAK_R_ERR;
2884                 break;
2885         case IO_XFER_ERROR_PEER_ABORTED:
2886                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2887                 ts->resp = SAS_TASK_COMPLETE;
2888                 ts->stat = SAS_NAK_R_ERR;
2889                 break;
2890         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2891                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2892                 ts->resp = SAS_TASK_COMPLETE;
2893                 ts->stat = SAS_DATA_UNDERRUN;
2894                 break;
2895         case IO_XFER_OPEN_RETRY_TIMEOUT:
2896                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2897                 ts->resp = SAS_TASK_COMPLETE;
2898                 ts->stat = SAS_OPEN_TO;
2899                 break;
2900         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2901                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2902                 ts->resp = SAS_TASK_COMPLETE;
2903                 ts->stat = SAS_OPEN_TO;
2904                 break;
2905         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2906                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2907                 ts->resp = SAS_TASK_COMPLETE;
2908                 ts->stat = SAS_OPEN_TO;
2909                 break;
2910         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2911                 pm8001_dbg(pm8001_ha, IO,
2912                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2913                 ts->resp = SAS_TASK_COMPLETE;
2914                 ts->stat = SAS_OPEN_TO;
2915                 break;
2916         case IO_XFER_ERROR_OFFSET_MISMATCH:
2917                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2918                 ts->resp = SAS_TASK_COMPLETE;
2919                 ts->stat = SAS_OPEN_TO;
2920                 break;
2921         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2922                 pm8001_dbg(pm8001_ha, IO,
2923                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2924                 ts->resp = SAS_TASK_COMPLETE;
2925                 ts->stat = SAS_OPEN_TO;
2926                 break;
2927         case IO_XFER_CMD_FRAME_ISSUED:
2928                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2929                 break;
2930         case IO_XFER_PIO_SETUP_ERROR:
2931                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2932                 ts->resp = SAS_TASK_COMPLETE;
2933                 ts->stat = SAS_OPEN_TO;
2934                 break;
2935         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2936                 pm8001_dbg(pm8001_ha, FAIL,
2937                            "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2938                 /* TBC: used default set values */
2939                 ts->resp = SAS_TASK_COMPLETE;
2940                 ts->stat = SAS_OPEN_TO;
2941                 break;
2942         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2943                 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2944                 /* TBC: used default set values */
2945                 ts->resp = SAS_TASK_COMPLETE;
2946                 ts->stat = SAS_OPEN_TO;
2947                 break;
2948         default:
2949                 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2950                 /* not allowed case. Therefore, return failed status */
2951                 ts->resp = SAS_TASK_COMPLETE;
2952                 ts->stat = SAS_OPEN_TO;
2953                 break;
2954         }
2955         spin_lock_irqsave(&t->task_state_lock, flags);
2956         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2957         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2958         t->task_state_flags |= SAS_TASK_STATE_DONE;
2959         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2960                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2961                 pm8001_dbg(pm8001_ha, FAIL,
2962                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2963                            t, event, ts->resp, ts->stat);
2964                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2965         } else {
2966                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2967                 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2968         }
2969 }
2970
2971 /*See the comments for mpi_ssp_completion */
2972 static void
2973 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2974 {
2975         u32 param, i;
2976         struct sas_task *t;
2977         struct pm8001_ccb_info *ccb;
2978         unsigned long flags;
2979         u32 status;
2980         u32 tag;
2981         struct smp_completion_resp *psmpPayload;
2982         struct task_status_struct *ts;
2983         struct pm8001_device *pm8001_dev;
2984         char *pdma_respaddr = NULL;
2985
2986         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2987         status = le32_to_cpu(psmpPayload->status);
2988         tag = le32_to_cpu(psmpPayload->tag);
2989
2990         ccb = &pm8001_ha->ccb_info[tag];
2991         param = le32_to_cpu(psmpPayload->param);
2992         t = ccb->task;
2993         ts = &t->task_status;
2994         pm8001_dev = ccb->device;
2995         if (status)
2996                 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2997         if (unlikely(!t || !t->lldd_task || !t->dev))
2998                 return;
2999
3000         pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
3001
3002         switch (status) {
3003
3004         case IO_SUCCESS:
3005                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
3006                 ts->resp = SAS_TASK_COMPLETE;
3007                 ts->stat = SAS_SAM_STAT_GOOD;
3008                 if (pm8001_dev)
3009                         atomic_dec(&pm8001_dev->running_req);
3010                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3011                         pm8001_dbg(pm8001_ha, IO,
3012                                    "DIRECT RESPONSE Length:%d\n",
3013                                    param);
3014                         pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
3015                                                 ((u64)sg_dma_address
3016                                                 (&t->smp_task.smp_resp))));
3017                         for (i = 0; i < param; i++) {
3018                                 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
3019                                 pm8001_dbg(pm8001_ha, IO,
3020                                            "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3021                                            i, *(pdma_respaddr + i),
3022                                            psmpPayload->_r_a[i]);
3023                         }
3024                 }
3025                 break;
3026         case IO_ABORTED:
3027                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3028                 ts->resp = SAS_TASK_COMPLETE;
3029                 ts->stat = SAS_ABORTED_TASK;
3030                 if (pm8001_dev)
3031                         atomic_dec(&pm8001_dev->running_req);
3032                 break;
3033         case IO_OVERFLOW:
3034                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3035                 ts->resp = SAS_TASK_COMPLETE;
3036                 ts->stat = SAS_DATA_OVERRUN;
3037                 ts->residual = 0;
3038                 if (pm8001_dev)
3039                         atomic_dec(&pm8001_dev->running_req);
3040                 break;
3041         case IO_NO_DEVICE:
3042                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3043                 ts->resp = SAS_TASK_COMPLETE;
3044                 ts->stat = SAS_PHY_DOWN;
3045                 break;
3046         case IO_ERROR_HW_TIMEOUT:
3047                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3048                 ts->resp = SAS_TASK_COMPLETE;
3049                 ts->stat = SAS_SAM_STAT_BUSY;
3050                 break;
3051         case IO_XFER_ERROR_BREAK:
3052                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3053                 ts->resp = SAS_TASK_COMPLETE;
3054                 ts->stat = SAS_SAM_STAT_BUSY;
3055                 break;
3056         case IO_XFER_ERROR_PHY_NOT_READY:
3057                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3058                 ts->resp = SAS_TASK_COMPLETE;
3059                 ts->stat = SAS_SAM_STAT_BUSY;
3060                 break;
3061         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3062                 pm8001_dbg(pm8001_ha, IO,
3063                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3064                 ts->resp = SAS_TASK_COMPLETE;
3065                 ts->stat = SAS_OPEN_REJECT;
3066                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3067                 break;
3068         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3069                 pm8001_dbg(pm8001_ha, IO,
3070                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3071                 ts->resp = SAS_TASK_COMPLETE;
3072                 ts->stat = SAS_OPEN_REJECT;
3073                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3074                 break;
3075         case IO_OPEN_CNX_ERROR_BREAK:
3076                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3077                 ts->resp = SAS_TASK_COMPLETE;
3078                 ts->stat = SAS_OPEN_REJECT;
3079                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3080                 break;
3081         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3082         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3083         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3084         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3085         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3086         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3087                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3088                 ts->resp = SAS_TASK_COMPLETE;
3089                 ts->stat = SAS_OPEN_REJECT;
3090                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3091                 pm8001_handle_event(pm8001_ha,
3092                                 pm8001_dev,
3093                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3094                 break;
3095         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3096                 pm8001_dbg(pm8001_ha, IO,
3097                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3098                 ts->resp = SAS_TASK_COMPLETE;
3099                 ts->stat = SAS_OPEN_REJECT;
3100                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3101                 break;
3102         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3103                 pm8001_dbg(pm8001_ha, IO,
3104                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3105                 ts->resp = SAS_TASK_COMPLETE;
3106                 ts->stat = SAS_OPEN_REJECT;
3107                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3108                 break;
3109         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3110                 pm8001_dbg(pm8001_ha, IO,
3111                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3112                 ts->resp = SAS_TASK_COMPLETE;
3113                 ts->stat = SAS_OPEN_REJECT;
3114                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3115                 break;
3116         case IO_XFER_ERROR_RX_FRAME:
3117                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3118                 ts->resp = SAS_TASK_COMPLETE;
3119                 ts->stat = SAS_DEV_NO_RESPONSE;
3120                 break;
3121         case IO_XFER_OPEN_RETRY_TIMEOUT:
3122                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3123                 ts->resp = SAS_TASK_COMPLETE;
3124                 ts->stat = SAS_OPEN_REJECT;
3125                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3126                 break;
3127         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3128                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3129                 ts->resp = SAS_TASK_COMPLETE;
3130                 ts->stat = SAS_QUEUE_FULL;
3131                 break;
3132         case IO_PORT_IN_RESET:
3133                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3134                 ts->resp = SAS_TASK_COMPLETE;
3135                 ts->stat = SAS_OPEN_REJECT;
3136                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3137                 break;
3138         case IO_DS_NON_OPERATIONAL:
3139                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3140                 ts->resp = SAS_TASK_COMPLETE;
3141                 ts->stat = SAS_DEV_NO_RESPONSE;
3142                 break;
3143         case IO_DS_IN_RECOVERY:
3144                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3145                 ts->resp = SAS_TASK_COMPLETE;
3146                 ts->stat = SAS_OPEN_REJECT;
3147                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3148                 break;
3149         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3150                 pm8001_dbg(pm8001_ha, IO,
3151                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3152                 ts->resp = SAS_TASK_COMPLETE;
3153                 ts->stat = SAS_OPEN_REJECT;
3154                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3155                 break;
3156         default:
3157                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3158                 ts->resp = SAS_TASK_COMPLETE;
3159                 ts->stat = SAS_DEV_NO_RESPONSE;
3160                 /* not allowed case. Therefore, return failed status */
3161                 break;
3162         }
3163         spin_lock_irqsave(&t->task_state_lock, flags);
3164         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3165         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3166         t->task_state_flags |= SAS_TASK_STATE_DONE;
3167         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3168                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3169                 pm8001_dbg(pm8001_ha, FAIL,
3170                            "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3171                            t, status, ts->resp, ts->stat);
3172                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3173         } else {
3174                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3175                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3176                 mb();/* in order to force CPU ordering */
3177                 t->task_done(t);
3178         }
3179 }
3180
3181 /**
3182  * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3183  * @pm8001_ha: our hba card information
3184  * @Qnum: the outbound queue message number.
3185  * @SEA: source of event to ack
3186  * @port_id: port id.
3187  * @phyId: phy id.
3188  * @param0: parameter 0.
3189  * @param1: parameter 1.
3190  */
3191 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3192         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3193 {
3194         struct hw_event_ack_req  payload;
3195         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3196
3197         struct inbound_queue_table *circularQ;
3198
3199         memset((u8 *)&payload, 0, sizeof(payload));
3200         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3201         payload.tag = cpu_to_le32(1);
3202         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3203                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3204         payload.param0 = cpu_to_le32(param0);
3205         payload.param1 = cpu_to_le32(param1);
3206         pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3207                         sizeof(payload), 0);
3208 }
3209
3210 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3211         u32 phyId, u32 phy_op);
3212
3213 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3214                                         void *piomb)
3215 {
3216         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3217         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3218         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3219         u32 lr_status_evt_portid =
3220                 le32_to_cpu(pPayload->lr_status_evt_portid);
3221         u8 deviceType = pPayload->sas_identify.dev_type;
3222         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3223         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3224         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3225         struct pm8001_port *port = &pm8001_ha->port[port_id];
3226
3227         if (deviceType == SAS_END_DEVICE) {
3228                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3229                                         PHY_NOTIFY_ENABLE_SPINUP);
3230         }
3231
3232         port->wide_port_phymap |= (1U << phy_id);
3233         pm8001_get_lrate_mode(phy, link_rate);
3234         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3235         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3236         phy->phy_attached = 1;
3237 }
3238
3239 /**
3240  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3241  * @pm8001_ha: our hba card information
3242  * @piomb: IO message buffer
3243  */
3244 static void
3245 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3246 {
3247         struct hw_event_resp *pPayload =
3248                 (struct hw_event_resp *)(piomb + 4);
3249         u32 lr_status_evt_portid =
3250                 le32_to_cpu(pPayload->lr_status_evt_portid);
3251         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3252
3253         u8 link_rate =
3254                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3255         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3256         u8 phy_id =
3257                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3258         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3259
3260         struct pm8001_port *port = &pm8001_ha->port[port_id];
3261         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3262         unsigned long flags;
3263         u8 deviceType = pPayload->sas_identify.dev_type;
3264         port->port_state = portstate;
3265         port->wide_port_phymap |= (1U << phy_id);
3266         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3267         pm8001_dbg(pm8001_ha, MSG,
3268                    "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3269                    port_id, phy_id, link_rate, portstate, deviceType);
3270
3271         switch (deviceType) {
3272         case SAS_PHY_UNUSED:
3273                 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3274                 break;
3275         case SAS_END_DEVICE:
3276                 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3277                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3278                         PHY_NOTIFY_ENABLE_SPINUP);
3279                 port->port_attached = 1;
3280                 pm8001_get_lrate_mode(phy, link_rate);
3281                 break;
3282         case SAS_EDGE_EXPANDER_DEVICE:
3283                 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3284                 port->port_attached = 1;
3285                 pm8001_get_lrate_mode(phy, link_rate);
3286                 break;
3287         case SAS_FANOUT_EXPANDER_DEVICE:
3288                 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3289                 port->port_attached = 1;
3290                 pm8001_get_lrate_mode(phy, link_rate);
3291                 break;
3292         default:
3293                 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3294                            deviceType);
3295                 break;
3296         }
3297         phy->phy_type |= PORT_TYPE_SAS;
3298         phy->identify.device_type = deviceType;
3299         phy->phy_attached = 1;
3300         if (phy->identify.device_type == SAS_END_DEVICE)
3301                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3302         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3303                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3304         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3305         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3306         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3307         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3308                 sizeof(struct sas_identify_frame)-4);
3309         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3310         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3311         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3312         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3313                 mdelay(200); /* delay a moment to wait for disk to spin up */
3314         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3315 }
3316
3317 /**
3318  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3319  * @pm8001_ha: our hba card information
3320  * @piomb: IO message buffer
3321  */
3322 static void
3323 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3324 {
3325         struct hw_event_resp *pPayload =
3326                 (struct hw_event_resp *)(piomb + 4);
3327         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3328         u32 lr_status_evt_portid =
3329                 le32_to_cpu(pPayload->lr_status_evt_portid);
3330         u8 link_rate =
3331                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3332         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3333         u8 phy_id =
3334                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3335
3336         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3337
3338         struct pm8001_port *port = &pm8001_ha->port[port_id];
3339         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3340         unsigned long flags;
3341         pm8001_dbg(pm8001_ha, DEVIO,
3342                    "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3343                    port_id, phy_id, link_rate, portstate);
3344
3345         port->port_state = portstate;
3346         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3347         port->port_attached = 1;
3348         pm8001_get_lrate_mode(phy, link_rate);
3349         phy->phy_type |= PORT_TYPE_SATA;
3350         phy->phy_attached = 1;
3351         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3352         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3353         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3354         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3355                 sizeof(struct dev_to_host_fis));
3356         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3357         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3358         phy->identify.device_type = SAS_SATA_DEV;
3359         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3360         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3361         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3362 }
3363
3364 /**
3365  * hw_event_phy_down -we should notify the libsas the phy is down.
3366  * @pm8001_ha: our hba card information
3367  * @piomb: IO message buffer
3368  */
3369 static void
3370 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3371 {
3372         struct hw_event_resp *pPayload =
3373                 (struct hw_event_resp *)(piomb + 4);
3374
3375         u32 lr_status_evt_portid =
3376                 le32_to_cpu(pPayload->lr_status_evt_portid);
3377         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3378         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3379         u8 phy_id =
3380                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3381         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3382
3383         struct pm8001_port *port = &pm8001_ha->port[port_id];
3384         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3385         u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3386         port->port_state = portstate;
3387         phy->identify.device_type = 0;
3388         phy->phy_attached = 0;
3389         switch (portstate) {
3390         case PORT_VALID:
3391                 break;
3392         case PORT_INVALID:
3393                 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3394                            port_id);
3395                 pm8001_dbg(pm8001_ha, MSG,
3396                            " Last phy Down and port invalid\n");
3397                 if (port_sata) {
3398                         phy->phy_type = 0;
3399                         port->port_attached = 0;
3400                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3401                                         port_id, phy_id, 0, 0);
3402                 }
3403                 sas_phy_disconnected(&phy->sas_phy);
3404                 break;
3405         case PORT_IN_RESET:
3406                 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3407                            port_id);
3408                 break;
3409         case PORT_NOT_ESTABLISHED:
3410                 pm8001_dbg(pm8001_ha, MSG,
3411                            " Phy Down and PORT_NOT_ESTABLISHED\n");
3412                 port->port_attached = 0;
3413                 break;
3414         case PORT_LOSTCOMM:
3415                 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3416                 pm8001_dbg(pm8001_ha, MSG,
3417                            " Last phy Down and port invalid\n");
3418                 if (port_sata) {
3419                         port->port_attached = 0;
3420                         phy->phy_type = 0;
3421                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3422                                         port_id, phy_id, 0, 0);
3423                 }
3424                 sas_phy_disconnected(&phy->sas_phy);
3425                 break;
3426         default:
3427                 port->port_attached = 0;
3428                 pm8001_dbg(pm8001_ha, DEVIO,
3429                            " Phy Down and(default) = 0x%x\n",
3430                            portstate);
3431                 break;
3432
3433         }
3434         if (port_sata && (portstate != PORT_IN_RESET))
3435                 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3436 }
3437
3438 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3439 {
3440         struct phy_start_resp *pPayload =
3441                 (struct phy_start_resp *)(piomb + 4);
3442         u32 status =
3443                 le32_to_cpu(pPayload->status);
3444         u32 phy_id =
3445                 le32_to_cpu(pPayload->phyid);
3446         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3447
3448         pm8001_dbg(pm8001_ha, INIT,
3449                    "phy start resp status:0x%x, phyid:0x%x\n",
3450                    status, phy_id);
3451         if (status == 0)
3452                 phy->phy_state = PHY_LINK_DOWN;
3453
3454         if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3455                         phy->enable_completion != NULL) {
3456                 complete(phy->enable_completion);
3457                 phy->enable_completion = NULL;
3458         }
3459         return 0;
3460
3461 }
3462
3463 /**
3464  * mpi_thermal_hw_event -The hw event has come.
3465  * @pm8001_ha: our hba card information
3466  * @piomb: IO message buffer
3467  */
3468 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3469 {
3470         struct thermal_hw_event *pPayload =
3471                 (struct thermal_hw_event *)(piomb + 4);
3472
3473         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3474         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3475
3476         if (thermal_event & 0x40) {
3477                 pm8001_dbg(pm8001_ha, IO,
3478                            "Thermal Event: Local high temperature violated!\n");
3479                 pm8001_dbg(pm8001_ha, IO,
3480                            "Thermal Event: Measured local high temperature %d\n",
3481                            ((rht_lht & 0xFF00) >> 8));
3482         }
3483         if (thermal_event & 0x10) {
3484                 pm8001_dbg(pm8001_ha, IO,
3485                            "Thermal Event: Remote high temperature violated!\n");
3486                 pm8001_dbg(pm8001_ha, IO,
3487                            "Thermal Event: Measured remote high temperature %d\n",
3488                            ((rht_lht & 0xFF000000) >> 24));
3489         }
3490         return 0;
3491 }
3492
3493 /**
3494  * mpi_hw_event -The hw event has come.
3495  * @pm8001_ha: our hba card information
3496  * @piomb: IO message buffer
3497  */
3498 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3499 {
3500         unsigned long flags, i;
3501         struct hw_event_resp *pPayload =
3502                 (struct hw_event_resp *)(piomb + 4);
3503         u32 lr_status_evt_portid =
3504                 le32_to_cpu(pPayload->lr_status_evt_portid);
3505         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3506         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3507         u8 phy_id =
3508                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3509         u16 eventType =
3510                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3511         u8 status =
3512                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3513         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3514         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3515         struct pm8001_port *port = &pm8001_ha->port[port_id];
3516         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3517         pm8001_dbg(pm8001_ha, DEV,
3518                    "portid:%d phyid:%d event:0x%x status:0x%x\n",
3519                    port_id, phy_id, eventType, status);
3520
3521         switch (eventType) {
3522
3523         case HW_EVENT_SAS_PHY_UP:
3524                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3525                 hw_event_sas_phy_up(pm8001_ha, piomb);
3526                 break;
3527         case HW_EVENT_SATA_PHY_UP:
3528                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3529                 hw_event_sata_phy_up(pm8001_ha, piomb);
3530                 break;
3531         case HW_EVENT_SATA_SPINUP_HOLD:
3532                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3533                 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3534                 break;
3535         case HW_EVENT_PHY_DOWN:
3536                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3537                 hw_event_phy_down(pm8001_ha, piomb);
3538                 if (pm8001_ha->reset_in_progress) {
3539                         pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3540                         return 0;
3541                 }
3542                 phy->phy_attached = 0;
3543                 phy->phy_state = PHY_LINK_DISABLE;
3544                 break;
3545         case HW_EVENT_PORT_INVALID:
3546                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3547                 sas_phy_disconnected(sas_phy);
3548                 phy->phy_attached = 0;
3549                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3550                 break;
3551         /* the broadcast change primitive received, tell the LIBSAS this event
3552         to revalidate the sas domain*/
3553         case HW_EVENT_BROADCAST_CHANGE:
3554                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3555                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3556                         port_id, phy_id, 1, 0);
3557                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3558                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3559                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3560                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3561                 break;
3562         case HW_EVENT_PHY_ERROR:
3563                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3564                 sas_phy_disconnected(&phy->sas_phy);
3565                 phy->phy_attached = 0;
3566                 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3567                 break;
3568         case HW_EVENT_BROADCAST_EXP:
3569                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3570                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3571                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3572                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3573                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3574                 break;
3575         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3576                 pm8001_dbg(pm8001_ha, MSG,
3577                            "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3578                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3579                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3580                 break;
3581         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3582                 pm8001_dbg(pm8001_ha, MSG,
3583                            "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3584                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3585                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3586                         port_id, phy_id, 0, 0);
3587                 break;
3588         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3589                 pm8001_dbg(pm8001_ha, MSG,
3590                            "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3591                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3592                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3593                         port_id, phy_id, 0, 0);
3594                 break;
3595         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3596                 pm8001_dbg(pm8001_ha, MSG,
3597                            "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3598                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3599                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3600                         port_id, phy_id, 0, 0);
3601                 break;
3602         case HW_EVENT_MALFUNCTION:
3603                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3604                 break;
3605         case HW_EVENT_BROADCAST_SES:
3606                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3607                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3608                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3609                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3610                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3611                 break;
3612         case HW_EVENT_INBOUND_CRC_ERROR:
3613                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3614                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3615                         HW_EVENT_INBOUND_CRC_ERROR,
3616                         port_id, phy_id, 0, 0);
3617                 break;
3618         case HW_EVENT_HARD_RESET_RECEIVED:
3619                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3620                 sas_notify_port_event(sas_phy, PORTE_HARD_RESET);
3621                 break;
3622         case HW_EVENT_ID_FRAME_TIMEOUT:
3623                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3624                 sas_phy_disconnected(sas_phy);
3625                 phy->phy_attached = 0;
3626                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3627                 break;
3628         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3629                 pm8001_dbg(pm8001_ha, MSG,
3630                            "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3631                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3632                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3633                         port_id, phy_id, 0, 0);
3634                 sas_phy_disconnected(sas_phy);
3635                 phy->phy_attached = 0;
3636                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3637                 break;
3638         case HW_EVENT_PORT_RESET_TIMER_TMO:
3639                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3640                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3641                         port_id, phy_id, 0, 0);
3642                 sas_phy_disconnected(sas_phy);
3643                 phy->phy_attached = 0;
3644                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3645                 if (pm8001_ha->phy[phy_id].reset_completion) {
3646                         pm8001_ha->phy[phy_id].port_reset_status =
3647                                         PORT_RESET_TMO;
3648                         complete(pm8001_ha->phy[phy_id].reset_completion);
3649                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3650                 }
3651                 break;
3652         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3653                 pm8001_dbg(pm8001_ha, MSG,
3654                            "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3655                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3656                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3657                         port_id, phy_id, 0, 0);
3658                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3659                         if (port->wide_port_phymap & (1 << i)) {
3660                                 phy = &pm8001_ha->phy[i];
3661                                 sas_notify_phy_event(&phy->sas_phy,
3662                                                 PHYE_LOSS_OF_SIGNAL);
3663                                 port->wide_port_phymap &= ~(1 << i);
3664                         }
3665                 }
3666                 break;
3667         case HW_EVENT_PORT_RECOVER:
3668                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3669                 hw_event_port_recover(pm8001_ha, piomb);
3670                 break;
3671         case HW_EVENT_PORT_RESET_COMPLETE:
3672                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3673                 if (pm8001_ha->phy[phy_id].reset_completion) {
3674                         pm8001_ha->phy[phy_id].port_reset_status =
3675                                         PORT_RESET_SUCCESS;
3676                         complete(pm8001_ha->phy[phy_id].reset_completion);
3677                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3678                 }
3679                 break;
3680         case EVENT_BROADCAST_ASYNCH_EVENT:
3681                 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3682                 break;
3683         default:
3684                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3685                            eventType);
3686                 break;
3687         }
3688         return 0;
3689 }
3690
3691 /**
3692  * mpi_phy_stop_resp - SPCv specific
3693  * @pm8001_ha: our hba card information
3694  * @piomb: IO message buffer
3695  */
3696 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3697 {
3698         struct phy_stop_resp *pPayload =
3699                 (struct phy_stop_resp *)(piomb + 4);
3700         u32 status =
3701                 le32_to_cpu(pPayload->status);
3702         u32 phyid =
3703                 le32_to_cpu(pPayload->phyid) & 0xFF;
3704         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3705         pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3706                    phyid, status);
3707         if (status == PHY_STOP_SUCCESS ||
3708                 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3709                 phy->phy_state = PHY_LINK_DISABLE;
3710         return 0;
3711 }
3712
3713 /**
3714  * mpi_set_controller_config_resp - SPCv specific
3715  * @pm8001_ha: our hba card information
3716  * @piomb: IO message buffer
3717  */
3718 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3719                         void *piomb)
3720 {
3721         struct set_ctrl_cfg_resp *pPayload =
3722                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3723         u32 status = le32_to_cpu(pPayload->status);
3724         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3725         u32 tag = le32_to_cpu(pPayload->tag);
3726
3727         pm8001_dbg(pm8001_ha, MSG,
3728                    "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3729                    status, err_qlfr_pgcd);
3730         pm8001_tag_free(pm8001_ha, tag);
3731
3732         return 0;
3733 }
3734
3735 /**
3736  * mpi_get_controller_config_resp - SPCv specific
3737  * @pm8001_ha: our hba card information
3738  * @piomb: IO message buffer
3739  */
3740 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3741                         void *piomb)
3742 {
3743         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3744
3745         return 0;
3746 }
3747
3748 /**
3749  * mpi_get_phy_profile_resp - SPCv specific
3750  * @pm8001_ha: our hba card information
3751  * @piomb: IO message buffer
3752  */
3753 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3754                         void *piomb)
3755 {
3756         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3757
3758         return 0;
3759 }
3760
3761 /**
3762  * mpi_flash_op_ext_resp - SPCv specific
3763  * @pm8001_ha: our hba card information
3764  * @piomb: IO message buffer
3765  */
3766 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3767 {
3768         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3769
3770         return 0;
3771 }
3772
3773 /**
3774  * mpi_set_phy_profile_resp - SPCv specific
3775  * @pm8001_ha: our hba card information
3776  * @piomb: IO message buffer
3777  */
3778 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3779                         void *piomb)
3780 {
3781         u32 tag;
3782         u8 page_code;
3783         int rc = 0;
3784         struct set_phy_profile_resp *pPayload =
3785                 (struct set_phy_profile_resp *)(piomb + 4);
3786         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3787         u32 status = le32_to_cpu(pPayload->status);
3788
3789         tag = le32_to_cpu(pPayload->tag);
3790         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3791         if (status) {
3792                 /* status is FAILED */
3793                 pm8001_dbg(pm8001_ha, FAIL,
3794                            "PhyProfile command failed  with status 0x%08X\n",
3795                            status);
3796                 rc = -1;
3797         } else {
3798                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3799                         pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3800                                    page_code);
3801                         rc = -1;
3802                 }
3803         }
3804         pm8001_tag_free(pm8001_ha, tag);
3805         return rc;
3806 }
3807
3808 /**
3809  * mpi_kek_management_resp - SPCv specific
3810  * @pm8001_ha: our hba card information
3811  * @piomb: IO message buffer
3812  */
3813 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3814                         void *piomb)
3815 {
3816         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3817
3818         u32 status = le32_to_cpu(pPayload->status);
3819         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3820         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3821
3822         pm8001_dbg(pm8001_ha, MSG,
3823                    "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3824                    status, kidx_new_curr_ksop, err_qlfr);
3825
3826         return 0;
3827 }
3828
3829 /**
3830  * mpi_dek_management_resp - SPCv specific
3831  * @pm8001_ha: our hba card information
3832  * @piomb: IO message buffer
3833  */
3834 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3835                         void *piomb)
3836 {
3837         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3838
3839         return 0;
3840 }
3841
3842 /**
3843  * ssp_coalesced_comp_resp - SPCv specific
3844  * @pm8001_ha: our hba card information
3845  * @piomb: IO message buffer
3846  */
3847 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3848                         void *piomb)
3849 {
3850         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3851
3852         return 0;
3853 }
3854
3855 /**
3856  * process_one_iomb - process one outbound Queue memory block
3857  * @pm8001_ha: our hba card information
3858  * @piomb: IO message buffer
3859  */
3860 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3861 {
3862         __le32 pHeader = *(__le32 *)piomb;
3863         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3864
3865         switch (opc) {
3866         case OPC_OUB_ECHO:
3867                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3868                 break;
3869         case OPC_OUB_HW_EVENT:
3870                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3871                 mpi_hw_event(pm8001_ha, piomb);
3872                 break;
3873         case OPC_OUB_THERM_HW_EVENT:
3874                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3875                 mpi_thermal_hw_event(pm8001_ha, piomb);
3876                 break;
3877         case OPC_OUB_SSP_COMP:
3878                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3879                 mpi_ssp_completion(pm8001_ha, piomb);
3880                 break;
3881         case OPC_OUB_SMP_COMP:
3882                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3883                 mpi_smp_completion(pm8001_ha, piomb);
3884                 break;
3885         case OPC_OUB_LOCAL_PHY_CNTRL:
3886                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3887                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3888                 break;
3889         case OPC_OUB_DEV_REGIST:
3890                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3891                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3892                 break;
3893         case OPC_OUB_DEREG_DEV:
3894                 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3895                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3896                 break;
3897         case OPC_OUB_GET_DEV_HANDLE:
3898                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3899                 break;
3900         case OPC_OUB_SATA_COMP:
3901                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3902                 mpi_sata_completion(pm8001_ha, piomb);
3903                 break;
3904         case OPC_OUB_SATA_EVENT:
3905                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3906                 mpi_sata_event(pm8001_ha, piomb);
3907                 break;
3908         case OPC_OUB_SSP_EVENT:
3909                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3910                 mpi_ssp_event(pm8001_ha, piomb);
3911                 break;
3912         case OPC_OUB_DEV_HANDLE_ARRIV:
3913                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3914                 /*This is for target*/
3915                 break;
3916         case OPC_OUB_SSP_RECV_EVENT:
3917                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3918                 /*This is for target*/
3919                 break;
3920         case OPC_OUB_FW_FLASH_UPDATE:
3921                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3922                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3923                 break;
3924         case OPC_OUB_GPIO_RESPONSE:
3925                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3926                 break;
3927         case OPC_OUB_GPIO_EVENT:
3928                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3929                 break;
3930         case OPC_OUB_GENERAL_EVENT:
3931                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3932                 pm8001_mpi_general_event(pm8001_ha, piomb);
3933                 break;
3934         case OPC_OUB_SSP_ABORT_RSP:
3935                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3936                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3937                 break;
3938         case OPC_OUB_SATA_ABORT_RSP:
3939                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3940                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3941                 break;
3942         case OPC_OUB_SAS_DIAG_MODE_START_END:
3943                 pm8001_dbg(pm8001_ha, MSG,
3944                            "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3945                 break;
3946         case OPC_OUB_SAS_DIAG_EXECUTE:
3947                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3948                 break;
3949         case OPC_OUB_GET_TIME_STAMP:
3950                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3951                 break;
3952         case OPC_OUB_SAS_HW_EVENT_ACK:
3953                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3954                 break;
3955         case OPC_OUB_PORT_CONTROL:
3956                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3957                 break;
3958         case OPC_OUB_SMP_ABORT_RSP:
3959                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3960                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3961                 break;
3962         case OPC_OUB_GET_NVMD_DATA:
3963                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3964                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3965                 break;
3966         case OPC_OUB_SET_NVMD_DATA:
3967                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3968                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3969                 break;
3970         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3971                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3972                 break;
3973         case OPC_OUB_SET_DEVICE_STATE:
3974                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3975                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3976                 break;
3977         case OPC_OUB_GET_DEVICE_STATE:
3978                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3979                 break;
3980         case OPC_OUB_SET_DEV_INFO:
3981                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3982                 break;
3983         /* spcv specifc commands */
3984         case OPC_OUB_PHY_START_RESP:
3985                 pm8001_dbg(pm8001_ha, MSG,
3986                            "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
3987                 mpi_phy_start_resp(pm8001_ha, piomb);
3988                 break;
3989         case OPC_OUB_PHY_STOP_RESP:
3990                 pm8001_dbg(pm8001_ha, MSG,
3991                            "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
3992                 mpi_phy_stop_resp(pm8001_ha, piomb);
3993                 break;
3994         case OPC_OUB_SET_CONTROLLER_CONFIG:
3995                 pm8001_dbg(pm8001_ha, MSG,
3996                            "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
3997                 mpi_set_controller_config_resp(pm8001_ha, piomb);
3998                 break;
3999         case OPC_OUB_GET_CONTROLLER_CONFIG:
4000                 pm8001_dbg(pm8001_ha, MSG,
4001                            "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
4002                 mpi_get_controller_config_resp(pm8001_ha, piomb);
4003                 break;
4004         case OPC_OUB_GET_PHY_PROFILE:
4005                 pm8001_dbg(pm8001_ha, MSG,
4006                            "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
4007                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4008                 break;
4009         case OPC_OUB_FLASH_OP_EXT:
4010                 pm8001_dbg(pm8001_ha, MSG,
4011                            "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4012                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4013                 break;
4014         case OPC_OUB_SET_PHY_PROFILE:
4015                 pm8001_dbg(pm8001_ha, MSG,
4016                            "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4017                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4018                 break;
4019         case OPC_OUB_KEK_MANAGEMENT_RESP:
4020                 pm8001_dbg(pm8001_ha, MSG,
4021                            "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4022                 mpi_kek_management_resp(pm8001_ha, piomb);
4023                 break;
4024         case OPC_OUB_DEK_MANAGEMENT_RESP:
4025                 pm8001_dbg(pm8001_ha, MSG,
4026                            "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4027                 mpi_dek_management_resp(pm8001_ha, piomb);
4028                 break;
4029         case OPC_OUB_SSP_COALESCED_COMP_RESP:
4030                 pm8001_dbg(pm8001_ha, MSG,
4031                            "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4032                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4033                 break;
4034         default:
4035                 pm8001_dbg(pm8001_ha, DEVIO,
4036                            "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4037                 break;
4038         }
4039 }
4040
4041 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4042 {
4043         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4044                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4045         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4046                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4047         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4048                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4049         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4050                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4051         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4052                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4053         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4054                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4055         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4056                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4057         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4058                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4059         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4060                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4061         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4062                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4063         pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4064                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6));
4065         pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4066                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7));
4067 }
4068
4069 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4070 {
4071         struct outbound_queue_table *circularQ;
4072         void *pMsg1 = NULL;
4073         u8 bc;
4074         u32 ret = MPI_IO_STATUS_FAIL;
4075         unsigned long flags;
4076         u32 regval;
4077
4078         /*
4079          * Fatal errors are programmed to be signalled in irq vector
4080          * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4081          * fatal_err_interrupt
4082          */
4083         if (vec == (pm8001_ha->max_q_num - 1)) {
4084                 u32 mipsall_ready;
4085
4086                 if (pm8001_ha->chip_id == chip_8008 ||
4087                     pm8001_ha->chip_id == chip_8009)
4088                         mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4089                 else
4090                         mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4091
4092                 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4093                 if ((regval & mipsall_ready) != mipsall_ready) {
4094                         pm8001_ha->controller_fatal_error = true;
4095                         pm8001_dbg(pm8001_ha, FAIL,
4096                                    "Firmware Fatal error! Regval:0x%x\n",
4097                                    regval);
4098                         print_scratchpad_registers(pm8001_ha);
4099                         return ret;
4100                 }
4101         }
4102         spin_lock_irqsave(&pm8001_ha->lock, flags);
4103         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4104         do {
4105                 /* spurious interrupt during setup if kexec-ing and
4106                  * driver doing a doorbell access w/ the pre-kexec oq
4107                  * interrupt setup.
4108                  */
4109                 if (!circularQ->pi_virt)
4110                         break;
4111                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4112                 if (MPI_IO_STATUS_SUCCESS == ret) {
4113                         /* process the outbound message */
4114                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4115                         /* free the message from the outbound circular buffer */
4116                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4117                                                         circularQ, bc);
4118                 }
4119                 if (MPI_IO_STATUS_BUSY == ret) {
4120                         /* Update the producer index from SPC */
4121                         circularQ->producer_index =
4122                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4123                         if (le32_to_cpu(circularQ->producer_index) ==
4124                                 circularQ->consumer_idx)
4125                                 /* OQ is empty */
4126                                 break;
4127                 }
4128         } while (1);
4129         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4130         return ret;
4131 }
4132
4133 /* DMA_... to our direction translation. */
4134 static const u8 data_dir_flags[] = {
4135         [DMA_BIDIRECTIONAL]     = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4136         [DMA_TO_DEVICE]         = DATA_DIR_OUT,         /* OUTBOUND */
4137         [DMA_FROM_DEVICE]       = DATA_DIR_IN,          /* INBOUND */
4138         [DMA_NONE]              = DATA_DIR_NONE,        /* NO TRANSFER */
4139 };
4140
4141 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4142                         struct smp_req *psmp_cmd, int mode, int length)
4143 {
4144         psmp_cmd->tag = hTag;
4145         psmp_cmd->device_id = cpu_to_le32(deviceID);
4146         if (mode == SMP_DIRECT) {
4147                 length = length - 4; /* subtract crc */
4148                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4149         } else {
4150                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4151         }
4152 }
4153
4154 /**
4155  * pm8001_chip_smp_req - send a SMP task to FW
4156  * @pm8001_ha: our hba card information.
4157  * @ccb: the ccb information this request used.
4158  */
4159 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4160         struct pm8001_ccb_info *ccb)
4161 {
4162         int elem, rc;
4163         struct sas_task *task = ccb->task;
4164         struct domain_device *dev = task->dev;
4165         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4166         struct scatterlist *sg_req, *sg_resp;
4167         u32 req_len, resp_len;
4168         struct smp_req smp_cmd;
4169         u32 opc;
4170         struct inbound_queue_table *circularQ;
4171         char *preq_dma_addr = NULL;
4172         __le64 tmp_addr;
4173         u32 i, length;
4174
4175         memset(&smp_cmd, 0, sizeof(smp_cmd));
4176         /*
4177          * DMA-map SMP request, response buffers
4178          */
4179         sg_req = &task->smp_task.smp_req;
4180         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4181         if (!elem)
4182                 return -ENOMEM;
4183         req_len = sg_dma_len(sg_req);
4184
4185         sg_resp = &task->smp_task.smp_resp;
4186         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4187         if (!elem) {
4188                 rc = -ENOMEM;
4189                 goto err_out;
4190         }
4191         resp_len = sg_dma_len(sg_resp);
4192         /* must be in dwords */
4193         if ((req_len & 0x3) || (resp_len & 0x3)) {
4194                 rc = -EINVAL;
4195                 goto err_out_2;
4196         }
4197
4198         opc = OPC_INB_SMP_REQUEST;
4199         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4200         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4201
4202         length = sg_req->length;
4203         pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4204         if (!(length - 8))
4205                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4206         else
4207                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4208
4209
4210         tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4211         preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4212
4213         /* INDIRECT MODE command settings. Use DMA */
4214         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4215                 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4216                 /* for SPCv indirect mode. Place the top 4 bytes of
4217                  * SMP Request header here. */
4218                 for (i = 0; i < 4; i++)
4219                         smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4220                 /* exclude top 4 bytes for SMP req header */
4221                 smp_cmd.long_smp_req.long_req_addr =
4222                         cpu_to_le64((u64)sg_dma_address
4223                                 (&task->smp_task.smp_req) + 4);
4224                 /* exclude 4 bytes for SMP req header and CRC */
4225                 smp_cmd.long_smp_req.long_req_size =
4226                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4227                 smp_cmd.long_smp_req.long_resp_addr =
4228                                 cpu_to_le64((u64)sg_dma_address
4229                                         (&task->smp_task.smp_resp));
4230                 smp_cmd.long_smp_req.long_resp_size =
4231                                 cpu_to_le32((u32)sg_dma_len
4232                                         (&task->smp_task.smp_resp)-4);
4233         } else { /* DIRECT MODE */
4234                 smp_cmd.long_smp_req.long_req_addr =
4235                         cpu_to_le64((u64)sg_dma_address
4236                                         (&task->smp_task.smp_req));
4237                 smp_cmd.long_smp_req.long_req_size =
4238                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4239                 smp_cmd.long_smp_req.long_resp_addr =
4240                         cpu_to_le64((u64)sg_dma_address
4241                                 (&task->smp_task.smp_resp));
4242                 smp_cmd.long_smp_req.long_resp_size =
4243                         cpu_to_le32
4244                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4245         }
4246         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4247                 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4248                 for (i = 0; i < length; i++)
4249                         if (i < 16) {
4250                                 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4251                                 pm8001_dbg(pm8001_ha, IO,
4252                                            "Byte[%d]:%x (DMA data:%x)\n",
4253                                            i, smp_cmd.smp_req16[i],
4254                                            *(preq_dma_addr));
4255                         } else {
4256                                 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4257                                 pm8001_dbg(pm8001_ha, IO,
4258                                            "Byte[%d]:%x (DMA data:%x)\n",
4259                                            i, smp_cmd.smp_req[i],
4260                                            *(preq_dma_addr));
4261                         }
4262         }
4263
4264         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4265                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4266         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4267                         sizeof(smp_cmd), 0);
4268         if (rc)
4269                 goto err_out_2;
4270         return 0;
4271
4272 err_out_2:
4273         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4274                         DMA_FROM_DEVICE);
4275 err_out:
4276         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4277                         DMA_TO_DEVICE);
4278         return rc;
4279 }
4280
4281 static int check_enc_sas_cmd(struct sas_task *task)
4282 {
4283         u8 cmd = task->ssp_task.cmd->cmnd[0];
4284
4285         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4286                 return 1;
4287         else
4288                 return 0;
4289 }
4290
4291 static int check_enc_sat_cmd(struct sas_task *task)
4292 {
4293         int ret = 0;
4294         switch (task->ata_task.fis.command) {
4295         case ATA_CMD_FPDMA_READ:
4296         case ATA_CMD_READ_EXT:
4297         case ATA_CMD_READ:
4298         case ATA_CMD_FPDMA_WRITE:
4299         case ATA_CMD_WRITE_EXT:
4300         case ATA_CMD_WRITE:
4301         case ATA_CMD_PIO_READ:
4302         case ATA_CMD_PIO_READ_EXT:
4303         case ATA_CMD_PIO_WRITE:
4304         case ATA_CMD_PIO_WRITE_EXT:
4305                 ret = 1;
4306                 break;
4307         default:
4308                 ret = 0;
4309                 break;
4310         }
4311         return ret;
4312 }
4313
4314 /**
4315  * pm80xx_chip_ssp_io_req - send a SSP task to FW
4316  * @pm8001_ha: our hba card information.
4317  * @ccb: the ccb information this request used.
4318  */
4319 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4320         struct pm8001_ccb_info *ccb)
4321 {
4322         struct sas_task *task = ccb->task;
4323         struct domain_device *dev = task->dev;
4324         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4325         struct ssp_ini_io_start_req ssp_cmd;
4326         u32 tag = ccb->ccb_tag;
4327         int ret;
4328         u64 phys_addr, end_addr;
4329         u32 end_addr_high, end_addr_low;
4330         struct inbound_queue_table *circularQ;
4331         u32 q_index, cpu_id;
4332         u32 opc = OPC_INB_SSPINIIOSTART;
4333
4334         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4335         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4336
4337         /* data address domain added for spcv; set to 0 by host,
4338          * used internally by controller
4339          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4340          */
4341         ssp_cmd.dad_dir_m_tlr =
4342                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4343         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4344         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4345         ssp_cmd.tag = cpu_to_le32(tag);
4346         if (task->ssp_task.enable_first_burst)
4347                 ssp_cmd.ssp_iu.efb_prio_attr = 0x80;
4348         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4349         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4350         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4351                        task->ssp_task.cmd->cmd_len);
4352         cpu_id = smp_processor_id();
4353         q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4354         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4355
4356         /* Check if encryption is set */
4357         if (pm8001_ha->chip->encrypt &&
4358                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4359                 pm8001_dbg(pm8001_ha, IO,
4360                            "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4361                            task->ssp_task.cmd->cmnd[0]);
4362                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4363                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4364                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4365                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4366
4367                 /* fill in PRD (scatter/gather) table, if any */
4368                 if (task->num_scatter > 1) {
4369                         pm8001_chip_make_sg(task->scatter,
4370                                                 ccb->n_elem, ccb->buf_prd);
4371                         phys_addr = ccb->ccb_dma_handle;
4372                         ssp_cmd.enc_addr_low =
4373                                 cpu_to_le32(lower_32_bits(phys_addr));
4374                         ssp_cmd.enc_addr_high =
4375                                 cpu_to_le32(upper_32_bits(phys_addr));
4376                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4377                 } else if (task->num_scatter == 1) {
4378                         u64 dma_addr = sg_dma_address(task->scatter);
4379
4380                         ssp_cmd.enc_addr_low =
4381                                 cpu_to_le32(lower_32_bits(dma_addr));
4382                         ssp_cmd.enc_addr_high =
4383                                 cpu_to_le32(upper_32_bits(dma_addr));
4384                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4385                         ssp_cmd.enc_esgl = 0;
4386
4387                         /* Check 4G Boundary */
4388                         end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4389                         end_addr_low = lower_32_bits(end_addr);
4390                         end_addr_high = upper_32_bits(end_addr);
4391
4392                         if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4393                                 pm8001_dbg(pm8001_ha, FAIL,
4394                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4395                                            dma_addr,
4396                                            le32_to_cpu(ssp_cmd.enc_len),
4397                                            end_addr_high, end_addr_low);
4398                                 pm8001_chip_make_sg(task->scatter, 1,
4399                                         ccb->buf_prd);
4400                                 phys_addr = ccb->ccb_dma_handle;
4401                                 ssp_cmd.enc_addr_low =
4402                                         cpu_to_le32(lower_32_bits(phys_addr));
4403                                 ssp_cmd.enc_addr_high =
4404                                         cpu_to_le32(upper_32_bits(phys_addr));
4405                                 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4406                         }
4407                 } else if (task->num_scatter == 0) {
4408                         ssp_cmd.enc_addr_low = 0;
4409                         ssp_cmd.enc_addr_high = 0;
4410                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4411                         ssp_cmd.enc_esgl = 0;
4412                 }
4413
4414                 /* XTS mode. All other fields are 0 */
4415                 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4416
4417                 /* set tweak values. Should be the start lba */
4418                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4419                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4420                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4421                                                 (task->ssp_task.cmd->cmnd[5]));
4422         } else {
4423                 pm8001_dbg(pm8001_ha, IO,
4424                            "Sending Normal SAS command 0x%x inb q %x\n",
4425                            task->ssp_task.cmd->cmnd[0], q_index);
4426                 /* fill in PRD (scatter/gather) table, if any */
4427                 if (task->num_scatter > 1) {
4428                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4429                                         ccb->buf_prd);
4430                         phys_addr = ccb->ccb_dma_handle;
4431                         ssp_cmd.addr_low =
4432                                 cpu_to_le32(lower_32_bits(phys_addr));
4433                         ssp_cmd.addr_high =
4434                                 cpu_to_le32(upper_32_bits(phys_addr));
4435                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4436                 } else if (task->num_scatter == 1) {
4437                         u64 dma_addr = sg_dma_address(task->scatter);
4438
4439                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4440                         ssp_cmd.addr_high =
4441                                 cpu_to_le32(upper_32_bits(dma_addr));
4442                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4443                         ssp_cmd.esgl = 0;
4444
4445                         /* Check 4G Boundary */
4446                         end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4447                         end_addr_low = lower_32_bits(end_addr);
4448                         end_addr_high = upper_32_bits(end_addr);
4449                         if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4450                                 pm8001_dbg(pm8001_ha, FAIL,
4451                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4452                                            dma_addr,
4453                                            le32_to_cpu(ssp_cmd.len),
4454                                            end_addr_high, end_addr_low);
4455                                 pm8001_chip_make_sg(task->scatter, 1,
4456                                         ccb->buf_prd);
4457                                 phys_addr = ccb->ccb_dma_handle;
4458                                 ssp_cmd.addr_low =
4459                                         cpu_to_le32(lower_32_bits(phys_addr));
4460                                 ssp_cmd.addr_high =
4461                                         cpu_to_le32(upper_32_bits(phys_addr));
4462                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4463                         }
4464                 } else if (task->num_scatter == 0) {
4465                         ssp_cmd.addr_low = 0;
4466                         ssp_cmd.addr_high = 0;
4467                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4468                         ssp_cmd.esgl = 0;
4469                 }
4470         }
4471         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4472                         &ssp_cmd, sizeof(ssp_cmd), q_index);
4473         return ret;
4474 }
4475
4476 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4477         struct pm8001_ccb_info *ccb)
4478 {
4479         struct sas_task *task = ccb->task;
4480         struct domain_device *dev = task->dev;
4481         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4482         u32 tag = ccb->ccb_tag;
4483         int ret;
4484         u32 q_index, cpu_id;
4485         struct sata_start_req sata_cmd;
4486         u32 hdr_tag, ncg_tag = 0;
4487         u64 phys_addr, end_addr;
4488         u32 end_addr_high, end_addr_low;
4489         u32 ATAP = 0x0;
4490         u32 dir;
4491         struct inbound_queue_table *circularQ;
4492         unsigned long flags;
4493         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4494         memset(&sata_cmd, 0, sizeof(sata_cmd));
4495         cpu_id = smp_processor_id();
4496         q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4497         circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4498
4499         if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4500                 ATAP = 0x04; /* no data*/
4501                 pm8001_dbg(pm8001_ha, IO, "no data\n");
4502         } else if (likely(!task->ata_task.device_control_reg_update)) {
4503                 if (task->ata_task.use_ncq &&
4504                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4505                         ATAP = 0x07; /* FPDMA */
4506                         pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4507                 } else if (task->ata_task.dma_xfer) {
4508                         ATAP = 0x06; /* DMA */
4509                         pm8001_dbg(pm8001_ha, IO, "DMA\n");
4510                 } else {
4511                         ATAP = 0x05; /* PIO*/
4512                         pm8001_dbg(pm8001_ha, IO, "PIO\n");
4513                 }
4514         }
4515         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4516                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4517                 ncg_tag = hdr_tag;
4518         }
4519         dir = data_dir_flags[task->data_dir] << 8;
4520         sata_cmd.tag = cpu_to_le32(tag);
4521         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4522         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4523
4524         sata_cmd.sata_fis = task->ata_task.fis;
4525         if (likely(!task->ata_task.device_control_reg_update))
4526                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4527         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4528
4529         /* Check if encryption is set */
4530         if (pm8001_ha->chip->encrypt &&
4531                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4532                 pm8001_dbg(pm8001_ha, IO,
4533                            "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4534                            sata_cmd.sata_fis.command);
4535                 opc = OPC_INB_SATA_DIF_ENC_IO;
4536
4537                 /* set encryption bit */
4538                 sata_cmd.ncqtag_atap_dir_m_dad =
4539                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4540                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4541                                                         /* dad (bit 0-1) is 0 */
4542                 /* fill in PRD (scatter/gather) table, if any */
4543                 if (task->num_scatter > 1) {
4544                         pm8001_chip_make_sg(task->scatter,
4545                                                 ccb->n_elem, ccb->buf_prd);
4546                         phys_addr = ccb->ccb_dma_handle;
4547                         sata_cmd.enc_addr_low =
4548                                 cpu_to_le32(lower_32_bits(phys_addr));
4549                         sata_cmd.enc_addr_high =
4550                                 cpu_to_le32(upper_32_bits(phys_addr));
4551                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4552                 } else if (task->num_scatter == 1) {
4553                         u64 dma_addr = sg_dma_address(task->scatter);
4554
4555                         sata_cmd.enc_addr_low =
4556                                 cpu_to_le32(lower_32_bits(dma_addr));
4557                         sata_cmd.enc_addr_high =
4558                                 cpu_to_le32(upper_32_bits(dma_addr));
4559                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4560                         sata_cmd.enc_esgl = 0;
4561
4562                         /* Check 4G Boundary */
4563                         end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4564                         end_addr_low = lower_32_bits(end_addr);
4565                         end_addr_high = upper_32_bits(end_addr);
4566                         if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4567                                 pm8001_dbg(pm8001_ha, FAIL,
4568                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4569                                            dma_addr,
4570                                            le32_to_cpu(sata_cmd.enc_len),
4571                                            end_addr_high, end_addr_low);
4572                                 pm8001_chip_make_sg(task->scatter, 1,
4573                                         ccb->buf_prd);
4574                                 phys_addr = ccb->ccb_dma_handle;
4575                                 sata_cmd.enc_addr_low =
4576                                         cpu_to_le32(lower_32_bits(phys_addr));
4577                                 sata_cmd.enc_addr_high =
4578                                         cpu_to_le32(upper_32_bits(phys_addr));
4579                                 sata_cmd.enc_esgl =
4580                                         cpu_to_le32(1 << 31);
4581                         }
4582                 } else if (task->num_scatter == 0) {
4583                         sata_cmd.enc_addr_low = 0;
4584                         sata_cmd.enc_addr_high = 0;
4585                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4586                         sata_cmd.enc_esgl = 0;
4587                 }
4588                 /* XTS mode. All other fields are 0 */
4589                 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4590
4591                 /* set tweak values. Should be the start lba */
4592                 sata_cmd.twk_val0 =
4593                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4594                                         (sata_cmd.sata_fis.lbah << 16) |
4595                                         (sata_cmd.sata_fis.lbam << 8) |
4596                                         (sata_cmd.sata_fis.lbal));
4597                 sata_cmd.twk_val1 =
4598                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4599                                          (sata_cmd.sata_fis.lbam_exp));
4600         } else {
4601                 pm8001_dbg(pm8001_ha, IO,
4602                            "Sending Normal SATA command 0x%x inb %x\n",
4603                            sata_cmd.sata_fis.command, q_index);
4604                 /* dad (bit 0-1) is 0 */
4605                 sata_cmd.ncqtag_atap_dir_m_dad =
4606                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4607                                         ((ATAP & 0x3f) << 10) | dir);
4608
4609                 /* fill in PRD (scatter/gather) table, if any */
4610                 if (task->num_scatter > 1) {
4611                         pm8001_chip_make_sg(task->scatter,
4612                                         ccb->n_elem, ccb->buf_prd);
4613                         phys_addr = ccb->ccb_dma_handle;
4614                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4615                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4616                         sata_cmd.esgl = cpu_to_le32(1U << 31);
4617                 } else if (task->num_scatter == 1) {
4618                         u64 dma_addr = sg_dma_address(task->scatter);
4619
4620                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4621                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4622                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4623                         sata_cmd.esgl = 0;
4624
4625                         /* Check 4G Boundary */
4626                         end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4627                         end_addr_low = lower_32_bits(end_addr);
4628                         end_addr_high = upper_32_bits(end_addr);
4629                         if (end_addr_high != sata_cmd.addr_high) {
4630                                 pm8001_dbg(pm8001_ha, FAIL,
4631                                            "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4632                                            dma_addr,
4633                                            le32_to_cpu(sata_cmd.len),
4634                                            end_addr_high, end_addr_low);
4635                                 pm8001_chip_make_sg(task->scatter, 1,
4636                                         ccb->buf_prd);
4637                                 phys_addr = ccb->ccb_dma_handle;
4638                                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4639                                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4640                                 sata_cmd.esgl = cpu_to_le32(1U << 31);
4641                         }
4642                 } else if (task->num_scatter == 0) {
4643                         sata_cmd.addr_low = 0;
4644                         sata_cmd.addr_high = 0;
4645                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4646                         sata_cmd.esgl = 0;
4647                 }
4648
4649                 /* scsi cdb */
4650                 sata_cmd.atapi_scsi_cdb[0] =
4651                         cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4652                                      (task->ata_task.atapi_packet[1] << 8) |
4653                                      (task->ata_task.atapi_packet[2] << 16) |
4654                                      (task->ata_task.atapi_packet[3] << 24)));
4655                 sata_cmd.atapi_scsi_cdb[1] =
4656                         cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4657                                      (task->ata_task.atapi_packet[5] << 8) |
4658                                      (task->ata_task.atapi_packet[6] << 16) |
4659                                      (task->ata_task.atapi_packet[7] << 24)));
4660                 sata_cmd.atapi_scsi_cdb[2] =
4661                         cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4662                                      (task->ata_task.atapi_packet[9] << 8) |
4663                                      (task->ata_task.atapi_packet[10] << 16) |
4664                                      (task->ata_task.atapi_packet[11] << 24)));
4665                 sata_cmd.atapi_scsi_cdb[3] =
4666                         cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4667                                      (task->ata_task.atapi_packet[13] << 8) |
4668                                      (task->ata_task.atapi_packet[14] << 16) |
4669                                      (task->ata_task.atapi_packet[15] << 24)));
4670         }
4671
4672         /* Check for read log for failed drive and return */
4673         if (sata_cmd.sata_fis.command == 0x2f) {
4674                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4675                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4676                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4677                         struct task_status_struct *ts;
4678
4679                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4680                         ts = &task->task_status;
4681
4682                         spin_lock_irqsave(&task->task_state_lock, flags);
4683                         ts->resp = SAS_TASK_COMPLETE;
4684                         ts->stat = SAS_SAM_STAT_GOOD;
4685                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4686                         task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4687                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4688                         if (unlikely((task->task_state_flags &
4689                                         SAS_TASK_STATE_ABORTED))) {
4690                                 spin_unlock_irqrestore(&task->task_state_lock,
4691                                                         flags);
4692                                 pm8001_dbg(pm8001_ha, FAIL,
4693                                            "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4694                                            task, ts->resp,
4695                                            ts->stat);
4696                                 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4697                                 return 0;
4698                         } else {
4699                                 spin_unlock_irqrestore(&task->task_state_lock,
4700                                                         flags);
4701                                 pm8001_ccb_task_free_done(pm8001_ha, task,
4702                                                                 ccb, tag);
4703                                 atomic_dec(&pm8001_ha_dev->running_req);
4704                                 return 0;
4705                         }
4706                 }
4707         }
4708         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4709                         &sata_cmd, sizeof(sata_cmd), q_index);
4710         return ret;
4711 }
4712
4713 /**
4714  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4715  * @pm8001_ha: our hba card information.
4716  * @phy_id: the phy id which we wanted to start up.
4717  */
4718 static int
4719 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4720 {
4721         struct phy_start_req payload;
4722         struct inbound_queue_table *circularQ;
4723         int ret;
4724         u32 tag = 0x01;
4725         u32 opcode = OPC_INB_PHYSTART;
4726         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4727         memset(&payload, 0, sizeof(payload));
4728         payload.tag = cpu_to_le32(tag);
4729
4730         pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4731
4732         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4733                         LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4734         /* SSC Disable and SAS Analog ST configuration */
4735         /**
4736         payload.ase_sh_lm_slr_phyid =
4737                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4738                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4739                 phy_id);
4740         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4741         **/
4742
4743         payload.sas_identify.dev_type = SAS_END_DEVICE;
4744         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4745         memcpy(payload.sas_identify.sas_addr,
4746                 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4747         payload.sas_identify.phy_id = phy_id;
4748         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4749                         sizeof(payload), 0);
4750         return ret;
4751 }
4752
4753 /**
4754  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4755  * @pm8001_ha: our hba card information.
4756  * @phy_id: the phy id which we wanted to start up.
4757  */
4758 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4759         u8 phy_id)
4760 {
4761         struct phy_stop_req payload;
4762         struct inbound_queue_table *circularQ;
4763         int ret;
4764         u32 tag = 0x01;
4765         u32 opcode = OPC_INB_PHYSTOP;
4766         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4767         memset(&payload, 0, sizeof(payload));
4768         payload.tag = cpu_to_le32(tag);
4769         payload.phy_id = cpu_to_le32(phy_id);
4770         ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4771                         sizeof(payload), 0);
4772         return ret;
4773 }
4774
4775 /*
4776  * see comments on pm8001_mpi_reg_resp.
4777  */
4778 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4779         struct pm8001_device *pm8001_dev, u32 flag)
4780 {
4781         struct reg_dev_req payload;
4782         u32     opc;
4783         u32 stp_sspsmp_sata = 0x4;
4784         struct inbound_queue_table *circularQ;
4785         u32 linkrate, phy_id;
4786         int rc, tag = 0xdeadbeef;
4787         struct pm8001_ccb_info *ccb;
4788         u8 retryFlag = 0x1;
4789         u16 firstBurstSize = 0;
4790         u16 ITNT = 2000;
4791         struct domain_device *dev = pm8001_dev->sas_device;
4792         struct domain_device *parent_dev = dev->parent;
4793         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4794
4795         memset(&payload, 0, sizeof(payload));
4796         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4797         if (rc)
4798                 return rc;
4799         ccb = &pm8001_ha->ccb_info[tag];
4800         ccb->device = pm8001_dev;
4801         ccb->ccb_tag = tag;
4802         payload.tag = cpu_to_le32(tag);
4803
4804         if (flag == 1) {
4805                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4806         } else {
4807                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4808                         stp_sspsmp_sata = 0x00; /* stp*/
4809                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4810                         pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4811                         pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4812                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4813         }
4814         if (parent_dev && dev_is_expander(parent_dev->dev_type))
4815                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4816         else
4817                 phy_id = pm8001_dev->attached_phy;
4818
4819         opc = OPC_INB_REG_DEV;
4820
4821         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4822                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4823
4824         payload.phyid_portid =
4825                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4826                 ((phy_id & 0xFF) << 8));
4827
4828         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4829                 ((linkrate & 0x0F) << 24) |
4830                 ((stp_sspsmp_sata & 0x03) << 28));
4831         payload.firstburstsize_ITNexustimeout =
4832                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4833
4834         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4835                 SAS_ADDR_SIZE);
4836
4837         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4838                         sizeof(payload), 0);
4839         if (rc)
4840                 pm8001_tag_free(pm8001_ha, tag);
4841
4842         return rc;
4843 }
4844
4845 /**
4846  * pm80xx_chip_phy_ctl_req - support the local phy operation
4847  * @pm8001_ha: our hba card information.
4848  * @phyId: the phy id which we wanted to operate
4849  * @phy_op: phy operation to request
4850  */
4851 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4852         u32 phyId, u32 phy_op)
4853 {
4854         u32 tag;
4855         int rc;
4856         struct local_phy_ctl_req payload;
4857         struct inbound_queue_table *circularQ;
4858         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4859         memset(&payload, 0, sizeof(payload));
4860         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4861         if (rc)
4862                 return rc;
4863         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4864         payload.tag = cpu_to_le32(tag);
4865         payload.phyop_phyid =
4866                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4867
4868         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4869                                   sizeof(payload), 0);
4870         if (rc)
4871                 pm8001_tag_free(pm8001_ha, tag);
4872
4873         return rc;
4874 }
4875
4876 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4877 {
4878 #ifdef PM8001_USE_MSIX
4879         return 1;
4880 #else
4881         u32 value;
4882
4883         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4884         if (value)
4885                 return 1;
4886         return 0;
4887 #endif
4888 }
4889
4890 /**
4891  * pm8001_chip_isr - PM8001 isr handler.
4892  * @pm8001_ha: our hba card information.
4893  * @vec: irq number.
4894  */
4895 static irqreturn_t
4896 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4897 {
4898         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4899         pm8001_dbg(pm8001_ha, DEVIO,
4900                    "irq vec %d, ODMR:0x%x\n",
4901                    vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4902         process_oq(pm8001_ha, vec);
4903         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4904         return IRQ_HANDLED;
4905 }
4906
4907 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4908                                     u32 operation, u32 phyid,
4909                                     u32 length, u32 *buf)
4910 {
4911         u32 tag , i, j = 0;
4912         int rc;
4913         struct set_phy_profile_req payload;
4914         struct inbound_queue_table *circularQ;
4915         u32 opc = OPC_INB_SET_PHY_PROFILE;
4916
4917         memset(&payload, 0, sizeof(payload));
4918         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4919         if (rc)
4920                 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4921         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4922         payload.tag = cpu_to_le32(tag);
4923         payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid  & 0xFF));
4924         pm8001_dbg(pm8001_ha, INIT,
4925                    " phy profile command for phy %x ,length is %d\n",
4926                    payload.ppc_phyid, length);
4927         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4928                 payload.reserved[j] =  cpu_to_le32(*((u32 *)buf + i));
4929                 j++;
4930         }
4931         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4932                         sizeof(payload), 0);
4933         if (rc)
4934                 pm8001_tag_free(pm8001_ha, tag);
4935 }
4936
4937 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4938         u32 length, u8 *buf)
4939 {
4940         u32 i;
4941
4942         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4943                 mpi_set_phy_profile_req(pm8001_ha,
4944                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4945                 length = length + PHY_DWORD_LENGTH;
4946         }
4947         pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
4948 }
4949
4950 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4951                 u32 phy, u32 length, u32 *buf)
4952 {
4953         u32 tag, opc;
4954         int rc, i;
4955         struct set_phy_profile_req payload;
4956         struct inbound_queue_table *circularQ;
4957
4958         memset(&payload, 0, sizeof(payload));
4959
4960         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4961         if (rc)
4962                 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
4963
4964         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4965         opc = OPC_INB_SET_PHY_PROFILE;
4966
4967         payload.tag = cpu_to_le32(tag);
4968         payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4969                                 | (phy & 0xFF));
4970
4971         for (i = 0; i < length; i++)
4972                 payload.reserved[i] = cpu_to_le32(*(buf + i));
4973
4974         rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4975                         sizeof(payload), 0);
4976         if (rc)
4977                 pm8001_tag_free(pm8001_ha, tag);
4978
4979         pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
4980 }
4981 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4982         .name                   = "pmc80xx",
4983         .chip_init              = pm80xx_chip_init,
4984         .chip_soft_rst          = pm80xx_chip_soft_rst,
4985         .chip_rst               = pm80xx_hw_chip_rst,
4986         .chip_iounmap           = pm8001_chip_iounmap,
4987         .isr                    = pm80xx_chip_isr,
4988         .is_our_interrupt       = pm80xx_chip_is_our_interrupt,
4989         .isr_process_oq         = process_oq,
4990         .interrupt_enable       = pm80xx_chip_interrupt_enable,
4991         .interrupt_disable      = pm80xx_chip_interrupt_disable,
4992         .make_prd               = pm8001_chip_make_sg,
4993         .smp_req                = pm80xx_chip_smp_req,
4994         .ssp_io_req             = pm80xx_chip_ssp_io_req,
4995         .sata_req               = pm80xx_chip_sata_req,
4996         .phy_start_req          = pm80xx_chip_phy_start_req,
4997         .phy_stop_req           = pm80xx_chip_phy_stop_req,
4998         .reg_dev_req            = pm80xx_chip_reg_dev_req,
4999         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5000         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
5001         .task_abort             = pm8001_chip_abort_task,
5002         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5003         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5004         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5005         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5006         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5007 };