drivers/scsi/pm8001/pm80xx_hwi.c

   1 /*
   2  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions, and the following disclaimer,
  12  * without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  * substantially similar to the "NO WARRANTY" disclaimer below
  15  * ("Disclaimer") and any redistribution must be conditioned upon
  16  * including a substantially similar Disclaimer requirement for further
  17  * binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  * of any contributors may be used to endorse or promote products derived
  20  * from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm80xx_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45 #include "pm80xx_tracepoints.h"
  46
  47 #define SMP_DIRECT 1
  48 #define SMP_INDIRECT 2
  49
  50
  51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
  52 {
  53         u32 reg_val;
  54         unsigned long start;
  55         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
  56         /* confirm the setting is written */
  57         start = jiffies + HZ; /* 1 sec */
  58         do {
  59                 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
  60         } while ((reg_val != shift_value) && time_before(jiffies, start));
  61         if (reg_val != shift_value) {
  62                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
  63                            reg_val);
  64                 return -1;
  65         }
  66         return 0;
  67 }
  68
  69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
  70                                 __le32 *destination,
  71                                 u32 dw_count, u32 bus_base_number)
  72 {
  73         u32 index, value, offset;
  74
  75         for (index = 0; index < dw_count; index += 4, destination++) {
  76                 offset = (soffset + index);
  77                 if (offset < (64 * 1024)) {
  78                         value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
  79                         *destination = cpu_to_le32(value);
  80                 }
  81         }
  82         return;
  83 }
  84
  85 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
  86         struct device_attribute *attr, char *buf)
  87 {
  88         struct Scsi_Host *shost = class_to_shost(cdev);
  89         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  90         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  91         void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
  92         u32 accum_len, reg_val, index, *temp;
  93         u32 status = 1;
  94         unsigned long start;
  95         u8 *direct_data;
  96         char *fatal_error_data = buf;
  97         u32 length_to_read;
  98         u32 offset;
  99
 100         pm8001_ha->forensic_info.data_buf.direct_data = buf;
 101         if (pm8001_ha->chip_id == chip_8001) {
 102                 pm8001_ha->forensic_info.data_buf.direct_data +=
 103                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 104                         "Not supported for SPC controller");
 105                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 106                         (char *)buf;
 107         }
 108         /* initialize variables for very first call from host application */
 109         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 110                 pm8001_dbg(pm8001_ha, IO,
 111                            "forensic_info TYPE_NON_FATAL..............\n");
 112                 direct_data = (u8 *)fatal_error_data;
 113                 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
 114                 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
 115                 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 116                 pm8001_ha->forensic_info.data_buf.read_len = 0;
 117                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 118
 119                 /* Write signature to fatal dump table */
 120                 pm8001_mw32(fatal_table_address,
 121                                 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
 122
 123                 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
 124                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
 125                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
 126                            pm8001_ha->forensic_info.data_buf.read_len);
 127                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
 128                            pm8001_ha->forensic_info.data_buf.direct_len);
 129                 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
 130                            pm8001_ha->forensic_info.data_buf.direct_offset);
 131         }
 132         if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
 133                 /* start to get data */
 134                 /* Program the MEMBASE II Shifting Register with 0x00.*/
 135                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 136                                 pm8001_ha->fatal_forensic_shift_offset);
 137                 pm8001_ha->forensic_last_offset = 0;
 138                 pm8001_ha->forensic_fatal_step = 0;
 139                 pm8001_ha->fatal_bar_loc = 0;
 140         }
 141
 142         /* Read until accum_len is retrieved */
 143         accum_len = pm8001_mr32(fatal_table_address,
 144                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 145         /* Determine length of data between previously stored transfer length
 146          * and current accumulated transfer length
 147          */
 148         length_to_read =
 149                 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
 150         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
 151                    accum_len);
 152         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
 153                    length_to_read);
 154         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
 155                    pm8001_ha->forensic_last_offset);
 156         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
 157                    pm8001_ha->forensic_info.data_buf.read_len);
 158         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
 159                    pm8001_ha->forensic_info.data_buf.direct_len);
 160         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
 161                    pm8001_ha->forensic_info.data_buf.direct_offset);
 162
 163         /* If accumulated length failed to read correctly fail the attempt.*/
 164         if (accum_len == 0xFFFFFFFF) {
 165                 pm8001_dbg(pm8001_ha, IO,
 166                            "Possible PCI issue 0x%x not expected\n",
 167                            accum_len);
 168                 return status;
 169         }
 170         /* If accumulated length is zero fail the attempt */
 171         if (accum_len == 0) {
 172                 pm8001_ha->forensic_info.data_buf.direct_data +=
 173                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 174                         "%08x ", 0xFFFFFFFF);
 175                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 176                         (char *)buf;
 177         }
 178         /* Accumulated length is good so start capturing the first data */
 179         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 180         if (pm8001_ha->forensic_fatal_step == 0) {
 181 moreData:
 182                 /* If data to read is less than SYSFS_OFFSET then reduce the
 183                  * length of dataLen
 184                  */
 185                 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
 186                                 > length_to_read) {
 187                         pm8001_ha->forensic_info.data_buf.direct_len =
 188                                 length_to_read -
 189                                 pm8001_ha->forensic_last_offset;
 190                 } else {
 191                         pm8001_ha->forensic_info.data_buf.direct_len =
 192                                 SYSFS_OFFSET;
 193                 }
 194                 if (pm8001_ha->forensic_info.data_buf.direct_data) {
 195                         /* Data is in bar, copy to host memory */
 196                         pm80xx_pci_mem_copy(pm8001_ha,
 197                         pm8001_ha->fatal_bar_loc,
 198                         pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
 199                         pm8001_ha->forensic_info.data_buf.direct_len, 1);
 200                 }
 201                 pm8001_ha->fatal_bar_loc +=
 202                         pm8001_ha->forensic_info.data_buf.direct_len;
 203                 pm8001_ha->forensic_info.data_buf.direct_offset +=
 204                         pm8001_ha->forensic_info.data_buf.direct_len;
 205                 pm8001_ha->forensic_last_offset +=
 206                         pm8001_ha->forensic_info.data_buf.direct_len;
 207                 pm8001_ha->forensic_info.data_buf.read_len =
 208                         pm8001_ha->forensic_info.data_buf.direct_len;
 209
 210                 if (pm8001_ha->forensic_last_offset  >= length_to_read) {
 211                         pm8001_ha->forensic_info.data_buf.direct_data +=
 212                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 213                                 "%08x ", 3);
 214                         for (index = 0; index <
 215                                 (pm8001_ha->forensic_info.data_buf.direct_len
 216                                  / 4); index++) {
 217                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 218                                 sprintf(
 219                                 pm8001_ha->forensic_info.data_buf.direct_data,
 220                                 "%08x ", *(temp + index));
 221                         }
 222
 223                         pm8001_ha->fatal_bar_loc = 0;
 224                         pm8001_ha->forensic_fatal_step = 1;
 225                         pm8001_ha->fatal_forensic_shift_offset = 0;
 226                         pm8001_ha->forensic_last_offset = 0;
 227                         status = 0;
 228                         offset = (int)
 229                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 230                         - (char *)buf);
 231                         pm8001_dbg(pm8001_ha, IO,
 232                                    "get_fatal_spcv:return1 0x%x\n", offset);
 233                         return (char *)pm8001_ha->
 234                                 forensic_info.data_buf.direct_data -
 235                                 (char *)buf;
 236                 }
 237                 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
 238                         pm8001_ha->forensic_info.data_buf.direct_data +=
 239                                 sprintf(pm8001_ha->
 240                                         forensic_info.data_buf.direct_data,
 241                                         "%08x ", 2);
 242                         for (index = 0; index <
 243                                 (pm8001_ha->forensic_info.data_buf.direct_len
 244                                  / 4); index++) {
 245                                 pm8001_ha->forensic_info.data_buf.direct_data
 246                                         += sprintf(pm8001_ha->
 247                                         forensic_info.data_buf.direct_data,
 248                                         "%08x ", *(temp + index));
 249                         }
 250                         status = 0;
 251                         offset = (int)
 252                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 253                         - (char *)buf);
 254                         pm8001_dbg(pm8001_ha, IO,
 255                                    "get_fatal_spcv:return2 0x%x\n", offset);
 256                         return (char *)pm8001_ha->
 257                                 forensic_info.data_buf.direct_data -
 258                                 (char *)buf;
 259                 }
 260
 261                 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
 262                 pm8001_ha->forensic_info.data_buf.direct_data +=
 263                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 264                                 "%08x ", 2);
 265                 for (index = 0; index <
 266                         (pm8001_ha->forensic_info.data_buf.direct_len
 267                          / 4) ; index++) {
 268                         pm8001_ha->forensic_info.data_buf.direct_data +=
 269                                 sprintf(pm8001_ha->
 270                                 forensic_info.data_buf.direct_data,
 271                                 "%08x ", *(temp + index));
 272                 }
 273                 pm8001_ha->fatal_forensic_shift_offset += 0x100;
 274                 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
 275                         pm8001_ha->fatal_forensic_shift_offset);
 276                 pm8001_ha->fatal_bar_loc = 0;
 277                 status = 0;
 278                 offset = (int)
 279                         ((char *)pm8001_ha->forensic_info.data_buf.direct_data
 280                         - (char *)buf);
 281                 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
 282                            offset);
 283                 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
 284                         (char *)buf;
 285         }
 286         if (pm8001_ha->forensic_fatal_step == 1) {
 287                 /* store previous accumulated length before triggering next
 288                  * accumulated length update
 289                  */
 290                 pm8001_ha->forensic_preserved_accumulated_transfer =
 291                         pm8001_mr32(fatal_table_address,
 292                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 293
 294                 /* continue capturing the fatal log until Dump status is 0x3 */
 295                 if (pm8001_mr32(fatal_table_address,
 296                         MPI_FATAL_EDUMP_TABLE_STATUS) <
 297                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
 298
 299                         /* reset fddstat bit by writing to zero*/
 300                         pm8001_mw32(fatal_table_address,
 301                                         MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
 302
 303                         /* set dump control value to '1' so that new data will
 304                          * be transferred to shared memory
 305                          */
 306                         pm8001_mw32(fatal_table_address,
 307                                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
 308                                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 309
 310                         /*Poll FDDHSHK  until clear */
 311                         start = jiffies + (2 * HZ); /* 2 sec */
 312
 313                         do {
 314                                 reg_val = pm8001_mr32(fatal_table_address,
 315                                         MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
 316                         } while ((reg_val) && time_before(jiffies, start));
 317
 318                         if (reg_val != 0) {
 319                                 pm8001_dbg(pm8001_ha, FAIL,
 320                                            "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
 321                                            reg_val);
 322                                /* Fail the dump if a timeout occurs */
 323                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 324                                 sprintf(
 325                                 pm8001_ha->forensic_info.data_buf.direct_data,
 326                                 "%08x ", 0xFFFFFFFF);
 327                                 return((char *)
 328                                 pm8001_ha->forensic_info.data_buf.direct_data
 329                                 - (char *)buf);
 330                         }
 331                         /* Poll status register until set to 2 or
 332                          * 3 for up to 2 seconds
 333                          */
 334                         start = jiffies + (2 * HZ); /* 2 sec */
 335
 336                         do {
 337                                 reg_val = pm8001_mr32(fatal_table_address,
 338                                         MPI_FATAL_EDUMP_TABLE_STATUS);
 339                         } while (((reg_val != 2) && (reg_val != 3)) &&
 340                                         time_before(jiffies, start));
 341
 342                         if (reg_val < 2) {
 343                                 pm8001_dbg(pm8001_ha, FAIL,
 344                                            "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
 345                                            reg_val);
 346                                 /* Fail the dump if a timeout occurs */
 347                                 pm8001_ha->forensic_info.data_buf.direct_data +=
 348                                 sprintf(
 349                                 pm8001_ha->forensic_info.data_buf.direct_data,
 350                                 "%08x ", 0xFFFFFFFF);
 351                                 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
 352                                                 (char *)buf);
 353                         }
 354         /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
 355                         pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
 356                         pm8001_cw32(pm8001_ha, 0,
 357                                         MEMBASE_II_SHIFT_REGISTER,
 358                                         pm8001_ha->fatal_forensic_shift_offset);
 359                 }
 360                 /* Read the next block of the debug data.*/
 361                 length_to_read = pm8001_mr32(fatal_table_address,
 362                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
 363                 pm8001_ha->forensic_preserved_accumulated_transfer;
 364                 if (length_to_read != 0x0) {
 365                         pm8001_ha->forensic_fatal_step = 0;
 366                         goto moreData;
 367                 } else {
 368                         pm8001_ha->forensic_info.data_buf.direct_data +=
 369                         sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 370                                 "%08x ", 4);
 371                         pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
 372                         pm8001_ha->forensic_info.data_buf.direct_len =  0;
 373                         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
 374                         pm8001_ha->forensic_info.data_buf.read_len = 0;
 375                 }
 376         }
 377         offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
 378                         - (char *)buf);
 379         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
 380         return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
 381                 (char *)buf);
 382 }
 383
 384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
 385  * location by the firmware.
 386  */
 387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
 388         struct device_attribute *attr, char *buf)
 389 {
 390         struct Scsi_Host *shost = class_to_shost(cdev);
 391         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 392         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
 393         void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
 394         u32 accum_len = 0;
 395         u32 total_len = 0;
 396         u32 reg_val = 0;
 397         u32 *temp = NULL;
 398         u32 index = 0;
 399         u32 output_length;
 400         unsigned long start = 0;
 401         char *buf_copy = buf;
 402
 403         temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
 404         if (++pm8001_ha->non_fatal_count == 1) {
 405                 if (pm8001_ha->chip_id == chip_8001) {
 406                         snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
 407                                 PAGE_SIZE, "Not supported for SPC controller");
 408                         return 0;
 409                 }
 410                 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
 411                 /*
 412                  * Step 1: Write the host buffer parameters in the MPI Fatal and
 413                  * Non-Fatal Error Dump Capture Table.This is the buffer
 414                  * where debug data will be DMAed to.
 415                  */
 416                 pm8001_mw32(nonfatal_table_address,
 417                 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
 418                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
 419
 420                 pm8001_mw32(nonfatal_table_address,
 421                 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
 422                 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
 423
 424                 pm8001_mw32(nonfatal_table_address,
 425                 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
 426
 427                 /* Optionally, set the DUMPCTRL bit to 1 if the host
 428                  * keeps sending active I/Os while capturing the non-fatal
 429                  * debug data. Otherwise, leave this bit set to zero
 430                  */
 431                 pm8001_mw32(nonfatal_table_address,
 432                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
 433
 434                 /*
 435                  * Step 2: Clear Accumulative Length of Debug Data Transferred
 436                  * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
 437                  * Capture Table to zero.
 438                  */
 439                 pm8001_mw32(nonfatal_table_address,
 440                                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
 441
 442                 /* initiallize previous accumulated length to 0 */
 443                 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
 444                 pm8001_ha->non_fatal_read_length = 0;
 445         }
 446
 447         total_len = pm8001_mr32(nonfatal_table_address,
 448                         MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
 449         /*
 450          * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
 451          * field and then request that the SPCv controller transfer the debug
 452          * data by setting bit 7 of the Inbound Doorbell Set Register.
 453          */
 454         pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
 455         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
 456                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
 457
 458         /*
 459          * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
 460          * 2 seconds) until register bit 7 is cleared.
 461          * This step only indicates the request is accepted by the controller.
 462          */
 463         start = jiffies + (2 * HZ); /* 2 sec */
 464         do {
 465                 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
 466                         SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
 467         } while ((reg_val != 0) && time_before(jiffies, start));
 468
 469         /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
 470          * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
 471          * the MPI Fatal and Non-Fatal Error Dump Capture Table.
 472          */
 473         start = jiffies + (2 * HZ); /* 2 sec */
 474         do {
 475                 reg_val = pm8001_mr32(nonfatal_table_address,
 476                                 MPI_FATAL_EDUMP_TABLE_STATUS);
 477         } while ((!reg_val) && time_before(jiffies, start));
 478
 479         if ((reg_val == 0x00) ||
 480                 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
 481                 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
 482                 pm8001_ha->non_fatal_read_length = 0;
 483                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
 484                 pm8001_ha->non_fatal_count = 0;
 485                 return (buf_copy - buf);
 486         } else if (reg_val ==
 487                         MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
 488                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
 489         } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
 490                 (pm8001_ha->non_fatal_read_length >= total_len)) {
 491                 pm8001_ha->non_fatal_read_length = 0;
 492                 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
 493                 pm8001_ha->non_fatal_count = 0;
 494         }
 495         accum_len = pm8001_mr32(nonfatal_table_address,
 496                         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
 497         output_length = accum_len -
 498                 pm8001_ha->forensic_preserved_accumulated_transfer;
 499
 500         for (index = 0; index < output_length/4; index++)
 501                 buf_copy += snprintf(buf_copy, PAGE_SIZE,
 502                                 "%08x ", *(temp+index));
 503
 504         pm8001_ha->non_fatal_read_length += output_length;
 505
 506         /* store current accumulated length to use in next iteration as
 507          * the previous accumulated length
 508          */
 509         pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
 510         return (buf_copy - buf);
 511 }
 512
 513 /**
 514  * read_main_config_table - read the configure table and save it.
 515  * @pm8001_ha: our hba card information
 516  */
 517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
 518 {
 519         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 520
 521         pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
 522                 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
 523         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
 524                 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
 525         pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
 526                 pm8001_mr32(address, MAIN_FW_REVISION);
 527         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
 528                 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
 529         pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl      =
 530                 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
 531         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
 532                 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
 533         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
 534                 pm8001_mr32(address, MAIN_GST_OFFSET);
 535         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
 536                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
 537         pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
 538                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
 539
 540         /* read Error Dump Offset and Length */
 541         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
 542                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
 543         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
 544                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
 545         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
 546                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
 547         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
 548                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
 549
 550         /* read GPIO LED settings from the configuration table */
 551         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
 552                 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
 553
 554         /* read analog Setting offset from the configuration table */
 555         pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
 556                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
 557
 558         pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
 559                 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
 560         pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
 561                 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
 562         /* read port recover and reset timeout */
 563         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
 564                 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
 565         /* read ILA and inactive firmware version */
 566         pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
 567                 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
 568         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
 569                 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
 570
 571         pm8001_dbg(pm8001_ha, DEV,
 572                    "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
 573                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
 574                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
 575                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
 576
 577         pm8001_dbg(pm8001_ha, DEV,
 578                    "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
 579                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
 580                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
 581                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
 582                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
 583                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
 584
 585         pm8001_dbg(pm8001_ha, DEV,
 586                    "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
 587                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
 588                    pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
 589 }
 590
 591 /**
 592  * read_general_status_table - read the general status table and save it.
 593  * @pm8001_ha: our hba card information
 594  */
 595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
 596 {
 597         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
 598         pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
 599                         pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
 600         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
 601                         pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
 602         pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
 603                         pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
 604         pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt          =
 605                         pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
 606         pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt           =
 607                         pm8001_mr32(address, GST_IOPTCNT_OFFSET);
 608         pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val     =
 609                         pm8001_mr32(address, GST_GPIO_INPUT_VAL);
 610         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
 611                         pm8001_mr32(address, GST_RERRINFO_OFFSET0);
 612         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
 613                         pm8001_mr32(address, GST_RERRINFO_OFFSET1);
 614         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
 615                         pm8001_mr32(address, GST_RERRINFO_OFFSET2);
 616         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
 617                         pm8001_mr32(address, GST_RERRINFO_OFFSET3);
 618         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
 619                         pm8001_mr32(address, GST_RERRINFO_OFFSET4);
 620         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
 621                         pm8001_mr32(address, GST_RERRINFO_OFFSET5);
 622         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
 623                         pm8001_mr32(address, GST_RERRINFO_OFFSET6);
 624         pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
 625                          pm8001_mr32(address, GST_RERRINFO_OFFSET7);
 626 }
 627 /**
 628  * read_phy_attr_table - read the phy attribute table and save it.
 629  * @pm8001_ha: our hba card information
 630  */
 631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
 632 {
 633         void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
 634         pm8001_ha->phy_attr_table.phystart1_16[0] =
 635                         pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
 636         pm8001_ha->phy_attr_table.phystart1_16[1] =
 637                         pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
 638         pm8001_ha->phy_attr_table.phystart1_16[2] =
 639                         pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
 640         pm8001_ha->phy_attr_table.phystart1_16[3] =
 641                         pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
 642         pm8001_ha->phy_attr_table.phystart1_16[4] =
 643                         pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
 644         pm8001_ha->phy_attr_table.phystart1_16[5] =
 645                         pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
 646         pm8001_ha->phy_attr_table.phystart1_16[6] =
 647                         pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
 648         pm8001_ha->phy_attr_table.phystart1_16[7] =
 649                         pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
 650         pm8001_ha->phy_attr_table.phystart1_16[8] =
 651                         pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
 652         pm8001_ha->phy_attr_table.phystart1_16[9] =
 653                         pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
 654         pm8001_ha->phy_attr_table.phystart1_16[10] =
 655                         pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
 656         pm8001_ha->phy_attr_table.phystart1_16[11] =
 657                         pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
 658         pm8001_ha->phy_attr_table.phystart1_16[12] =
 659                         pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
 660         pm8001_ha->phy_attr_table.phystart1_16[13] =
 661                         pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
 662         pm8001_ha->phy_attr_table.phystart1_16[14] =
 663                         pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
 664         pm8001_ha->phy_attr_table.phystart1_16[15] =
 665                         pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
 666
 667         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
 668                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
 669         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
 670                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
 671         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
 672                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
 673         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
 674                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
 675         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
 676                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
 677         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
 678                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
 679         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
 680                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
 681         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
 682                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
 683         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
 684                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
 685         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
 686                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
 687         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
 688                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
 689         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
 690                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
 691         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
 692                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
 693         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
 694                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
 695         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
 696                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
 697         pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
 698                         pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
 699
 700 }
 701
 702 /**
 703  * read_inbnd_queue_table - read the inbound queue table and save it.
 704  * @pm8001_ha: our hba card information
 705  */
 706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 707 {
 708         int i;
 709         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 710         for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 711                 u32 offset = i * 0x20;
 712                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 713                         get_pci_bar_index(pm8001_mr32(address,
 714                                 (offset + IB_PIPCI_BAR)));
 715                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 716                         pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
 717         }
 718 }
 719
 720 /**
 721  * read_outbnd_queue_table - read the outbound queue table and save it.
 722  * @pm8001_ha: our hba card information
 723  */
 724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 725 {
 726         int i;
 727         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 728         for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 729                 u32 offset = i * 0x24;
 730                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 731                         get_pci_bar_index(pm8001_mr32(address,
 732                                 (offset + OB_CIPCI_BAR)));
 733                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 734                         pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
 735         }
 736 }
 737
 738 /**
 739  * init_default_table_values - init the default table.
 740  * @pm8001_ha: our hba card information
 741  */
 742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 743 {
 744         int i;
 745         u32 offsetib, offsetob;
 746         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 747         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 748         u32 ib_offset = pm8001_ha->ib_offset;
 749         u32 ob_offset = pm8001_ha->ob_offset;
 750         u32 ci_offset = pm8001_ha->ci_offset;
 751         u32 pi_offset = pm8001_ha->pi_offset;
 752
 753         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr         =
 754                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 755         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr         =
 756                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 757         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size               =
 758                                                         PM8001_EVENT_LOG_SIZE;
 759         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity           = 0x01;
 760         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr     =
 761                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 762         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr     =
 763                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 764         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size           =
 765                                                         PM8001_EVENT_LOG_SIZE;
 766         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       = 0x01;
 767         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
 768
 769         /* Enable higher IQs and OQs, 32 to 63, bit 16 */
 770         if (pm8001_ha->max_q_num > 32)
 771                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 772                                                         1 << 16;
 773         /* Disable end to end CRC checking */
 774         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
 775
 776         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 777                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 778                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 779                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 780                         pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
 781                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 782                 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
 783                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 784                   (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
 785                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 786                         pm8001_ha->memoryMap.region[ib_offset + i].total_len;
 787                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 788                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
 789                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 790                         pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
 791                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 792                         pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
 793                 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
 794                 offsetib = i * 0x20;
 795                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 796                         get_pci_bar_index(pm8001_mr32(addressib,
 797                                 (offsetib + 0x14)));
 798                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 799                         pm8001_mr32(addressib, (offsetib + 0x18));
 800                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 801                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 802
 803                 pm8001_dbg(pm8001_ha, DEV,
 804                            "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
 805                            pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
 806                            pm8001_ha->inbnd_q_tbl[i].pi_offset);
 807         }
 808         for (i = 0; i < pm8001_ha->max_q_num; i++) {
 809                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 810                         PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 811                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 812                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
 813                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 814                         pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
 815                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 816                   (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
 817                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 818                         pm8001_ha->memoryMap.region[ob_offset + i].total_len;
 819                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 820                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
 821                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 822                         pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
 823                 /* interrupt vector based on oq */
 824                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
 825                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 826                         pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
 827                 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
 828                 offsetob = i * 0x24;
 829                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 830                         get_pci_bar_index(pm8001_mr32(addressob,
 831                         offsetob + 0x14));
 832                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 833                         pm8001_mr32(addressob, (offsetob + 0x18));
 834                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 835                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 836
 837                 pm8001_dbg(pm8001_ha, DEV,
 838                            "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
 839                            pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
 840                            pm8001_ha->outbnd_q_tbl[i].ci_offset);
 841         }
 842 }
 843
 844 /**
 845  * update_main_config_table - update the main default table to the HBA.
 846  * @pm8001_ha: our hba card information
 847  */
 848 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 849 {
 850         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 851         pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
 852                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
 853         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
 854                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
 855         pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
 856                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
 857         pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
 858                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
 859         pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
 860                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
 861         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
 862                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
 863         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
 864                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
 865         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
 866                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
 867         pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
 868                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
 869         /* Update Fatal error interrupt vector */
 870         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
 871                                         ((pm8001_ha->max_q_num - 1) << 8);
 872         pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
 873                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
 874         pm8001_dbg(pm8001_ha, DEV,
 875                    "Updated Fatal error interrupt vector 0x%x\n",
 876                    pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
 877
 878         pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
 879                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
 880
 881         /* SPCv specific */
 882         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
 883         /* Set GPIOLED to 0x2 for LED indicator */
 884         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
 885         pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
 886                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
 887         pm8001_dbg(pm8001_ha, DEV,
 888                    "Programming DW 0x21 in main cfg table with 0x%x\n",
 889                    pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
 890
 891         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 892                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 893         pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
 894                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
 895
 896         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
 897         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 898                                                         PORT_RECOVERY_TIMEOUT;
 899         if (pm8001_ha->chip_id == chip_8006) {
 900                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
 901                                         0x0000ffff;
 902                 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
 903                                         CHIP_8006_PORT_RECOVERY_TIMEOUT;
 904         }
 905         pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
 906                         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
 907 }
 908
 909 /**
 910  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 911  * @pm8001_ha: our hba card information
 912  * @number: entry in the queue
 913  */
 914 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 915                                          int number)
 916 {
 917         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 918         u16 offset = number * 0x20;
 919         pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
 920                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 921         pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
 922                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 923         pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
 924                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 925         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
 926                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 927         pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
 928                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 929
 930         pm8001_dbg(pm8001_ha, DEV,
 931                    "IQ %d: Element pri size 0x%x\n",
 932                    number,
 933                    pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 934
 935         pm8001_dbg(pm8001_ha, DEV,
 936                    "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
 937                    pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
 938                    pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 939
 940         pm8001_dbg(pm8001_ha, DEV,
 941                    "CI upper base addr 0x%x CI lower base addr 0x%x\n",
 942                    pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
 943                    pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 944 }
 945
 946 /**
 947  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 948  * @pm8001_ha: our hba card information
 949  * @number: entry in the queue
 950  */
 951 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 952                                                  int number)
 953 {
 954         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 955         u16 offset = number * 0x24;
 956         pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
 957                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 958         pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
 959                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 960         pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
 961                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 962         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
 963                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 964         pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
 965                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 966         pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
 967                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 968
 969         pm8001_dbg(pm8001_ha, DEV,
 970                    "OQ %d: Element pri size 0x%x\n",
 971                    number,
 972                    pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 973
 974         pm8001_dbg(pm8001_ha, DEV,
 975                    "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
 976                    pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
 977                    pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 978
 979         pm8001_dbg(pm8001_ha, DEV,
 980                    "PI upper base addr 0x%x PI lower base addr 0x%x\n",
 981                    pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
 982                    pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 983 }
 984
 985 /**
 986  * mpi_init_check - check firmware initialization status.
 987  * @pm8001_ha: our hba card information
 988  */
 989 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 990 {
 991         u32 max_wait_count;
 992         u32 value;
 993         u32 gst_len_mpistate;
 994
 995         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 996         table is updated */
 997         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
 998         /* wait until Inbound DoorBell Clear Register toggled */
 999         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1000                 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1001         } else {
1002                 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1003         }
1004         do {
1005                 msleep(FW_READY_INTERVAL);
1006                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1007                 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1008         } while ((value != 0) && (--max_wait_count));
1009
1010         if (!max_wait_count) {
1011                 /* additional check */
1012                 pm8001_dbg(pm8001_ha, FAIL,
1013                            "Inb doorbell clear not toggled[value:%x]\n",
1014                            value);
1015                 return -EBUSY;
1016         }
1017         /* check the MPI-State for initialization up to 100ms*/
1018         max_wait_count = 5;/* 100 msec */
1019         do {
1020                 msleep(FW_READY_INTERVAL);
1021                 gst_len_mpistate =
1022                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1023                                         GST_GSTLEN_MPIS_OFFSET);
1024         } while ((GST_MPI_STATE_INIT !=
1025                 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1026         if (!max_wait_count)
1027                 return -EBUSY;
1028
1029         /* check MPI Initialization error */
1030         gst_len_mpistate = gst_len_mpistate >> 16;
1031         if (0x0000 != gst_len_mpistate)
1032                 return -EBUSY;
1033
1034         /*
1035          *  As per controller datasheet, after successful MPI
1036          *  initialization minimum 500ms delay is required before
1037          *  issuing commands.
1038          */
1039         msleep(500);
1040
1041         return 0;
1042 }
1043
1044 /**
1045  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1046  * This function sleeps hence it must not be used in atomic context.
1047  * @pm8001_ha: our hba card information
1048  */
1049 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1050 {
1051         u32 value;
1052         u32 max_wait_count;
1053         u32 max_wait_time;
1054         u32 expected_mask;
1055         int ret = 0;
1056
1057         /* reset / PCIe ready */
1058         max_wait_time = max_wait_count = 5;     /* 100 milli sec */
1059         do {
1060                 msleep(FW_READY_INTERVAL);
1061                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1062         } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1063
1064         /* check ila, RAAE and iops status */
1065         if ((pm8001_ha->chip_id != chip_8008) &&
1066                         (pm8001_ha->chip_id != chip_8009)) {
1067                 max_wait_time = max_wait_count = 180;   /* 3600 milli sec */
1068                 expected_mask = SCRATCH_PAD_ILA_READY |
1069                         SCRATCH_PAD_RAAE_READY |
1070                         SCRATCH_PAD_IOP0_READY |
1071                         SCRATCH_PAD_IOP1_READY;
1072         } else {
1073                 max_wait_time = max_wait_count = 170;   /* 3400 milli sec */
1074                 expected_mask = SCRATCH_PAD_ILA_READY |
1075                         SCRATCH_PAD_RAAE_READY |
1076                         SCRATCH_PAD_IOP0_READY;
1077         }
1078         do {
1079                 msleep(FW_READY_INTERVAL);
1080                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1081         } while (((value & expected_mask) !=
1082                                  expected_mask) && (--max_wait_count));
1083         if (!max_wait_count) {
1084                 pm8001_dbg(pm8001_ha, INIT,
1085                 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1086                         max_wait_time * FW_READY_INTERVAL, value);
1087                 ret = -1;
1088         } else {
1089                 pm8001_dbg(pm8001_ha, MSG,
1090                         "All FW components ready by %d ms\n",
1091                         (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1092         }
1093         return ret;
1094 }
1095
1096 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1097 {
1098         void __iomem *base_addr;
1099         u32     value;
1100         u32     offset;
1101         u32     pcibar;
1102         u32     pcilogic;
1103
1104         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1105
1106         /*
1107          * lower 26 bits of SCRATCHPAD0 register describes offset within the
1108          * PCIe BAR where the MPI configuration table is present
1109          */
1110         offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1111
1112         pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1113                    offset, value);
1114         /*
1115          * Upper 6 bits describe the offset within PCI config space where BAR
1116          * is located.
1117          */
1118         pcilogic = (value & 0xFC000000) >> 26;
1119         pcibar = get_pci_bar_index(pcilogic);
1120         pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1121
1122         /*
1123          * Make sure the offset falls inside the ioremapped PCI BAR
1124          */
1125         if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1126                 pm8001_dbg(pm8001_ha, FAIL,
1127                         "Main cfg tbl offset outside %u > %u\n",
1128                                 offset, pm8001_ha->io_mem[pcibar].memsize);
1129                 return -EBUSY;
1130         }
1131         pm8001_ha->main_cfg_tbl_addr = base_addr =
1132                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1133
1134         /*
1135          * Validate main configuration table address: first DWord should read
1136          * "PMCS"
1137          */
1138         value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1139         if (memcmp(&value, "PMCS", 4) != 0) {
1140                 pm8001_dbg(pm8001_ha, FAIL,
1141                         "BAD main config signature 0x%x\n",
1142                                 value);
1143                 return -EBUSY;
1144         }
1145         pm8001_dbg(pm8001_ha, INIT,
1146                         "VALID main config signature 0x%x\n", value);
1147         pm8001_ha->general_stat_tbl_addr =
1148                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1149                                         0xFFFFFF);
1150         pm8001_ha->inbnd_q_tbl_addr =
1151                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1152                                         0xFFFFFF);
1153         pm8001_ha->outbnd_q_tbl_addr =
1154                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1155                                         0xFFFFFF);
1156         pm8001_ha->ivt_tbl_addr =
1157                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1158                                         0xFFFFFF);
1159         pm8001_ha->pspa_q_tbl_addr =
1160                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1161                                         0xFFFFFF);
1162         pm8001_ha->fatal_tbl_addr =
1163                 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1164                                         0xFFFFFF);
1165
1166         pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1167                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1168         pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1169                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1170         pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1171                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1172         pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1173                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1174         pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1175                    pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1176         pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1177                    pm8001_ha->main_cfg_tbl_addr,
1178                    pm8001_ha->general_stat_tbl_addr);
1179         pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1180                    pm8001_ha->inbnd_q_tbl_addr,
1181                    pm8001_ha->outbnd_q_tbl_addr);
1182         pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1183                    pm8001_ha->pspa_q_tbl_addr,
1184                    pm8001_ha->ivt_tbl_addr);
1185         return 0;
1186 }
1187
1188 /**
1189  * pm80xx_set_thermal_config - support the thermal configuration
1190  * @pm8001_ha: our hba card information.
1191  */
1192 int
1193 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1194 {
1195         struct set_ctrl_cfg_req payload;
1196         int rc;
1197         u32 tag;
1198         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1199         u32 page_code;
1200
1201         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1202         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1203         if (rc)
1204                 return rc;
1205
1206         payload.tag = cpu_to_le32(tag);
1207
1208         if (IS_SPCV_12G(pm8001_ha->pdev))
1209                 page_code = THERMAL_PAGE_CODE_7H;
1210         else
1211                 page_code = THERMAL_PAGE_CODE_8H;
1212
1213         payload.cfg_pg[0] =
1214                 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1215                             (THERMAL_ENABLE << 8) | page_code);
1216         payload.cfg_pg[1] =
1217                 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1218
1219         pm8001_dbg(pm8001_ha, DEV,
1220                    "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1221                    payload.cfg_pg[0], payload.cfg_pg[1]);
1222
1223         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1224                         sizeof(payload), 0);
1225         if (rc)
1226                 pm8001_tag_free(pm8001_ha, tag);
1227         return rc;
1228
1229 }
1230
1231 /**
1232 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1233 * Timer configuration page
1234 * @pm8001_ha: our hba card information.
1235 */
1236 static int
1237 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1238 {
1239         struct set_ctrl_cfg_req payload;
1240         SASProtocolTimerConfig_t SASConfigPage;
1241         int rc;
1242         u32 tag;
1243         u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1244
1245         memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1246         memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1247
1248         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1249         if (rc)
1250                 return rc;
1251
1252         payload.tag = cpu_to_le32(tag);
1253
1254         SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1255         SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1256         SASConfigPage.STP_SSP_MCT_TMO =
1257                 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1258         SASConfigPage.STP_FRM_TMO =
1259                 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1260                             (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1261         SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1262
1263         SASConfigPage.OPNRJT_RTRY_INTVL =
1264                 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1265         SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1266                 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1267         SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1268                 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1269         SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1270
1271         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1272                    le32_to_cpu(SASConfigPage.pageCode));
1273         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI  0x%08x\n",
1274                    le32_to_cpu(SASConfigPage.MST_MSI));
1275         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO  0x%08x\n",
1276                    le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1277         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO  0x%08x\n",
1278                    le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1279         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO  0x%08x\n",
1280                    le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1281         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL  0x%08x\n",
1282                    le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1283         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO  0x%08x\n",
1284                    le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1285         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR  0x%08x\n",
1286                    le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1287         pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP  0x%08x\n",
1288                    le32_to_cpu(SASConfigPage.MAX_AIP));
1289
1290         memcpy(&payload.cfg_pg, &SASConfigPage,
1291                          sizeof(SASProtocolTimerConfig_t));
1292
1293         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1294                         sizeof(payload), 0);
1295         if (rc)
1296                 pm8001_tag_free(pm8001_ha, tag);
1297
1298         return rc;
1299 }
1300
1301 /**
1302  * pm80xx_get_encrypt_info - Check for encryption
1303  * @pm8001_ha: our hba card information.
1304  */
1305 static int
1306 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1307 {
1308         u32 scratch3_value;
1309         int ret = -1;
1310
1311         /* Read encryption status from SCRATCH PAD 3 */
1312         scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1313
1314         if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1315                                         SCRATCH_PAD3_ENC_READY) {
1316                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1317                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1318                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1319                                                 SCRATCH_PAD3_SMF_ENABLED)
1320                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1321                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1322                                                 SCRATCH_PAD3_SMA_ENABLED)
1323                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1324                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1325                                                 SCRATCH_PAD3_SMB_ENABLED)
1326                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1327                 pm8001_ha->encrypt_info.status = 0;
1328                 pm8001_dbg(pm8001_ha, INIT,
1329                            "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1330                            scratch3_value,
1331                            pm8001_ha->encrypt_info.cipher_mode,
1332                            pm8001_ha->encrypt_info.sec_mode,
1333                            pm8001_ha->encrypt_info.status);
1334                 ret = 0;
1335         } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1336                                         SCRATCH_PAD3_ENC_DISABLED) {
1337                 pm8001_dbg(pm8001_ha, INIT,
1338                            "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1339                            scratch3_value);
1340                 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1341                 pm8001_ha->encrypt_info.cipher_mode = 0;
1342                 pm8001_ha->encrypt_info.sec_mode = 0;
1343                 ret = 0;
1344         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1345                                 SCRATCH_PAD3_ENC_DIS_ERR) {
1346                 pm8001_ha->encrypt_info.status =
1347                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1348                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1349                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1350                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1351                                         SCRATCH_PAD3_SMF_ENABLED)
1352                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1353                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1354                                         SCRATCH_PAD3_SMA_ENABLED)
1355                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1356                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1357                                         SCRATCH_PAD3_SMB_ENABLED)
1358                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1359                 pm8001_dbg(pm8001_ha, INIT,
1360                            "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1361                            scratch3_value,
1362                            pm8001_ha->encrypt_info.cipher_mode,
1363                            pm8001_ha->encrypt_info.sec_mode,
1364                            pm8001_ha->encrypt_info.status);
1365         } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1366                                  SCRATCH_PAD3_ENC_ENA_ERR) {
1367
1368                 pm8001_ha->encrypt_info.status =
1369                         (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1370                 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1371                         pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1372                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1373                                         SCRATCH_PAD3_SMF_ENABLED)
1374                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1375                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1376                                         SCRATCH_PAD3_SMA_ENABLED)
1377                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1378                 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1379                                         SCRATCH_PAD3_SMB_ENABLED)
1380                         pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1381
1382                 pm8001_dbg(pm8001_ha, INIT,
1383                            "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1384                            scratch3_value,
1385                            pm8001_ha->encrypt_info.cipher_mode,
1386                            pm8001_ha->encrypt_info.sec_mode,
1387                            pm8001_ha->encrypt_info.status);
1388         }
1389         return ret;
1390 }
1391
1392 /**
1393  * pm80xx_encrypt_update - update flash with encryption information
1394  * @pm8001_ha: our hba card information.
1395  */
1396 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1397 {
1398         struct kek_mgmt_req payload;
1399         int rc;
1400         u32 tag;
1401         u32 opc = OPC_INB_KEK_MANAGEMENT;
1402
1403         memset(&payload, 0, sizeof(struct kek_mgmt_req));
1404         rc = pm8001_tag_alloc(pm8001_ha, &tag);
1405         if (rc)
1406                 return rc;
1407
1408         payload.tag = cpu_to_le32(tag);
1409         /* Currently only one key is used. New KEK index is 1.
1410          * Current KEK index is 1. Store KEK to NVRAM is 1.
1411          */
1412         payload.new_curidx_ksop =
1413                 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1414                              KEK_MGMT_SUBOP_KEYCARDUPDATE));
1415
1416         pm8001_dbg(pm8001_ha, DEV,
1417                    "Saving Encryption info to flash. payload 0x%x\n",
1418                    le32_to_cpu(payload.new_curidx_ksop));
1419
1420         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1421                         sizeof(payload), 0);
1422         if (rc)
1423                 pm8001_tag_free(pm8001_ha, tag);
1424
1425         return rc;
1426 }
1427
1428 /**
1429  * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1430  * @pm8001_ha: our hba card information
1431  */
1432 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1433 {
1434         int ret;
1435         u8 i = 0;
1436
1437         /* check the firmware status */
1438         if (-1 == check_fw_ready(pm8001_ha)) {
1439                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1440                 return -EBUSY;
1441         }
1442
1443         /* Initialize the controller fatal error flag */
1444         pm8001_ha->controller_fatal_error = false;
1445
1446         /* Initialize pci space address eg: mpi offset */
1447         ret = init_pci_device_addresses(pm8001_ha);
1448         if (ret) {
1449                 pm8001_dbg(pm8001_ha, FAIL,
1450                         "Failed to init pci addresses");
1451                 return ret;
1452         }
1453         init_default_table_values(pm8001_ha);
1454         read_main_config_table(pm8001_ha);
1455         read_general_status_table(pm8001_ha);
1456         read_inbnd_queue_table(pm8001_ha);
1457         read_outbnd_queue_table(pm8001_ha);
1458         read_phy_attr_table(pm8001_ha);
1459
1460         /* update main config table ,inbound table and outbound table */
1461         update_main_config_table(pm8001_ha);
1462         for (i = 0; i < pm8001_ha->max_q_num; i++) {
1463                 update_inbnd_queue_table(pm8001_ha, i);
1464                 update_outbnd_queue_table(pm8001_ha, i);
1465         }
1466         /* notify firmware update finished and check initialization status */
1467         if (0 == mpi_init_check(pm8001_ha)) {
1468                 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1469         } else
1470                 return -EBUSY;
1471
1472         /* send SAS protocol timer configuration page to FW */
1473         ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1474
1475         /* Check for encryption */
1476         if (pm8001_ha->chip->encrypt) {
1477                 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1478                 ret = pm80xx_get_encrypt_info(pm8001_ha);
1479                 if (ret == -1) {
1480                         pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1481                         if (pm8001_ha->encrypt_info.status == 0x81) {
1482                                 pm8001_dbg(pm8001_ha, INIT,
1483                                            "Encryption enabled with error.Saving encryption key to flash\n");
1484                                 pm80xx_encrypt_update(pm8001_ha);
1485                         }
1486                 }
1487         }
1488         return 0;
1489 }
1490
1491 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1492 {
1493         u32 max_wait_count;
1494         u32 value;
1495         u32 gst_len_mpistate;
1496         int ret;
1497
1498         ret = init_pci_device_addresses(pm8001_ha);
1499         if (ret) {
1500                 pm8001_dbg(pm8001_ha, FAIL,
1501                         "Failed to init pci addresses");
1502                 return ret;
1503         }
1504
1505         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1506         table is stop */
1507         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1508
1509         /* wait until Inbound DoorBell Clear Register toggled */
1510         if (IS_SPCV_12G(pm8001_ha->pdev)) {
1511                 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1512         } else {
1513                 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1514         }
1515         do {
1516                 msleep(FW_READY_INTERVAL);
1517                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1518                 value &= SPCv_MSGU_CFG_TABLE_RESET;
1519         } while ((value != 0) && (--max_wait_count));
1520
1521         if (!max_wait_count) {
1522                 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1523                 return -1;
1524         }
1525
1526         /* check the MPI-State for termination in progress */
1527         /* wait until Inbound DoorBell Clear Register toggled */
1528         max_wait_count = 100; /* 2 sec for spcv/ve */
1529         do {
1530                 msleep(FW_READY_INTERVAL);
1531                 gst_len_mpistate =
1532                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1533                         GST_GSTLEN_MPIS_OFFSET);
1534                 if (GST_MPI_STATE_UNINIT ==
1535                         (gst_len_mpistate & GST_MPI_STATE_MASK))
1536                         break;
1537         } while (--max_wait_count);
1538         if (!max_wait_count) {
1539                 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1540                            gst_len_mpistate & GST_MPI_STATE_MASK);
1541                 return -1;
1542         }
1543
1544         return 0;
1545 }
1546
1547 /**
1548  * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1549  * @pm8001_ha: our hba card information
1550  *
1551  * Fatal errors are recoverable only after a host reboot.
1552  */
1553 int
1554 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1555 {
1556         int ret = 0;
1557         u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1558                                             MSGU_SCRATCH_PAD_RSVD_0);
1559         u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1560                                             MSGU_SCRATCH_PAD_RSVD_1);
1561         u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1562         u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1563         u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1564
1565         if (pm8001_ha->chip_id != chip_8006 &&
1566                         pm8001_ha->chip_id != chip_8074 &&
1567                         pm8001_ha->chip_id != chip_8076) {
1568                 return 0;
1569         }
1570
1571         if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1572                 pm8001_dbg(pm8001_ha, FAIL,
1573                         "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1574                                 scratch_pad1, scratch_pad2, scratch_pad3,
1575                                 scratch_pad_rsvd0, scratch_pad_rsvd1);
1576                 ret = 1;
1577         }
1578
1579         return ret;
1580 }
1581
1582 /**
1583  * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1584  * FW register status are reset to the originated status.
1585  * @pm8001_ha: our hba card information
1586  */
1587
1588 static int
1589 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1590 {
1591         u32 regval;
1592         u32 bootloader_state;
1593         u32 ibutton0, ibutton1;
1594
1595         /* Process MPI table uninitialization only if FW is ready */
1596         if (!pm8001_ha->controller_fatal_error) {
1597                 /* Check if MPI is in ready state to reset */
1598                 if (mpi_uninit_check(pm8001_ha) != 0) {
1599                         u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1600                         u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1601                         u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1602                         u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1603                         pm8001_dbg(pm8001_ha, FAIL,
1604                                    "MPI state is not ready scratch: %x:%x:%x:%x\n",
1605                                    r0, r1, r2, r3);
1606                         /* if things aren't ready but the bootloader is ok then
1607                          * try the reset anyway.
1608                          */
1609                         if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1610                                 return -1;
1611                 }
1612         }
1613         /* checked for reset register normal state; 0x0 */
1614         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1615         pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1616                    regval);
1617
1618         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1619         msleep(500);
1620
1621         regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1622         pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1623                    regval);
1624
1625         if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1626                         SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1627                 pm8001_dbg(pm8001_ha, MSG,
1628                            " soft reset successful [regval: 0x%x]\n",
1629                            regval);
1630         } else {
1631                 pm8001_dbg(pm8001_ha, MSG,
1632                            " soft reset failed [regval: 0x%x]\n",
1633                            regval);
1634
1635                 /* check bootloader is successfully executed or in HDA mode */
1636                 bootloader_state =
1637                         pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1638                         SCRATCH_PAD1_BOOTSTATE_MASK;
1639
1640                 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1641                         pm8001_dbg(pm8001_ha, MSG,
1642                                    "Bootloader state - HDA mode SEEPROM\n");
1643                 } else if (bootloader_state ==
1644                                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1645                         pm8001_dbg(pm8001_ha, MSG,
1646                                    "Bootloader state - HDA mode Bootstrap Pin\n");
1647                 } else if (bootloader_state ==
1648                                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1649                         pm8001_dbg(pm8001_ha, MSG,
1650                                    "Bootloader state - HDA mode soft reset\n");
1651                 } else if (bootloader_state ==
1652                                         SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1653                         pm8001_dbg(pm8001_ha, MSG,
1654                                    "Bootloader state-HDA mode critical error\n");
1655                 }
1656                 return -EBUSY;
1657         }
1658
1659         /* check the firmware status after reset */
1660         if (-1 == check_fw_ready(pm8001_ha)) {
1661                 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1662                 /* check iButton feature support for motherboard controller */
1663                 if (pm8001_ha->pdev->subsystem_vendor !=
1664                         PCI_VENDOR_ID_ADAPTEC2 &&
1665                         pm8001_ha->pdev->subsystem_vendor !=
1666                         PCI_VENDOR_ID_ATTO &&
1667                         pm8001_ha->pdev->subsystem_vendor != 0) {
1668                         ibutton0 = pm8001_cr32(pm8001_ha, 0,
1669                                                MSGU_SCRATCH_PAD_RSVD_0);
1670                         ibutton1 = pm8001_cr32(pm8001_ha, 0,
1671                                                MSGU_SCRATCH_PAD_RSVD_1);
1672                         if (!ibutton0 && !ibutton1) {
1673                                 pm8001_dbg(pm8001_ha, FAIL,
1674                                            "iButton Feature is not Available!!!\n");
1675                                 return -EBUSY;
1676                         }
1677                         if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1678                                 pm8001_dbg(pm8001_ha, FAIL,
1679                                            "CRC Check for iButton Feature Failed!!!\n");
1680                                 return -EBUSY;
1681                         }
1682                 }
1683         }
1684         pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1685         return 0;
1686 }
1687
1688 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1689 {
1690         u32 i;
1691
1692         pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1693
1694         /* do SPCv chip reset. */
1695         pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1696         pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1697
1698         /* Check this ..whether delay is required or no */
1699         /* delay 10 usec */
1700         udelay(10);
1701
1702         /* wait for 20 msec until the firmware gets reloaded */
1703         i = 20;
1704         do {
1705                 mdelay(1);
1706         } while ((--i) != 0);
1707
1708         pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1709 }
1710
1711 /**
1712  * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1713  * @pm8001_ha: our hba card information
1714  */
1715 static void
1716 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1717 {
1718         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1719         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1720 }
1721
1722 /**
1723  * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1724  * @pm8001_ha: our hba card information
1725  */
1726 static void
1727 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1728 {
1729         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1730 }
1731
1732 /**
1733  * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1734  * @pm8001_ha: our hba card information
1735  * @vec: interrupt number to enable
1736  */
1737 static void
1738 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1739 {
1740 #ifdef PM8001_USE_MSIX
1741         if (vec < 32)
1742                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
1743         else
1744                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
1745                             1U << (vec - 32));
1746         return;
1747 #endif
1748         pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1749
1750 }
1751
1752 /**
1753  * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1754  * @pm8001_ha: our hba card information
1755  * @vec: interrupt number to disable
1756  */
1757 static void
1758 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1759 {
1760 #ifdef PM8001_USE_MSIX
1761         if (vec == 0xFF) {
1762                 /* disable all vectors 0-31, 32-63 */
1763                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
1764                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
1765         } else if (vec < 32)
1766                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
1767         else
1768                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
1769                             1U << (vec - 32));
1770         return;
1771 #endif
1772         pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1773 }
1774
1775 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1776                 struct pm8001_device *pm8001_ha_dev)
1777 {
1778         struct pm8001_ccb_info *ccb;
1779         struct sas_task *task;
1780         struct task_abort_req task_abort;
1781         u32 opc = OPC_INB_SATA_ABORT;
1782         int ret;
1783
1784         pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG;
1785         pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG;
1786
1787         task = sas_alloc_slow_task(GFP_ATOMIC);
1788         if (!task) {
1789                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1790                 return;
1791         }
1792         task->task_done = pm8001_task_done;
1793
1794         ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1795         if (!ccb) {
1796                 sas_free_task(task);
1797                 return;
1798         }
1799
1800         memset(&task_abort, 0, sizeof(task_abort));
1801         task_abort.abort_all = cpu_to_le32(1);
1802         task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1803         task_abort.tag = cpu_to_le32(ccb->ccb_tag);
1804
1805         ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
1806                                    sizeof(task_abort), 0);
1807         pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1808         if (ret) {
1809                 sas_free_task(task);
1810                 pm8001_ccb_free(pm8001_ha, ccb);
1811         }
1812 }
1813
1814 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1815                 struct pm8001_device *pm8001_ha_dev)
1816 {
1817         struct sata_start_req sata_cmd;
1818         int res;
1819         struct pm8001_ccb_info *ccb;
1820         struct sas_task *task = NULL;
1821         struct host_to_dev_fis fis;
1822         struct domain_device *dev;
1823         u32 opc = OPC_INB_SATA_HOST_OPSTART;
1824
1825         task = sas_alloc_slow_task(GFP_ATOMIC);
1826         if (!task) {
1827                 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1828                 return;
1829         }
1830         task->task_done = pm8001_task_done;
1831
1832         /*
1833          * Allocate domain device by ourselves as libsas is not going to
1834          * provide any.
1835          */
1836         dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1837         if (!dev) {
1838                 sas_free_task(task);
1839                 pm8001_dbg(pm8001_ha, FAIL,
1840                            "Domain device cannot be allocated\n");
1841                 return;
1842         }
1843
1844         task->dev = dev;
1845         task->dev->lldd_dev = pm8001_ha_dev;
1846
1847         ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1848         if (!ccb) {
1849                 sas_free_task(task);
1850                 kfree(dev);
1851                 return;
1852         }
1853
1854         pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1855         pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1856
1857         memset(&sata_cmd, 0, sizeof(sata_cmd));
1858
1859         /* construct read log FIS */
1860         memset(&fis, 0, sizeof(struct host_to_dev_fis));
1861         fis.fis_type = 0x27;
1862         fis.flags = 0x80;
1863         fis.command = ATA_CMD_READ_LOG_EXT;
1864         fis.lbal = 0x10;
1865         fis.sector_count = 0x1;
1866
1867         sata_cmd.tag = cpu_to_le32(ccb->ccb_tag);
1868         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1869         sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1870         memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1871
1872         res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
1873                                    sizeof(sata_cmd), 0);
1874         pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1875         if (res) {
1876                 sas_free_task(task);
1877                 pm8001_ccb_free(pm8001_ha, ccb);
1878                 kfree(dev);
1879         }
1880 }
1881
1882 /**
1883  * mpi_ssp_completion - process the event that FW response to the SSP request.
1884  * @pm8001_ha: our hba card information
1885  * @piomb: the message contents of this outbound message.
1886  *
1887  * When FW has completed a ssp request for example a IO request, after it has
1888  * filled the SG data with the data, it will trigger this event representing
1889  * that he has finished the job; please check the corresponding buffer.
1890  * So we will tell the caller who maybe waiting the result to tell upper layer
1891  * that the task has been finished.
1892  */
1893 static void
1894 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1895 {
1896         struct sas_task *t;
1897         struct pm8001_ccb_info *ccb;
1898         unsigned long flags;
1899         u32 status;
1900         u32 param;
1901         u32 tag;
1902         struct ssp_completion_resp *psspPayload;
1903         struct task_status_struct *ts;
1904         struct ssp_response_iu *iu;
1905         struct pm8001_device *pm8001_dev;
1906         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1907         status = le32_to_cpu(psspPayload->status);
1908         tag = le32_to_cpu(psspPayload->tag);
1909         ccb = &pm8001_ha->ccb_info[tag];
1910         if ((status == IO_ABORTED) && ccb->open_retry) {
1911                 /* Being completed by another */
1912                 ccb->open_retry = 0;
1913                 return;
1914         }
1915         pm8001_dev = ccb->device;
1916         param = le32_to_cpu(psspPayload->param);
1917         t = ccb->task;
1918
1919         if (status && status != IO_UNDERFLOW)
1920                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1921         if (unlikely(!t || !t->lldd_task || !t->dev))
1922                 return;
1923         ts = &t->task_status;
1924
1925         pm8001_dbg(pm8001_ha, DEV,
1926                    "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1927
1928         /* Print sas address of IO failed device */
1929         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1930                 (status != IO_UNDERFLOW))
1931                 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1932                            SAS_ADDR(t->dev->sas_addr));
1933
1934         switch (status) {
1935         case IO_SUCCESS:
1936                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1937                            param);
1938                 if (param == 0) {
1939                         ts->resp = SAS_TASK_COMPLETE;
1940                         ts->stat = SAS_SAM_STAT_GOOD;
1941                 } else {
1942                         ts->resp = SAS_TASK_COMPLETE;
1943                         ts->stat = SAS_PROTO_RESPONSE;
1944                         ts->residual = param;
1945                         iu = &psspPayload->ssp_resp_iu;
1946                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1947                 }
1948                 if (pm8001_dev)
1949                         atomic_dec(&pm8001_dev->running_req);
1950                 break;
1951         case IO_ABORTED:
1952                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1953                 ts->resp = SAS_TASK_COMPLETE;
1954                 ts->stat = SAS_ABORTED_TASK;
1955                 if (pm8001_dev)
1956                         atomic_dec(&pm8001_dev->running_req);
1957                 break;
1958         case IO_UNDERFLOW:
1959                 /* SSP Completion with error */
1960                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1961                            param);
1962                 ts->resp = SAS_TASK_COMPLETE;
1963                 ts->stat = SAS_DATA_UNDERRUN;
1964                 ts->residual = param;
1965                 if (pm8001_dev)
1966                         atomic_dec(&pm8001_dev->running_req);
1967                 break;
1968         case IO_NO_DEVICE:
1969                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1970                 ts->resp = SAS_TASK_UNDELIVERED;
1971                 ts->stat = SAS_PHY_DOWN;
1972                 if (pm8001_dev)
1973                         atomic_dec(&pm8001_dev->running_req);
1974                 break;
1975         case IO_XFER_ERROR_BREAK:
1976                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1977                 ts->resp = SAS_TASK_COMPLETE;
1978                 ts->stat = SAS_OPEN_REJECT;
1979                 /* Force the midlayer to retry */
1980                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1981                 if (pm8001_dev)
1982                         atomic_dec(&pm8001_dev->running_req);
1983                 break;
1984         case IO_XFER_ERROR_PHY_NOT_READY:
1985                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1986                 ts->resp = SAS_TASK_COMPLETE;
1987                 ts->stat = SAS_OPEN_REJECT;
1988                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1989                 if (pm8001_dev)
1990                         atomic_dec(&pm8001_dev->running_req);
1991                 break;
1992         case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1993                 pm8001_dbg(pm8001_ha, IO,
1994                            "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
1995                 ts->resp = SAS_TASK_COMPLETE;
1996                 ts->stat = SAS_OPEN_REJECT;
1997                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1998                 if (pm8001_dev)
1999                         atomic_dec(&pm8001_dev->running_req);
2000                 break;
2001         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2002                 pm8001_dbg(pm8001_ha, IO,
2003                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2004                 ts->resp = SAS_TASK_COMPLETE;
2005                 ts->stat = SAS_OPEN_REJECT;
2006                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2007                 if (pm8001_dev)
2008                         atomic_dec(&pm8001_dev->running_req);
2009                 break;
2010         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2011                 pm8001_dbg(pm8001_ha, IO,
2012                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2013                 ts->resp = SAS_TASK_COMPLETE;
2014                 ts->stat = SAS_OPEN_REJECT;
2015                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2016                 if (pm8001_dev)
2017                         atomic_dec(&pm8001_dev->running_req);
2018                 break;
2019         case IO_OPEN_CNX_ERROR_BREAK:
2020                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2021                 ts->resp = SAS_TASK_COMPLETE;
2022                 ts->stat = SAS_OPEN_REJECT;
2023                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2024                 if (pm8001_dev)
2025                         atomic_dec(&pm8001_dev->running_req);
2026                 break;
2027         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2028         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2029         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2030         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2031         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2032         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2033                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2034                 ts->resp = SAS_TASK_COMPLETE;
2035                 ts->stat = SAS_OPEN_REJECT;
2036                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2037                 if (!t->uldd_task)
2038                         pm8001_handle_event(pm8001_ha,
2039                                 pm8001_dev,
2040                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2041                 break;
2042         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2043                 pm8001_dbg(pm8001_ha, IO,
2044                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2045                 ts->resp = SAS_TASK_COMPLETE;
2046                 ts->stat = SAS_OPEN_REJECT;
2047                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2048                 if (pm8001_dev)
2049                         atomic_dec(&pm8001_dev->running_req);
2050                 break;
2051         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2052                 pm8001_dbg(pm8001_ha, IO,
2053                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2054                 ts->resp = SAS_TASK_COMPLETE;
2055                 ts->stat = SAS_OPEN_REJECT;
2056                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2057                 if (pm8001_dev)
2058                         atomic_dec(&pm8001_dev->running_req);
2059                 break;
2060         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2061                 pm8001_dbg(pm8001_ha, IO,
2062                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2063                 ts->resp = SAS_TASK_UNDELIVERED;
2064                 ts->stat = SAS_OPEN_REJECT;
2065                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2066                 if (pm8001_dev)
2067                         atomic_dec(&pm8001_dev->running_req);
2068                 break;
2069         case IO_XFER_ERROR_NAK_RECEIVED:
2070                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2071                 ts->resp = SAS_TASK_COMPLETE;
2072                 ts->stat = SAS_OPEN_REJECT;
2073                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2074                 if (pm8001_dev)
2075                         atomic_dec(&pm8001_dev->running_req);
2076                 break;
2077         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2078                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2079                 ts->resp = SAS_TASK_COMPLETE;
2080                 ts->stat = SAS_NAK_R_ERR;
2081                 if (pm8001_dev)
2082                         atomic_dec(&pm8001_dev->running_req);
2083                 break;
2084         case IO_XFER_ERROR_DMA:
2085                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2086                 ts->resp = SAS_TASK_COMPLETE;
2087                 ts->stat = SAS_OPEN_REJECT;
2088                 if (pm8001_dev)
2089                         atomic_dec(&pm8001_dev->running_req);
2090                 break;
2091         case IO_XFER_OPEN_RETRY_TIMEOUT:
2092                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2093                 ts->resp = SAS_TASK_COMPLETE;
2094                 ts->stat = SAS_OPEN_REJECT;
2095                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2096                 if (pm8001_dev)
2097                         atomic_dec(&pm8001_dev->running_req);
2098                 break;
2099         case IO_XFER_ERROR_OFFSET_MISMATCH:
2100                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2101                 ts->resp = SAS_TASK_COMPLETE;
2102                 ts->stat = SAS_OPEN_REJECT;
2103                 if (pm8001_dev)
2104                         atomic_dec(&pm8001_dev->running_req);
2105                 break;
2106         case IO_PORT_IN_RESET:
2107                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2108                 ts->resp = SAS_TASK_COMPLETE;
2109                 ts->stat = SAS_OPEN_REJECT;
2110                 if (pm8001_dev)
2111                         atomic_dec(&pm8001_dev->running_req);
2112                 break;
2113         case IO_DS_NON_OPERATIONAL:
2114                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2115                 ts->resp = SAS_TASK_COMPLETE;
2116                 ts->stat = SAS_OPEN_REJECT;
2117                 if (!t->uldd_task)
2118                         pm8001_handle_event(pm8001_ha,
2119                                 pm8001_dev,
2120                                 IO_DS_NON_OPERATIONAL);
2121                 break;
2122         case IO_DS_IN_RECOVERY:
2123                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2124                 ts->resp = SAS_TASK_COMPLETE;
2125                 ts->stat = SAS_OPEN_REJECT;
2126                 if (pm8001_dev)
2127                         atomic_dec(&pm8001_dev->running_req);
2128                 break;
2129         case IO_TM_TAG_NOT_FOUND:
2130                 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2131                 ts->resp = SAS_TASK_COMPLETE;
2132                 ts->stat = SAS_OPEN_REJECT;
2133                 if (pm8001_dev)
2134                         atomic_dec(&pm8001_dev->running_req);
2135                 break;
2136         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2137                 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2138                 ts->resp = SAS_TASK_COMPLETE;
2139                 ts->stat = SAS_OPEN_REJECT;
2140                 if (pm8001_dev)
2141                         atomic_dec(&pm8001_dev->running_req);
2142                 break;
2143         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2144                 pm8001_dbg(pm8001_ha, IO,
2145                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2146                 ts->resp = SAS_TASK_COMPLETE;
2147                 ts->stat = SAS_OPEN_REJECT;
2148                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2149                 if (pm8001_dev)
2150                         atomic_dec(&pm8001_dev->running_req);
2151                 break;
2152         default:
2153                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2154                 /* not allowed case. Therefore, return failed status */
2155                 ts->resp = SAS_TASK_COMPLETE;
2156                 ts->stat = SAS_OPEN_REJECT;
2157                 if (pm8001_dev)
2158                         atomic_dec(&pm8001_dev->running_req);
2159                 break;
2160         }
2161         pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2162                    psspPayload->ssp_resp_iu.status);
2163         spin_lock_irqsave(&t->task_state_lock, flags);
2164         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2165         t->task_state_flags |= SAS_TASK_STATE_DONE;
2166         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2167                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2168                 pm8001_dbg(pm8001_ha, FAIL,
2169                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2170                            t, status, ts->resp, ts->stat);
2171                 pm8001_ccb_task_free(pm8001_ha, ccb);
2172                 if (t->slow_task)
2173                         complete(&t->slow_task->completion);
2174         } else {
2175                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2176                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2177         }
2178 }
2179
2180 /*See the comments for mpi_ssp_completion */
2181 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2182 {
2183         struct sas_task *t;
2184         unsigned long flags;
2185         struct task_status_struct *ts;
2186         struct pm8001_ccb_info *ccb;
2187         struct pm8001_device *pm8001_dev;
2188         struct ssp_event_resp *psspPayload =
2189                 (struct ssp_event_resp *)(piomb + 4);
2190         u32 event = le32_to_cpu(psspPayload->event);
2191         u32 tag = le32_to_cpu(psspPayload->tag);
2192         u32 port_id = le32_to_cpu(psspPayload->port_id);
2193
2194         ccb = &pm8001_ha->ccb_info[tag];
2195         t = ccb->task;
2196         pm8001_dev = ccb->device;
2197         if (event)
2198                 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2199         if (unlikely(!t || !t->lldd_task || !t->dev))
2200                 return;
2201         ts = &t->task_status;
2202         pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2203                    port_id, tag, event);
2204         switch (event) {
2205         case IO_OVERFLOW:
2206                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2207                 ts->resp = SAS_TASK_COMPLETE;
2208                 ts->stat = SAS_DATA_OVERRUN;
2209                 ts->residual = 0;
2210                 if (pm8001_dev)
2211                         atomic_dec(&pm8001_dev->running_req);
2212                 break;
2213         case IO_XFER_ERROR_BREAK:
2214                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2215                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2216                 return;
2217         case IO_XFER_ERROR_PHY_NOT_READY:
2218                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2219                 ts->resp = SAS_TASK_COMPLETE;
2220                 ts->stat = SAS_OPEN_REJECT;
2221                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2222                 break;
2223         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2224                 pm8001_dbg(pm8001_ha, IO,
2225                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2226                 ts->resp = SAS_TASK_COMPLETE;
2227                 ts->stat = SAS_OPEN_REJECT;
2228                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2229                 break;
2230         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2231                 pm8001_dbg(pm8001_ha, IO,
2232                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2233                 ts->resp = SAS_TASK_COMPLETE;
2234                 ts->stat = SAS_OPEN_REJECT;
2235                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2236                 break;
2237         case IO_OPEN_CNX_ERROR_BREAK:
2238                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2239                 ts->resp = SAS_TASK_COMPLETE;
2240                 ts->stat = SAS_OPEN_REJECT;
2241                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2242                 break;
2243         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2244         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2245         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2246         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2247         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2248         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2249                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2250                 ts->resp = SAS_TASK_COMPLETE;
2251                 ts->stat = SAS_OPEN_REJECT;
2252                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2253                 if (!t->uldd_task)
2254                         pm8001_handle_event(pm8001_ha,
2255                                 pm8001_dev,
2256                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2257                 break;
2258         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2259                 pm8001_dbg(pm8001_ha, IO,
2260                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2261                 ts->resp = SAS_TASK_COMPLETE;
2262                 ts->stat = SAS_OPEN_REJECT;
2263                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2264                 break;
2265         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2266                 pm8001_dbg(pm8001_ha, IO,
2267                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2268                 ts->resp = SAS_TASK_COMPLETE;
2269                 ts->stat = SAS_OPEN_REJECT;
2270                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2271                 break;
2272         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2273                 pm8001_dbg(pm8001_ha, IO,
2274                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2275                 ts->resp = SAS_TASK_COMPLETE;
2276                 ts->stat = SAS_OPEN_REJECT;
2277                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2278                 break;
2279         case IO_XFER_ERROR_NAK_RECEIVED:
2280                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2281                 ts->resp = SAS_TASK_COMPLETE;
2282                 ts->stat = SAS_OPEN_REJECT;
2283                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2284                 break;
2285         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2286                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2287                 ts->resp = SAS_TASK_COMPLETE;
2288                 ts->stat = SAS_NAK_R_ERR;
2289                 break;
2290         case IO_XFER_OPEN_RETRY_TIMEOUT:
2291                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2292                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2293                 return;
2294         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2295                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2296                 ts->resp = SAS_TASK_COMPLETE;
2297                 ts->stat = SAS_DATA_OVERRUN;
2298                 break;
2299         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2300                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2301                 ts->resp = SAS_TASK_COMPLETE;
2302                 ts->stat = SAS_DATA_OVERRUN;
2303                 break;
2304         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2305                 pm8001_dbg(pm8001_ha, IO,
2306                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2307                 ts->resp = SAS_TASK_COMPLETE;
2308                 ts->stat = SAS_DATA_OVERRUN;
2309                 break;
2310         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2311                 pm8001_dbg(pm8001_ha, IO,
2312                            "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2313                 ts->resp = SAS_TASK_COMPLETE;
2314                 ts->stat = SAS_DATA_OVERRUN;
2315                 break;
2316         case IO_XFER_ERROR_OFFSET_MISMATCH:
2317                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2318                 ts->resp = SAS_TASK_COMPLETE;
2319                 ts->stat = SAS_DATA_OVERRUN;
2320                 break;
2321         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2322                 pm8001_dbg(pm8001_ha, IO,
2323                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2324                 ts->resp = SAS_TASK_COMPLETE;
2325                 ts->stat = SAS_DATA_OVERRUN;
2326                 break;
2327         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2328                 pm8001_dbg(pm8001_ha, IOERR,
2329                            "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2330                 /* TBC: used default set values */
2331                 ts->resp = SAS_TASK_COMPLETE;
2332                 ts->stat = SAS_DATA_OVERRUN;
2333                 break;
2334         case IO_XFER_CMD_FRAME_ISSUED:
2335                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2336                 return;
2337         default:
2338                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2339                 /* not allowed case. Therefore, return failed status */
2340                 ts->resp = SAS_TASK_COMPLETE;
2341                 ts->stat = SAS_DATA_OVERRUN;
2342                 break;
2343         }
2344         spin_lock_irqsave(&t->task_state_lock, flags);
2345         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2346         t->task_state_flags |= SAS_TASK_STATE_DONE;
2347         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2348                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2349                 pm8001_dbg(pm8001_ha, FAIL,
2350                            "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2351                            t, event, ts->resp, ts->stat);
2352                 pm8001_ccb_task_free(pm8001_ha, ccb);
2353         } else {
2354                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2355                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2356         }
2357 }
2358
2359 /*See the comments for mpi_ssp_completion */
2360 static void
2361 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2362                 struct outbound_queue_table *circularQ, void *piomb)
2363 {
2364         struct sas_task *t;
2365         struct pm8001_ccb_info *ccb;
2366         u32 param;
2367         u32 status;
2368         u32 tag;
2369         int i, j;
2370         u8 sata_addr_low[4];
2371         u32 temp_sata_addr_low, temp_sata_addr_hi;
2372         u8 sata_addr_hi[4];
2373         struct sata_completion_resp *psataPayload;
2374         struct task_status_struct *ts;
2375         struct ata_task_resp *resp ;
2376         u32 *sata_resp;
2377         struct pm8001_device *pm8001_dev;
2378         unsigned long flags;
2379
2380         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2381         status = le32_to_cpu(psataPayload->status);
2382         param = le32_to_cpu(psataPayload->param);
2383         tag = le32_to_cpu(psataPayload->tag);
2384
2385         ccb = &pm8001_ha->ccb_info[tag];
2386         t = ccb->task;
2387         pm8001_dev = ccb->device;
2388
2389         if (t) {
2390                 if (t->dev && (t->dev->lldd_dev))
2391                         pm8001_dev = t->dev->lldd_dev;
2392         } else {
2393                 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2394                 return;
2395         }
2396
2397         if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2398                 && unlikely(!t || !t->lldd_task || !t->dev)) {
2399                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2400                 return;
2401         }
2402
2403         ts = &t->task_status;
2404
2405         if (status != IO_SUCCESS) {
2406                 pm8001_dbg(pm8001_ha, FAIL,
2407                         "IO failed device_id %u status 0x%x tag %d\n",
2408                         pm8001_dev->device_id, status, tag);
2409         }
2410
2411         /* Print sas address of IO failed device */
2412         if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2413                 (status != IO_UNDERFLOW)) {
2414                 if (!((t->dev->parent) &&
2415                         (dev_is_expander(t->dev->parent->dev_type)))) {
2416                         for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2417                                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2418                         for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2419                                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2420                         memcpy(&temp_sata_addr_low, sata_addr_low,
2421                                 sizeof(sata_addr_low));
2422                         memcpy(&temp_sata_addr_hi, sata_addr_hi,
2423                                 sizeof(sata_addr_hi));
2424                         temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2425                                                 |((temp_sata_addr_hi << 8) &
2426                                                 0xff0000) |
2427                                                 ((temp_sata_addr_hi >> 8)
2428                                                 & 0xff00) |
2429                                                 ((temp_sata_addr_hi << 24) &
2430                                                 0xff000000));
2431                         temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2432                                                 & 0xff) |
2433                                                 ((temp_sata_addr_low << 8)
2434                                                 & 0xff0000) |
2435                                                 ((temp_sata_addr_low >> 8)
2436                                                 & 0xff00) |
2437                                                 ((temp_sata_addr_low << 24)
2438                                                 & 0xff000000)) +
2439                                                 pm8001_dev->attached_phy +
2440                                                 0x10);
2441                         pm8001_dbg(pm8001_ha, FAIL,
2442                                    "SAS Address of IO Failure Drive:%08x%08x\n",
2443                                    temp_sata_addr_hi,
2444                                    temp_sata_addr_low);
2445
2446                 } else {
2447                         pm8001_dbg(pm8001_ha, FAIL,
2448                                    "SAS Address of IO Failure Drive:%016llx\n",
2449                                    SAS_ADDR(t->dev->sas_addr));
2450                 }
2451         }
2452         switch (status) {
2453         case IO_SUCCESS:
2454                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2455                 if (param == 0) {
2456                         ts->resp = SAS_TASK_COMPLETE;
2457                         ts->stat = SAS_SAM_STAT_GOOD;
2458                         /* check if response is for SEND READ LOG */
2459                         if (pm8001_dev &&
2460                             (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2461                                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2462                                 /* Free the tag */
2463                                 pm8001_tag_free(pm8001_ha, tag);
2464                                 sas_free_task(t);
2465                                 return;
2466                         }
2467                 } else {
2468                         u8 len;
2469                         ts->resp = SAS_TASK_COMPLETE;
2470                         ts->stat = SAS_PROTO_RESPONSE;
2471                         ts->residual = param;
2472                         pm8001_dbg(pm8001_ha, IO,
2473                                    "SAS_PROTO_RESPONSE len = %d\n",
2474                                    param);
2475                         sata_resp = &psataPayload->sata_resp[0];
2476                         resp = (struct ata_task_resp *)ts->buf;
2477                         if (t->ata_task.dma_xfer == 0 &&
2478                             t->data_dir == DMA_FROM_DEVICE) {
2479                                 len = sizeof(struct pio_setup_fis);
2480                                 pm8001_dbg(pm8001_ha, IO,
2481                                            "PIO read len = %d\n", len);
2482                         } else if (t->ata_task.use_ncq &&
2483                                    t->data_dir != DMA_NONE) {
2484                                 len = sizeof(struct set_dev_bits_fis);
2485                                 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2486                                            len);
2487                         } else {
2488                                 len = sizeof(struct dev_to_host_fis);
2489                                 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2490                                            len);
2491                         }
2492                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2493                                 resp->frame_len = len;
2494                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2495                                 ts->buf_valid_size = sizeof(*resp);
2496                         } else
2497                                 pm8001_dbg(pm8001_ha, IO,
2498                                            "response too large\n");
2499                 }
2500                 if (pm8001_dev)
2501                         atomic_dec(&pm8001_dev->running_req);
2502                 break;
2503         case IO_ABORTED:
2504                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2505                 ts->resp = SAS_TASK_COMPLETE;
2506                 ts->stat = SAS_ABORTED_TASK;
2507                 if (pm8001_dev)
2508                         atomic_dec(&pm8001_dev->running_req);
2509                 break;
2510                 /* following cases are to do cases */
2511         case IO_UNDERFLOW:
2512                 /* SATA Completion with error */
2513                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2514                 ts->resp = SAS_TASK_COMPLETE;
2515                 ts->stat = SAS_DATA_UNDERRUN;
2516                 ts->residual = param;
2517                 if (pm8001_dev)
2518                         atomic_dec(&pm8001_dev->running_req);
2519                 break;
2520         case IO_NO_DEVICE:
2521                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2522                 ts->resp = SAS_TASK_UNDELIVERED;
2523                 ts->stat = SAS_PHY_DOWN;
2524                 if (pm8001_dev)
2525                         atomic_dec(&pm8001_dev->running_req);
2526                 break;
2527         case IO_XFER_ERROR_BREAK:
2528                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2529                 ts->resp = SAS_TASK_COMPLETE;
2530                 ts->stat = SAS_INTERRUPTED;
2531                 if (pm8001_dev)
2532                         atomic_dec(&pm8001_dev->running_req);
2533                 break;
2534         case IO_XFER_ERROR_PHY_NOT_READY:
2535                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2536                 ts->resp = SAS_TASK_COMPLETE;
2537                 ts->stat = SAS_OPEN_REJECT;
2538                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2539                 if (pm8001_dev)
2540                         atomic_dec(&pm8001_dev->running_req);
2541                 break;
2542         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2543                 pm8001_dbg(pm8001_ha, IO,
2544                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2545                 ts->resp = SAS_TASK_COMPLETE;
2546                 ts->stat = SAS_OPEN_REJECT;
2547                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2548                 if (pm8001_dev)
2549                         atomic_dec(&pm8001_dev->running_req);
2550                 break;
2551         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2552                 pm8001_dbg(pm8001_ha, IO,
2553                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2554                 ts->resp = SAS_TASK_COMPLETE;
2555                 ts->stat = SAS_OPEN_REJECT;
2556                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2557                 if (pm8001_dev)
2558                         atomic_dec(&pm8001_dev->running_req);
2559                 break;
2560         case IO_OPEN_CNX_ERROR_BREAK:
2561                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2562                 ts->resp = SAS_TASK_COMPLETE;
2563                 ts->stat = SAS_OPEN_REJECT;
2564                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2565                 if (pm8001_dev)
2566                         atomic_dec(&pm8001_dev->running_req);
2567                 break;
2568         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2569         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2570         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2571         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2572         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2573         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2574                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2575                 ts->resp = SAS_TASK_COMPLETE;
2576                 ts->stat = SAS_DEV_NO_RESPONSE;
2577                 if (!t->uldd_task) {
2578                         pm8001_handle_event(pm8001_ha,
2579                                 pm8001_dev,
2580                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2581                         ts->resp = SAS_TASK_UNDELIVERED;
2582                         ts->stat = SAS_QUEUE_FULL;
2583                         spin_unlock_irqrestore(&circularQ->oq_lock,
2584                                         circularQ->lock_flags);
2585                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2586                         spin_lock_irqsave(&circularQ->oq_lock,
2587                                         circularQ->lock_flags);
2588                         return;
2589                 }
2590                 break;
2591         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2592                 pm8001_dbg(pm8001_ha, IO,
2593                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2594                 ts->resp = SAS_TASK_UNDELIVERED;
2595                 ts->stat = SAS_OPEN_REJECT;
2596                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2597                 if (!t->uldd_task) {
2598                         pm8001_handle_event(pm8001_ha,
2599                                 pm8001_dev,
2600                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2601                         ts->resp = SAS_TASK_UNDELIVERED;
2602                         ts->stat = SAS_QUEUE_FULL;
2603                         spin_unlock_irqrestore(&circularQ->oq_lock,
2604                                         circularQ->lock_flags);
2605                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2606                         spin_lock_irqsave(&circularQ->oq_lock,
2607                                         circularQ->lock_flags);
2608                         return;
2609                 }
2610                 break;
2611         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2612                 pm8001_dbg(pm8001_ha, IO,
2613                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2614                 ts->resp = SAS_TASK_COMPLETE;
2615                 ts->stat = SAS_OPEN_REJECT;
2616                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2617                 if (pm8001_dev)
2618                         atomic_dec(&pm8001_dev->running_req);
2619                 break;
2620         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2621                 pm8001_dbg(pm8001_ha, IO,
2622                            "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2623                 ts->resp = SAS_TASK_COMPLETE;
2624                 ts->stat = SAS_DEV_NO_RESPONSE;
2625                 if (!t->uldd_task) {
2626                         pm8001_handle_event(pm8001_ha,
2627                                 pm8001_dev,
2628                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2629                         ts->resp = SAS_TASK_UNDELIVERED;
2630                         ts->stat = SAS_QUEUE_FULL;
2631                         spin_unlock_irqrestore(&circularQ->oq_lock,
2632                                         circularQ->lock_flags);
2633                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2634                         spin_lock_irqsave(&circularQ->oq_lock,
2635                                         circularQ->lock_flags);
2636                         return;
2637                 }
2638                 break;
2639         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2640                 pm8001_dbg(pm8001_ha, IO,
2641                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2642                 ts->resp = SAS_TASK_COMPLETE;
2643                 ts->stat = SAS_OPEN_REJECT;
2644                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2645                 if (pm8001_dev)
2646                         atomic_dec(&pm8001_dev->running_req);
2647                 break;
2648         case IO_XFER_ERROR_NAK_RECEIVED:
2649                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2650                 ts->resp = SAS_TASK_COMPLETE;
2651                 ts->stat = SAS_NAK_R_ERR;
2652                 if (pm8001_dev)
2653                         atomic_dec(&pm8001_dev->running_req);
2654                 break;
2655         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2656                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2657                 ts->resp = SAS_TASK_COMPLETE;
2658                 ts->stat = SAS_NAK_R_ERR;
2659                 if (pm8001_dev)
2660                         atomic_dec(&pm8001_dev->running_req);
2661                 break;
2662         case IO_XFER_ERROR_DMA:
2663                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2664                 ts->resp = SAS_TASK_COMPLETE;
2665                 ts->stat = SAS_ABORTED_TASK;
2666                 if (pm8001_dev)
2667                         atomic_dec(&pm8001_dev->running_req);
2668                 break;
2669         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2670                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2671                 ts->resp = SAS_TASK_UNDELIVERED;
2672                 ts->stat = SAS_DEV_NO_RESPONSE;
2673                 if (pm8001_dev)
2674                         atomic_dec(&pm8001_dev->running_req);
2675                 break;
2676         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2677                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2678                 ts->resp = SAS_TASK_COMPLETE;
2679                 ts->stat = SAS_DATA_UNDERRUN;
2680                 if (pm8001_dev)
2681                         atomic_dec(&pm8001_dev->running_req);
2682                 break;
2683         case IO_XFER_OPEN_RETRY_TIMEOUT:
2684                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2685                 ts->resp = SAS_TASK_COMPLETE;
2686                 ts->stat = SAS_OPEN_TO;
2687                 if (pm8001_dev)
2688                         atomic_dec(&pm8001_dev->running_req);
2689                 break;
2690         case IO_PORT_IN_RESET:
2691                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2692                 ts->resp = SAS_TASK_COMPLETE;
2693                 ts->stat = SAS_DEV_NO_RESPONSE;
2694                 if (pm8001_dev)
2695                         atomic_dec(&pm8001_dev->running_req);
2696                 break;
2697         case IO_DS_NON_OPERATIONAL:
2698                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2699                 ts->resp = SAS_TASK_COMPLETE;
2700                 ts->stat = SAS_DEV_NO_RESPONSE;
2701                 if (!t->uldd_task) {
2702                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2703                                         IO_DS_NON_OPERATIONAL);
2704                         ts->resp = SAS_TASK_UNDELIVERED;
2705                         ts->stat = SAS_QUEUE_FULL;
2706                         spin_unlock_irqrestore(&circularQ->oq_lock,
2707                                         circularQ->lock_flags);
2708                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2709                         spin_lock_irqsave(&circularQ->oq_lock,
2710                                         circularQ->lock_flags);
2711                         return;
2712                 }
2713                 break;
2714         case IO_DS_IN_RECOVERY:
2715                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2716                 ts->resp = SAS_TASK_COMPLETE;
2717                 ts->stat = SAS_DEV_NO_RESPONSE;
2718                 if (pm8001_dev)
2719                         atomic_dec(&pm8001_dev->running_req);
2720                 break;
2721         case IO_DS_IN_ERROR:
2722                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2723                 ts->resp = SAS_TASK_COMPLETE;
2724                 ts->stat = SAS_DEV_NO_RESPONSE;
2725                 if (!t->uldd_task) {
2726                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2727                                         IO_DS_IN_ERROR);
2728                         ts->resp = SAS_TASK_UNDELIVERED;
2729                         ts->stat = SAS_QUEUE_FULL;
2730                         spin_unlock_irqrestore(&circularQ->oq_lock,
2731                                         circularQ->lock_flags);
2732                         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2733                         spin_lock_irqsave(&circularQ->oq_lock,
2734                                         circularQ->lock_flags);
2735                         return;
2736                 }
2737                 break;
2738         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2739                 pm8001_dbg(pm8001_ha, IO,
2740                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2741                 ts->resp = SAS_TASK_COMPLETE;
2742                 ts->stat = SAS_OPEN_REJECT;
2743                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2744                 if (pm8001_dev)
2745                         atomic_dec(&pm8001_dev->running_req);
2746                 break;
2747         default:
2748                 pm8001_dbg(pm8001_ha, DEVIO,
2749                                 "Unknown status device_id %u status 0x%x tag %d\n",
2750                         pm8001_dev->device_id, status, tag);
2751                 /* not allowed case. Therefore, return failed status */
2752                 ts->resp = SAS_TASK_COMPLETE;
2753                 ts->stat = SAS_DEV_NO_RESPONSE;
2754                 if (pm8001_dev)
2755                         atomic_dec(&pm8001_dev->running_req);
2756                 break;
2757         }
2758         spin_lock_irqsave(&t->task_state_lock, flags);
2759         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2760         t->task_state_flags |= SAS_TASK_STATE_DONE;
2761         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2762                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2763                 pm8001_dbg(pm8001_ha, FAIL,
2764                            "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2765                            t, status, ts->resp, ts->stat);
2766                 pm8001_ccb_task_free(pm8001_ha, ccb);
2767                 if (t->slow_task)
2768                         complete(&t->slow_task->completion);
2769         } else {
2770                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2771                 spin_unlock_irqrestore(&circularQ->oq_lock,
2772                                 circularQ->lock_flags);
2773                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2774                 spin_lock_irqsave(&circularQ->oq_lock,
2775                                 circularQ->lock_flags);
2776         }
2777 }
2778
2779 /*See the comments for mpi_ssp_completion */
2780 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2781                 struct outbound_queue_table *circularQ, void *piomb)
2782 {
2783         struct sas_task *t;
2784         struct task_status_struct *ts;
2785         struct pm8001_ccb_info *ccb;
2786         struct pm8001_device *pm8001_dev;
2787         struct sata_event_resp *psataPayload =
2788                 (struct sata_event_resp *)(piomb + 4);
2789         u32 event = le32_to_cpu(psataPayload->event);
2790         u32 tag = le32_to_cpu(psataPayload->tag);
2791         u32 port_id = le32_to_cpu(psataPayload->port_id);
2792         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2793
2794         if (event)
2795                 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2796
2797         /* Check if this is NCQ error */
2798         if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2799                 /* find device using device id */
2800                 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2801                 /* send read log extension */
2802                 if (pm8001_dev)
2803                         pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2804                 return;
2805         }
2806
2807         ccb = &pm8001_ha->ccb_info[tag];
2808         t = ccb->task;
2809         pm8001_dev = ccb->device;
2810
2811         if (unlikely(!t || !t->lldd_task || !t->dev)) {
2812                 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2813                 return;
2814         }
2815
2816         ts = &t->task_status;
2817         pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2818                    port_id, tag, event);
2819         switch (event) {
2820         case IO_OVERFLOW:
2821                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2822                 ts->resp = SAS_TASK_COMPLETE;
2823                 ts->stat = SAS_DATA_OVERRUN;
2824                 ts->residual = 0;
2825                 break;
2826         case IO_XFER_ERROR_BREAK:
2827                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2828                 ts->resp = SAS_TASK_COMPLETE;
2829                 ts->stat = SAS_INTERRUPTED;
2830                 break;
2831         case IO_XFER_ERROR_PHY_NOT_READY:
2832                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2833                 ts->resp = SAS_TASK_COMPLETE;
2834                 ts->stat = SAS_OPEN_REJECT;
2835                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2836                 break;
2837         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2838                 pm8001_dbg(pm8001_ha, IO,
2839                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2840                 ts->resp = SAS_TASK_COMPLETE;
2841                 ts->stat = SAS_OPEN_REJECT;
2842                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2843                 break;
2844         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2845                 pm8001_dbg(pm8001_ha, IO,
2846                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2847                 ts->resp = SAS_TASK_COMPLETE;
2848                 ts->stat = SAS_OPEN_REJECT;
2849                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2850                 break;
2851         case IO_OPEN_CNX_ERROR_BREAK:
2852                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2853                 ts->resp = SAS_TASK_COMPLETE;
2854                 ts->stat = SAS_OPEN_REJECT;
2855                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2856                 break;
2857         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2858         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2859         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2860         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2861         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2862         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2863                 pm8001_dbg(pm8001_ha, FAIL,
2864                            "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2865                 ts->resp = SAS_TASK_UNDELIVERED;
2866                 ts->stat = SAS_DEV_NO_RESPONSE;
2867                 if (!t->uldd_task) {
2868                         pm8001_handle_event(pm8001_ha,
2869                                 pm8001_dev,
2870                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2871                         ts->resp = SAS_TASK_COMPLETE;
2872                         ts->stat = SAS_QUEUE_FULL;
2873                         return;
2874                 }
2875                 break;
2876         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2877                 pm8001_dbg(pm8001_ha, IO,
2878                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2879                 ts->resp = SAS_TASK_UNDELIVERED;
2880                 ts->stat = SAS_OPEN_REJECT;
2881                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2882                 break;
2883         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2884                 pm8001_dbg(pm8001_ha, IO,
2885                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2886                 ts->resp = SAS_TASK_COMPLETE;
2887                 ts->stat = SAS_OPEN_REJECT;
2888                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2889                 break;
2890         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2891                 pm8001_dbg(pm8001_ha, IO,
2892                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2893                 ts->resp = SAS_TASK_COMPLETE;
2894                 ts->stat = SAS_OPEN_REJECT;
2895                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2896                 break;
2897         case IO_XFER_ERROR_NAK_RECEIVED:
2898                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2899                 ts->resp = SAS_TASK_COMPLETE;
2900                 ts->stat = SAS_NAK_R_ERR;
2901                 break;
2902         case IO_XFER_ERROR_PEER_ABORTED:
2903                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2904                 ts->resp = SAS_TASK_COMPLETE;
2905                 ts->stat = SAS_NAK_R_ERR;
2906                 break;
2907         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2908                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2909                 ts->resp = SAS_TASK_COMPLETE;
2910                 ts->stat = SAS_DATA_UNDERRUN;
2911                 break;
2912         case IO_XFER_OPEN_RETRY_TIMEOUT:
2913                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2914                 ts->resp = SAS_TASK_COMPLETE;
2915                 ts->stat = SAS_OPEN_TO;
2916                 break;
2917         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2918                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2919                 ts->resp = SAS_TASK_COMPLETE;
2920                 ts->stat = SAS_OPEN_TO;
2921                 break;
2922         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2923                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2924                 ts->resp = SAS_TASK_COMPLETE;
2925                 ts->stat = SAS_OPEN_TO;
2926                 break;
2927         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2928                 pm8001_dbg(pm8001_ha, IO,
2929                            "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2930                 ts->resp = SAS_TASK_COMPLETE;
2931                 ts->stat = SAS_OPEN_TO;
2932                 break;
2933         case IO_XFER_ERROR_OFFSET_MISMATCH:
2934                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2935                 ts->resp = SAS_TASK_COMPLETE;
2936                 ts->stat = SAS_OPEN_TO;
2937                 break;
2938         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2939                 pm8001_dbg(pm8001_ha, IO,
2940                            "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2941                 ts->resp = SAS_TASK_COMPLETE;
2942                 ts->stat = SAS_OPEN_TO;
2943                 break;
2944         case IO_XFER_CMD_FRAME_ISSUED:
2945                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2946                 break;
2947         case IO_XFER_PIO_SETUP_ERROR:
2948                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2949                 ts->resp = SAS_TASK_COMPLETE;
2950                 ts->stat = SAS_OPEN_TO;
2951                 break;
2952         case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2953                 pm8001_dbg(pm8001_ha, FAIL,
2954                            "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2955                 /* TBC: used default set values */
2956                 ts->resp = SAS_TASK_COMPLETE;
2957                 ts->stat = SAS_OPEN_TO;
2958                 break;
2959         case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2960                 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2961                 /* TBC: used default set values */
2962                 ts->resp = SAS_TASK_COMPLETE;
2963                 ts->stat = SAS_OPEN_TO;
2964                 break;
2965         default:
2966                 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2967                 /* not allowed case. Therefore, return failed status */
2968                 ts->resp = SAS_TASK_COMPLETE;
2969                 ts->stat = SAS_OPEN_TO;
2970                 break;
2971         }
2972 }
2973
2974 /*See the comments for mpi_ssp_completion */
2975 static void
2976 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2977 {
2978         u32 param, i;
2979         struct sas_task *t;
2980         struct pm8001_ccb_info *ccb;
2981         unsigned long flags;
2982         u32 status;
2983         u32 tag;
2984         struct smp_completion_resp *psmpPayload;
2985         struct task_status_struct *ts;
2986         struct pm8001_device *pm8001_dev;
2987
2988         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2989         status = le32_to_cpu(psmpPayload->status);
2990         tag = le32_to_cpu(psmpPayload->tag);
2991
2992         ccb = &pm8001_ha->ccb_info[tag];
2993         param = le32_to_cpu(psmpPayload->param);
2994         t = ccb->task;
2995         ts = &t->task_status;
2996         pm8001_dev = ccb->device;
2997         if (status)
2998                 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2999         if (unlikely(!t || !t->lldd_task || !t->dev))
3000                 return;
3001
3002         pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
3003
3004         switch (status) {
3005
3006         case IO_SUCCESS:
3007                 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
3008                 ts->resp = SAS_TASK_COMPLETE;
3009                 ts->stat = SAS_SAM_STAT_GOOD;
3010                 if (pm8001_dev)
3011                         atomic_dec(&pm8001_dev->running_req);
3012                 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3013                         struct scatterlist *sg_resp = &t->smp_task.smp_resp;
3014                         u8 *payload;
3015                         void *to;
3016
3017                         pm8001_dbg(pm8001_ha, IO,
3018                                    "DIRECT RESPONSE Length:%d\n",
3019                                    param);
3020                         to = kmap_atomic(sg_page(sg_resp));
3021                         payload = to + sg_resp->offset;
3022                         for (i = 0; i < param; i++) {
3023                                 *(payload + i) = psmpPayload->_r_a[i];
3024                                 pm8001_dbg(pm8001_ha, IO,
3025                                            "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3026                                            i, *(payload + i),
3027                                            psmpPayload->_r_a[i]);
3028                         }
3029                         kunmap_atomic(to);
3030                 }
3031                 break;
3032         case IO_ABORTED:
3033                 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3034                 ts->resp = SAS_TASK_COMPLETE;
3035                 ts->stat = SAS_ABORTED_TASK;
3036                 if (pm8001_dev)
3037                         atomic_dec(&pm8001_dev->running_req);
3038                 break;
3039         case IO_OVERFLOW:
3040                 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3041                 ts->resp = SAS_TASK_COMPLETE;
3042                 ts->stat = SAS_DATA_OVERRUN;
3043                 ts->residual = 0;
3044                 if (pm8001_dev)
3045                         atomic_dec(&pm8001_dev->running_req);
3046                 break;
3047         case IO_NO_DEVICE:
3048                 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3049                 ts->resp = SAS_TASK_COMPLETE;
3050                 ts->stat = SAS_PHY_DOWN;
3051                 break;
3052         case IO_ERROR_HW_TIMEOUT:
3053                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3054                 ts->resp = SAS_TASK_COMPLETE;
3055                 ts->stat = SAS_SAM_STAT_BUSY;
3056                 break;
3057         case IO_XFER_ERROR_BREAK:
3058                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3059                 ts->resp = SAS_TASK_COMPLETE;
3060                 ts->stat = SAS_SAM_STAT_BUSY;
3061                 break;
3062         case IO_XFER_ERROR_PHY_NOT_READY:
3063                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3064                 ts->resp = SAS_TASK_COMPLETE;
3065                 ts->stat = SAS_SAM_STAT_BUSY;
3066                 break;
3067         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3068                 pm8001_dbg(pm8001_ha, IO,
3069                            "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3070                 ts->resp = SAS_TASK_COMPLETE;
3071                 ts->stat = SAS_OPEN_REJECT;
3072                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3073                 break;
3074         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3075                 pm8001_dbg(pm8001_ha, IO,
3076                            "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3077                 ts->resp = SAS_TASK_COMPLETE;
3078                 ts->stat = SAS_OPEN_REJECT;
3079                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3080                 break;
3081         case IO_OPEN_CNX_ERROR_BREAK:
3082                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3083                 ts->resp = SAS_TASK_COMPLETE;
3084                 ts->stat = SAS_OPEN_REJECT;
3085                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3086                 break;
3087         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3088         case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3089         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3090         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3091         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3092         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3093                 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3094                 ts->resp = SAS_TASK_COMPLETE;
3095                 ts->stat = SAS_OPEN_REJECT;
3096                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3097                 pm8001_handle_event(pm8001_ha,
3098                                 pm8001_dev,
3099                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3100                 break;
3101         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3102                 pm8001_dbg(pm8001_ha, IO,
3103                            "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3104                 ts->resp = SAS_TASK_COMPLETE;
3105                 ts->stat = SAS_OPEN_REJECT;
3106                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3107                 break;
3108         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3109                 pm8001_dbg(pm8001_ha, IO,
3110                            "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3111                 ts->resp = SAS_TASK_COMPLETE;
3112                 ts->stat = SAS_OPEN_REJECT;
3113                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3114                 break;
3115         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3116                 pm8001_dbg(pm8001_ha, IO,
3117                            "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3118                 ts->resp = SAS_TASK_COMPLETE;
3119                 ts->stat = SAS_OPEN_REJECT;
3120                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3121                 break;
3122         case IO_XFER_ERROR_RX_FRAME:
3123                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3124                 ts->resp = SAS_TASK_COMPLETE;
3125                 ts->stat = SAS_DEV_NO_RESPONSE;
3126                 break;
3127         case IO_XFER_OPEN_RETRY_TIMEOUT:
3128                 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3129                 ts->resp = SAS_TASK_COMPLETE;
3130                 ts->stat = SAS_OPEN_REJECT;
3131                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3132                 break;
3133         case IO_ERROR_INTERNAL_SMP_RESOURCE:
3134                 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3135                 ts->resp = SAS_TASK_COMPLETE;
3136                 ts->stat = SAS_QUEUE_FULL;
3137                 break;
3138         case IO_PORT_IN_RESET:
3139                 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3140                 ts->resp = SAS_TASK_COMPLETE;
3141                 ts->stat = SAS_OPEN_REJECT;
3142                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3143                 break;
3144         case IO_DS_NON_OPERATIONAL:
3145                 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3146                 ts->resp = SAS_TASK_COMPLETE;
3147                 ts->stat = SAS_DEV_NO_RESPONSE;
3148                 break;
3149         case IO_DS_IN_RECOVERY:
3150                 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3151                 ts->resp = SAS_TASK_COMPLETE;
3152                 ts->stat = SAS_OPEN_REJECT;
3153                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3154                 break;
3155         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3156                 pm8001_dbg(pm8001_ha, IO,
3157                            "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3158                 ts->resp = SAS_TASK_COMPLETE;
3159                 ts->stat = SAS_OPEN_REJECT;
3160                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3161                 break;
3162         default:
3163                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3164                 ts->resp = SAS_TASK_COMPLETE;
3165                 ts->stat = SAS_DEV_NO_RESPONSE;
3166                 /* not allowed case. Therefore, return failed status */
3167                 break;
3168         }
3169         spin_lock_irqsave(&t->task_state_lock, flags);
3170         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3171         t->task_state_flags |= SAS_TASK_STATE_DONE;
3172         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3173                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3174                 pm8001_dbg(pm8001_ha, FAIL,
3175                            "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3176                            t, status, ts->resp, ts->stat);
3177                 pm8001_ccb_task_free(pm8001_ha, ccb);
3178         } else {
3179                 spin_unlock_irqrestore(&t->task_state_lock, flags);
3180                 pm8001_ccb_task_free(pm8001_ha, ccb);
3181                 mb();/* in order to force CPU ordering */
3182                 t->task_done(t);
3183         }
3184 }
3185
3186 /**
3187  * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3188  * @pm8001_ha: our hba card information
3189  * @Qnum: the outbound queue message number.
3190  * @SEA: source of event to ack
3191  * @port_id: port id.
3192  * @phyId: phy id.
3193  * @param0: parameter 0.
3194  * @param1: parameter 1.
3195  */
3196 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3197         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3198 {
3199         struct hw_event_ack_req  payload;
3200         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3201
3202         memset((u8 *)&payload, 0, sizeof(payload));
3203         payload.tag = cpu_to_le32(1);
3204         payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3205                 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3206         payload.param0 = cpu_to_le32(param0);
3207         payload.param1 = cpu_to_le32(param1);
3208
3209         pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload,
3210                              sizeof(payload), 0);
3211 }
3212
3213 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3214         u32 phyId, u32 phy_op);
3215
3216 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3217                                         void *piomb)
3218 {
3219         struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3220         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3221         u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3222         u32 lr_status_evt_portid =
3223                 le32_to_cpu(pPayload->lr_status_evt_portid);
3224         u8 deviceType = pPayload->sas_identify.dev_type;
3225         u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3226         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3227         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3228         struct pm8001_port *port = &pm8001_ha->port[port_id];
3229
3230         if (deviceType == SAS_END_DEVICE) {
3231                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3232                                         PHY_NOTIFY_ENABLE_SPINUP);
3233         }
3234
3235         port->wide_port_phymap |= (1U << phy_id);
3236         pm8001_get_lrate_mode(phy, link_rate);
3237         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3238         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3239         phy->phy_attached = 1;
3240 }
3241
3242 /**
3243  * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3244  * @pm8001_ha: our hba card information
3245  * @piomb: IO message buffer
3246  */
3247 static void
3248 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3249 {
3250         struct hw_event_resp *pPayload =
3251                 (struct hw_event_resp *)(piomb + 4);
3252         u32 lr_status_evt_portid =
3253                 le32_to_cpu(pPayload->lr_status_evt_portid);
3254         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3255
3256         u8 link_rate =
3257                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3258         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3259         u8 phy_id =
3260                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3261         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3262
3263         struct pm8001_port *port = &pm8001_ha->port[port_id];
3264         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3265         unsigned long flags;
3266         u8 deviceType = pPayload->sas_identify.dev_type;
3267         phy->port = port;
3268         port->port_id = port_id;
3269         port->port_state = portstate;
3270         port->wide_port_phymap |= (1U << phy_id);
3271         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3272         pm8001_dbg(pm8001_ha, MSG,
3273                    "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3274                    port_id, phy_id, link_rate, portstate, deviceType);
3275
3276         switch (deviceType) {
3277         case SAS_PHY_UNUSED:
3278                 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3279                 break;
3280         case SAS_END_DEVICE:
3281                 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3282                 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3283                         PHY_NOTIFY_ENABLE_SPINUP);
3284                 port->port_attached = 1;
3285                 pm8001_get_lrate_mode(phy, link_rate);
3286                 break;
3287         case SAS_EDGE_EXPANDER_DEVICE:
3288                 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3289                 port->port_attached = 1;
3290                 pm8001_get_lrate_mode(phy, link_rate);
3291                 break;
3292         case SAS_FANOUT_EXPANDER_DEVICE:
3293                 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3294                 port->port_attached = 1;
3295                 pm8001_get_lrate_mode(phy, link_rate);
3296                 break;
3297         default:
3298                 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3299                            deviceType);
3300                 break;
3301         }
3302         phy->phy_type |= PORT_TYPE_SAS;
3303         phy->identify.device_type = deviceType;
3304         phy->phy_attached = 1;
3305         if (phy->identify.device_type == SAS_END_DEVICE)
3306                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3307         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3308                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3309         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3310         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3311         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3312         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3313                 sizeof(struct sas_identify_frame)-4);
3314         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3315         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3316         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3317         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3318                 mdelay(200); /* delay a moment to wait for disk to spin up */
3319         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3320 }
3321
3322 /**
3323  * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3324  * @pm8001_ha: our hba card information
3325  * @piomb: IO message buffer
3326  */
3327 static void
3328 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3329 {
3330         struct hw_event_resp *pPayload =
3331                 (struct hw_event_resp *)(piomb + 4);
3332         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3333         u32 lr_status_evt_portid =
3334                 le32_to_cpu(pPayload->lr_status_evt_portid);
3335         u8 link_rate =
3336                 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3337         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3338         u8 phy_id =
3339                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3340
3341         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3342
3343         struct pm8001_port *port = &pm8001_ha->port[port_id];
3344         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3345         unsigned long flags;
3346         pm8001_dbg(pm8001_ha, DEVIO,
3347                    "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3348                    port_id, phy_id, link_rate, portstate);
3349
3350         phy->port = port;
3351         port->port_id = port_id;
3352         port->port_state = portstate;
3353         phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3354         port->port_attached = 1;
3355         pm8001_get_lrate_mode(phy, link_rate);
3356         phy->phy_type |= PORT_TYPE_SATA;
3357         phy->phy_attached = 1;
3358         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3359         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3360         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3361         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3362                 sizeof(struct dev_to_host_fis));
3363         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3364         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3365         phy->identify.device_type = SAS_SATA_DEV;
3366         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3367         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3368         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3369 }
3370
3371 /**
3372  * hw_event_phy_down - we should notify the libsas the phy is down.
3373  * @pm8001_ha: our hba card information
3374  * @piomb: IO message buffer
3375  */
3376 static void
3377 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3378 {
3379         struct hw_event_resp *pPayload =
3380                 (struct hw_event_resp *)(piomb + 4);
3381
3382         u32 lr_status_evt_portid =
3383                 le32_to_cpu(pPayload->lr_status_evt_portid);
3384         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3385         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3386         u8 phy_id =
3387                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3388         u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3389
3390         struct pm8001_port *port = &pm8001_ha->port[port_id];
3391         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3392         u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3393         port->port_state = portstate;
3394         phy->identify.device_type = 0;
3395         phy->phy_attached = 0;
3396         switch (portstate) {
3397         case PORT_VALID:
3398                 break;
3399         case PORT_INVALID:
3400                 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3401                            port_id);
3402                 pm8001_dbg(pm8001_ha, MSG,
3403                            " Last phy Down and port invalid\n");
3404                 if (port_sata) {
3405                         phy->phy_type = 0;
3406                         port->port_attached = 0;
3407                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3408                                         port_id, phy_id, 0, 0);
3409                 }
3410                 sas_phy_disconnected(&phy->sas_phy);
3411                 break;
3412         case PORT_IN_RESET:
3413                 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3414                            port_id);
3415                 break;
3416         case PORT_NOT_ESTABLISHED:
3417                 pm8001_dbg(pm8001_ha, MSG,
3418                            " Phy Down and PORT_NOT_ESTABLISHED\n");
3419                 port->port_attached = 0;
3420                 break;
3421         case PORT_LOSTCOMM:
3422                 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3423                 pm8001_dbg(pm8001_ha, MSG,
3424                            " Last phy Down and port invalid\n");
3425                 if (port_sata) {
3426                         port->port_attached = 0;
3427                         phy->phy_type = 0;
3428                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3429                                         port_id, phy_id, 0, 0);
3430                 }
3431                 sas_phy_disconnected(&phy->sas_phy);
3432                 break;
3433         default:
3434                 port->port_attached = 0;
3435                 pm8001_dbg(pm8001_ha, DEVIO,
3436                            " Phy Down and(default) = 0x%x\n",
3437                            portstate);
3438                 break;
3439
3440         }
3441         if (port_sata && (portstate != PORT_IN_RESET))
3442                 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3443                                 GFP_ATOMIC);
3444 }
3445
3446 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3447 {
3448         struct phy_start_resp *pPayload =
3449                 (struct phy_start_resp *)(piomb + 4);
3450         u32 status =
3451                 le32_to_cpu(pPayload->status);
3452         u32 phy_id =
3453                 le32_to_cpu(pPayload->phyid) & 0xFF;
3454         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3455
3456         pm8001_dbg(pm8001_ha, INIT,
3457                    "phy start resp status:0x%x, phyid:0x%x\n",
3458                    status, phy_id);
3459         if (status == 0)
3460                 phy->phy_state = PHY_LINK_DOWN;
3461
3462         if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3463                         phy->enable_completion != NULL) {
3464                 complete(phy->enable_completion);
3465                 phy->enable_completion = NULL;
3466         }
3467         return 0;
3468
3469 }
3470
3471 /**
3472  * mpi_thermal_hw_event - a thermal hw event has come.
3473  * @pm8001_ha: our hba card information
3474  * @piomb: IO message buffer
3475  */
3476 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3477 {
3478         struct thermal_hw_event *pPayload =
3479                 (struct thermal_hw_event *)(piomb + 4);
3480
3481         u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3482         u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3483
3484         if (thermal_event & 0x40) {
3485                 pm8001_dbg(pm8001_ha, IO,
3486                            "Thermal Event: Local high temperature violated!\n");
3487                 pm8001_dbg(pm8001_ha, IO,
3488                            "Thermal Event: Measured local high temperature %d\n",
3489                            ((rht_lht & 0xFF00) >> 8));
3490         }
3491         if (thermal_event & 0x10) {
3492                 pm8001_dbg(pm8001_ha, IO,
3493                            "Thermal Event: Remote high temperature violated!\n");
3494                 pm8001_dbg(pm8001_ha, IO,
3495                            "Thermal Event: Measured remote high temperature %d\n",
3496                            ((rht_lht & 0xFF000000) >> 24));
3497         }
3498         return 0;
3499 }
3500
3501 /**
3502  * mpi_hw_event - The hw event has come.
3503  * @pm8001_ha: our hba card information
3504  * @piomb: IO message buffer
3505  */
3506 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3507 {
3508         unsigned long flags, i;
3509         struct hw_event_resp *pPayload =
3510                 (struct hw_event_resp *)(piomb + 4);
3511         u32 lr_status_evt_portid =
3512                 le32_to_cpu(pPayload->lr_status_evt_portid);
3513         u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3514         u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3515         u8 phy_id =
3516                 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3517         u16 eventType =
3518                 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3519         u8 status =
3520                 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3521         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3522         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3523         struct pm8001_port *port = &pm8001_ha->port[port_id];
3524         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3525         pm8001_dbg(pm8001_ha, DEV,
3526                    "portid:%d phyid:%d event:0x%x status:0x%x\n",
3527                    port_id, phy_id, eventType, status);
3528
3529         switch (eventType) {
3530
3531         case HW_EVENT_SAS_PHY_UP:
3532                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3533                 hw_event_sas_phy_up(pm8001_ha, piomb);
3534                 break;
3535         case HW_EVENT_SATA_PHY_UP:
3536                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3537                 hw_event_sata_phy_up(pm8001_ha, piomb);
3538                 break;
3539         case HW_EVENT_SATA_SPINUP_HOLD:
3540                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3541                 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3542                         GFP_ATOMIC);
3543                 break;
3544         case HW_EVENT_PHY_DOWN:
3545                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3546                 hw_event_phy_down(pm8001_ha, piomb);
3547                 if (pm8001_ha->reset_in_progress) {
3548                         pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3549                         return 0;
3550                 }
3551                 phy->phy_attached = 0;
3552                 phy->phy_state = PHY_LINK_DISABLE;
3553                 break;
3554         case HW_EVENT_PORT_INVALID:
3555                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3556                 sas_phy_disconnected(sas_phy);
3557                 phy->phy_attached = 0;
3558                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3559                         GFP_ATOMIC);
3560                 break;
3561         /* the broadcast change primitive received, tell the LIBSAS this event
3562         to revalidate the sas domain*/
3563         case HW_EVENT_BROADCAST_CHANGE:
3564                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3565                 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3566                         port_id, phy_id, 1, 0);
3567                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3568                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3569                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3570                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3571                         GFP_ATOMIC);
3572                 break;
3573         case HW_EVENT_PHY_ERROR:
3574                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3575                 sas_phy_disconnected(&phy->sas_phy);
3576                 phy->phy_attached = 0;
3577                 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3578                 break;
3579         case HW_EVENT_BROADCAST_EXP:
3580                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3581                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3582                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3583                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3584                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3585                         GFP_ATOMIC);
3586                 break;
3587         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3588                 pm8001_dbg(pm8001_ha, MSG,
3589                            "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3590                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3591                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3592                 break;
3593         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3594                 pm8001_dbg(pm8001_ha, MSG,
3595                            "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3596                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3597                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3598                         port_id, phy_id, 0, 0);
3599                 break;
3600         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3601                 pm8001_dbg(pm8001_ha, MSG,
3602                            "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3603                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3604                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3605                         port_id, phy_id, 0, 0);
3606                 break;
3607         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3608                 pm8001_dbg(pm8001_ha, MSG,
3609                            "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3610                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3611                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3612                         port_id, phy_id, 0, 0);
3613                 break;
3614         case HW_EVENT_MALFUNCTION:
3615                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3616                 break;
3617         case HW_EVENT_BROADCAST_SES:
3618                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3619                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3620                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3621                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3622                 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3623                         GFP_ATOMIC);
3624                 break;
3625         case HW_EVENT_INBOUND_CRC_ERROR:
3626                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3627                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3628                         HW_EVENT_INBOUND_CRC_ERROR,
3629                         port_id, phy_id, 0, 0);
3630                 break;
3631         case HW_EVENT_HARD_RESET_RECEIVED:
3632                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3633                 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3634                 break;
3635         case HW_EVENT_ID_FRAME_TIMEOUT:
3636                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3637                 sas_phy_disconnected(sas_phy);
3638                 phy->phy_attached = 0;
3639                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3640                         GFP_ATOMIC);
3641                 break;
3642         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3643                 pm8001_dbg(pm8001_ha, MSG,
3644                            "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3645                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3646                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3647                         port_id, phy_id, 0, 0);
3648                 sas_phy_disconnected(sas_phy);
3649                 phy->phy_attached = 0;
3650                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3651                         GFP_ATOMIC);
3652                 break;
3653         case HW_EVENT_PORT_RESET_TIMER_TMO:
3654                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3655                 if (!pm8001_ha->phy[phy_id].reset_completion) {
3656                         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3657                                 port_id, phy_id, 0, 0);
3658                 }
3659                 sas_phy_disconnected(sas_phy);
3660                 phy->phy_attached = 0;
3661                 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3662                         GFP_ATOMIC);
3663                 if (pm8001_ha->phy[phy_id].reset_completion) {
3664                         pm8001_ha->phy[phy_id].port_reset_status =
3665                                         PORT_RESET_TMO;
3666                         complete(pm8001_ha->phy[phy_id].reset_completion);
3667                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3668                 }
3669                 break;
3670         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3671                 pm8001_dbg(pm8001_ha, MSG,
3672                            "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3673                 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3674                         HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3675                         port_id, phy_id, 0, 0);
3676                 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3677                         if (port->wide_port_phymap & (1 << i)) {
3678                                 phy = &pm8001_ha->phy[i];
3679                                 sas_notify_phy_event(&phy->sas_phy,
3680                                         PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3681                                 port->wide_port_phymap &= ~(1 << i);
3682                         }
3683                 }
3684                 break;
3685         case HW_EVENT_PORT_RECOVER:
3686                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3687                 hw_event_port_recover(pm8001_ha, piomb);
3688                 break;
3689         case HW_EVENT_PORT_RESET_COMPLETE:
3690                 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3691                 if (pm8001_ha->phy[phy_id].reset_completion) {
3692                         pm8001_ha->phy[phy_id].port_reset_status =
3693                                         PORT_RESET_SUCCESS;
3694                         complete(pm8001_ha->phy[phy_id].reset_completion);
3695                         pm8001_ha->phy[phy_id].reset_completion = NULL;
3696                 }
3697                 break;
3698         case EVENT_BROADCAST_ASYNCH_EVENT:
3699                 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3700                 break;
3701         default:
3702                 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3703                            eventType);
3704                 break;
3705         }
3706         return 0;
3707 }
3708
3709 /**
3710  * mpi_phy_stop_resp - SPCv specific
3711  * @pm8001_ha: our hba card information
3712  * @piomb: IO message buffer
3713  */
3714 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3715 {
3716         struct phy_stop_resp *pPayload =
3717                 (struct phy_stop_resp *)(piomb + 4);
3718         u32 status =
3719                 le32_to_cpu(pPayload->status);
3720         u32 phyid =
3721                 le32_to_cpu(pPayload->phyid) & 0xFF;
3722         struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3723         pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3724                    phyid, status);
3725         if (status == PHY_STOP_SUCCESS ||
3726                 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3727                 phy->phy_state = PHY_LINK_DISABLE;
3728         return 0;
3729 }
3730
3731 /**
3732  * mpi_set_controller_config_resp - SPCv specific
3733  * @pm8001_ha: our hba card information
3734  * @piomb: IO message buffer
3735  */
3736 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3737                         void *piomb)
3738 {
3739         struct set_ctrl_cfg_resp *pPayload =
3740                         (struct set_ctrl_cfg_resp *)(piomb + 4);
3741         u32 status = le32_to_cpu(pPayload->status);
3742         u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3743
3744         pm8001_dbg(pm8001_ha, MSG,
3745                    "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3746                    status, err_qlfr_pgcd);
3747
3748         return 0;
3749 }
3750
3751 /**
3752  * mpi_get_controller_config_resp - SPCv specific
3753  * @pm8001_ha: our hba card information
3754  * @piomb: IO message buffer
3755  */
3756 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3757                         void *piomb)
3758 {
3759         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3760
3761         return 0;
3762 }
3763
3764 /**
3765  * mpi_get_phy_profile_resp - SPCv specific
3766  * @pm8001_ha: our hba card information
3767  * @piomb: IO message buffer
3768  */
3769 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3770                         void *piomb)
3771 {
3772         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3773
3774         return 0;
3775 }
3776
3777 /**
3778  * mpi_flash_op_ext_resp - SPCv specific
3779  * @pm8001_ha: our hba card information
3780  * @piomb: IO message buffer
3781  */
3782 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3783 {
3784         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3785
3786         return 0;
3787 }
3788
3789 /**
3790  * mpi_set_phy_profile_resp - SPCv specific
3791  * @pm8001_ha: our hba card information
3792  * @piomb: IO message buffer
3793  */
3794 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3795                         void *piomb)
3796 {
3797         u32 tag;
3798         u8 page_code;
3799         int rc = 0;
3800         struct set_phy_profile_resp *pPayload =
3801                 (struct set_phy_profile_resp *)(piomb + 4);
3802         u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3803         u32 status = le32_to_cpu(pPayload->status);
3804
3805         tag = le32_to_cpu(pPayload->tag);
3806         page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3807         if (status) {
3808                 /* status is FAILED */
3809                 pm8001_dbg(pm8001_ha, FAIL,
3810                            "PhyProfile command failed  with status 0x%08X\n",
3811                            status);
3812                 rc = -1;
3813         } else {
3814                 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3815                         pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3816                                    page_code);
3817                         rc = -1;
3818                 }
3819         }
3820         pm8001_tag_free(pm8001_ha, tag);
3821         return rc;
3822 }
3823
3824 /**
3825  * mpi_kek_management_resp - SPCv specific
3826  * @pm8001_ha: our hba card information
3827  * @piomb: IO message buffer
3828  */
3829 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3830                         void *piomb)
3831 {
3832         struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3833
3834         u32 status = le32_to_cpu(pPayload->status);
3835         u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3836         u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3837
3838         pm8001_dbg(pm8001_ha, MSG,
3839                    "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3840                    status, kidx_new_curr_ksop, err_qlfr);
3841
3842         return 0;
3843 }
3844
3845 /**
3846  * mpi_dek_management_resp - SPCv specific
3847  * @pm8001_ha: our hba card information
3848  * @piomb: IO message buffer
3849  */
3850 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3851                         void *piomb)
3852 {
3853         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3854
3855         return 0;
3856 }
3857
3858 /**
3859  * ssp_coalesced_comp_resp - SPCv specific
3860  * @pm8001_ha: our hba card information
3861  * @piomb: IO message buffer
3862  */
3863 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3864                         void *piomb)
3865 {
3866         pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3867
3868         return 0;
3869 }
3870
3871 /**
3872  * process_one_iomb - process one outbound Queue memory block
3873  * @pm8001_ha: our hba card information
3874  * @circularQ: outbound circular queue
3875  * @piomb: IO message buffer
3876  */
3877 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3878                 struct outbound_queue_table *circularQ, void *piomb)
3879 {
3880         __le32 pHeader = *(__le32 *)piomb;
3881         u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3882
3883         switch (opc) {
3884         case OPC_OUB_ECHO:
3885                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3886                 break;
3887         case OPC_OUB_HW_EVENT:
3888                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3889                 mpi_hw_event(pm8001_ha, piomb);
3890                 break;
3891         case OPC_OUB_THERM_HW_EVENT:
3892                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3893                 mpi_thermal_hw_event(pm8001_ha, piomb);
3894                 break;
3895         case OPC_OUB_SSP_COMP:
3896                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3897                 mpi_ssp_completion(pm8001_ha, piomb);
3898                 break;
3899         case OPC_OUB_SMP_COMP:
3900                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3901                 mpi_smp_completion(pm8001_ha, piomb);
3902                 break;
3903         case OPC_OUB_LOCAL_PHY_CNTRL:
3904                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3905                 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3906                 break;
3907         case OPC_OUB_DEV_REGIST:
3908                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3909                 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3910                 break;
3911         case OPC_OUB_DEREG_DEV:
3912                 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3913                 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3914                 break;
3915         case OPC_OUB_GET_DEV_HANDLE:
3916                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3917                 break;
3918         case OPC_OUB_SATA_COMP:
3919                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3920                 mpi_sata_completion(pm8001_ha, circularQ, piomb);
3921                 break;
3922         case OPC_OUB_SATA_EVENT:
3923                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3924                 mpi_sata_event(pm8001_ha, circularQ, piomb);
3925                 break;
3926         case OPC_OUB_SSP_EVENT:
3927                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3928                 mpi_ssp_event(pm8001_ha, piomb);
3929                 break;
3930         case OPC_OUB_DEV_HANDLE_ARRIV:
3931                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3932                 /*This is for target*/
3933                 break;
3934         case OPC_OUB_SSP_RECV_EVENT:
3935                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3936                 /*This is for target*/
3937                 break;
3938         case OPC_OUB_FW_FLASH_UPDATE:
3939                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3940                 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3941                 break;
3942         case OPC_OUB_GPIO_RESPONSE:
3943                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3944                 break;
3945         case OPC_OUB_GPIO_EVENT:
3946                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3947                 break;
3948         case OPC_OUB_GENERAL_EVENT:
3949                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3950                 pm8001_mpi_general_event(pm8001_ha, piomb);
3951                 break;
3952         case OPC_OUB_SSP_ABORT_RSP:
3953                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3954                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3955                 break;
3956         case OPC_OUB_SATA_ABORT_RSP:
3957                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3958                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3959                 break;
3960         case OPC_OUB_SAS_DIAG_MODE_START_END:
3961                 pm8001_dbg(pm8001_ha, MSG,
3962                            "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3963                 break;
3964         case OPC_OUB_SAS_DIAG_EXECUTE:
3965                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3966                 break;
3967         case OPC_OUB_GET_TIME_STAMP:
3968                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3969                 break;
3970         case OPC_OUB_SAS_HW_EVENT_ACK:
3971                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3972                 break;
3973         case OPC_OUB_PORT_CONTROL:
3974                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3975                 break;
3976         case OPC_OUB_SMP_ABORT_RSP:
3977                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3978                 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3979                 break;
3980         case OPC_OUB_GET_NVMD_DATA:
3981                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3982                 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3983                 break;
3984         case OPC_OUB_SET_NVMD_DATA:
3985                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3986                 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3987                 break;
3988         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3989                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3990                 break;
3991         case OPC_OUB_SET_DEVICE_STATE:
3992                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3993                 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3994                 break;
3995         case OPC_OUB_GET_DEVICE_STATE:
3996                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3997                 break;
3998         case OPC_OUB_SET_DEV_INFO:
3999                 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4000                 break;
4001         /* spcv specific commands */
4002         case OPC_OUB_PHY_START_RESP:
4003                 pm8001_dbg(pm8001_ha, MSG,
4004                            "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
4005                 mpi_phy_start_resp(pm8001_ha, piomb);
4006                 break;
4007         case OPC_OUB_PHY_STOP_RESP:
4008                 pm8001_dbg(pm8001_ha, MSG,
4009                            "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
4010                 mpi_phy_stop_resp(pm8001_ha, piomb);
4011                 break;
4012         case OPC_OUB_SET_CONTROLLER_CONFIG:
4013                 pm8001_dbg(pm8001_ha, MSG,
4014                            "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
4015                 mpi_set_controller_config_resp(pm8001_ha, piomb);
4016                 break;
4017         case OPC_OUB_GET_CONTROLLER_CONFIG:
4018                 pm8001_dbg(pm8001_ha, MSG,
4019                            "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
4020                 mpi_get_controller_config_resp(pm8001_ha, piomb);
4021                 break;
4022         case OPC_OUB_GET_PHY_PROFILE:
4023                 pm8001_dbg(pm8001_ha, MSG,
4024                            "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
4025                 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4026                 break;
4027         case OPC_OUB_FLASH_OP_EXT:
4028                 pm8001_dbg(pm8001_ha, MSG,
4029                            "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4030                 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4031                 break;
4032         case OPC_OUB_SET_PHY_PROFILE:
4033                 pm8001_dbg(pm8001_ha, MSG,
4034                            "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4035                 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4036                 break;
4037         case OPC_OUB_KEK_MANAGEMENT_RESP:
4038                 pm8001_dbg(pm8001_ha, MSG,
4039                            "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4040                 mpi_kek_management_resp(pm8001_ha, piomb);
4041                 break;
4042         case OPC_OUB_DEK_MANAGEMENT_RESP:
4043                 pm8001_dbg(pm8001_ha, MSG,
4044                            "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4045                 mpi_dek_management_resp(pm8001_ha, piomb);
4046                 break;
4047         case OPC_OUB_SSP_COALESCED_COMP_RESP:
4048                 pm8001_dbg(pm8001_ha, MSG,
4049                            "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4050                 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4051                 break;
4052         default:
4053                 pm8001_dbg(pm8001_ha, DEVIO,
4054                            "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4055                 break;
4056         }
4057 }
4058
4059 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4060 {
4061         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4062                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4063         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4064                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4065         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4066                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4067         pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4068                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4069         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4070                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4071         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4072                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4073         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4074                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4075         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4076                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4077         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4078                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4079         pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4080                    pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4081         pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4082                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0));
4083         pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4084                    pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1));
4085 }
4086
4087 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4088 {
4089         struct outbound_queue_table *circularQ;
4090         void *pMsg1 = NULL;
4091         u8 bc;
4092         u32 ret = MPI_IO_STATUS_FAIL;
4093         u32 regval;
4094
4095         /*
4096          * Fatal errors are programmed to be signalled in irq vector
4097          * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4098          * fatal_err_interrupt
4099          */
4100         if (vec == (pm8001_ha->max_q_num - 1)) {
4101                 u32 mipsall_ready;
4102
4103                 if (pm8001_ha->chip_id == chip_8008 ||
4104                     pm8001_ha->chip_id == chip_8009)
4105                         mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4106                 else
4107                         mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4108
4109                 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4110                 if ((regval & mipsall_ready) != mipsall_ready) {
4111                         pm8001_ha->controller_fatal_error = true;
4112                         pm8001_dbg(pm8001_ha, FAIL,
4113                                    "Firmware Fatal error! Regval:0x%x\n",
4114                                    regval);
4115                         pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4116                         print_scratchpad_registers(pm8001_ha);
4117                         return ret;
4118                 } else {
4119                         /*read scratchpad rsvd 0 register*/
4120                         regval = pm8001_cr32(pm8001_ha, 0,
4121                                              MSGU_SCRATCH_PAD_RSVD_0);
4122                         switch (regval) {
4123                         case NON_FATAL_SPBC_LBUS_ECC_ERR:
4124                         case NON_FATAL_BDMA_ERR:
4125                         case NON_FATAL_THERM_OVERTEMP_ERR:
4126                                 /*Clear the register*/
4127                                 pm8001_cw32(pm8001_ha, 0,
4128                                             MSGU_SCRATCH_PAD_RSVD_0,
4129                                             0x00000000);
4130                                 break;
4131                         default:
4132                                 break;
4133                         }
4134                 }
4135         }
4136         circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4137         spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4138         do {
4139                 /* spurious interrupt during setup if kexec-ing and
4140                  * driver doing a doorbell access w/ the pre-kexec oq
4141                  * interrupt setup.
4142                  */
4143                 if (!circularQ->pi_virt)
4144                         break;
4145                 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4146                 if (MPI_IO_STATUS_SUCCESS == ret) {
4147                         /* process the outbound message */
4148                         process_one_iomb(pm8001_ha, circularQ,
4149                                                 (void *)(pMsg1 - 4));
4150                         /* free the message from the outbound circular buffer */
4151                         pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4152                                                         circularQ, bc);
4153                 }
4154                 if (MPI_IO_STATUS_BUSY == ret) {
4155                         /* Update the producer index from SPC */
4156                         circularQ->producer_index =
4157                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4158                         if (le32_to_cpu(circularQ->producer_index) ==
4159                                 circularQ->consumer_idx)
4160                                 /* OQ is empty */
4161                                 break;
4162                 }
4163         } while (1);
4164         spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4165         return ret;
4166 }
4167
4168 /* DMA_... to our direction translation. */
4169 static const u8 data_dir_flags[] = {
4170         [DMA_BIDIRECTIONAL]     = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4171         [DMA_TO_DEVICE]         = DATA_DIR_OUT,         /* OUTBOUND */
4172         [DMA_FROM_DEVICE]       = DATA_DIR_IN,          /* INBOUND */
4173         [DMA_NONE]              = DATA_DIR_NONE,        /* NO TRANSFER */
4174 };
4175
4176 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4177                         struct smp_req *psmp_cmd, int mode, int length)
4178 {
4179         psmp_cmd->tag = hTag;
4180         psmp_cmd->device_id = cpu_to_le32(deviceID);
4181         if (mode == SMP_DIRECT) {
4182                 length = length - 4; /* subtract crc */
4183                 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4184         } else {
4185                 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4186         }
4187 }
4188
4189 /**
4190  * pm80xx_chip_smp_req - send an SMP task to FW
4191  * @pm8001_ha: our hba card information.
4192  * @ccb: the ccb information this request used.
4193  */
4194 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4195         struct pm8001_ccb_info *ccb)
4196 {
4197         int elem, rc;
4198         struct sas_task *task = ccb->task;
4199         struct domain_device *dev = task->dev;
4200         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4201         struct scatterlist *sg_req, *sg_resp, *smp_req;
4202         u32 req_len, resp_len;
4203         struct smp_req smp_cmd;
4204         u32 opc;
4205         u32 i, length;
4206         u8 *payload;
4207         u8 *to;
4208
4209         memset(&smp_cmd, 0, sizeof(smp_cmd));
4210         /*
4211          * DMA-map SMP request, response buffers
4212          */
4213         sg_req = &task->smp_task.smp_req;
4214         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4215         if (!elem)
4216                 return -ENOMEM;
4217         req_len = sg_dma_len(sg_req);
4218
4219         sg_resp = &task->smp_task.smp_resp;
4220         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4221         if (!elem) {
4222                 rc = -ENOMEM;
4223                 goto err_out;
4224         }
4225         resp_len = sg_dma_len(sg_resp);
4226         /* must be in dwords */
4227         if ((req_len & 0x3) || (resp_len & 0x3)) {
4228                 rc = -EINVAL;
4229                 goto err_out_2;
4230         }
4231
4232         opc = OPC_INB_SMP_REQUEST;
4233         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4234
4235         length = sg_req->length;
4236         pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4237         if (!(length - 8))
4238                 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4239         else
4240                 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4241
4242
4243         smp_req = &task->smp_task.smp_req;
4244         to = kmap_atomic(sg_page(smp_req));
4245         payload = to + smp_req->offset;
4246
4247         /* INDIRECT MODE command settings. Use DMA */
4248         if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4249                 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4250                 /* for SPCv indirect mode. Place the top 4 bytes of
4251                  * SMP Request header here. */
4252                 for (i = 0; i < 4; i++)
4253                         smp_cmd.smp_req16[i] = *(payload + i);
4254                 /* exclude top 4 bytes for SMP req header */
4255                 smp_cmd.long_smp_req.long_req_addr =
4256                         cpu_to_le64((u64)sg_dma_address
4257                                 (&task->smp_task.smp_req) + 4);
4258                 /* exclude 4 bytes for SMP req header and CRC */
4259                 smp_cmd.long_smp_req.long_req_size =
4260                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4261                 smp_cmd.long_smp_req.long_resp_addr =
4262                                 cpu_to_le64((u64)sg_dma_address
4263                                         (&task->smp_task.smp_resp));
4264                 smp_cmd.long_smp_req.long_resp_size =
4265                                 cpu_to_le32((u32)sg_dma_len
4266                                         (&task->smp_task.smp_resp)-4);
4267         } else { /* DIRECT MODE */
4268                 smp_cmd.long_smp_req.long_req_addr =
4269                         cpu_to_le64((u64)sg_dma_address
4270                                         (&task->smp_task.smp_req));
4271                 smp_cmd.long_smp_req.long_req_size =
4272                         cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4273                 smp_cmd.long_smp_req.long_resp_addr =
4274                         cpu_to_le64((u64)sg_dma_address
4275                                 (&task->smp_task.smp_resp));
4276                 smp_cmd.long_smp_req.long_resp_size =
4277                         cpu_to_le32
4278                         ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4279         }
4280         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4281                 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4282                 for (i = 0; i < length; i++)
4283                         if (i < 16) {
4284                                 smp_cmd.smp_req16[i] = *(payload + i);
4285                                 pm8001_dbg(pm8001_ha, IO,
4286                                            "Byte[%d]:%x (DMA data:%x)\n",
4287                                            i, smp_cmd.smp_req16[i],
4288                                            *(payload));
4289                         } else {
4290                                 smp_cmd.smp_req[i] = *(payload + i);
4291                                 pm8001_dbg(pm8001_ha, IO,
4292                                            "Byte[%d]:%x (DMA data:%x)\n",
4293                                            i, smp_cmd.smp_req[i],
4294                                            *(payload));
4295                         }
4296         }
4297         kunmap_atomic(to);
4298         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4299                                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4300         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd,
4301                                   sizeof(smp_cmd), 0);
4302         if (rc)
4303                 goto err_out_2;
4304         return 0;
4305
4306 err_out_2:
4307         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4308                         DMA_FROM_DEVICE);
4309 err_out:
4310         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4311                         DMA_TO_DEVICE);
4312         return rc;
4313 }
4314
4315 static int check_enc_sas_cmd(struct sas_task *task)
4316 {
4317         u8 cmd = task->ssp_task.cmd->cmnd[0];
4318
4319         if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4320                 return 1;
4321         else
4322                 return 0;
4323 }
4324
4325 static int check_enc_sat_cmd(struct sas_task *task)
4326 {
4327         int ret = 0;
4328         switch (task->ata_task.fis.command) {
4329         case ATA_CMD_FPDMA_READ:
4330         case ATA_CMD_READ_EXT:
4331         case ATA_CMD_READ:
4332         case ATA_CMD_FPDMA_WRITE:
4333         case ATA_CMD_WRITE_EXT:
4334         case ATA_CMD_WRITE:
4335         case ATA_CMD_PIO_READ:
4336         case ATA_CMD_PIO_READ_EXT:
4337         case ATA_CMD_PIO_WRITE:
4338         case ATA_CMD_PIO_WRITE_EXT:
4339                 ret = 1;
4340                 break;
4341         default:
4342                 ret = 0;
4343                 break;
4344         }
4345         return ret;
4346 }
4347
4348 /**
4349  * pm80xx_chip_ssp_io_req - send an SSP task to FW
4350  * @pm8001_ha: our hba card information.
4351  * @ccb: the ccb information this request used.
4352  */
4353 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4354         struct pm8001_ccb_info *ccb)
4355 {
4356         struct sas_task *task = ccb->task;
4357         struct domain_device *dev = task->dev;
4358         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4359         struct ssp_ini_io_start_req ssp_cmd;
4360         u32 tag = ccb->ccb_tag;
4361         u64 phys_addr, end_addr;
4362         u32 end_addr_high, end_addr_low;
4363         u32 q_index, cpu_id;
4364         u32 opc = OPC_INB_SSPINIIOSTART;
4365
4366         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4367         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4368
4369         /* data address domain added for spcv; set to 0 by host,
4370          * used internally by controller
4371          * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4372          */
4373         ssp_cmd.dad_dir_m_tlr =
4374                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4375         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4376         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4377         ssp_cmd.tag = cpu_to_le32(tag);
4378         if (task->ssp_task.enable_first_burst)
4379                 ssp_cmd.ssp_iu.efb_prio_attr = 0x80;
4380         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4381         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4382         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4383                        task->ssp_task.cmd->cmd_len);
4384         cpu_id = smp_processor_id();
4385         q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4386
4387         /* Check if encryption is set */
4388         if (pm8001_ha->chip->encrypt &&
4389                 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4390                 pm8001_dbg(pm8001_ha, IO,
4391                            "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4392                            task->ssp_task.cmd->cmnd[0]);
4393                 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4394                 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4395                 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4396                         ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4397
4398                 /* fill in PRD (scatter/gather) table, if any */
4399                 if (task->num_scatter > 1) {
4400                         pm8001_chip_make_sg(task->scatter,
4401                                                 ccb->n_elem, ccb->buf_prd);
4402                         phys_addr = ccb->ccb_dma_handle;
4403                         ssp_cmd.enc_addr_low =
4404                                 cpu_to_le32(lower_32_bits(phys_addr));
4405                         ssp_cmd.enc_addr_high =
4406                                 cpu_to_le32(upper_32_bits(phys_addr));
4407                         ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4408                 } else if (task->num_scatter == 1) {
4409                         u64 dma_addr = sg_dma_address(task->scatter);
4410
4411                         ssp_cmd.enc_addr_low =
4412                                 cpu_to_le32(lower_32_bits(dma_addr));
4413                         ssp_cmd.enc_addr_high =
4414                                 cpu_to_le32(upper_32_bits(dma_addr));
4415                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4416                         ssp_cmd.enc_esgl = 0;
4417
4418                         /* Check 4G Boundary */
4419                         end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4420                         end_addr_low = lower_32_bits(end_addr);
4421                         end_addr_high = upper_32_bits(end_addr);
4422
4423                         if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4424                                 pm8001_dbg(pm8001_ha, FAIL,
4425                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4426                                            dma_addr,
4427                                            le32_to_cpu(ssp_cmd.enc_len),
4428                                            end_addr_high, end_addr_low);
4429                                 pm8001_chip_make_sg(task->scatter, 1,
4430                                         ccb->buf_prd);
4431                                 phys_addr = ccb->ccb_dma_handle;
4432                                 ssp_cmd.enc_addr_low =
4433                                         cpu_to_le32(lower_32_bits(phys_addr));
4434                                 ssp_cmd.enc_addr_high =
4435                                         cpu_to_le32(upper_32_bits(phys_addr));
4436                                 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4437                         }
4438                 } else if (task->num_scatter == 0) {
4439                         ssp_cmd.enc_addr_low = 0;
4440                         ssp_cmd.enc_addr_high = 0;
4441                         ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4442                         ssp_cmd.enc_esgl = 0;
4443                 }
4444
4445                 /* XTS mode. All other fields are 0 */
4446                 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4447
4448                 /* set tweak values. Should be the start lba */
4449                 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4450                                                 (task->ssp_task.cmd->cmnd[3] << 16) |
4451                                                 (task->ssp_task.cmd->cmnd[4] << 8) |
4452                                                 (task->ssp_task.cmd->cmnd[5]));
4453         } else {
4454                 pm8001_dbg(pm8001_ha, IO,
4455                            "Sending Normal SAS command 0x%x inb q %x\n",
4456                            task->ssp_task.cmd->cmnd[0], q_index);
4457                 /* fill in PRD (scatter/gather) table, if any */
4458                 if (task->num_scatter > 1) {
4459                         pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4460                                         ccb->buf_prd);
4461                         phys_addr = ccb->ccb_dma_handle;
4462                         ssp_cmd.addr_low =
4463                                 cpu_to_le32(lower_32_bits(phys_addr));
4464                         ssp_cmd.addr_high =
4465                                 cpu_to_le32(upper_32_bits(phys_addr));
4466                         ssp_cmd.esgl = cpu_to_le32(1<<31);
4467                 } else if (task->num_scatter == 1) {
4468                         u64 dma_addr = sg_dma_address(task->scatter);
4469
4470                         ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4471                         ssp_cmd.addr_high =
4472                                 cpu_to_le32(upper_32_bits(dma_addr));
4473                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4474                         ssp_cmd.esgl = 0;
4475
4476                         /* Check 4G Boundary */
4477                         end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4478                         end_addr_low = lower_32_bits(end_addr);
4479                         end_addr_high = upper_32_bits(end_addr);
4480                         if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4481                                 pm8001_dbg(pm8001_ha, FAIL,
4482                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4483                                            dma_addr,
4484                                            le32_to_cpu(ssp_cmd.len),
4485                                            end_addr_high, end_addr_low);
4486                                 pm8001_chip_make_sg(task->scatter, 1,
4487                                         ccb->buf_prd);
4488                                 phys_addr = ccb->ccb_dma_handle;
4489                                 ssp_cmd.addr_low =
4490                                         cpu_to_le32(lower_32_bits(phys_addr));
4491                                 ssp_cmd.addr_high =
4492                                         cpu_to_le32(upper_32_bits(phys_addr));
4493                                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4494                         }
4495                 } else if (task->num_scatter == 0) {
4496                         ssp_cmd.addr_low = 0;
4497                         ssp_cmd.addr_high = 0;
4498                         ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4499                         ssp_cmd.esgl = 0;
4500                 }
4501         }
4502
4503         return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd,
4504                                     sizeof(ssp_cmd), q_index);
4505 }
4506
4507 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4508         struct pm8001_ccb_info *ccb)
4509 {
4510         struct sas_task *task = ccb->task;
4511         struct domain_device *dev = task->dev;
4512         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4513         struct ata_queued_cmd *qc = task->uldd_task;
4514         u32 tag = ccb->ccb_tag;
4515         u32 q_index, cpu_id;
4516         struct sata_start_req sata_cmd;
4517         u32 hdr_tag, ncg_tag = 0;
4518         u64 phys_addr, end_addr;
4519         u32 end_addr_high, end_addr_low;
4520         u32 ATAP = 0x0;
4521         u32 dir;
4522         unsigned long flags;
4523         u32 opc = OPC_INB_SATA_HOST_OPSTART;
4524         memset(&sata_cmd, 0, sizeof(sata_cmd));
4525         cpu_id = smp_processor_id();
4526         q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4527
4528         if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4529                 ATAP = 0x04; /* no data*/
4530                 pm8001_dbg(pm8001_ha, IO, "no data\n");
4531         } else if (likely(!task->ata_task.device_control_reg_update)) {
4532                 if (task->ata_task.use_ncq &&
4533                     dev->sata_dev.class != ATA_DEV_ATAPI) {
4534                         ATAP = 0x07; /* FPDMA */
4535                         pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4536                 } else if (task->ata_task.dma_xfer) {
4537                         ATAP = 0x06; /* DMA */
4538                         pm8001_dbg(pm8001_ha, IO, "DMA\n");
4539                 } else {
4540                         ATAP = 0x05; /* PIO*/
4541                         pm8001_dbg(pm8001_ha, IO, "PIO\n");
4542                 }
4543         }
4544         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4545                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4546                 ncg_tag = hdr_tag;
4547         }
4548         dir = data_dir_flags[task->data_dir] << 8;
4549         sata_cmd.tag = cpu_to_le32(tag);
4550         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4551         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4552
4553         sata_cmd.sata_fis = task->ata_task.fis;
4554         if (likely(!task->ata_task.device_control_reg_update))
4555                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4556         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4557
4558         /* Check if encryption is set */
4559         if (pm8001_ha->chip->encrypt &&
4560                 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4561                 pm8001_dbg(pm8001_ha, IO,
4562                            "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4563                            sata_cmd.sata_fis.command);
4564                 opc = OPC_INB_SATA_DIF_ENC_IO;
4565
4566                 /* set encryption bit */
4567                 sata_cmd.ncqtag_atap_dir_m_dad =
4568                         cpu_to_le32(((ncg_tag & 0xff)<<16)|
4569                                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4570                                                         /* dad (bit 0-1) is 0 */
4571                 /* fill in PRD (scatter/gather) table, if any */
4572                 if (task->num_scatter > 1) {
4573                         pm8001_chip_make_sg(task->scatter,
4574                                                 ccb->n_elem, ccb->buf_prd);
4575                         phys_addr = ccb->ccb_dma_handle;
4576                         sata_cmd.enc_addr_low =
4577                                 cpu_to_le32(lower_32_bits(phys_addr));
4578                         sata_cmd.enc_addr_high =
4579                                 cpu_to_le32(upper_32_bits(phys_addr));
4580                         sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4581                 } else if (task->num_scatter == 1) {
4582                         u64 dma_addr = sg_dma_address(task->scatter);
4583
4584                         sata_cmd.enc_addr_low =
4585                                 cpu_to_le32(lower_32_bits(dma_addr));
4586                         sata_cmd.enc_addr_high =
4587                                 cpu_to_le32(upper_32_bits(dma_addr));
4588                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4589                         sata_cmd.enc_esgl = 0;
4590
4591                         /* Check 4G Boundary */
4592                         end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4593                         end_addr_low = lower_32_bits(end_addr);
4594                         end_addr_high = upper_32_bits(end_addr);
4595                         if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4596                                 pm8001_dbg(pm8001_ha, FAIL,
4597                                            "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4598                                            dma_addr,
4599                                            le32_to_cpu(sata_cmd.enc_len),
4600                                            end_addr_high, end_addr_low);
4601                                 pm8001_chip_make_sg(task->scatter, 1,
4602                                         ccb->buf_prd);
4603                                 phys_addr = ccb->ccb_dma_handle;
4604                                 sata_cmd.enc_addr_low =
4605                                         cpu_to_le32(lower_32_bits(phys_addr));
4606                                 sata_cmd.enc_addr_high =
4607                                         cpu_to_le32(upper_32_bits(phys_addr));
4608                                 sata_cmd.enc_esgl =
4609                                         cpu_to_le32(1 << 31);
4610                         }
4611                 } else if (task->num_scatter == 0) {
4612                         sata_cmd.enc_addr_low = 0;
4613                         sata_cmd.enc_addr_high = 0;
4614                         sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4615                         sata_cmd.enc_esgl = 0;
4616                 }
4617                 /* XTS mode. All other fields are 0 */
4618                 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4619
4620                 /* set tweak values. Should be the start lba */
4621                 sata_cmd.twk_val0 =
4622                         cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4623                                         (sata_cmd.sata_fis.lbah << 16) |
4624                                         (sata_cmd.sata_fis.lbam << 8) |
4625                                         (sata_cmd.sata_fis.lbal));
4626                 sata_cmd.twk_val1 =
4627                         cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4628                                          (sata_cmd.sata_fis.lbam_exp));
4629         } else {
4630                 pm8001_dbg(pm8001_ha, IO,
4631                            "Sending Normal SATA command 0x%x inb %x\n",
4632                            sata_cmd.sata_fis.command, q_index);
4633                 /* dad (bit 0-1) is 0 */
4634                 sata_cmd.ncqtag_atap_dir_m_dad =
4635                         cpu_to_le32(((ncg_tag & 0xff)<<16) |
4636                                         ((ATAP & 0x3f) << 10) | dir);
4637
4638                 /* fill in PRD (scatter/gather) table, if any */
4639                 if (task->num_scatter > 1) {
4640                         pm8001_chip_make_sg(task->scatter,
4641                                         ccb->n_elem, ccb->buf_prd);
4642                         phys_addr = ccb->ccb_dma_handle;
4643                         sata_cmd.addr_low = lower_32_bits(phys_addr);
4644                         sata_cmd.addr_high = upper_32_bits(phys_addr);
4645                         sata_cmd.esgl = cpu_to_le32(1U << 31);
4646                 } else if (task->num_scatter == 1) {
4647                         u64 dma_addr = sg_dma_address(task->scatter);
4648
4649                         sata_cmd.addr_low = lower_32_bits(dma_addr);
4650                         sata_cmd.addr_high = upper_32_bits(dma_addr);
4651                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4652                         sata_cmd.esgl = 0;
4653
4654                         /* Check 4G Boundary */
4655                         end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4656                         end_addr_low = lower_32_bits(end_addr);
4657                         end_addr_high = upper_32_bits(end_addr);
4658                         if (end_addr_high != sata_cmd.addr_high) {
4659                                 pm8001_dbg(pm8001_ha, FAIL,
4660                                            "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4661                                            dma_addr,
4662                                            le32_to_cpu(sata_cmd.len),
4663                                            end_addr_high, end_addr_low);
4664                                 pm8001_chip_make_sg(task->scatter, 1,
4665                                         ccb->buf_prd);
4666                                 phys_addr = ccb->ccb_dma_handle;
4667                                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4668                                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4669                                 sata_cmd.esgl = cpu_to_le32(1U << 31);
4670                         }
4671                 } else if (task->num_scatter == 0) {
4672                         sata_cmd.addr_low = 0;
4673                         sata_cmd.addr_high = 0;
4674                         sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4675                         sata_cmd.esgl = 0;
4676                 }
4677
4678                 /* scsi cdb */
4679                 sata_cmd.atapi_scsi_cdb[0] =
4680                         cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4681                                      (task->ata_task.atapi_packet[1] << 8) |
4682                                      (task->ata_task.atapi_packet[2] << 16) |
4683                                      (task->ata_task.atapi_packet[3] << 24)));
4684                 sata_cmd.atapi_scsi_cdb[1] =
4685                         cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4686                                      (task->ata_task.atapi_packet[5] << 8) |
4687                                      (task->ata_task.atapi_packet[6] << 16) |
4688                                      (task->ata_task.atapi_packet[7] << 24)));
4689                 sata_cmd.atapi_scsi_cdb[2] =
4690                         cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4691                                      (task->ata_task.atapi_packet[9] << 8) |
4692                                      (task->ata_task.atapi_packet[10] << 16) |
4693                                      (task->ata_task.atapi_packet[11] << 24)));
4694                 sata_cmd.atapi_scsi_cdb[3] =
4695                         cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4696                                      (task->ata_task.atapi_packet[13] << 8) |
4697                                      (task->ata_task.atapi_packet[14] << 16) |
4698                                      (task->ata_task.atapi_packet[15] << 24)));
4699         }
4700
4701         /* Check for read log for failed drive and return */
4702         if (sata_cmd.sata_fis.command == 0x2f) {
4703                 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4704                         (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4705                         (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4706                         struct task_status_struct *ts;
4707
4708                         pm8001_ha_dev->id &= 0xDFFFFFFF;
4709                         ts = &task->task_status;
4710
4711                         spin_lock_irqsave(&task->task_state_lock, flags);
4712                         ts->resp = SAS_TASK_COMPLETE;
4713                         ts->stat = SAS_SAM_STAT_GOOD;
4714                         task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4715                         task->task_state_flags |= SAS_TASK_STATE_DONE;
4716                         if (unlikely((task->task_state_flags &
4717                                         SAS_TASK_STATE_ABORTED))) {
4718                                 spin_unlock_irqrestore(&task->task_state_lock,
4719                                                         flags);
4720                                 pm8001_dbg(pm8001_ha, FAIL,
4721                                            "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4722                                            task, ts->resp,
4723                                            ts->stat);
4724                                 pm8001_ccb_task_free(pm8001_ha, ccb);
4725                                 return 0;
4726                         } else {
4727                                 spin_unlock_irqrestore(&task->task_state_lock,
4728                                                         flags);
4729                                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
4730                                 atomic_dec(&pm8001_ha_dev->running_req);
4731                                 return 0;
4732                         }
4733                 }
4734         }
4735         trace_pm80xx_request_issue(pm8001_ha->id,
4736                                 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
4737                                 ccb->ccb_tag, opc,
4738                                 qc ? qc->tf.command : 0, // ata opcode
4739                                 ccb->device ? atomic_read(&ccb->device->running_req) : 0);
4740         return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd,
4741                                     sizeof(sata_cmd), q_index);
4742 }
4743
4744 /**
4745  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4746  * @pm8001_ha: our hba card information.
4747  * @phy_id: the phy id which we wanted to start up.
4748  */
4749 static int
4750 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4751 {
4752         struct phy_start_req payload;
4753         u32 tag = 0x01;
4754         u32 opcode = OPC_INB_PHYSTART;
4755
4756         memset(&payload, 0, sizeof(payload));
4757         payload.tag = cpu_to_le32(tag);
4758
4759         pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4760
4761         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4762                         LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4763         /* SSC Disable and SAS Analog ST configuration */
4764         /*
4765         payload.ase_sh_lm_slr_phyid =
4766                 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4767                 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4768                 phy_id);
4769         Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4770         */
4771
4772         payload.sas_identify.dev_type = SAS_END_DEVICE;
4773         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4774         memcpy(payload.sas_identify.sas_addr,
4775           &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4776         payload.sas_identify.phy_id = phy_id;
4777
4778         return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4779                                     sizeof(payload), 0);
4780 }
4781
4782 /**
4783  * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4784  * @pm8001_ha: our hba card information.
4785  * @phy_id: the phy id which we wanted to start up.
4786  */
4787 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4788         u8 phy_id)
4789 {
4790         struct phy_stop_req payload;
4791         u32 tag = 0x01;
4792         u32 opcode = OPC_INB_PHYSTOP;
4793
4794         memset(&payload, 0, sizeof(payload));
4795         payload.tag = cpu_to_le32(tag);
4796         payload.phy_id = cpu_to_le32(phy_id);
4797
4798         return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4799                                     sizeof(payload), 0);
4800 }
4801
4802 /*
4803  * see comments on pm8001_mpi_reg_resp.
4804  */
4805 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4806         struct pm8001_device *pm8001_dev, u32 flag)
4807 {
4808         struct reg_dev_req payload;
4809         u32     opc;
4810         u32 stp_sspsmp_sata = 0x4;
4811         u32 linkrate, phy_id;
4812         int rc;
4813         struct pm8001_ccb_info *ccb;
4814         u8 retryFlag = 0x1;
4815         u16 firstBurstSize = 0;
4816         u16 ITNT = 2000;
4817         struct domain_device *dev = pm8001_dev->sas_device;
4818         struct domain_device *parent_dev = dev->parent;
4819         struct pm8001_port *port = dev->port->lldd_port;
4820
4821         memset(&payload, 0, sizeof(payload));
4822         ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4823         if (!ccb)
4824                 return -SAS_QUEUE_FULL;
4825
4826         payload.tag = cpu_to_le32(ccb->ccb_tag);
4827
4828         if (flag == 1) {
4829                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4830         } else {
4831                 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4832                         stp_sspsmp_sata = 0x00; /* stp*/
4833                 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4834                         dev_is_expander(pm8001_dev->dev_type))
4835                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4836         }
4837         if (parent_dev && dev_is_expander(parent_dev->dev_type))
4838                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4839         else
4840                 phy_id = pm8001_dev->attached_phy;
4841
4842         opc = OPC_INB_REG_DEV;
4843
4844         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4845                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4846
4847         payload.phyid_portid =
4848                 cpu_to_le32(((port->port_id) & 0xFF) |
4849                 ((phy_id & 0xFF) << 8));
4850
4851         payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4852                 ((linkrate & 0x0F) << 24) |
4853                 ((stp_sspsmp_sata & 0x03) << 28));
4854         payload.firstburstsize_ITNexustimeout =
4855                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4856
4857         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4858                 SAS_ADDR_SIZE);
4859
4860         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4861                         sizeof(payload), 0);
4862         if (rc)
4863                 pm8001_ccb_free(pm8001_ha, ccb);
4864
4865         return rc;
4866 }
4867
4868 /**
4869  * pm80xx_chip_phy_ctl_req - support the local phy operation
4870  * @pm8001_ha: our hba card information.
4871  * @phyId: the phy id which we wanted to operate
4872  * @phy_op: phy operation to request
4873  */
4874 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4875         u32 phyId, u32 phy_op)
4876 {
4877         u32 tag;
4878         int rc;
4879         struct local_phy_ctl_req payload;
4880         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4881
4882         memset(&payload, 0, sizeof(payload));
4883         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4884         if (rc)
4885                 return rc;
4886
4887         payload.tag = cpu_to_le32(tag);
4888         payload.phyop_phyid =
4889                 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4890
4891         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4892                                   sizeof(payload), 0);
4893         if (rc)
4894                 pm8001_tag_free(pm8001_ha, tag);
4895
4896         return rc;
4897 }
4898
4899 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4900 {
4901 #ifdef PM8001_USE_MSIX
4902         return 1;
4903 #else
4904         u32 value;
4905
4906         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4907         if (value)
4908                 return 1;
4909         return 0;
4910 #endif
4911 }
4912
4913 /**
4914  * pm80xx_chip_isr - PM8001 isr handler.
4915  * @pm8001_ha: our hba card information.
4916  * @vec: irq number.
4917  */
4918 static irqreturn_t
4919 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4920 {
4921         pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4922         pm8001_dbg(pm8001_ha, DEVIO,
4923                    "irq vec %d, ODMR:0x%x\n",
4924                    vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4925         process_oq(pm8001_ha, vec);
4926         pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4927         return IRQ_HANDLED;
4928 }
4929
4930 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4931                                     u32 operation, u32 phyid,
4932                                     u32 length, u32 *buf)
4933 {
4934         u32 tag, i, j = 0;
4935         int rc;
4936         struct set_phy_profile_req payload;
4937         u32 opc = OPC_INB_SET_PHY_PROFILE;
4938
4939         memset(&payload, 0, sizeof(payload));
4940         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4941         if (rc) {
4942                 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4943                 return;
4944         }
4945
4946         payload.tag = cpu_to_le32(tag);
4947         payload.ppc_phyid =
4948                 cpu_to_le32(((operation & 0xF) << 8) | (phyid  & 0xFF));
4949         pm8001_dbg(pm8001_ha, INIT,
4950                    " phy profile command for phy %x ,length is %d\n",
4951                    le32_to_cpu(payload.ppc_phyid), length);
4952         for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4953                 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4954                 j++;
4955         }
4956         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4957                                   sizeof(payload), 0);
4958         if (rc)
4959                 pm8001_tag_free(pm8001_ha, tag);
4960 }
4961
4962 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4963         u32 length, u8 *buf)
4964 {
4965         u32 i;
4966
4967         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4968                 mpi_set_phy_profile_req(pm8001_ha,
4969                         SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4970                 length = length + PHY_DWORD_LENGTH;
4971         }
4972         pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
4973 }
4974
4975 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4976                 u32 phy, u32 length, u32 *buf)
4977 {
4978         u32 tag, opc;
4979         int rc, i;
4980         struct set_phy_profile_req payload;
4981
4982         memset(&payload, 0, sizeof(payload));
4983
4984         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4985         if (rc) {
4986                 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
4987                 return;
4988         }
4989
4990         opc = OPC_INB_SET_PHY_PROFILE;
4991
4992         payload.tag = cpu_to_le32(tag);
4993         payload.ppc_phyid =
4994                 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4995                             | (phy & 0xFF));
4996
4997         for (i = 0; i < length; i++)
4998                 payload.reserved[i] = cpu_to_le32(*(buf + i));
4999
5000         rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
5001                         sizeof(payload), 0);
5002         if (rc)
5003                 pm8001_tag_free(pm8001_ha, tag);
5004
5005         pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
5006 }
5007 const struct pm8001_dispatch pm8001_80xx_dispatch = {
5008         .name                   = "pmc80xx",
5009         .chip_init              = pm80xx_chip_init,
5010         .chip_soft_rst          = pm80xx_chip_soft_rst,
5011         .chip_rst               = pm80xx_hw_chip_rst,
5012         .chip_iounmap           = pm8001_chip_iounmap,
5013         .isr                    = pm80xx_chip_isr,
5014         .is_our_interrupt       = pm80xx_chip_is_our_interrupt,
5015         .isr_process_oq         = process_oq,
5016         .interrupt_enable       = pm80xx_chip_interrupt_enable,
5017         .interrupt_disable      = pm80xx_chip_interrupt_disable,
5018         .make_prd               = pm8001_chip_make_sg,
5019         .smp_req                = pm80xx_chip_smp_req,
5020         .ssp_io_req             = pm80xx_chip_ssp_io_req,
5021         .sata_req               = pm80xx_chip_sata_req,
5022         .phy_start_req          = pm80xx_chip_phy_start_req,
5023         .phy_stop_req           = pm80xx_chip_phy_stop_req,
5024         .reg_dev_req            = pm80xx_chip_reg_dev_req,
5025         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
5026         .phy_ctl_req            = pm80xx_chip_phy_ctl_req,
5027         .task_abort             = pm8001_chip_abort_task,
5028         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
5029         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
5030         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
5031         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5032         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
5033         .fatal_errors           = pm80xx_fatal_errors,
5034         .hw_event_ack_req       = pm80xx_hw_event_ack_req,
5035 };